-- ***************************************************************************** -- BSDL file for design dac38j84 -- Designer: Scott Kaylor -- Company: Texas Instruments -- Date: 26JUNE14 -- ***************************************************************************** -------------------------------------------------------------------------------- -- * This BSDL file has been syntax checked with: -- * - Intellitech iBSDL Compiler (http://www.intellitech.com) -------------------------------------------------------------------------------- entity dac38j84 is -- This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP : string := "S_PGA_N144"); -- This section declares all the ports in the design. port ( pad_dacclkn : linkage bit; pad_dacclkp : linkage bit; pad_iforce : linkage bit; pad_resetb : in bit; pad_rx0n : in bit; pad_rx0p : in bit; pad_rx1n : in bit; pad_rx1p : in bit; pad_rx2n : in bit; pad_rx2p : in bit; pad_rx3n : in bit; pad_rx3p : in bit; pad_rx4n : in bit; pad_rx4p : in bit; pad_rx5n : in bit; pad_rx5p : in bit; pad_rx6n : in bit; pad_rx6p : in bit; pad_rx7n : in bit; pad_rx7p : in bit; pad_sclk : in bit; pad_sdenb : in bit; pad_sleep : in bit; pad_nc1 : in bit; pad_nc2 : in bit; pad_sysrefn : linkage bit; pad_sysrefp : linkage bit; pad_tclk : in bit; pad_tdi : in bit; pad_testmode : in bit; pad_tms : in bit; pad_trstb : in bit; pad_txenable : in bit; -- pad_tdo : inout bit; -- pad_alarm : inout bit; -- pad_sdio : inout bit; -- pad_sdo : inout bit; -- pad_sync_n_ab : inout bit; -- pad_sync_n_cd : inout bit; pad_tdo : out bit; pad_alarm : out bit; pad_sdio : inout bit; pad_sdo : out bit; pad_sync_n_ab : buffer bit; pad_sync_n_cd : buffer bit; pad_syncbn : linkage bit; pad_syncbp : linkage bit; pad_vsense : linkage bit ); use STD_1149_1_2001.all; attribute COMPONENT_CONFORMANCE of dac38j84: entity is "STD_1149_1_1993"; attribute PIN_MAP of dac38j84 : entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. This information is -- extracted from the port-to-pin map file that was read in using the -- "read_pin_map" command. constant S_PGA_N144: PIN_MAP_STRING := "pad_dacclkn : A9," & "pad_dacclkp : A10," & "pad_iforce : C5," & "pad_resetb : K8," & "pad_rx0n : H1," & "pad_rx0p : G1," & "pad_rx1n : J1," & "pad_rx1p : K1," & "pad_rx2n : M1," & "pad_rx2p : L1," & "pad_rx3n : M2," & "pad_rx3p : M3," & "pad_rx4n : E1," & "pad_rx4p : F1," & "pad_rx5n : D1," & "pad_rx5p : C1," & "pad_rx6n : A1," & "pad_rx6p : B1," & "pad_rx7n : A2," & "pad_rx7p : A3," & "pad_sclk : L9," & "pad_sdenb : M9," & "pad_sleep : M8," & "pad_nc1 : M6," & "pad_nc2 : M7," & "pad_sysrefn : A6," & "pad_sysrefp : A7," & "pad_tclk : K4," & "pad_tdi : L5," & "pad_testmode : K3," & "pad_tms : L4," & "pad_trstb : J3," & "pad_txenable : K5," & "pad_alarm : L8," & "pad_sdio : L10," & "pad_sdo : M10," & "pad_sync_n_ab : L6," & "pad_sync_n_cd : L7," & "pad_syncbn : B6," & "pad_syncbp : B7," & "pad_tdo : M5," & "pad_vsense : C4"; -- This section specifies the TAP ports. For the TAP TCK port, the parameters in -- the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of pad_tclk : signal is (2.0000e+07, BOTH); attribute TAP_SCAN_IN of pad_tdi : signal is true; attribute TAP_SCAN_MODE of pad_tms : signal is true; attribute TAP_SCAN_OUT of pad_tdo : signal is true; attribute TAP_SCAN_RESET of pad_trstb: signal is true; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of dac38j84: entity is 8; -- Specifies the boundary-scan instructions implemented in the design and their -- opcodes. attribute INSTRUCTION_OPCODE of dac38j84: entity is "BYPASS (11111111)," & "IDCODE (00000001)," & "SAMPLE (00000010)," & --"PRELOAD (00000010)," & "EXTEST (00000000)"; -- Specifies the bit pattern that is loaded into the instruction register when -- the TAP controller passes through the Capture-IR state. The standard mandates -- that the two LSBs must be "01". The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of dac38j84: entity is "00000001"; -- Specifies the bit pattern that is loaded into the DEVICE_ID register during -- the IDCODE instruction when the TAP controller passes through the Capture-DR -- state. attribute IDCODE_REGISTER of dac38j84: entity is "0000" & --Version "1011100110100001" & --Device "00000010111" & --Manufacturer "1"; --Required -- This section specifies the test data register placed between TDI and TDO for -- each implemented instruction. attribute REGISTER_ACCESS of dac38j84: entity is "BYPASS (BYPASS)," & "BOUNDARY (EXTEST, SAMPLE)," & "DEVICE_ID (IDCODE)"; -- Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of dac38j84: entity is 32; -- The following list specifies the characteristics of each cell in the boundary -- scan register from TDI to TDO. The following is a description of the label -- fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not have a port -- name. -- function: Is the function of the cell as defined by the standard. Is one -- of input, output2, output3, bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be loaded with -- for safe operation when the software might otherwise choose a -- random value. -- ccell : The control cell number. Specifies the control cell that -- drives the output enable for this port. -- disval : Specifies the value that is loaded into the control cell to -- disable the output enable for the corresponding port. -- rslt : Resulting state. Shows the state of the driver when it is -- disabled. attribute BOUNDARY_REGISTER of dac38j84: entity is -- TDI -> TDO -- -- num cell port function safe [ccell disval rslt] -- "31 (BC_2, pad_nc1, input, X )," & "30 (BC_2, pad_nc2, input, X )," & "29 (BC_2, pad_txenable, input, X )," & "28 (BC_4, pad_testmode, input, X )," & "27 (BC_2, pad_sdenb, input, X )," & "26 (BC_4, pad_sclk, input, X )," & "25 (BC_2, pad_resetb, input, X )," & "24 (BC_2, pad_sleep, input, X )," & "23 (BC_2, pad_alarm, output3, X, 22, 1, Z )," & "22 (BC_2, *, control, 1 )," & "21 (BC_2, pad_sdo, output3, X, 20, 1, Z )," & "20 (BC_2, *, control, 1 )," & "19 (BC_2, pad_sync_n_ab, output2, X )," & "18 (BC_2, pad_sync_n_cd, output2, X )," & "17 (BC_1, *, control, 1 )," & "16 (BC_7, pad_sdio, bidir, X, 17, 1, Z )," & "15 (BC_4, pad_rx0p, input, X )," & "14 (BC_4, pad_rx0n, input, X )," & "13 (BC_4, pad_rx1p, input, X )," & "12 (BC_4, pad_rx1n, input, X )," & "11 (BC_4, pad_rx2p, input, X )," & "10 (BC_4, pad_rx2n, input, X )," & "9 (BC_4, pad_rx3p, input, X )," & "8 (BC_4, pad_rx3n, input, X )," & "7 (BC_4, pad_rx4p, input, X )," & "6 (BC_4, pad_rx4n, input, X )," & "5 (BC_4, pad_rx5p, input, X )," & "4 (BC_4, pad_rx5n, input, X )," & "3 (BC_4, pad_rx6p, input, X )," & "2 (BC_4, pad_rx6n, input, X )," & "1 (BC_4, pad_rx7p, input, X )," & "0 (BC_4, pad_rx7n, input, X )"; end dac38j84;