--> Initialize
0x00004400 <- 0x0000101e; Get initial value of ADC External Control
0x00004400 -> 0x0000101e; Initialize ADC External Control
0x00004400 -> 0x0000101f; Power up ADC
0x00004440 -> 0x00007fff
0x00004444 -> 0x0000b1ff; Set Configuration Register
0x00004448 -> 0x0000007f; Set Channel I Offset
0x0000444c -> 0x0000807f; Set Channel I Full Scale
0x00004468 -> 0x0000007f; Set Channel Q Offset
0x0000446c -> 0x0000807f; Set Channel Q Full Scale
0x0000447c -> 0x0000007f; Set Phase Coarse Adjust
0x00004478 -> 0x000000ff; Set Phase Fine Adjust
0x00004464 -> 0x000043ff; Set Extended Configuration
0x00004400 -> 0x0000001f; Clear Cal Run
0x00004400 <- 0x0000001f; Read to ensure PCIe flush
0x00004400 -> 0x0000101f; Set Cal Run
0x00004400 <- 0x0000301f; Read to ensure PCIe flush
0x00004400 <- 0x0000301f; Poll for ADC Cal done
0x00004400 <- 0x0000301f; Poll for ADC Cal done
0x00004400 <- 0x0000101f; Poll for ADC Cal done
0x00004464 -> 0x0000c3ff; Enable Test Pattern Output
0x00004464 -> 0x000043ff; Disable Test Pattern Output
--> Configure
0x00004464 -> 0x000063ff; Set Extended Configuration
0x00004464 -> 0x0000e3ff; Enable Test Pattern Output
0x00004464 -> 0x000063ff; Disable Test Pattern Output
--> Configure Offset 0 (do nothing)
0x00004464 -> 0x000063ff; Set Extended Configuration
0x00004464 -> 0x000063ff; Set Extended Configuration
============> Read Data
--> Configure Offset 48
0x00004464 -> 0x000043ff; Set Extended Configuration
0x00004448 -> 0x0000307f; Set Channel I Offset
0x00004464 -> 0x000063ff; Set Extended Configuration
============> Read Data
--> Back to normal
0x00004464 -> 0x000043ff; Set Extended Configuration
0x00004448 -> 0x0000007f; Set Channel I Offset
0x00004464 -> 0x000063ff; Set Extended Configuration