# DAC39RF12 Initialization Register File - JMODE 3 Configuration (Subclass 1, One-Shot SYSREF) # Format: RXXX0xAAAAAADD # Where XXX = decimal register number (= hex address in decimal) # AAAAAA = 16-bit register address (hex) # DD = 8-bit data value (hex) # # JMODE 3: 16-bit, standard mode, M=2 (I and Q), 640 MSPS (L=4, M=2, F=2, S=2, K=32) # JCTRL=0x22: SUBCLASS=1, SFORMAT=1, JENC=0(8b/10b), TI_MODE=0, SCR=0 (scrambling disabled) # SYSREF: ONE-SHOT mode (capture next SYSREF pulse, then ignore all subsequent pulses) # LMFC: 10 MHz (Frame_clock / K = 320 MHz / 32) # # Structure: Disable JESD+DP first, configure everything, then enable at the end. # No intermediate JESD_EN/DP_EN toggles. # ============================================================ # 1. Disable datapath and JESD subsystem (must be first) # ============================================================ R736 0x02E000 R256 0x010000 # ============================================================ # 2. Clear JESD status flags (write 0xFF to clear all) # ============================================================ R263 0x0107FF # ============================================================ # 3. Lane crossbar mapping (LANE_SEL[0:15]) # Maps physical SerDes lanes to logical JESD lanes. # Actual PCB routing for this board (NOT TI EVM mapping) # ============================================================ # Active mapping (straight 0-15): R304 0x013000 R305 0x013101 R306 0x013202 R307 0x013303 R308 0x013404 R309 0x013505 R310 0x013606 R311 0x013707 R312 0x013808 R313 0x013909 R314 0x013A0A R315 0x013B0B R316 0x013C0C R317 0x013D0D R318 0x013E0E R319 0x013F0F # Alternate mapping (custom PCB routing): #R304 0x013009 #R305 0x01310B #R306 0x01320F #R307 0x013305 #R308 0x013403 #R309 0x013500 #R310 0x013601 #R311 0x013702 #R312 0x013807 #R313 0x01390D #R314 0x013A0C #R315 0x013B0E #R316 0x013C06 #R317 0x013D04 #R318 0x013E0A #R319 0x013F08 # ============================================================ # 4. Lane inversion (LANE_INV) # ALL 16 lanes inverted (actual PCB differential pair routing) # ============================================================ # New inversion (all lanes inverted): R302 0x012EFF R303 0x012FFF # ============================================================ # 5. Lane enable (LANE_EN) - Enable lanes 0-3 for L=4 # Register 0x0140: bits[7:0] = lanes 0-7 enable mask # Register 0x0141: bits[7:0] = lanes 8-15 enable mask # For L=4, enable logical lanes 0-3: 0x0F # ============================================================ R320 0x01400F R321 0x014100 # ============================================================ # 6. SerDes equalizer control # EQ_CTRL = 0x01: EQMODE=1 (adaptive), no manual overrides # ============================================================ R450 0x01C201 # ============================================================ # 7. K parameter (K=32, so KM1=31=0x1F) # CRITICAL: Must match FPGA JESD IP configuration # Lane rate: 6.4 Gbps (M=2, N'=16, S=2, Fc=320MHz) # LMFC frequency = Frame_clock / K = 320 MHz / 32 = 10 MHz # ============================================================ R261 0x01051F # ============================================================ # 8. NCO control (direct baseband mode) # NCO_CTRL = 0x00: All NCO features disabled → direct baseband # ============================================================ R768 0x030000 # ============================================================ # 9. JMODE = 0xC3 (Mode 3: L=4, M=2, F=2, S=2, 16-bit) # bits[5:0] = 3, bits[7:6] = reserved (set by EVM) # ============================================================ R257 0x0101C3 # ============================================================ # 10. JCTRL = 0x22 (8b/10b, scrambling DISABLED, subclass 1) # bit[0] SCR = 0 (scrambling DISABLED) # bit[1] SFORMAT = 1 (signed 2's complement) # bit[4] JENC = 0 (8b/10b link layer) # bit[5] SUBCLASS = 1 (subclass 1, continuous SYSREF, deterministic latency) # bit[6] TI_MODE = 0 (not using TI FPGA transmitter IP) # ============================================================ R259 0x010322 # ============================================================ # 11. DUC interpolation factor # DUC_L = 0x07 (16x interpolation: 640MSPS * 16 = 10.24 GSPS) # Values: 0=1x, 1=2x, 2=3x, 3=4x, 4=6x, 5=8x, 6=12x, 7=16x # ============================================================ R737 0x02E107 # ============================================================ # 12. JESD_M = 2 (2 sample streams: I and Q) # ============================================================ R258 0x010202 # ============================================================ # 13. SerDes PLL configuration (for 6.4 Gbps lane rate) # REFDIV = 0x10 (divide by 16) # MPY = 0x14 (multiply by 20) # RATE = 0x00 (rate divider) # VRANGE = 0x00 (VCO > 2.17 GHz) # ============================================================ R264 0x010810 R265 0x010914 R266 0x010A00 R267 0x010B00 # ============================================================ # 14. SYSREF configuration (ONE-SHOT for subclass 1) # SYSREF_CTRL = 0xA0: PROC_EN=1 (enable), RECV_SLEEP=1 (one-shot) # bit[7] RECV_SLEEP = 1 (one-shot: capture next SYSREF, then sleep/ignore rest) # bit[5] PROC_EN = 1 (enable SYSREF processing) # ============================================================ R128 0x0080A0 # ============================================================ # 15. SYSREF alignment (ENABLED for subclass 1) # SYSREF_ALIGN_EN = 0x01 (enable SYSREF alignment for deterministic latency) # ============================================================ R160 0x00A001 # ============================================================ # 16. TX enable and DAC source routing # ============================================================ R760 0x02F803 R740 0x02E401 R740 0x02E411 # ============================================================ # 17. NCO frequency / DDS registers (all zeros = DC) # ============================================================ R800 0x032000 R801 0x032100 R802 0x032200 R803 0x032300 R804 0x032400 R805 0x032500 R806 0x032600 R807 0x032719 # ============================================================ # 18. SPI_SYNC sequence (apply NCO settings) # ============================================================ R772 0x030400 R772 0x030401 R772 0x030400 # ============================================================ # 19. DDS amplitude (AMP[0]) # AMP registers should be changed when DP_EN=0 (we are still disabled) # ============================================================ R792 0x031879 R793 0x031928 # ============================================================ # 20. SPI_SYNC again and second frequency word # ============================================================ R772 0x030400 R772 0x030401 R772 0x030400 R800 0x032000 R801 0x032100 R802 0x032200 R803 0x032300 R804 0x032400 R805 0x032500 R806 0x032600 R807 0x032732 R772 0x030400 R772 0x030401 R772 0x030400 # ============================================================ # 21. JESD reset + enable sequence (must be last) # Assert JESD_RST, enable JESD_EN, enable DP_EN, release JESD_RST # ============================================================ R736 0x02E001 R256 0x010001