Operating System Name : Windows 10 Enterprise LTSC 2019 64 bit default
Error code : 102.000000
Error Description: 
Read DDR to file
TIMED_OUT_ERROR
Possible reasons for Time Out Error:                                                                  1.FPGA may be in reset.                                                                                  2.Clock from ADC EVM is not received by TSW Board. Please check if D4 LED is blinking.                                                                                                                      3.SYNC is not established between ADC and FPGA. Please check if D3 LED is OFF. Possible reasons for SYNC Failure:                                                                                                                      a.JESD Ref clock Input Frequency to the TSW board from ADC EVM is not correct.                                                                                                                                     b.JESD configuration is not same in ADC and the INI file selected.
ADC/DAC name : AFE79xx_6RX_24410
IID: 7.000000
Device config details:

[ADC]
Interface name="TSW14J57RevE_16L_XCVR_ADCBRAMDACDDR"
Number of channels=12
Channel Pattern=1,2,3,4,5,6,7,8,9,10,11,12,0,0,0,0
Data Postprocessing=1:32768
\\operation:operand
\\operaion
\\0=bit shift
\\1=xor
\\2=and
\\3=or
\\4=not
\\operand
\\value(+ve if bitshift by right and -ve if bitshift by left)
\\E.g 0:-2,1:1024
\\bitshift by left 2 times and then xor by 1024
Number of Bits=16
Max sample Rate=7500000000
Register_Config="-"
\\[Register Address]:[Register Value]:[Number of Bytes to be sent as]
DLL Version=1.0
Read EVM Setup Procedure="EVM Setup Procedure not available"
\\use <> as delimiter for newline
[Version 1.0]
JESD IP Core_CS=0
JESD IP Core_F=4
JESD IP Core_HD=0
JESD IP Core_K=16
JESD IP Core_L=6
JESD IP Core_M=12
JESD IP Core_N=16
JESD IP Core_NTotal=16
JESD IP Core_S=1
JESD IP Core_SCR=1
JESD IP Core_Tailbits=0
JESD IP Core_LaneSync=1
JESD IP Core_Subclass=1
JESD IP Core_JESDV=1
MIF Config= 0.611G to 12.5G:RX:RX_PMA_x40
\\List of Lane Rate Range,PLL Type and their MIF File names that needs to be configured,separated by ":"
\\These MIF Files need to be present under MIF Files Folder
Fabric PLL Counter = 0.611G to 12.5G:0x080202
Invert Sync Polarity = 0 
\\Invert Sync polarity, 1:invert; 0: do not invert
\\Invert Serdes Data, 1:invert; 0: do not invert
Enable Individual Lane Inversion = 1
Invert Serdes Data = 108 
Transceiver Mode = 1
\\1:xcvr mode; 0: TX/RX only mode
Lane Mapping=lane0:5,lane1:6,lane2:4,lane3:3,lane4:2,lane5:0
skipreconfig=0

skipreconfig = 0

Mixer Type =1
\\Bit Packing Channel Pattern =C1S1[15:0],C2S1[15:0],C3S1[15:0],C4S1[15:0],C5S1[15:0],C6S1[15:0],C7S1[15:0],C8S1[15:0],C9S1[15:0],C10S1[15:0],C11S1[15:0],C12S1[15:0]
\\0-> Straight Mixer - Default - (Fout=Fin+NCO)
\\1-> Down Mixer (Fout=Fin-NCO)