#ifndef ADS114S08_DRV_ADS114S08CONFIG #define ADS114S08_DRV_ADS114S08CONFIG //VOLTAGE REFERENCE /* The ADS114S0x offers an integrated low-drift 2.5-V reference. For applications that require a different reference voltage value or a ratiometric measurement approach, the ADS114S08 offers two differential reference input pairs (REFP0, REFN0 and REFP1, REFN1). The specified external reference voltage range is 0.5 V to AVDD. The reference voltage is shown in Equation 7, where V(REFPx) and V(REFNx) are the absolute positive and absolute negative reference voltages. VREF = V(REFPx) – V(REFNx) The magnitude of the reference voltage together with the PGA gain establishes the ADC full-scale differential input range as defined by FSR = ±VREF / Gain. The device has two individually selectable reference input buffers to lower the reference input current. Use the REFP_BUF and REFN_BUF bits in the reference control register (05h) to enable or disable the positive and negative reference buffers respectively. Note that these bits are active low. Writing a 1 to REFP_BUF or REFN_BUF disables the reference buffers. The reference buffers are recommended to be disabled when the internal reference is selected for measurements. When the external reference input is at the supply voltage (REFPx at AVDD or REFNx at AVSS), the reference buffer is recomended to be disabled. */ //PGA //For linear operation, the PGA output voltages must not exceed AVDD – 0.15 V or AVSS + 0.15 V. //TWO WIRE MEASUREMENT /* Ideally, choosing the largest IDAC current provides the best performance by increasing the sensor signal above any noise in the system. However, there are several other considerations in determining the values. First, higher current may lead to self-heating of the RTD, which adds error to the measurement. Second, the reference resistance acts as a level shift for the sensor measurement. This level shift is used to raise the DC bias of the analog input signal so that the voltage is within the input range of the PGA. Generally, the analog input signal is set near mid-supply for best operation. VAIN1 = IIDAC1 • (RRTD + RREF) VAIN2 = IIDAC1 • RREF Additionally, the output voltage of the IDAC source calculated from VAIN1 must be low enough from AVDD to be within the compliance voltage of the IDAC current source. When the IDAC output voltage rises too close to AVDD, the IDAC loses compliance and the excitation current is reduced. Output Code = 2^23 • Gain • VRTD / VREF = 2^23 • Gain • (IIDAC1 • RRTD) / (IIDAC1 • RREF) = 2^23 • Gain • RRTD / RREF RRTD = RREF • Output Code / (2^23 • Gain) VAIN1 = 1000uA * (400 + 2000) = 2.4v VAIN2 = 1000uA * (2000) = 2v */ /********************************************************************************/ //THREE WIRE MEASUREMENT 1 IDACS /* In this topology, two measurements are taken for lead resistance cancellation. In the first measurement, the ADC measures the voltage across the RTD and the resistance for lead 1 as driven by the single excitation current source. In the second measurement, the ADC measures the resistance for lead 3 as driven by the same excitation current source. This method assumes that the resistance in lead 1 and lead 3 are equal. By subtracting the second measurement from the first, the RTD resistance can be accurately measured, and the lead resistance cancelled. VAIN1 = IIDAC1 • (RRTD + RREF) VAIN2 = IIDAC1 • RREF Output code 1 = 2^23 • Gain • (VRTD + VLEAD1) / VREF = 2^23 • Gain • IIDAC • (RRTD + RLEAD1) / (IIDAC • RREF) = 2^23 • Gain • (RRTD + RLEAD1) / RREF Output code 2 = 2^23 • Gain • VLEAD3 / VREF = 2^23 • Gain • IIDAC • RLEAD3 / (IIDAC • RREF) = 2^23 • Gain • RLEAD3 / RREF Output code 1 – Output code 2 = [2^23 • Gain • (VRTD + VLEAD1) / VREF] – [2^23 • Gain • RLEAD3 / RREF] = 2^23 • Gain • VRTD /VREF RRTD = RREF • (Output code 1 – Output code 2) / (2^23 • Gain) VAIN1 = 1000uA * (400 + 2000) = 2.4v VAIN2 = 1000uA * (2000) = 2v */ /********************************************************************************/ //THREE WIRE MEASUREMENT 2 IDACS /* VAIN1 = [IIDAC1 • (RRTD + RLEAD1)] + [(IIDAC1 + IIDAC2) • (RLEAD3 + RREF)] VAIN2 = (IIDAC2 • RLEAD2) + [(IIDAC1 + IIDAC2) • (RLEAD3 + RREF)] VREF = (IIDAC1 + IIDAC2) • RREF = 2 • IIDAC • RREF Verify that VAIN1 and VAIN2 are within the input range of the PGA given the gain setting and supply voltage. Use the maximum RTD resistance based on the desired temperature measurement. VAIN1 = (IIDAC1 • RRTD) + (IIDAC1 + IIDAC2) • RREF VAIN2 = (IIDAC1 + IIDAC2) • RREF Additionally, verify the output voltage of the IDAC sources calculated from VAIN0 and VAIN3 are low enough from AVDD to be within the compliance voltage of the IDAC current source. Because the voltage for IDAC1 always be higher than that of IDAC2, it is sufficient to calculate the output voltage at VAIN0 to verify the IDAC compliance voltage. This calculation is already shown in Equation 29, because VAIN0 is the same potential as VAIN1 Output code = 2^23 • Gain • VRTD / VREF = 2^23 • Gain • IIDAC • RRTD / (2 • IIDAC • RREF) = 2^22 • Gain • RRTD / RREF RRTD = RREF • Output code / (2^22 • Gain) VAIN1 = (1000uA • 2000) + (1000uA + 1000uA) • 2000 = 2 + 4 = 6 VAIN2 = (1000uA + 1000uA) * 2000 = 4v */ /********************************************************************************/ //FOUR WIRE MEASUREMENT /* To verify that the design is within the ADC range of operation, Calculate the voltages for AIN1 and AIN2 and the maximum differential input voltage. Verify that VAIN1 and VAIN2 are within the input range of the PGA given the gain setting and supply voltage. Use the maximum RTD resistance based on the desired temperature measurement. VAIN1 = IIDAC1 • (RRTD + RREF) VAIN2 = IIDAC1 • RREF Additionally, verify that the voltage seen at the IDAC pin (where VAIN0 = VAIN1) is within the current source compliance voltage. When the IDAC output voltage rises too close to AVDD, the IDAC loses compliance and the excitation current is reduced. Output code = 2^23 • Gain • VRTD / VREF = 2^23 • Gain • (IIDAC1 • RRTD) / (IIDAC1 • RREF) = 2^23 • Gain • RRTD / RRE RRTD = RREF • Output code / (2^23 • Gain) VAIN1 = 1000uA * (400 + 2000) = 2.4v VAIN2 = 1000uA * (2000) = 2v */ /********************************************************************************/ /********************************************************************************/ /* * * @name Board Resistance */ //The reference resistor must be larger than the maximum RTD value //The reference resistance and PGA gain determines the positive full-scale range of the measurement #define R68 1000 // Biasing resistors #define R70 1000 #define R70 1000 #define RREF 2000 //MSIO-PCB //resistance for 4-20ma #define RBURDEN 24.9 //MSIO-PCB /********************************************************************************/ /********************************************************************************/ /* * @name RESET Command instead of RESET pin */ #define RESET_PIN_CONTROLLED // Use RESET pin #define RTD_VBIAS VBIAS_DEFAULT //CHOP METE MUCHO RETARDO, USAR SOLO EN LAS RTD //USAR DATA SAMPLE A 20SPS PARA RTD, FILTRA EL RUIDO DE 50 Y 60HZ /********************************************************************************/ /* * @name RTD Connections for 2-Wire (Figure 2-1 of A Basic Guide to RTD Measurements (Rev. A)) * */ //defines for registers //CH1 #define RTD_TWO_WIRE_CH1_INPUT_MUX ADS_P_AIN1 | ADS_N_AIN2 // MuxP = Ain1, MuxN = Ain2 #define RTD_TWO_WIRE_CH1_IDACMUX ADS_IDAC2_OFF | ADS_IDAC1_A0 // IDAC1 Mux = AIN0, IDAC2 off //CH2 #define RTD_TWO_WIRE_CH2_INPUT_MUX ADS_P_AIN5 | ADS_N_AIN6 // MuxP = Ain1, MuxN = Ain2 #define RTD_TWO_WIRE_CH2_IDACMUX ADS_IDAC2_OFF | ADS_IDAC1_A4 // IDAC1 Mux = AIN0, IDAC2 off //CH3 #define RTD_TWO_WIRE_CH3_INPUT_MUX ADS_P_AIN9 | ADS_N_AIN10 // MuxP = Ain1, MuxN = Ain2 #define RTD_TWO_WIRE_CH3_IDACMUX ADS_IDAC2_OFF | ADS_IDAC1_A8 // IDAC1 Mux = AIN0, IDAC2 off #define RTD_TWO_WIRE_PGA ADS_PGA_ENABLED | ADS_GAIN_2 // PGA enabled, PGA gain = 2X //chop mode habilitado por jagi, no estaba por defecto #define RTD_TWO_WIRE_DATARATE ADS_GLOBALCHOP | ADS_CONVMODE_CONT | ADS_FILTERTYPE_LL | ADS_DR_20 // Continous conversion, low latency filter, 20 SPS rate #define RTD_TWO_WIRE_REF_SEL ADS_REFP_BYP_ENABLE | ADS_REFSEL_P0 | ADS_REFINT_ON_ALWAYS // RefN Enabled, RefP0 and RefN0 selected, Internal Ref always on #define RTD_TWO_WIRE_IDACMAG ADS_IDACMAG_1000 // IDAC Mag 1 mA //defines for conversion #define RTD_TWO_WIRE_REF_RES RREF #define RTD_TWO_WIRE_EXT_VREF 0.001 * RTD_TWO_WIRE_REF_RES //0.001 es la corriente del IDAC (este define no se usa para rdt) /********************************************************************************/ /* * @name RTD Connections for 3-Wire 1 Idacs (Figure 2-4 of A Basic Guide to RTD Measurements (Rev. A)) * */ //defines for registers //CH1 #define RTD_THREE_WIRE_ONE_IDAC_CH1_INPUT_MUX ADS_P_AIN1 | ADS_N_AIN2 // MuxP = Ain1, MuxN = Ain2 #define RTD_THREE_WIRE_ONE_IDAC_CH1_INPUT_MUX2 ADS_P_AIN2 | ADS_N_AIN3 // MuxP = Ain2, MuxN = Ain3 #define RTD_THREE_WIRE_ONE_IDAC_CH1_IDACMUX ADS_IDAC2_OFF | ADS_IDAC1_A0 // IDAC1 Mux = AIN0, IDAC2 Mux = AIN3 //CH2 #define RTD_THREE_WIRE_ONE_IDAC_CH2_INPUT_MUX ADS_P_AIN5 | ADS_N_AIN6 // MuxP = Ain1, MuxN = Ain2 #define RTD_THREE_WIRE_ONE_IDAC_CH2_INPUT_MUX2 ADS_P_AIN2 | ADS_N_AIN3 // MuxP = Ain2, MuxN = Ain3 #define RTD_THREE_WIRE_ONE_IDAC_CH2_IDACMUX ADS_IDAC2_OFF | ADS_IDAC1_A4 // IDAC1 Mux = AIN0, IDAC2 Mux = AIN3 //CH3 #define RTD_THREE_WIRE_ONE_IDAC_CH3_INPUT_MUX ADS_P_AIN9 | ADS_N_AIN10 // MuxP = Ain1, MuxN = Ain2 #define RTD_THREE_WIRE_ONE_IDAC_CH3_INPUT_MUX2 ADS_P_AIN2 | ADS_N_AIN3 // MuxP = Ain2, MuxN = Ain3 #define RTD_THREE_WIRE_ONE_IDAC_CH3_IDACMUX ADS_IDAC2_OFF | ADS_IDAC1_A8 // IDAC1 Mux = AIN0, IDAC2 Mux = AIN3 //GENERIC DEFINES FOR TWO WIRE ONE IDAC #define RTD_THREE_WIRE_ONE_IDAC_PGA ADS_PGA_ENABLED | ADS_GAIN_2 // PGA enabled, PGA gain = 2X //chop mode habilitado por jagi, no estaba por defecto #define RTD_THREE_WIRE_ONE_IDAC_DATARATE ADS_GLOBALCHOP | ADS_CONVMODE_CONT | ADS_FILTERTYPE_LL | ADS_DR_20 // Continous conversion, low latency filter, 20 SPS rate #define RTD_THREE_WIRE_ONE_IDAC_REF_SEL ADS_REFP_BYP_ENABLE | ADS_REFSEL_P0 | ADS_REFINT_ON_ALWAYS // RefN Enabled, RefP0 and RefN0 selected, Internal Ref always on #define RTD_THREE_WIRE_ONE_IDAC_IDACMAG ADS_IDACMAG_1000 // IDAC Mag 1 mA //defines for conversion #define RTD_THREE_WIRE_ONE_IDAC_REF_RES RREF #define RTD_THREE_WIRE_ONE_IDAC_EXT_VREF 0.001 * RTD_THREE_WIRE_ONE_IDAC_REF_RES //0.001 es la corriente del IDAC (este define no se usa para rdt) /********************************************************************************/ /* * @name RTD Connections for 3-Wire 2 Idacs (Figure 2-3 of A Basic Guide to RTD Measurements (Rev. A)) * */ //defines for registers //CH1 #define RTD_THREE_WIRE_TWO_IDAC_CH1_INPUT_MUX ADS_P_AIN1 | ADS_N_AIN2 // MuxP = Ain1, MuxN = Ain2 #define RTD_THREE_WIRE_TWO_IDAC_CH1_INPUT_MUX2 ADS_P_AIN2 | ADS_N_AIN3 // MuxP = Ain2, MuxN = Ain3 #define RTD_THREE_WIRE_TWO_IDAC_CH1_IDACMUX ADS_IDAC2_A3 | ADS_IDAC1_A0 // IDAC1 Mux = AIN0, IDAC2 Mux = AIN3 //CH2 #define RTD_THREE_WIRE_TWO_IDAC_CH2_INPUT_MUX ADS_P_AIN5 | ADS_N_AIN6 // MuxP = Ain1, MuxN = Ain2 #define RTD_THREE_WIRE_TWO_IDAC_CH2_INPUT_MUX2 ADS_P_AIN2 | ADS_N_AIN3 // MuxP = Ain2, MuxN = Ain3 #define RTD_THREE_WIRE_TWO_IDAC_CH2_IDACMUX ADS_IDAC2_A7 | ADS_IDAC1_A4 // IDAC1 Mux = AIN0, IDAC2 Mux = AIN3 //CH3 #define RTD_THREE_WIRE_TWO_IDAC_CH3_INPUT_MUX ADS_P_AIN9 | ADS_N_AIN10 // MuxP = Ain1, MuxN = Ain2 #define RTD_THREE_WIRE_TWO_IDAC_CH3_INPUT_MUX2 ADS_P_AIN2 | ADS_N_AIN3 // MuxP = Ain2, MuxN = Ain3 #define RTD_THREE_WIRE_TWO_IDAC_CH3_IDACMUX ADS_IDAC2_A11 | ADS_IDAC1_A8 // IDAC1 Mux = AIN0, IDAC2 Mux = AIN3 //GENERIC DEFINES FOR THREE WIRE TWO IDACS #define RTD_THREE_WIRE_TWO_IDAC_PGA ADS_PGA_ENABLED | ADS_GAIN_2 // PGA enabled, PGA gain = 2X //chop mode habilitado por jagi, no estaba por defecto #define RTD_THREE_WIRE_TWO_IDAC_DATARATE ADS_GLOBALCHOP | ADS_CONVMODE_CONT | ADS_FILTERTYPE_LL | ADS_DR_20 // Continous conversion, low latency filter, 20 SPS rate #define RTD_THREE_WIRE_TWO_IDAC_REF_SEL ADS_REFP_BYP_ENABLE | ADS_REFSEL_P0 | ADS_REFINT_ON_ALWAYS // RefN Enabled, RefP0 and RefN0 selected, Internal Ref always on #define RTD_THREE_WIRE_TWO_IDAC_IDACMAG ADS_IDACMAG_1000 // IDAC Mag 1 mA //defines for conversion #define RTD_THREE_WIRE_TWO_IDAC_REF_RES RREF #define RTD_THREE_WIRE_TWO_IDAC_EXT_VREF 0.001 * RTD_THREE_WIRE_TWO_IDAC_REF_RES //0.001 es la corriente del IDAC (este define no se usa para rdt) /********************************************************************************/ /* * @name RTD Connections for 4-Wire (Figure 2-6 of A Basic Guide to RTD Measurements (Rev. A)) * */ //defines for registers //CH1 #define RTD_FOUR_WIRE_CH1_INPUT_MUX ADS_P_AIN1 | ADS_N_AIN2 // MuxP = Ain1, MuxN = Ain2 #define RTD_FOUR_WIRE_CH1_IDACMUX ADS_IDAC2_OFF | ADS_IDAC1_A0 // IDAC1 Mux = AIN0, IDAC2 off //CH2 #define RTD_FOUR_WIRE_CH2_INPUT_MUX ADS_P_AIN5 | ADS_N_AIN6 // MuxP = Ain5, MuxN = Ain6 #define RTD_FOUR_WIRE_CH2_IDACMUX ADS_IDAC2_OFF | ADS_IDAC1_A4 // IDAC1 Mux = AIN4, IDAC2 off //CH3 #define RTD_FOUR_WIRE_CH3_INPUT_MUX ADS_P_AIN9 | ADS_N_AIN10 // MuxP = Ain1, MuxN = Ain2 #define RTD_FOUR_WIRE_CH3_IDACMUX ADS_IDAC2_OFF | ADS_IDAC1_A8 // IDAC1 Mux = AIN0, IDAC2 off //GENERIC DEFINES FOR FOUR WIRE #define RTD_FOUR_WIRE_PGA ADS_PGA_ENABLED | ADS_GAIN_2 // PGA enabled, PGA gain = 2X //chop mode habilitado por jagi, no estaba por defecto #define RTD_FOUR_WIRE_DATARATE ADS_GLOBALCHOP | ADS_CONVMODE_CONT | ADS_FILTERTYPE_LL | ADS_DR_20 // Continous conversion, low latency filter, 20 SPS rate #define RTD_FOUR_WIRE_REF_SEL ADS_REFP_BYP_ENABLE | ADS_REFSEL_P0 | ADS_REFINT_ON_ALWAYS // RefN Enabled, RefP0 and RefN0 selected, Internal Ref always on #define RTD_FOUR_WIRE_IDACMAG ADS_IDACMAG_1000 // IDAC Mag 1 mA //defines for conversion #define RTD_FOUR_WIRE_REF_RES RREF #define RTD_FOUR_WIRE_INT_VREF 0.001 * RTD_THREE_WIRE_TWO_IDAC_REF_RES //0.001 es la corriente del IDAC (este define no se usa para rdt) /********************************************************************************/ //If the thermocouple leads are long, then resistor biasing may create additional error. Long resistive leads will //react with the bias current to develop a voltage error in the measurement. //These current sources are used to pull apart the positive and negative leads of a thermocouple //during a burn-out condition. This is useful even if the thermocouple is biased from only one end by a DC source, //such as a reference voltage or VBIAS line. The positive burn-out current source pulls the positive lead high //enough so that the ADC reads a positive full-scale reading. //In general, the burn-out measurement using BOCS should be a separate measurement than the normal //temperature measurement. Using the BOCS may induce error when the thermocouple is not burned out. Extra //current may lead to self-heating of the sensor. //When enabling the BOCS for a burn-out measurement, ensure that there is additional time for voltage setting //between measurements. Filter capacitance may require time for voltage settling in both the burn-out and //temperature measurement. //When the device is set to 64 or 128, the PGA is set to a gain of 32, and additional gain is established with digital scaling. //The input-referred noise does still improve compared to the gain = 32 setting because the PGA is biased with a higher supply //current to reduce noise. /* * @name Thermocouple Connections (Figure 2-4 (pag 20) de SBAA274A) * * AIN2 <- AINP Thermocouple * AIN1 <- AINN Thermocouple * */ #define TC1_VBIAS ADS_VBIAS_LVL_DIV2 | ADS_VB_AIN1 #define TC1_INPUT_MUX ADS_N_AIN1 | ADS_P_AIN2 // MuxN = Ain1, MuxP = Ain2 for Thermocouple #define TC1_PGA ADS_PGA_ENABLED | ADS_GAIN_1 // PGA enabled, PGA gain = 2X #define TC1_DATARATE ADS_GLOBALCHOP | ADS_CONVMODE_CONT | ADS_FILTERTYPE_LL | ADS_DR_20 // Continous conversion, low latency filter, 20 SPS rate #define TC1_REF_SEL ADS_REFP_BYP_DISABLE | ADS_REFN_BYP_DISABLE | ADS_REFSEL_INT | ADS_REFINT_ON_ALWAYS // RefN Enabled, RefP0 and RefN0 selected, Internal Ref always on #define TC1_IDACMAG ADS_IDACMAG_OFF // IDAC Mag off #define TC1_IDACMUX ADS_IDAC2_OFF | ADS_IDAC1_OFF // IDAC1 off, IDAC2 off #define TC1_INT_VREF INT_VREF /********************************************************************************/ /* * @name Bridge Thermocouple Connections (Figure 2-4 (pag 20) de SBAA274A) * * AIN6 <- AINP Thermocouple * AIN5 <- AINN Thermocouple * */ #define TC2_VBIAS ADS_VBIAS_LVL_DIV2 | ADS_VB_AIN5 #define TC2_INPUT_MUX ADS_N_AIN5 | ADS_P_AIN6 // MuxN = Ain5, MuxP = Ain6 for Thermocouple #define TC2_PGA ADS_PGA_ENABLED | ADS_GAIN_16 // PGA enabled, PGA gain = 2X #define TC2_DATARATE ADS_GLOBALCHOP | ADS_CONVMODE_CONT | ADS_FILTERTYPE_LL | ADS_DR_20 // Continous conversion, low latency filter, 20 SPS rate #define TC2_REF_SEL ADS_REFP_BYP_DISABLE | ADS_REFN_BYP_DISABLE | ADS_REFSEL_INT | ADS_REFINT_ON_ALWAYS // RefN Disable, RefP0 and RefN0 selected, Int Ref always on #define TC2_IDACMAG ADS_IDACMAG_OFF // IDAC Mag off #define TC2_IDACMUX ADS_IDAC2_OFF | ADS_IDAC1_OFF // IDAC1 off, IDAC2 off #define TC2_INT_VREF INT_VREF /********************************************************************************/ /* * @name Thermocouple Connections (Figure 2-4 (pag 20) de SBAA274A) * * AIN10 <- AINP Thermocouple * AIN9 <- AINN Thermocouple * */ //el tercer thermocouple no puede llevar bias, porque la seleccion del bias llega hasta AIN5 #define TC3_VBIAS VBIAS_DEFAULT #define TC3_INPUT_MUX ADS_N_AIN9 | ADS_P_AIN10 // MuxN = Ain9, MuxP = Ain10 for Thermocouple #define TC3_PGA ADS_PGA_ENABLED | ADS_GAIN_2 // PGA enabled, PGA gain = 2X #define TC3_DATARATE ADS_GLOBALCHOP | ADS_CONVMODE_CONT | ADS_FILTERTYPE_LL | ADS_DR_20 // Continous conversion, low latency filter, 20 SPS rate #define TC3_REF_SEL ADS_REFP_BYP_DISABLE | ADS_REFN_BYP_DISABLE | ADS_REFSEL_INT | ADS_REFINT_ON_ALWAYS // RefN Enabled, RefP0 and RefN0 selected, Int Ref always on #define TC3_IDACMAG ADS_IDACMAG_OFF // IDAC Mag off #define TC3_IDACMUX ADS_IDAC2_OFF | ADS_IDAC1_OFF // IDAC1 off, IDAC2 off #define TC3_INT_VREF INT_VREF /********************************************************************************/ /* * @name Thermistor Connections (Figure 19 of ADS114S08 EVM User's Guide) on J8 * * REFP0 <- VREF * REFN0 <- GND * AIN8 <- AINP * AIN9 <- AINN * */ #define THERMISTOR_VBIAS VBIAS_DEFAULT #define THERMISTOR_INPUT_MUX ADS_P_AIN8 | ADS_N_AIN9 // MuxP = Ain8, MuxN = Ain9 #define THERMISTOR_WIRE_PGA ADS_PGA_ENABLED | ADS_GAIN_1 // PGA enabled, PGA gain = 1X #define THERMISTOR_WIRE_DATARATE ADS_CONVMODE_CONT | ADS_FILTERTYPE_LL | ADS_DR_20 // Continous conversion, low latency filter, 20 SPS rate #define THERMISTOR_WIRE_REF_SEL ADS_REFN_BYP_ENABLE | ADS_REFSEL_INT | ADS_REFINT_ON_ALWAYS // Internal Ref, Int Ref always on #define THERMISTOR_WIRE_IDACMAG ADS_IDACMAG_OFF // IDAC Mag off #define THERMISTOR_WIRE_IDACMUX ADS_IDAC2_OFF | ADS_IDAC1_OFF // IDAC1 off, IDAC2 off #define THERMISTOR_VREF INT_VREF #define THERMISTOR_RBIAS 2959.0 /********************************************************************************/ /* * @name 4-20ma Connections * * REFP0 <- VREF * REFN0 <- GND * AIN8 <- AINP * AIN9 <- AINN * */ //CH1 #define AIN_4_20MA_CH1_INPUT_MUX ADS_P_AIN0 | ADS_N_AINCOM // MuxP = Ain0, MuxN = Aincom //CH2 #define AIN_4_20MA_CH2_INPUT_MUX ADS_P_AIN1 | ADS_N_AINCOM // MuxP = Ain1, MuxN = Aincom //CH3 #define AIN_4_20MA_CH3_INPUT_MUX ADS_P_AIN2 | ADS_N_AINCOM // MuxP = Ain2, MuxN = Aincom //CH4 #define AIN_4_20MA_CH4_INPUT_MUX ADS_P_AIN3 | ADS_N_AINCOM // MuxP = Ain3, MuxN = Aincom //CH5 #define AIN_4_20MA_CH5_INPUT_MUX ADS_P_AIN4 | ADS_N_AINCOM // MuxP = Ain4, MuxN = Aincom //CH6 #define AIN_4_20MA_CH6_INPUT_MUX ADS_P_AIN5 | ADS_N_AINCOM // MuxP = Ain5, MuxN = Aincom //CH7 #define AIN_4_20MA_CH7_INPUT_MUX ADS_P_AIN6 | ADS_N_AINCOM // MuxP = Ain6, MuxN = Aincom //CH8 #define AIN_4_20MA_CH8_INPUT_MUX ADS_P_AIN7 | ADS_N_AINCOM // MuxP = Ain7, MuxN = Aincom //CH9 #define AIN_4_20MA_CH9_INPUT_MUX ADS_P_AIN8 | ADS_N_AINCOM // MuxP = Ain8, MuxN = Aincom //CH10 #define AIN_4_20MA_CH10_INPUT_MUX ADS_P_AIN9 | ADS_N_AINCOM // MuxP = Ain9, MuxN = Aincom //GENERIC DEFINES FOR 4-20MA MEASUREMENT TODO JAGI #define AIN_4_20MA_VBIAS VBIAS_DEFAULT #define AIN_4_20MA_PGA ADS_PGA_ENABLED | ADS_GAIN_4 // PGA enabled, PGA gain = 4X #define AIN_4_20MA_DATARATE ADS_CONVMODE_CONT | ADS_FILTERTYPE_LL | ADS_DR_20 // Continous conversion, low latency filter, 20 SPS rate #define AIN_4_20MA_REF_SEL ADS_REFP_BYP_DISABLE | ADS_REFSEL_INT | ADS_REFINT_ON_ALWAYS // RefP and RefN Disable, Internal Ref selected, Internal Ref always on #define AIN_4_20MA_IDACMAG ADS_IDACMAG_OFF // IDAC Mag off #define AIN_4_20MA_IDACMUX ADS_IDAC2_OFF | ADS_IDAC1_OFF // IDACS off #define AIN_4_20MA_INT_VREF INT_VREF #endif