----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 12/09/2025 01:00:19 PM
-- Design Name: 
-- Module Name: ads9219_controller - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity ads9219_controller is
    port (
        sysclk_p : in std_logic;
        sysclk_n : in std_logic;
        -- ADS9219 interface
        i_fclk_p : in std_logic;
        i_fclk_m : in std_logic;
        i_dclk_p : in std_logic;
        i_dclk_m : in std_logic;
        i_douta_p : in std_logic;
        i_douta_m : in std_logic;
        i_doutb_p : in std_logic;
        i_doutb_m : in std_logic;

        --
        o_smpl_clk_p : out std_logic;
        -- o_smpl_clk_m : out std_logic; -- grounded for single-ended clock
        o_smpl_sync : out std_logic;
--        o_pwdn_n : out std_logic;
        o_reset_n : out std_logic;
        -- ADS9219 config interface
        o_cs_n : out std_logic;
        o_spi_en : out std_logic;
        o_spi_sclk : out std_logic;
        o_spi_sdi : out std_logic;
        i_spi_sdo : in std_logic             
    );
end ads9219_controller;

architecture Behavioral of ads9219_controller is

    signal dclk_se, dclk_buf : std_logic;
    signal douta_se : std_logic;
    signal doutb_se : std_logic;
    signal fclk_se : std_logic;

    signal douta_re : std_logic;
    signal douta_fe : std_logic;

    component clk_wiz_0
        port (-- Clock in ports
            -- Clock out ports
            clk_out1 : out std_logic;
            clk_out2 : out std_logic;
            -- Status and control signals
            locked : out std_logic;
            clk_in1_p : in std_logic;
            clk_in1_n : in std_logic
        );
    end component;

    signal clk_200mhz : std_logic;
    signal clk_10mhz : std_logic;
    signal clk_locked : std_logic;

    attribute MARK_DEBUG : string;
    attribute MARK_DEBUG of dclk_se : signal is "TRUE";
    attribute MARK_DEBUG of fclk_se : signal is "TRUE";
    attribute MARK_DEBUG of douta_se : signal is "TRUE";
    attribute MARK_DEBUG of douta_re : signal is "TRUE";
    attribute MARK_DEBUG of douta_fe : signal is "TRUE";
    attribute MARK_DEBUG of clk_10mhz : signal is "TRUE";

-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------

    clk_gen : clk_wiz_0
    port map(
        -- Clock out ports  
        clk_out1 => clk_200mhz,
        clk_out2 => clk_10mhz,
        -- Status and control signals                
        locked => clk_locked,
        -- Clock in ports
        clk_in1_p => sysclk_p,
        clk_in1_n => sysclk_n
    );

    -- IBUFDS: Differential Input Buffer
    -- 7 Series
    -- Xilinx HDL Language Template, version 2023.1
    DCLK_IBUFDS_INST : IBUFDS
    generic map(
        DIFF_TERM => TRUE, -- Differential Termination
        IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
        IOSTANDARD => "LVDS_25")
    port map(
        O => dclk_se, -- Buffer output
        I => i_dclk_p, -- Diff_p buffer input (connect directly to top-level port)
        IB => i_dclk_m -- Diff_n buffer input (connect directly to top-level port)
    );
    -- End of IBUFDS_inst instantiation

    -- IBUFDS: Differential Input Buffer
    -- 7 Series
    -- Xilinx HDL Language Template, version 2023.1
    FCLK_IBUFDS_INST : IBUFDS
    generic map(
        DIFF_TERM => TRUE, -- Differential Termination
        IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
        IOSTANDARD => "LVDS_25")
    port map(
        O => fclk_se, -- Buffer output
        I => i_fclk_p, -- Diff_p buffer input (connect directly to top-level port)
        IB => i_fclk_m -- Diff_n buffer input (connect directly to top-level port)
    );
    -- End of IBUFDS_inst instantiation

    -- IBUFDS: Differential Input Buffer
    -- 7 Series
    -- Xilinx HDL Language Template, version 2023.1
    DOUTA_IBUFDS_INST : IBUFDS
    generic map(
        DIFF_TERM => TRUE, -- Differential Termination
        IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
        IOSTANDARD => "LVDS_25")
    port map(
        O => douta_se, -- Buffer output
        I => i_douta_p, -- Diff_p buffer input (connect directly to top-level port)
        IB => i_douta_m -- Diff_n buffer input (connect directly to top-level port)
    );
    -- End of IBUFDS_inst instantiation

    -- IBUFDS: Differential Input Buffer
    -- 7 Series
    -- Xilinx HDL Language Template, version 2023.1
    DOUTB_IBUFDS_INST : IBUFDS
    generic map(
        DIFF_TERM => TRUE, -- Differential Termination
        IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
        IOSTANDARD => "LVDS_25")
    port map(
        O => doutb_se, -- Buffer output
        I => i_doutb_p, -- Diff_p buffer input (connect directly to top-level port)
        IB => i_doutb_m -- Diff_n buffer input (connect directly to top-level port)
    );
    -- End of IBUFDS_inst instantiation

    DCLK_BUFG_INST : BUFG
    port map(
        I => dclk_se,
        O => dclk_buf
    );

    -- IDDR: Double Data Rate Input Register with Set, Reset
    -- and Clock Enable.
    -- 7 Series
    -- Xilinx HDL Language Template, version 2023.1
    DOUTA_IDDR_INST : IDDR
    generic map(
        DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE"
        -- or "SAME_EDGE_PIPELINED"
        INIT_Q1 => '0', -- Initial value of Q1: '0' or '1'
        INIT_Q2 => '0', -- Initial value of Q2: '0' or '1'
        SRTYPE => "SYNC") -- Set/Reset type: "SYNC" or "ASYNC"
    port map(
        Q1 => douta_re, -- 1-bit output for positive edge of clock
        Q2 => douta_fe, -- 1-bit output for negative edge of clock
        C => dclk_buf, -- 1-bit clock input
        CE => '1', -- 1-bit clock enable input
        D => douta_se, -- 1-bit DDR data input
        R => '0', -- 1-bit reset
        S => '0' -- 1-bit set
    );
    -- End of IDDR_inst instantiation

    -- Assing output
    o_smpl_clk_p <= clk_10mhz;
    o_reset_n <= '1';
    
end Behavioral;