# SYSCLK set_property IOSTANDARD LVDS_25 [get_ports sysclk_p] set_property PACKAGE_PIN R3 [get_ports sysclk_p] set_property PACKAGE_PIN P3 [get_ports sysclk_n] set_property IOSTANDARD LVDS_25 [get_ports sysclk_n] # LVDS Frame Clock set_property IOSTANDARD LVDS_25 [get_ports i_fclk_p] set_property PACKAGE_PIN E17 [get_ports i_fclk_p] set_property PACKAGE_PIN E18 [get_ports i_fclk_m] set_property IOSTANDARD LVDS_25 [get_ports i_fclk_m] set_property DIFF_TERM TRUE [get_ports i_fclk_p] # Set for Single-Ended Sample Clock set_property PACKAGE_PIN J24 [get_ports o_smpl_clk_p] set_property IOSTANDARD LVCMOS18 [get_ports o_smpl_clk_p] #set_property PACKAGE_PIN H24 [get_ports FMC1_HPC_LA26_N] #set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA26_N] # LVDS Data clock set_property IOSTANDARD LVDS_25 [get_ports i_dclk_p] set_property PACKAGE_PIN D18 [get_ports i_dclk_p] set_property PACKAGE_PIN C18 [get_ports i_dclk_m] set_property IOSTANDARD LVDS_25 [get_ports i_dclk_m] set_property DIFF_TERM TRUE [get_ports i_dclk_p] # RESET_N set_property PACKAGE_PIN G22 [get_ports o_reset_n] set_property IOSTANDARD LVCMOS18 [get_ports o_reset_n] # SPI SDO set_property PACKAGE_PIN G24 [get_ports i_spi_sdo] set_property IOSTANDARD LVCMOS18 [get_ports i_spi_sdo] # SPI SDI set_property PACKAGE_PIN E26 [get_ports o_spi_sdi] set_property IOSTANDARD LVCMOS18 [get_ports o_spi_sdi] # CS_N set_property PACKAGE_PIN G25 [get_ports o_cs_n] set_property IOSTANDARD LVCMOS18 [get_ports o_cs_n] # DOUT A set_property IOSTANDARD LVDS_25 [get_ports i_douta_p] set_property PACKAGE_PIN H14 [get_ports i_douta_p] set_property PACKAGE_PIN H15 [get_ports i_douta_m] set_property IOSTANDARD LVDS_25 [get_ports i_douta_m] set_property DIFF_TERM TRUE [get_ports i_douta_p] # DOUT B set_property IOSTANDARD LVDS_25 [get_ports i_doutb_p] set_property PACKAGE_PIN F18 [get_ports i_doutb_p] set_property PACKAGE_PIN F19 [get_ports i_doutb_m] set_property IOSTANDARD LVDS_25 [get_ports i_doutb_m] set_property DIFF_TERM TRUE [get_ports i_doutb_p] # SPI EN set_property PACKAGE_PIN K22 [get_ports o_spi_en] set_property IOSTANDARD LVCMOS18 [get_ports o_spi_en] # SPI SCLK set_property PACKAGE_PIN E25 [get_ports o_spi_sclk] set_property IOSTANDARD LVCMOS18 [get_ports o_spi_sclk] # SMPL SYNC set_property PACKAGE_PIN H26 [get_ports o_smpl_sync] set_property IOSTANDARD LVCMOS18 [get_ports o_smpl_sync] create_debug_core u_ila_0 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0] set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property port_width 1 [get_debug_ports u_ila_0/clk] connect_debug_port u_ila_0/clk [get_nets [list clk_gen/inst/clk_out1]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] set_property port_width 1 [get_debug_ports u_ila_0/probe0] connect_debug_port u_ila_0/probe0 [get_nets [list dclk_se]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] set_property port_width 1 [get_debug_ports u_ila_0/probe1] connect_debug_port u_ila_0/probe1 [get_nets [list douta_fe]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] set_property port_width 1 [get_debug_ports u_ila_0/probe2] connect_debug_port u_ila_0/probe2 [get_nets [list douta_re]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] set_property port_width 1 [get_debug_ports u_ila_0/probe3] connect_debug_port u_ila_0/probe3 [get_nets [list douta_se]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] set_property port_width 1 [get_debug_ports u_ila_0/probe4] connect_debug_port u_ila_0/probe4 [get_nets [list fclk_se]] set_property C_CLK_INPUT_FREQ_HZ 200000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] connect_debug_port dbg_hub/clk [get_nets u_ila_0_clk_out1] set_property CONFIG_MODE SPIx4 [current_design] set_property CFGBVS VCCO [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]