#------------------------------------------
# TIMING CONSTRAINTS
#------------------------------------------
# Set Reference to 192MHz by default
create_clock -period 5.208 -name jesd204_dac_refclk [get_ports refclk0p]


# Set DRP Clock to 192.0MHz
create_clock -period 5.208 -name jesd204_dac_drpclk [get_ports drpclkp]

# Set AXI-Lite Clock to 100.0MHz by default
#create_clock -period 10.000 -name jesd204_dac_axi_aclk [get_ports s_axi_aclk]

set_property PACKAGE_PIN AG14 [get_ports led0]
set_property IOSTANDARD LVCMOS33 [get_ports led0]
set_property PACKAGE_PIN AF13 [get_ports led1]
set_property IOSTANDARD LVCMOS33 [get_ports led1]
set_property PACKAGE_PIN AE13 [get_ports led2]
set_property IOSTANDARD LVCMOS33 [get_ports led2]
set_property PACKAGE_PIN AJ14     [get_ports led3] 
set_property IOSTANDARD  LVCMOS33 [get_ports led3] 

set_property PACKAGE_PIN AE14 [get_ports sw_e]
set_property IOSTANDARD LVCMOS33 [get_ports sw_e]
set_property PACKAGE_PIN AG13 [get_ports sw_c]
set_property IOSTANDARD LVCMOS33 [get_ports sw_c]

# refclk
set_property -dict {PACKAGE_PIN G8} [get_ports refclk0p]
set_property -dict {PACKAGE_PIN G7} [get_ports refclk0n]

set_property PACKAGE_PIN Y4 [get_ports drpclkp]
set_property IOSTANDARD LVDS [get_ports drpclkp]
set_property DIFF_TERM_ADV TERM_100 [get_ports drpclkp]

# sync
set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports tx_sync]

# sysref
set_property PACKAGE_PIN Y2 [get_ports tx_sysrefp]
set_property IOSTANDARD LVDS [get_ports tx_sysrefp]
set_property DIFF_TERM_ADV TERM_100 [get_ports tx_sysrefp]


# GTH4's
# Lanes [0-3] - Bank 229
set_property LOC GTHE4_CHANNEL_X1Y8 [get_cells -hier -filter {name =~ i_jesd204_dac_support_block/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_dac_phy_gt_i/inst/gen_gtwizard_gthe4_top.jesd204_dac_phy_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y11 [get_cells -hier -filter {name =~ i_jesd204_dac_support_block/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_dac_phy_gt_i/inst/gen_gtwizard_gthe4_top.jesd204_dac_phy_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y9 [get_cells -hier -filter {name =~ i_jesd204_dac_support_block/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_dac_phy_gt_i/inst/gen_gtwizard_gthe4_top.jesd204_dac_phy_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y10 [get_cells -hier -filter {name =~ i_jesd204_dac_support_block/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_dac_phy_gt_i/inst/gen_gtwizard_gthe4_top.jesd204_dac_phy_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[1].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST}]

# Lanes [4-7] - Bank 228
set_property LOC GTHE4_CHANNEL_X1Y6 [get_cells -hier -filter {name =~ i_jesd204_dac_support_block/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_dac_phy_gt_i/inst/gen_gtwizard_gthe4_top.jesd204_dac_phy_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[2].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y7 [get_cells -hier -filter {name =~ i_jesd204_dac_support_block/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_dac_phy_gt_i/inst/gen_gtwizard_gthe4_top.jesd204_dac_phy_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[2].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[1].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y4 [get_cells -hier -filter {name =~ i_jesd204_dac_support_block/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_dac_phy_gt_i/inst/gen_gtwizard_gthe4_top.jesd204_dac_phy_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[2].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[2].GTHE4_CHANNEL_PRIM_INST}]
set_property LOC GTHE4_CHANNEL_X1Y5 [get_cells -hier -filter {name =~ i_jesd204_dac_support_block/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_dac_phy_gt_i/inst/gen_gtwizard_gthe4_top.jesd204_dac_phy_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[2].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST}]


