module jesd204_dac_sig_gen (
  input         clk,
  input         rst_n,

  //Channel 0
  output [7:0] lane0_a0h,
  output [7:0] lane0_a2h,
  output [7:0] lane0_a4h,
  output [7:0] lane0_a6h,
  //Channel 1
  output [7:0] lane1_a0l,
  output [7:0] lane1_a2l,
  output [7:0] lane1_a4l,
  output [7:0] lane1_a6l,
  //Channel 2
  output [7:0] lane2_a1h,
  output [7:0] lane2_a3h,
  output [7:0] lane2_a5h,
  output [7:0] lane2_a7h,
  //Channel 3
  output [7:0] lane3_a1l,
  output [7:0] lane3_a3l,
  output [7:0] lane3_a5l,
  output [7:0] lane3_a7l,
  //Channel 4
  output [7:0] lane4_b0h,
  output [7:0] lane4_b2h,
  output [7:0] lane4_b4h,
  output [7:0] lane4_b6h,
  //Channel 5
  output [7:0] lane5_b0l,
  output [7:0] lane5_b2l,
  output [7:0] lane5_b4l,
  output [7:0] lane5_b6l,
  //Channel 6
  output [7:0] lane6_b1h,
  output [7:0] lane6_b3h,
  output [7:0] lane6_b5h,
  output [7:0] lane6_b7h,
  //Channel 7
  output [7:0] lane7_b1l,
  output [7:0] lane7_b3l,
  output [7:0] lane7_b5l,
  output [7:0] lane7_b7l,
  input         ready_in
);

wire [15:0] sine_lut64_16bit [63:0];
`include "sine_lut64_16bit.vh"

  //Channel 0
  reg [7:0] lane0_a0h_reg;
  reg [7:0] lane0_a2h_reg;
  reg [7:0] lane0_a4h_reg;
  reg [7:0] lane0_a6h_reg;
  reg  [5:0] index0 = 0;
  //Channel 1
  reg [7:0] lane1_a0l_reg;
  reg [7:0] lane1_a2l_reg;
  reg [7:0] lane1_a4l_reg;
  reg [7:0] lane1_a6l_reg;
  reg  [5:0] index1 = 0;
  //Channel 2
  reg [7:0] lane2_a1h_reg;
  reg [7:0] lane2_a3h_reg;
  reg [7:0] lane2_a5h_reg;
  reg [7:0] lane2_a7h_reg;
  reg  [5:0] index2 = 0;
  //Channel 3
  reg [7:0] lane3_a1l_reg;
  reg [7:0] lane3_a3l_reg;
  reg [7:0] lane3_a5l_reg;
  reg [7:0] lane3_a7l_reg;
  reg  [5:0] index3 = 0;
  //Channel 4
  reg [7:0] lane4_b0h_reg;
  reg [7:0] lane4_b2h_reg;
  reg [7:0] lane4_b4h_reg;
  reg [7:0] lane4_b6h_reg;
  reg  [5:0] index4 = 0;
  //Channel 5
  reg [7:0] lane5_b0l_reg;
  reg [7:0] lane5_b2l_reg;
  reg [7:0] lane5_b4l_reg;
  reg [7:0] lane5_b6l_reg;
  reg  [5:0] index5 = 0;
  //Channel 6
  reg [7:0] lane6_b1h_reg;
  reg [7:0] lane6_b3h_reg;
  reg [7:0] lane6_b5h_reg;
  reg [7:0] lane6_b7h_reg;
  reg  [5:0] index6 = 0;
  //Channel 7
  reg [7:0] lane7_b1l_reg;
  reg [7:0] lane7_b3l_reg;
  reg [7:0] lane7_b5l_reg;
  reg [7:0] lane7_b7l_reg;
  reg  [5:0] index7 = 0;

always @(posedge clk, negedge rst_n)
begin
  if(!rst_n)
  begin
    //Channel 0
    index0 <= 0;
    //Channel 1
    index1 <= 0;
    //Channel 2
    index2 <= 0;
    //Channel 3
    index3 <= 0;
    //Channel 4
    index4 <= 0;
    //Channel 5
    index5 <= 0;
    //Channel 6
    index6 <= 0;
    //Channel 7
    index7 <= 0;
  end
  else
  begin
    if(ready_in)
        begin
// same 24MHz sine wave for DAC A and B
        //Channel 0
        lane0_a0h_reg <= { sine_lut64_16bit[index0][15:8] };
        lane0_a2h_reg <= { sine_lut64_16bit[index0+2][15:8] };
        lane0_a4h_reg <= { sine_lut64_16bit[index0+4][15:8] };
        lane0_a6h_reg <= { sine_lut64_16bit[index0+6][15:8] };
        index0 <= index0+8;
        //Channel 1
        lane1_a0l_reg <= { sine_lut64_16bit[index1][7:0] };
        lane1_a2l_reg <= { sine_lut64_16bit[index1+2][7:0] };
        lane1_a4l_reg <= { sine_lut64_16bit[index1+4][7:0] };
        lane1_a6l_reg <= { sine_lut64_16bit[index1+6][7:0] };
        index1 <= index1+8;
        //Channel 2
        lane2_a1h_reg <= { sine_lut64_16bit[index2+1][15:8] };
        lane2_a3h_reg <= { sine_lut64_16bit[index2+3][15:8] };
        lane2_a5h_reg <= { sine_lut64_16bit[index2+5][15:8] };
        lane2_a7h_reg <= { sine_lut64_16bit[index2+7][15:8] };
        index2 <= index2+8;
        //Channel 3
        lane3_a1l_reg <= { sine_lut64_16bit[index3+1][7:0] };
        lane3_a3l_reg <= { sine_lut64_16bit[index3+3][7:0] };
        lane3_a5l_reg <= { sine_lut64_16bit[index3+5][7:0] };
        lane3_a7l_reg <= { sine_lut64_16bit[index3+7][7:0] };
        index3 <= index3+8;
        //Channel 4
        lane4_b0h_reg <= { sine_lut64_16bit[index4][15:8] };
        lane4_b2h_reg <= { sine_lut64_16bit[index4+2][15:8] };
        lane4_b4h_reg <= { sine_lut64_16bit[index4+4][15:8] };
        lane4_b6h_reg <= { sine_lut64_16bit[index4+6][15:8] };
        index4 <= index4+8;
        //Channel 5
        lane5_b0l_reg <= { sine_lut64_16bit[index5][7:0] };
        lane5_b2l_reg <= { sine_lut64_16bit[index5+2][7:0] };
        lane5_b4l_reg <= { sine_lut64_16bit[index5+4][7:0] };
        lane5_b6l_reg <= { sine_lut64_16bit[index5+6][7:0] };
        index5 <= index5+8;
        //Channel 6
        lane6_b1h_reg <= { sine_lut64_16bit[index6+1][15:8] };
        lane6_b3h_reg <= { sine_lut64_16bit[index6+3][15:8] };
        lane6_b5h_reg <= { sine_lut64_16bit[index6+5][15:8] };
        lane6_b7h_reg <= { sine_lut64_16bit[index6+7][15:8] };
        index6 <= index6+8;
        //Channel 7
        lane7_b1l_reg <= { sine_lut64_16bit[index7+1][7:0] };
        lane7_b3l_reg <= { sine_lut64_16bit[index7+3][7:0] };
        lane7_b5l_reg <= { sine_lut64_16bit[index7+5][7:0] };
        lane7_b7l_reg <= { sine_lut64_16bit[index7+7][7:0] };
        index7 <= index7+8;  
        end
//48MHz sine wave for DAC A, 192MHz square wave for DAC B
//        begin
//        //Channel 0
//        lane0_a0h_reg <= { sine_lut64_16bit[index0][15:8] };
//        lane0_a2h_reg <= { sine_lut64_16bit[index0+4][15:8] };
//        lane0_a4h_reg <= { sine_lut64_16bit[index0+8][15:8] };
//        lane0_a6h_reg <= { sine_lut64_16bit[index0+12][15:8] };
//        index0 <= index0+16;
//        //Channel 1
//        lane1_a0l_reg <= { sine_lut64_16bit[index1][7:0] };
//        lane1_a2l_reg <= { sine_lut64_16bit[index1+4][7:0] };
//        lane1_a4l_reg <= { sine_lut64_16bit[index1+8][7:0] };
//        lane1_a6l_reg <= { sine_lut64_16bit[index1+12][7:0] };
//        index1 <= index1+16;
//        //Channel 2
//        lane2_a1h_reg <= { sine_lut64_16bit[index2+2][15:8] };
//        lane2_a3h_reg <= { sine_lut64_16bit[index2+6][15:8] };
//        lane2_a5h_reg <= { sine_lut64_16bit[index2+10][15:8] };
//        lane2_a7h_reg <= { sine_lut64_16bit[index2+14][15:8] };
//        index2 <= index2+16;
//        //Channel 3
//        lane3_a1l_reg <= { sine_lut64_16bit[index3+2][7:0] };
//        lane3_a3l_reg <= { sine_lut64_16bit[index3+6][7:0] };
//        lane3_a5l_reg <= { sine_lut64_16bit[index3+10][7:0] };
//        lane3_a7l_reg <= { sine_lut64_16bit[index3+14][7:0] };
//        index3 <= index3+16;
//        //Channel 4
//        lane4_b0h_reg <= 0;
//        lane4_b2h_reg <= 0;
//        lane4_b4h_reg <= 8'h7F;
//        lane4_b6h_reg <= 8'h7F;
//        index4 <= index4+8;
//        //Channel 5
//        lane5_b0l_reg <= 0;
//        lane5_b2l_reg <= 0;
//        lane5_b4l_reg <= 8'hFF;
//        lane5_b6l_reg <= 8'hFF;
//        index5 <= index5+8;
//        //Channel 6
//        lane6_b1h_reg <= 0;
//        lane6_b3h_reg <= 0;
//        lane6_b5h_reg <= 8'h7F;
//        lane6_b7h_reg <= 8'h7F;
//        index6 <= index6+8;
//        //Channel 7
//        lane7_b1l_reg <= 0;
//        lane7_b3l_reg <= 0;
//        lane7_b5l_reg <= 8'hFF;
//        lane7_b7l_reg <= 8'hFF;
//        index7 <= index7+8;  
//        end
  end
end//always

//assign the registered samples and control bits to the outputs
//Channel 0
assign lane0_a0h = lane0_a0h_reg;
assign lane0_a2h = lane0_a2h_reg;
assign lane0_a4h = lane0_a4h_reg;
assign lane0_a6h = lane0_a6h_reg;
//Channel 1
assign lane1_a0l = lane1_a0l_reg;
assign lane1_a2l = lane1_a2l_reg;
assign lane1_a4l = lane1_a4l_reg;
assign lane1_a6l = lane1_a6l_reg;
//Channel 2
assign lane2_a1h = lane2_a1h_reg;
assign lane2_a3h = lane2_a3h_reg;
assign lane2_a5h = lane2_a5h_reg;
assign lane2_a7h = lane2_a7h_reg;
//Channel 3
assign lane3_a1l = lane3_a1l_reg;
assign lane3_a3l = lane3_a3l_reg;
assign lane3_a5l = lane3_a5l_reg;
assign lane3_a7l = lane3_a7l_reg;
//Channel 4
assign lane4_b0h = lane4_b0h_reg;
assign lane4_b2h = lane4_b2h_reg;
assign lane4_b4h = lane4_b4h_reg;
assign lane4_b6h = lane4_b6h_reg;
//Channel 5
assign lane5_b0l = lane5_b0l_reg;
assign lane5_b2l = lane5_b2l_reg;
assign lane5_b4l = lane5_b4l_reg;
assign lane5_b6l = lane5_b6l_reg;
//Channel 6
assign lane6_b1h = lane6_b1h_reg;
assign lane6_b3h = lane6_b3h_reg;
assign lane6_b5h = lane6_b5h_reg;
assign lane6_b7h = lane6_b7h_reg;
//Channel 7
assign lane7_b1l = lane7_b1l_reg;
assign lane7_b3l = lane7_b3l_reg;
assign lane7_b5l = lane7_b5l_reg;
assign lane7_b7l = lane7_b7l_reg;

endmodule
