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Please refer to the applicable // agreement for further details. //Naming convention- All active low signals are denoted with _n and registered signals are denoted with _r in their names `timescale 1ps / 1ps module jesd204b_ed #( parameter L = 8, // Number of lanes per converter device S = 20 // Number of transmitter samples per converter per frame ) ( input device_clk, //Device clock- Reference clock from ADC input mgmt_clk, //Management clock - 100MHz input global_rst_n, //Active low asynchronous global reset input rx_sysref, //Input SYSREF input [L-1:0] rx_serial_data, //Serial Input from ADC output wire rx_altsyncn, //Alternate SYNC- Used by ADC12DJxx00 output wire rx_sync_n, //SYNC output of JESDIP- Most TI ADCs use this SYNC //LED Signals output reg link_clk_led, //LED to indicate link clock. blinks at 10Hz output reg rx_altsyncn_led, //LED to indicate SYNC. LED is ON if SYNC is lost //Signals connected to output pins so that logic is not deleted by Fitter output reg rx_dataout_reg, output reg rx_somfout, output reg rx_validout ); //Declarations for JESDIP output reg jesd204_rx_link_valid_reg; reg [L*32-1:0] jesd204_rx_link_data_reg; reg rx_somf_reg; wire [S*12-1:0] rx_dataout; wire [5-1:0] rx_csr_l; wire [8-1:0] rx_csr_f; wire [8-1:0] rx_csr_m; wire [5-1:0] rx_csr_n; wire [5-1:0] rx_csr_k; wire [L*32-1:0] jesd204_rx_link_data; wire jesd204_rx_link_valid; wire [5-1:0] rx_csr_s; wire [L-1:0] rx_csr_lane_powerdown; wire [4-1:0] rx_csr_testmode; wire dev_lane_aligned; wire rx_dev_sync_n; wire [3:0] rx_sof, rx_somf; //Declarations for Transceiver Reset Controller wire [L-1:0] rx_cal_busy; wire [L-1:0] rx_ready; wire [L-1:0] rx_analogreset; wire [L-1:0] rx_digitalreset; //Interface signals between JESDPHY and JESD Base reg [L*4*8-1:0] serdes_data_in; reg [L-1:0] serdes_data_valid; reg [L*4-1:0] serdes_Kdata_in; reg [L*4-1:0] serdes_errDetect_in; reg [L*4-1:0] serdes_disperr_in; wire [L*4*8-1:0] rx_parallel_data; wire [L-1:0] rx_parallel_data_valid; wire [L*4-1:0] rx_disperr; wire [L*4-1:0] rx_errdetect; wire [L*4-1:0] rx_datak; wire [L-1:0] rx_std_pcfifo_empty; wire [L-1:0] rx_std_pcfifo_full; wire pll_ref_clk; wire [L-1:0] rx_is_lockedtodata; //SYSREF Signals reg jesd_sysref_dly; wire jesd_sysref_gapped; //Debug Signals reg [31:0] link_clk_cntr; parameter LINK_CLK_COUNT= 32'd30000000; //300 MHz reduced to 10 Hz //Assigning SYNC output assign rx_altsyncn = rx_dev_sync_n; assign rx_sync_n = rx_dev_sync_n; assign rx_altsyncn_led = ~(rx_dev_sync_n); //LED is ON if SYNC is lost // tie global_rst_n to 1.8 V //wire global_rst_n = 1'b1; always @(posedge rx_link_clk) begin serdes_data_in <= rx_parallel_data ; serdes_data_valid <= rx_parallel_data_valid ; serdes_Kdata_in <= rx_datak ; // K char serdes_errDetect_in <= rx_errdetect ; // errdetect serdes_disperr_in <= rx_disperr ; // Disperr end //GAPPED PERIODIC SYSREF assign jesd_sysref_gapped = (!jesd_sysref_dly) & rx_sysref; always @(posedge rx_link_clk or negedge rx_link_clk_rstn) begin if (!rx_link_clk_rstn) jesd_sysref_dly <= 1'b0; else jesd_sysref_dly <= rx_sysref; end //Reset and clock generator module jesd_clk_rst_gen jesd_clk_rst_gen0( .device_clk (device_clk), //Device clock .rstn (global_rst_n), //Global reset .rx_is_lockedtodata (rx_is_lockedtodata), //Rx locked signal from PHY .rx_ready (rx_ready), //ready signal from reset controller .rx_pll_ref_clk (pll_ref_clk), //PLL Reference clock- Device clock .phy_rst (phy_rst), //PHY reset signal- reset synchronous with device clock .rx_link_clk (rx_link_clk), //Link Clock .rx_link_clk_rstn (rx_link_clk_rstn), //Link clock reset .pll_locked (core_pll_locked) //PLL locked signal ); //JESD PHY Instantiation xcvr_jesd_rx i0_xcvr_jesd_rx ( .csr_bit_reversal (1'd0), // csr_bit_reversal.export .csr_byte_reversal (1'd0), // csr_byte_reversal.export .csr_lane_polarity (8'hF0), // csr_lane_polarity.export- Device sends inveretd data on lanes[7:4] .csr_lane_powerdown (8'd0), // csr_lane_powerdown.export .jesd204_rx_pcs_data (rx_parallel_data[L*4*8-1:0]), // jesd204_rx_pcs_data.export .jesd204_rx_pcs_data_valid (rx_parallel_data_valid[L-1:0]), // jesd204_rx_pcs_data_valid.export .jesd204_rx_pcs_disperr (rx_disperr[L*4-1:0]), // jesd204_rx_pcs_disperr.export .jesd204_rx_pcs_errdetect (rx_errdetect[L*4-1:0]), // jesd204_rx_pcs_errdetect.export .jesd204_rx_pcs_kchar_data (rx_datak[L*4-1:0]), // jesd204_rx_pcs_kchar_data.export .patternalign_en (8'hFF), // patternalign_en.export .phy_csr_rx_pcfifo_empty (rx_std_pcfifo_empty[L-1:0]), // phy_csr_rx_pcfifo_empty .phy_csr_rx_pcfifo_full (rx_std_pcfifo_full[L-1:0]), // phy_csr_rx_pcfifo_full.export .pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk .rx_analogreset (rx_analogreset[L-1:0]), // rx_analogreset.rx_analogreset .rx_cal_busy (rx_cal_busy[L-1:0]), // rx_cal_busy.rx_cal_busy .rx_digitalreset (rx_digitalreset[L-1:0]), // rx_digitalreset.rx_digitalreset .rx_islockedtodata (rx_is_lockedtodata[L-1:0]), // rx_is_lockedtodata .rx_serial_data (rx_serial_data[L-1:0]), // rx_serial_data.rx_serial_data .rxlink_clk ({L{rx_link_clk}}), // rxlink_clk.clk .rxlink_rst_n_reset_n (rx_link_clk_rstn), // rxlink_clk reset .rxphy_clk () // rxphy_clk.export ); //Reset controller instantiation xcvr_rst_rx xcvr_rst_rx_inst1( .clock(mgmt_clk), // clock.clk .reset(~global_rst_n), // reset.reset .rx_analogreset(rx_analogreset), // rx_analogreset.rx_analogreset .rx_digitalreset(rx_digitalreset), // rx_digitalreset.rx_digitalreset .rx_ready(rx_ready), // rx_ready.rx_ready .rx_is_lockedtodata(rx_is_lockedtodata), // rx_is_lockedtodata.rx_is_lockedtodata .rx_cal_busy (rx_cal_busy) // rx_cal_busy.rx_cal_busy ); //JESD Base IP for RX //JESD Avalon slave is not used. All the slave signals are made inactive altera_jesd2041 u_jesd204 ( .rxlink_clk (rx_link_clk), .rxlink_rst_n_reset_n (rx_link_clk_rstn), .jesd204_rx_avs_clk (mgmt_clk), .jesd204_rx_avs_rst_n (global_rst_n), .jesd204_rx_avs_chipselect (1'b1), .jesd204_rx_avs_address (8'b0), .jesd204_rx_avs_read (1'b0), .jesd204_rx_avs_readdata (), .jesd204_rx_avs_waitrequest (), .jesd204_rx_avs_write (1'b0), .jesd204_rx_avs_writedata (32'b0), .jesd204_rx_link_data (jesd204_rx_link_data[255:0]), .jesd204_rx_link_valid (jesd204_rx_link_valid), .jesd204_rx_link_ready (1'b1), .jesd204_rx_dlb_data (), .jesd204_rx_dlb_data_valid (), .jesd204_rx_dlb_kchar_data (), .jesd204_rx_dlb_errdetect (), .jesd204_rx_dlb_disperr (), .alldev_lane_aligned (dev_lane_aligned), .sysref (jesd_sysref_gapped), .jesd204_rx_frame_error (jesd204_rx_frame_error), .jesd204_rx_int (jesd204_rx_int), .dev_lane_aligned (dev_lane_aligned), .dev_sync_n (rx_dev_sync_n), .csr_rx_testmode (), .sof (rx_sof), .somf (rx_somf[3:0]), .csr_f (rx_csr_f[7:0]), .csr_k (rx_csr_k[4:0]), .csr_l (rx_csr_l[4:0]), .csr_m (rx_csr_m[7:0]), .csr_n (rx_csr_n[4:0]), .csr_s (rx_csr_s[4:0]), .csr_cf (), .csr_cs (), .csr_hd (), .csr_np (), .csr_lane_powerdown (rx_csr_lane_powerdown[7:0]), .csr_lane_polarity (), .csr_bit_reversal (), .csr_byte_reversal (), .patternalign_en (), .rx_islockedtodata (rx_is_lockedtodata[7:0]), .rx_cal_busy (rx_cal_busy[7:0]), .jesd204_rx_pcs_data (serdes_data_in), //rx_parallel_data), .jesd204_rx_pcs_data_valid (serdes_data_valid), //rx_parallel_data_valid), .jesd204_rx_pcs_kchar_data (serdes_Kdata_in), //rx_datak), .jesd204_rx_pcs_errdetect (serdes_errDetect_in), //rx_errdetect), .jesd204_rx_pcs_disperr (serdes_disperr_in), //rx_disperr .phy_csr_rx_pcfifo_full (rx_std_pcfifo_full), .phy_csr_rx_pcfifo_empty (rx_std_pcfifo_empty) ); /////////////////////////////////////////////////////////////////////////////////////// // Transport Layer /////////////////////////////////////////////////////////////////////////////////////// //Registering IP outputs always @(posedge rx_link_clk or negedge rx_link_clk_rstn) begin if(!rx_link_clk_rstn) begin jesd204_rx_link_valid_reg <= 1'b0; jesd204_rx_link_data_reg <= 256'b0; rx_somf_reg <= 1'b0; end else begin jesd204_rx_link_valid_reg <= jesd204_rx_link_valid; jesd204_rx_link_data_reg <= jesd204_rx_link_data; rx_somf_reg <= rx_somf[3]; end end jesd_ed_transport jesd_transport0( //Input .rx_link_clk (rx_link_clk), //Link clock input .rx_link_clk_rstn (rx_link_clk_rstn), //Link clock reset .jesd204_rx_link_valid (jesd204_rx_link_valid_reg), //JESDIP link valid signal .jesd204_rx_link_data (jesd204_rx_link_data_reg), //JESDIP link dataout .somf (rx_somf_reg), //SOMF signal from JESDIP //output .rx_dataout (rx_dataout), //transport layer dataout- 20 samples per link clock .rx_validout (rx_validout), //transport layer valid signal .rx_somfout (rx_somfout) //valid SOMF, aligned with rx_dataout ); //LED Section //300MHz Link clock reduced to 10Hz and is given to led output always @(posedge rx_link_clk or negedge rx_link_clk_rstn) begin if(~rx_link_clk_rstn) link_clk_led <= 1'b0; else if (link_clk_cntr == (LINK_CLK_COUNT -1)) link_clk_led <= ~(link_clk_led); end always @(posedge rx_link_clk or negedge rx_link_clk_rstn) begin if(~rx_link_clk_rstn) link_clk_cntr <= {32{1'b0}}; else if (link_clk_cntr == (LINK_CLK_COUNT -1)) link_clk_cntr <= {32{1'b0}}; else link_clk_cntr <= link_clk_cntr + 1'b1; end //If any signal is created but not used in logic block and is not assigned as output, the fitter will delete the signal and it can't be viewed in Signal Tap //To prevent rx_dataout signals from deletion, ANDed all 240 bits and assigned to one output pin //User can delete this block if the transport layer signals are used somewhere else always @(posedge rx_link_clk or negedge rx_link_clk_rstn) begin if(~rx_link_clk_rstn) rx_dataout_reg <= 1'b0; else rx_dataout_reg <= &(rx_dataout[239:0]); end endmodule