From b287f7c7f2eca5ea52207e20d6a5a3dbcc7fdda8 Mon Sep 17 00:00:00 2001 From: Josiitaa RL Date: Wed, 27 Mar 2024 17:03:31 +0530 Subject: [PATCH 1/3] BIST Integration with SBL+BootApp --- packages/ti/boot/sbl/board/k3/sbl_main.c | 277 ++- packages/ti/boot/sbl/board/k3/sbl_main.h | 49 + packages/ti/boot/sbl/build/boot_app.mk | 29 + packages/ti/boot/sbl/build/sbl_img.mk | 35 + .../ti/boot/sbl/example/boot_app/bist/bist.c | 646 +++++++ .../ti/boot/sbl/example/boot_app/bist/bist.h | 78 + .../sbl/example/boot_app/bist/lbist_utils.c | 762 ++++++++ .../sbl/example/boot_app/bist/lbist_utils.h | 92 + .../sbl/example/boot_app/bist/pbist_utils.c | 1640 +++++++++++++++++ .../sbl/example/boot_app/bist/pbist_utils.h | 93 + .../sbl/example/boot_app/bist/power_seq.c | 176 ++ .../sbl/example/boot_app/bist/power_seq.h | 79 + .../bist/soc/j784s4/armv8_power_utils.c | 233 +++ .../bist/soc/j784s4/armv8_power_utils.h | 64 + .../boot_app/bist/soc/j784s4/bist_core_defs.c | 432 +++++ .../boot_app/bist/soc/j784s4/bist_core_defs.h | 176 ++ .../boot_app/bist/soc/j784s4/lbist_defs.c | 474 +++++ .../boot_app/bist/soc/j784s4/lbist_defs.h | 99 + .../boot_app/bist/soc/j784s4/pbist_defs.c | 1438 +++++++++++++++ .../boot_app/bist/soc/j784s4/pbist_defs.h | 118 ++ .../boot/sbl/example/boot_app/boot_app_main.c | 69 +- packages/ti/boot/sbl/sbl_component.mk | 1 + .../src/rm_pm_hal/pm/soc/j784s4/dmsc.c | 7 +- 23 files changed, 7061 insertions(+), 6 deletions(-) create mode 100644 packages/ti/boot/sbl/example/boot_app/bist/bist.c create mode 100644 packages/ti/boot/sbl/example/boot_app/bist/bist.h create mode 100644 packages/ti/boot/sbl/example/boot_app/bist/lbist_utils.c create mode 100644 packages/ti/boot/sbl/example/boot_app/bist/lbist_utils.h create mode 100644 packages/ti/boot/sbl/example/boot_app/bist/pbist_utils.c create mode 100644 packages/ti/boot/sbl/example/boot_app/bist/pbist_utils.h create mode 100644 packages/ti/boot/sbl/example/boot_app/bist/power_seq.c create mode 100644 packages/ti/boot/sbl/example/boot_app/bist/power_seq.h create mode 100755 packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/armv8_power_utils.c create mode 100755 packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/armv8_power_utils.h create mode 100755 packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/bist_core_defs.c create mode 100755 packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/bist_core_defs.h create mode 100755 packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/lbist_defs.c create mode 100755 packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/lbist_defs.h create mode 100755 packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/pbist_defs.c create mode 100755 packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/pbist_defs.h diff --git a/packages/ti/boot/sbl/board/k3/sbl_main.c b/packages/ti/boot/sbl/board/k3/sbl_main.c index 82a51774..947dd552 100755 --- a/packages/ti/boot/sbl/board/k3/sbl_main.c +++ b/packages/ti/boot/sbl/board/k3/sbl_main.c @@ -7,7 +7,7 @@ */ /* - * Copyright (C) 2018-2022 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018-2024 Texas Instruments Incorporated - http://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -43,6 +43,16 @@ #include "sbl_main.h" #include #include +#if defined (SBL_ENABLE_BIST) +#include +#include +#include +#include +#include +#if defined(SOC_J784S4) +#include +#endif +#endif /********************************************************************** ************************** Macros ************************************ @@ -245,6 +255,208 @@ const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] = }; +#if defined (SBL_ENABLE_BIST) + +void SBL_unlockPllMmrs(void) +{ + HW_WR_REG32(PLL0_LOCKKEY0, KICK0_UNLOCK); + HW_WR_REG32(PLL0_LOCKKEY1, KICK1_UNLOCK); + HW_WR_REG32(PLL1_LOCKKEY0, KICK0_UNLOCK); + HW_WR_REG32(PLL1_LOCKKEY1, KICK1_UNLOCK); + HW_WR_REG32(PLL2_LOCKKEY0, KICK0_UNLOCK); + HW_WR_REG32(PLL2_LOCKKEY1, KICK1_UNLOCK); + HW_WR_REG32(PLL3_LOCKKEY0, KICK0_UNLOCK); + HW_WR_REG32(PLL3_LOCKKEY1, KICK1_UNLOCK); + HW_WR_REG32(PLL4_LOCKKEY0, KICK0_UNLOCK); + HW_WR_REG32(PLL4_LOCKKEY1, KICK1_UNLOCK); + HW_WR_REG32(PLL5_LOCKKEY0, KICK0_UNLOCK); + HW_WR_REG32(PLL5_LOCKKEY1, KICK1_UNLOCK); + HW_WR_REG32(PLL6_LOCKKEY0, KICK0_UNLOCK); + HW_WR_REG32(PLL6_LOCKKEY1, KICK1_UNLOCK); + HW_WR_REG32(PLL7_LOCKKEY0, KICK0_UNLOCK); + HW_WR_REG32(PLL7_LOCKKEY1, KICK1_UNLOCK); + HW_WR_REG32(PLL8_LOCKKEY0, KICK0_UNLOCK); + HW_WR_REG32(PLL8_LOCKKEY1, KICK1_UNLOCK); + HW_WR_REG32(PLL9_LOCKKEY0, KICK0_UNLOCK); + HW_WR_REG32(PLL9_LOCKKEY1, KICK1_UNLOCK); + HW_WR_REG32(PLL12_LOCKKEY0, KICK0_UNLOCK); + HW_WR_REG32(PLL12_LOCKKEY1, KICK1_UNLOCK); + HW_WR_REG32(PLL14_LOCKKEY0, KICK0_UNLOCK); + HW_WR_REG32(PLL14_LOCKKEY1, KICK1_UNLOCK); + HW_WR_REG32(PLL16_LOCKKEY0, KICK0_UNLOCK); + HW_WR_REG32(PLL16_LOCKKEY1, KICK1_UNLOCK); + HW_WR_REG32(PLL17_LOCKKEY0, KICK0_UNLOCK); + HW_WR_REG32(PLL17_LOCKKEY1, KICK1_UNLOCK); + HW_WR_REG32(PLL19_LOCKKEY0, KICK0_UNLOCK); + HW_WR_REG32(PLL19_LOCKKEY1, KICK1_UNLOCK); + HW_WR_REG32(PLL25_LOCKKEY0, KICK0_UNLOCK); + HW_WR_REG32(PLL25_LOCKKEY1, KICK1_UNLOCK); + HW_WR_REG32(PLL26_LOCKKEY0, KICK0_UNLOCK); + HW_WR_REG32(PLL26_LOCKKEY1, KICK1_UNLOCK); +#if defined (SOC_J784S4) + HW_WR_REG32(PLL27_LOCKKEY0, KICK0_UNLOCK); + HW_WR_REG32(PLL27_LOCKKEY1, KICK1_UNLOCK); + HW_WR_REG32(PLL28_LOCKKEY0, KICK0_UNLOCK); + HW_WR_REG32(PLL28_LOCKKEY1, KICK1_UNLOCK); +#endif +} + + +static void MainDomainBootSetup(void) +{ + int32_t retVal = CSL_EFAIL; + Sciclient_DefaultBoardCfgInfo_t boardCfgInfo; + retVal = Sciclient_getDefaultBoardCfgInfo(&boardCfgInfo); + + if(CSL_PASS != retVal) + { + SBL_log(SBL_LOG_ERR, "Sciclient get default board config...FAILED \n"); + SblErrLoop(__FILE__, __LINE__); + } + + /* Unlock PLL MMRs putting back to same state prior to reset */ + SBL_log(SBL_LOG_MAX, "Unlocking pll mmrs ..."); + SBL_unlockPllMmrs(); + SBL_log(SBL_LOG_MAX, "done.\n"); + + Sciclient_BoardCfgPrms_t bootAppBoardCfgPrms = { + .boardConfigLow = (uint32_t)boardCfgInfo.boardCfgLow, + .boardConfigHigh = 0, + .boardConfigSize = boardCfgInfo.boardCfgLowSize, + .devGrp = DEVGRP_01 + }; + Sciclient_BoardCfgPrms_t bootAppBoardCfgPmPrms = { + .boardConfigLow = (uint32_t)NULL, + .boardConfigHigh = 0, + .boardConfigSize = 0, + .devGrp = DEVGRP_01 + }; + Sciclient_BoardCfgPrms_t bootAppBoardCfgRmPrms = { + .boardConfigLow = (uint32_t)boardCfgInfo.boardCfgLowRm, + .boardConfigHigh = 0, + .boardConfigSize = boardCfgInfo.boardCfgLowRmSize, + .devGrp = DEVGRP_01 + }; + Sciclient_BoardCfgPrms_t bootAppBoardCfgSecPrms = { + .boardConfigLow = (uint32_t)boardCfgInfo.boardCfgLowSec, + .boardConfigHigh = 0, + .boardConfigSize = boardCfgInfo.boardCfgLowSecSize, + .devGrp = DEVGRP_01 + }; + retVal = Sciclient_boardCfg(&bootAppBoardCfgPrms); + if (retVal != CSL_PASS) + { + SBL_log(SBL_LOG_MAX,"Sciclient_boardCfg() failed.\n"); + } + retVal = Sciclient_boardCfgPm(&bootAppBoardCfgPmPrms); + if (retVal != CSL_PASS) + { + SBL_log(SBL_LOG_MAX,"Sciclient_boardCfgPm() failed.\n"); + } + retVal = Sciclient_boardCfgRm(&bootAppBoardCfgRmPrms); + if (retVal != CSL_PASS) + { + SBL_log(SBL_LOG_MAX,"Sciclient_boardCfgRm() failed.\n"); + } + retVal = Sciclient_boardCfgSec(&bootAppBoardCfgSecPrms); + if (retVal != CSL_PASS) + { + SBL_log(SBL_LOG_MAX,"Sciclient_boardCfgSec() failed.\n"); + } + /* Init Pinmux */ + if(Board_init(BOARD_INIT_PINMUX_CONFIG) != BOARD_SOK) + { + SBL_log(SBL_LOG_ERR,"Board_init failed for BOARD_INIT_PINMUX_CONFIG\n"); + } + /* Init PLLS */ + Board_init(BOARD_INIT_PLL_MAIN); + + /* Init Clocks */ + Board_initParams_t initParams; + Board_getInitParams(&initParams); + initParams.mainClkGrp = BOARD_MAIN_CLOCK_GROUP1; + initParams.mcuClkGrp = BOARD_MCU_CLOCK_GROUP1; + Board_setInitParams(&initParams); + if(Board_init(BOARD_INIT_MODULE_CLOCK_MAIN) != BOARD_SOK) + { + SBL_log(SBL_LOG_ERR,"Board_init failed for BOARD_INIT_MODULE_CLOCK\n"); + } + + /* Unlock CTRL MMR */ + SBL_log(SBL_LOG_MAX, "Unlocking CTRL MMRs ..."); + if(Board_init(BOARD_INIT_UNLOCK_MMR) != BOARD_SOK) + { + SBL_log(SBL_LOG_ERR,"Board_init failed for BOARD_INIT_UNLOCK_MMR\n"); + } + SBL_log(SBL_LOG_MAX, "done.\n"); +} + +#endif + +/* Refer TISCI_MSG_SYS_RESET in TISCI user guide for more details + http://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/pm/sysreset.html */ +int32_t SBL_swResetMainDomain(void) +{ + int32_t retVal = E_FAIL; + + struct tisci_msg_sys_reset_req request; + struct tisci_msg_sys_reset_resp response = {0}; + + Sciclient_ReqPrm_t reqParam = {0}; + Sciclient_RespPrm_t respParam = {0}; + + memset(&request, 0, sizeof(request)); + request.domain = 0x2; /* 0x2 corresponds to the MAIN domain */ + + reqParam.messageType = (uint16_t) TISCI_MSG_SYS_RESET; + reqParam.flags = (uint32_t) TISCI_MSG_FLAG_AOP; + reqParam.pReqPayload = (const uint8_t *) &request; + reqParam.reqPayloadSize = (uint32_t) sizeof (request); + reqParam.timeout = (uint32_t) SCICLIENT_SERVICE_WAIT_FOREVER; + respParam.flags = (uint32_t) 0; /* Populated by the API */ + respParam.pRespPayload = (uint8_t *) &response; + respParam.respPayloadSize = (uint32_t) sizeof (response); + + retVal = Sciclient_service(&reqParam, &respParam); + if (((respParam.flags & TISCI_MSG_FLAG_ACK) == 0) || (retVal != CSL_PASS)) { + SBL_log(SBL_LOG_ERR,"SBL_swResetMainDomain failed, retVal = %d\n resp flag = 0x%08x\n", + retVal, respParam.flags); + } + + return retVal; +} + +void SBL_runPBIST(uint32_t instanceId, bool runNegTest) +{ + int32_t testResult = 0; + + + if(runNegTest) + { + /* Run test on provided instance */ + testResult = PBIST_runTest(instanceId, true); + /* PBIST_runtTest return value (-1 = failure and 0 = pass) */ + if ( testResult != 0) + { + SBL_log(SBL_LOG_ERR,"PBIST negative test failed for %d\n", + instanceId); + } + } + else + { + /* Run test on provided instance */ + testResult = PBIST_runTest(instanceId, false); + /* PBIST_runtTest return value (-1 = failure and 0 = pass) */ + if ( testResult != 0) + { + SBL_log(SBL_LOG_ERR,"PBIST functional test failed for %d\n", + instanceId); + } + } +} + +volatile uint32_t loopSwResetMainDomain = 0xDEADBEEF; + int main() { int32_t retVal = CSL_PASS; @@ -384,12 +596,67 @@ int main() #endif #endif SBL_ADD_PROFILE_POINT; - if (CSL_PASS != Board_init(SBL_CLOCK_INIT)) + if(Board_init(SBL_CLOCK_INIT) != BOARD_SOK) + { + SBL_log(SBL_LOG_ERR,"Board_init failed for SBL_CLOCK_INIT\n"); + retVal = CSL_EFAIL; + } + SBL_log(SBL_LOG_MAX, "done.\n"); +#endif + +#if defined (SBL_ENABLE_BIST) +#if 0 + /* For debug purpose */ + if(loopSwResetMainDomain == 0xDEADBEEF) { - retVal = CSL_EFAIL; - SBL_log(SBL_LOG_ERR, "\n Failed to initialize clocks !! \n"); + SBL_log(SBL_LOG_MAX, "Connect CCS and change loopSwResetMainDomain to 0!\n"); + SBL_log(SBL_LOG_MAX, "After that the MAIN domain will be reset!\n"); + } + while(loopSwResetMainDomain == 0xDEADBEEF); +#endif + + /* Initialize SDL Osal Layer */ + int32_t ret = SDL_TEST_osalInit(); + if (ret != SDL_PASS) + { + SBL_log(SBL_LOG_MAX,"Error: Init Failed\n"); } + /* PBIST MAININFRA_1 Negative / Positive */ + SBL_runPBIST(PBIST_INSTANCE_MAININFRA_1, true); + SBL_runPBIST(PBIST_INSTANCE_MAININFRA_1, false); + + /* PBIST MAININFRA_0 Negative / Positive */ + SBL_runPBIST(PBIST_INSTANCE_MAININFRA_0, true); + SBL_runPBIST(PBIST_INSTANCE_MAININFRA_0, false); + + /* PBIST MSMC Negative / Positive */ + SBL_runPBIST(PBIST_INSTANCE_MSMC, true); + SBL_runPBIST(PBIST_INSTANCE_MSMC, false); + + /* PBIST NAVSS Negative / Positive */ + SBL_runPBIST(PBIST_INSTANCE_NAVSS, true); + SBL_runPBIST(PBIST_INSTANCE_NAVSS, false); + + /* PBIST HC Negative / Positive */ + SBL_runPBIST(PBIST_INSTANCE_HC, true); + SBL_runPBIST(PBIST_INSTANCE_HC, false); + + /* PBIST CODEC1 Negative / Positive */ + /* Impacts QNX SD driver, can be uncommented for Linux boot */ + /* + SBL_runPBIST(PBIST_INSTANCE_CODEC_1, true); + SBL_runPBIST(PBIST_INSTANCE_CODEC_1, false); + */ + + /* Reset Main Domain */ + SBL_log(SBL_LOG_MAX, "Resetting Main Domain ..."); + SBL_swResetMainDomain(); + SBL_log(SBL_LOG_MAX, "done.\n"); + + /* Recover Main Domain */ + SBL_log(SBL_LOG_MAX, "Recovering Main Domain ..."); + MainDomainBootSetup(); SBL_log(SBL_LOG_MAX, "done.\n"); #endif @@ -420,10 +687,12 @@ int main() *gtcRegister = *gtcRegister | CSL_GTC_CFG1_CNTCR_EN_MASK | CSL_GTC_CFG1_CNTCR_HDBG_MASK; #if defined(SOC_J721E) || (!defined(SBL_ENABLE_HLOS_BOOT) && defined(SOC_J7200)) || (!defined(SBL_ENABLE_HLOS_BOOT) && defined(SOC_J784S4)) +#if !defined (SBL_ENABLE_BIST) /* Configure external Ethernet PHY and pinmux */ SBL_ConfigureEthernet(); #endif #endif +#endif #if !defined(BOOT_PERF) SBL_log(SBL_LOG_MAX, "Copying EEPROM content to DDR ... \n"); diff --git a/packages/ti/boot/sbl/board/k3/sbl_main.h b/packages/ti/boot/sbl/board/k3/sbl_main.h index 8a3aca49..70bc87d4 100644 --- a/packages/ti/boot/sbl/board/k3/sbl_main.h +++ b/packages/ti/boot/sbl/board/k3/sbl_main.h @@ -85,6 +85,55 @@ #endif #endif +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ + +#if defined (SBL_ENABLE_BIST) +#define KICK0_UNLOCK (0x68EF3490U) +#define KICK1_UNLOCK (0xD172BC5AU) + +#define PLL0_LOCKKEY0 (0x00680010U) +#define PLL0_LOCKKEY1 (0x00680014U) +#define PLL1_LOCKKEY0 (0x00681010U) +#define PLL1_LOCKKEY1 (0x00681014U) +#define PLL2_LOCKKEY0 (0x00682010U) +#define PLL2_LOCKKEY1 (0x00682014U) +#define PLL3_LOCKKEY0 (0x00683010U) +#define PLL3_LOCKKEY1 (0x00683014U) +#define PLL4_LOCKKEY0 (0x00684010U) +#define PLL4_LOCKKEY1 (0x00684014U) +#define PLL5_LOCKKEY0 (0x00685010U) +#define PLL5_LOCKKEY1 (0x00685014U) +#define PLL6_LOCKKEY0 (0x00686010U) +#define PLL6_LOCKKEY1 (0x00686014U) +#define PLL7_LOCKKEY0 (0x00687010U) +#define PLL7_LOCKKEY1 (0x00687014U) +#define PLL8_LOCKKEY0 (0x00688010U) +#define PLL8_LOCKKEY1 (0x00688014U) +#define PLL9_LOCKKEY0 (0x00689010U) +#define PLL9_LOCKKEY1 (0x00689014U) +#define PLL12_LOCKKEY0 (0x0068C010U) +#define PLL12_LOCKKEY1 (0x0068C014U) +#define PLL14_LOCKKEY0 (0x0068E010U) +#define PLL14_LOCKKEY1 (0x0068E014U) +#define PLL16_LOCKKEY0 (0x00690010U) +#define PLL16_LOCKKEY1 (0x00690014U) +#define PLL17_LOCKKEY0 (0x00691010U) +#define PLL17_LOCKKEY1 (0x00691014U) +#define PLL19_LOCKKEY0 (0x00693010U) +#define PLL19_LOCKKEY1 (0x00693014U) +#define PLL25_LOCKKEY0 (0x00699010U) +#define PLL25_LOCKKEY1 (0x00699014U) +#define PLL26_LOCKKEY0 (0x0069A010U) +#define PLL26_LOCKKEY1 (0x0069A014U) +#if defined(SOC_J784S4) +#define PLL27_LOCKKEY0 (0x0069B010U) +#define PLL27_LOCKKEY1 (0x0069B014U) +#define PLL28_LOCKKEY0 (0x0069C010U) +#define PLL28_LOCKKEY1 (0x0069C014U) +#endif +#endif /* ========================================================================== */ /* Function Declarations */ /* ========================================================================== */ diff --git a/packages/ti/boot/sbl/build/boot_app.mk b/packages/ti/boot/sbl/build/boot_app.mk index c17ccb9b..c2606d46 100644 --- a/packages/ti/boot/sbl/build/boot_app.mk +++ b/packages/ti/boot/sbl/build/boot_app.mk @@ -49,6 +49,35 @@ ifeq ($(BOOTMODE), mmcsd) COMP_LIST_COMMON += mmcsd sbl_lib_mmcsd fatfs_indp endif CFLAGS_LOCAL_COMMON += -DBOOT_MMCSD + ifeq ($(BOARD),$(filter $(BOARD), j784s4_evm)) + CFLAGS_LOCAL_COMMON += -DBIST_TASK_ENABLED + #CFLAGS_LOCAL_COMMON += + INCDIR += $(PDK_SBL_COMP_PATH)/example/boot_app/bist + INCDIR += $(PDK_SBL_COMP_PATH)/example/boot_app/bist/soc/$(SOC) + # SDL Include Files + SDL_INSTALL_PATH=$(PDK_INSTALL_PATH)/../../sdl + INCDIR += $(SDL_INSTALL_PATH)/ + INCDIR += $(SDL_INSTALL_PATH)/src/sdl + INCDIR += $(SDL_INSTALL_PATH)/include + INCDIR += $(SDL_INSTALL_PATH)/include/soc/$(SOC) + + # SDL Source File Paths + SRCDIR += $(SDL_INSTALL_PATH)/test/osal/src + SRCDIR += $(PDK_SBL_COMP_PATH)/example/boot_app/bist + SRCDIR += $(PDK_SBL_COMP_PATH)/example/boot_app/bist/soc/$(SOC) + + # SDL Integration + EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/osal/lib/$(SOC)/r5f/$(BUILD_PROFILE)/sdl_osal.$(LIBEXT) + EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/src/ip/lib/$(SOC)/r5f/$(BUILD_PROFILE)/sdl_ip.$(LIBEXT) + EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/src/sdl/lib/$(SOC)/r5f/$(BUILD_PROFILE)/sdl_api.$(LIBEXT) + EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/src/ip/r5/lib/$(SOC)/r5f/$(BUILD_PROFILE)/r5f_core.$(LIBEXT) + + SRCS_COMMON += osal_interface.c + SRCS_COMMON += bist.c bist_core_defs.c + SRCS_COMMON += lbist_utils.c lbist_defs.c + SRCS_COMMON += pbist_utils.c pbist_defs.c + SRCS_COMMON += power_seq.c armv8_power_utils.c + endif endif ifeq ($(BOOTMODE), ospi) ifeq ($(BUILD_HS), yes) diff --git a/packages/ti/boot/sbl/build/sbl_img.mk b/packages/ti/boot/sbl/build/sbl_img.mk index 11d2d347..22088991 100644 --- a/packages/ti/boot/sbl/build/sbl_img.mk +++ b/packages/ti/boot/sbl/build/sbl_img.mk @@ -111,6 +111,41 @@ else ifeq ($(BOOTMODE), xip) SBL_CFLAGS += -DOSPI_FREQ_166 endif COMP_LIST_COMMON += sbl_lib_cust$(HS_SUFFIX) +else ifeq ($(BOOTMODE), mmcsd) +ifeq ($(BOARD),$(filter $(BOARD), j784s4_evm)) + #SBL_CFLAGS = $(CUST_SBL_FLAGS) + # Uncomment to enable PBIST functionality in SBL + SBL_CFLAGS += -DSBL_ENABLE_BIST + SUPRESS_WARNINGS_FLAG += -Wno-unused-but-set-variable + + COMP_LIST_COMMON += sbl_lib_$(BOOTMODE)$(HS_SUFFIX) + + # SDL Include Files + SDL_INSTALL_PATH=$(PDK_INSTALL_PATH)/../../sdl + INCDIR += $(SDL_INSTALL_PATH)/ + INCDIR += $(SDL_INSTALL_PATH)/src/sdl + INCDIR += $(SDL_INSTALL_PATH)/include + INCDIR += $(SDL_INSTALL_PATH)/include/soc/$(SOC) + INCDIR += $(PDK_SBL_COMP_PATH)/example/boot_app/bist/soc/$(SOC) + INCDIR += $(PDK_SBL_COMP_PATH)/example/boot_app/bist + + # SDL Source File Paths + SRCDIR += $(SDL_INSTALL_PATH)/test/osal/src + SRCDIR += $(PDK_SBL_COMP_PATH)/example/boot_app/bist + SRCDIR += $(PDK_SBL_COMP_PATH)/example/boot_app/bist/soc/$(SOC) + + # SDL Integration + EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/osal/lib/$(SOC)/r5f/$(BUILD_PROFILE)/sdl_osal.$(LIBEXT) + EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/src/ip/lib/$(SOC)/r5f/$(BUILD_PROFILE)/sdl_ip.$(LIBEXT) + EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/src/sdl/lib/$(SOC)/r5f/$(BUILD_PROFILE)/sdl_api.$(LIBEXT) + EXT_LIB_LIST_COMMON += $(SDL_INSTALL_PATH)/binary/src/ip/r5/lib/$(SOC)/r5f/$(BUILD_PROFILE)/r5f_core.$(LIBEXT) + + SRCS_COMMON += osal_interface.c + SRCS_COMMON += bist.c bist_core_defs.c + SRCS_COMMON += lbist_utils.c lbist_defs.c + SRCS_COMMON += pbist_utils.c pbist_defs.c + SRCS_COMMON += power_seq.c armv8_power_utils.c +endif else COMP_LIST_COMMON += sbl_lib_$(BOOTMODE)$(DMA_SUFFIX)$(HLOS_SUFFIX)$(HS_SUFFIX) endif # ifeq ($(BOOTMODE), cust) diff --git a/packages/ti/boot/sbl/example/boot_app/bist/bist.c b/packages/ti/boot/sbl/example/boot_app/bist/bist.c new file mode 100644 index 00000000..3775eafb --- /dev/null +++ b/packages/ti/boot/sbl/example/boot_app/bist/bist.c @@ -0,0 +1,646 @@ +/* +* +* Copyright (c) 2022 Texas Instruments Incorporated +* +* All rights reserved not granted herein. +* +* Limited License. +* +* Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive +* license under copyrights and patents it now or hereafter owns or controls to make, +* have made, use, import, offer to sell and sell ("Utilize") this software subject to the +* terms herein. With respect to the foregoing patent license, such license is granted +* solely to the extent that any such patent is necessary to Utilize the software alone. +* The patent license shall not apply to any combinations which include this software, +* other than combinations with devices manufactured by or for TI ("TI Devices"). +* No hardware patent is licensed hereunder. +* +* Redistributions must preserve existing copyright notices and reproduce this license +* (including the above copyright notice and the disclaimer and (if applicable) source +* code license limitations below) in the documentation and/or other materials provided +* with the distribution +* +* Redistribution and use in binary form, without modification, are permitted provided +* that the following conditions are met: +* +* * No reverse engineering, decompilation, or disassembly of this software is +* permitted with respect to any software provided in binary form. +* +* * any redistribution and use are licensed by TI for use only with TI Devices. +* +* * Nothing shall obligate TI to provide you with source code for the software +* licensed and provided to you in object code. +* +* If software source code is provided to you, modification and redistribution of the +* source code are permitted provided that the following conditions are met: +* +* * any redistribution and use of the source code, including any resulting derivative +* works, are licensed by TI for use only with TI Devices. +* +* * any redistribution and use of any object code compiled from the source code +* and any resulting derivative works, are licensed by TI for use only with TI Devices. +* +* Neither the name of Texas Instruments Incorporated nor the names of its suppliers +* +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* DISCLAIMER. +* +* THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS +* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED +* OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + +/** + * \file bist.c + * + * \brief This file implements BIST task function + */ + +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ + +#include + +#include "lbist_utils.h" +#include "pbist_utils.h" +#include "bist_core_defs.h" + +#include +#include + +#include +#include + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ + +/* This flag adds more verbose prints */ +//#define DEBUG + +/* This flags enables gathering timing information for BIST stages */ +#define GATHER_BIST_STAGE_DETAILS + +/* For PBIST and LBIST stage tests, status is saved in bitfields. + * For these bitfields, status is represented by below defines */ +#define TEST_PASS_BIT 1 +#define TEST_FAIL_NOT_RUN_BIT 0 + +/* ========================================================================== */ +/* Internal Function Declarations */ +/* ========================================================================== */ + +/* ========================================================================== */ +/* Global Variables */ +/* ========================================================================== */ + +/* ========================================================================== */ +/* External Variables */ +/* ========================================================================== */ + +/* ========================================================================== */ +/* Function Definitions */ +/* ========================================================================== */ + +static const char *testStatusPrint(int32_t status) +{ + char *name; + + switch(status) + { + case (TEST_PASS_BIT): + name="PASS"; + break; + case (TEST_FAIL_NOT_RUN_BIT): + name="FAIL or NOT RUN"; + break; + default: + name="INVALID STATUS"; + break; + } + + return name; +} + + +void bist_TaskFxn(void) +{ + int32_t testResult = 0; + int32_t i, j; + int32_t *pbist_array; + int32_t *lbist_array; + /* Bitmap representing status of each PBIST test in each boot stage */ + int32_t pbist_stage_status[NUM_BOOT_STAGES]; + /* Bitmap representing status of each negative PBIST test in each boot stage */ + int32_t pbist_stage_neg_status[NUM_BOOT_STAGES]; + /* Bitmap representing status of each PBIST check of ROM in each boot stage */ + #if defined (SOC_J7200) || defined (SOC_J721S2) || defined (SOC_J784S4) + int32_t pbist_stage_rom_test_status[NUM_BOOT_STAGES]; + #endif + /* Bitmap representing status of each LBIST test in each boot stage */ + int32_t lbist_stage_status[NUM_BOOT_STAGES]; + + /* Initialize boot stage status bitmaps to "not run/fail" */ + for (i = 0; i < NUM_BOOT_STAGES; i++) + { + pbist_stage_status[i] = 0x0; + pbist_stage_neg_status[i] = 0x0; + lbist_stage_status[i] = 0x0; + #if defined (SOC_J7200) || defined (SOC_J721S2) || defined (SOC_J784S4) + pbist_stage_rom_test_status[i]=0x0; + #endif + } + + testResult = PBIST_commonInit(); + + if (testResult != 0) + { + UART_printf("PBIST_commonInit ...FAILED \n"); + } + else + { + /* This example presents a scenario in which the BISTs are performed in stages + * with booting of specific cores performed after certain stages. This example + * is adapted from the MCUSW Boot App for J721E. No cores are actually loaded + * in this example. Only the flow of performing BIST in stages is shown. */ + /* Run pre-boot-stage PBIST's. The definitions of the pre-boot-stage PBIST's + * are found in soc//bist_core_defs.c.*/ + for (i = 0; i < num_pbists_pre_boot; i++) + { + #if defined (SOC_J7200) || defined (SOC_J721S2) || defined (SOC_J784S4) + /* Run test on selected instance */ + testResult = PBIST_runTest(pbist_pre_boot_stage[i], (uint8_t)PBIST_TEST_NEGATIVE); + /* Convert signed return value (with -1 = failure and 0 = pass) to become + * 0 = failure and 1 = pass */ + pbist_pre_boot_stage_neg_status[i] = testResult + 1; + if ( testResult != 0) + { + UART_printf("PBIST negative test failed for %d\n", + pbist_pre_boot_stage[i]); + break; + } + #else + /* Run test on selected instance */ + testResult = PBIST_runTest(pbist_pre_boot_stage[i], (uint8_t)1); + /* Convert signed return value (with -1 = failure and 0 = pass) to become + * 0 = failure and 1 = pass */ + pbist_pre_boot_stage_neg_status[i] = testResult + 1; + if ( testResult != 0) + { + UART_printf("PBIST negative test failed for %d\n", + pbist_pre_boot_stage[i]); + break; + } + #endif + + } + + for (i = 0; i < num_pbists_pre_boot; i++) + { + #if defined (SOC_J7200) || defined (SOC_J721S2) || defined (SOC_J784S4) + /* Run test on selected instance */ + testResult = PBIST_runTest(pbist_pre_boot_stage[i],(uint8_t)PBIST_TEST_POSITIVE); + /* Convert signed return value (with -1 = failure and 0 = pass) to become + * 0 = failure and 1 = pass */ + pbist_pre_boot_stage_status[i] = testResult + 1; + if ( testResult != 0) + { + UART_printf("PBIST functional test failed for %d\n", + pbist_pre_boot_stage[i]); + break; + } + #else + /* Run test on selected instance */ + testResult = PBIST_runTest(pbist_pre_boot_stage[i], (uint8_t)0); + /* Convert signed return value (with -1 = failure and 0 = pass) to become + * 0 = failure and 1 = pass */ + pbist_pre_boot_stage_status[i] = testResult + 1; + if ( testResult != 0) + { + UART_printf("PBIST functional test failed for %d\n", + pbist_pre_boot_stage[i]); + break; + } + #endif + } + #if defined (SOC_J7200) || defined (SOC_J721S2) || defined (SOC_J784S4) + for (i = 0; i < num_pbists_pre_boot; i++) + { + /* Run test on selected instance */ + testResult = PBIST_runTest(pbist_pre_boot_stage[i], (uint8_t)PBIST_TEST_ROM); + /* Convert signed return value (with -1 = failure and 0 = pass) to become + * 0 = failure and 1 = pass */ + pbist_pre_boot_stage_rom_test_status[i] = testResult + 1; + if ( testResult != 0) + { + UART_printf("PBIST ROM test failed for %d\n", + pbist_pre_boot_stage[i]); + } + } + #endif + + /* Run pre-boot-stage LBIST's. The definitions of the pre-boot-stage LBIST's + * are found in soc//bist_core_defs.c. */ + for (i = 0; i < num_lbists_pre_boot; i++) + { + /* Run test on selected instance */ + testResult = LBIST_runTest(lbist_pre_boot_stage[i]); + lbist_pre_boot_stage_status[i] = testResult; + if ((testResult == -1) || + (testResult == LBIST_POST_COMPLETED_FAILURE) || + (testResult == LBIST_POST_ATTEMPTED_TIMEOUT)) + { + UART_printf("LBIST functional test failed for %d\n", + lbist_pre_boot_stage[i]); + break; + } + } + + /* After running PBIST potentially on MSMC, re-initialize the CLEC */ + testResult = PBIST_commonInit(); + + if (testResult != 0) + { + UART_printf("PBIST_commonInit after pre-boot stage ...FAILED \n"); + } + + /* Run LBIST and PBIST before each boot stage. The definitions of the LBIST + * and PBIST sections for each stage are defined in + * soc//bist_core_defs.c. */ + for (j = 0; j < NUM_BOOT_STAGES; j++) + { + pbist_array = pbist_array_stage[j]; + lbist_array = lbist_array_stage[j]; + for (i = 0; i < num_pbists_per_boot_stage[j]; i++) + { + PBIST_clecConfig(pbist_array[i]); + + #if defined (SOC_J7200) || defined (SOC_J721S2) || defined (SOC_J784S4) + /* Run test on selected instance */ + /*MCU instances are not supported for neg and pos test, + So skipped according to the pbist_first_boot_stage array sequence */ + #if defined (SOC_J784S4) + if((i==27)|| (i==28)||(i==29)) + { + continue; + } + /* Main Infra0/1, NAVSS and MSMC should be run in SBL, if Boot App is running in DDR */ + if((i==7)|| (i==2)||(i==6)||(i==25)) + { + continue; + } + /* HC has MMCSD in Auxiallary list, run this in SBL */ + if(i==9) + { + continue; + } + /* TODO: Codecs are impacting QNX SDMMC driver */ + if ((i==12) || (i==1)) + { + continue; + } + /* TODO: DSS is impacting QNX SDMMC driver */ + if (i==4) + { + continue; + } + /* TODO: Debugging issue with A72s PBIST, do not run */ + if ((i==13)|| (i==14)||(i==15)||(i==16)) + { + continue; + } + #endif + /*MCU instances are not supported for neg and pos test, + So skipped according to the pbist_first_boot_stage array sequence */ + #if defined (SOC_J7200) + if((i== 6U)|| (i==7U)||(i==8U)) + { + continue; + } + #endif + /*MCU instances are not supported for neg and pos test, + So skipped according to the pbist_first_boot_stage array sequence */ + #if defined (SOC_J721S2) + if((i==14)|| (i==15)||(i==16)) + { + continue; + } + #endif + testResult = PBIST_runTest(pbist_array[i], (uint8_t)PBIST_TEST_NEGATIVE); + + /* Convert signed return value (with -1 = failure and 0 = pass) to become + * a single bit as part of bitfield with 0 = failure and 1 = pass */ + pbist_stage_neg_status[j] |= ((uint32_t)(testResult + 1) << i); + if ( testResult != 0) + { + UART_printf("PBIST negative test failed for %d\n", + pbist_array[i]); + break; + } + #else + /* Run test on selected instance */ + testResult = PBIST_runTest(pbist_array[i], (uint8_t)1); + + /* Convert signed return value (with -1 = failure and 0 = pass) to become + * a single bit as part of bitfield with 0 = failure and 1 = pass */ + pbist_stage_neg_status[j] |= ((uint32_t)(testResult + 1) << i); + if ( testResult != 0) + { + UART_printf("PBIST negative test failed for %d\n", + pbist_array[i]); + break; + } + #endif + } + + for (i = 0; i < num_pbists_per_boot_stage[j]; i++) + { + #if defined (SOC_J7200) || defined (SOC_J721S2) || defined (SOC_J784S4) + /* Run test on selected instance */ + /*MCU instances are not supported for neg and pos test, + So skipped according to the pbist_first_boot_stage array sequence */ + #if defined (SOC_J784S4) + if((i==27)|| (i==28)||(i==29)) + { + continue; + } + /* Main Infra0/1, NAVSS and MSMC should be run in SBL, if Boot App is running in DDR */ + if((i==7)|| (i==2)||(i==6)||(i==25)) + { + continue; + } + /* HC has MMCSD in Auxiallary list, run this in SBL */ + if(i==9) + { + continue; + } + /* TODO: Codecs are impacting QNX SDMMC driver */ + if ((i==12) || (i==1)) + { + continue; + } + /* TODO: DSS is impacting QNX SDMMC driver */ + if (i==4) + { + continue; + } + /* TODO: Debugging issue with A72s PBIST, do not run */ + if ((i==13)|| (i==14)||(i==15)||(i==16)) + { + continue; + } + #endif + /*MCU instances are not supported for neg and pos test, + So skipped according to the pbist_first_boot_stage array sequence */ + #if defined (SOC_J7200) + if((i== 6U)|| (i==7U)||(i==8U)) + { + continue; + } + #endif + /*MCU instances are not supported for neg and pos test, + So skipped according to the pbist_first_boot_stage array sequence */ + #if defined (SOC_J721S2) + if((i==14)|| (i==15)||(i==16)) + { + continue; + } + #endif + testResult = PBIST_runTest(pbist_array[i], (uint8_t)PBIST_TEST_POSITIVE); + + /* Convert signed return value (with -1 = failure and 0 = pass) to become + * a single bit as part of bitfield with 0 = failure and 1 = pass */ + pbist_stage_status[j] |= ((uint32_t)(testResult + 1) << i); + if ( testResult != 0) + { + UART_printf("PBIST functional test failed for %d\n", + pbist_array[i]); + break; + } + #else + testResult = PBIST_runTest(pbist_array[i], (uint8_t)0); + + /* Convert signed return value (with -1 = failure and 0 = pass) to become + * a single bit as part of bitfield with 0 = failure and 1 = pass */ + pbist_stage_status[j] |= ((uint32_t)(testResult + 1) << i); + if ( testResult != 0) + { + UART_printf("PBIST functional test failed for %d\n", + pbist_array[i]); + break; + } + #endif + } + #if defined (SOC_J7200) || defined (SOC_J721S2) || defined (SOC_J784S4) + for (i = 0; i < num_pbists_per_boot_stage[j]; i++) + { + /* Main Infra0/1, NAVSS and MSMC should be run in SBL, if Boot App is running in DDR */ + if((i==7)|| (i==2)||(i==6)||(i==25)) + { + continue; + } + /* HC has MMCSD in Auxiallary list, run this in SBL */ + if(i==9) + { + continue; + } + /* TODO: Codecs are impacting QNX SDMMC driver */ + if ((i==12) || (i==1)) + { + continue; + } + /* TODO: DSS is impacting QNX SDMMC driver */ + if (i==4) + { + continue; + } + /* TODO: Debugging issue with A72s PBIST, do not run */ + if ((i==13)|| (i==14)||(i==15)||(i==16)) + { + continue; + } + /* Run test on selected instance */ + testResult = PBIST_runTest(pbist_array[i], (uint8_t)PBIST_TEST_ROM); + + /* Convert signed return value (with -1 = failure and 0 = pass) to become + * a single bit as part of bitfield with 0 = failure and 1 = pass */ + pbist_stage_rom_test_status[j] |= ((uint32_t)(testResult + 1) << i); + if ( testResult != 0) + { + UART_printf("PBIST ROM test failed for %d\n", + pbist_array[i]); + } + } + #endif +#if defined(DEBUG) + UART_printf( "Ran PBIST for Stage %d\n", j); +#endif + for (i = 0; i < num_lbists_per_boot_stage[j]; i++) + { + testResult = LBIST_runTest(lbist_array[i]); + + /* Convert signed return value (with -1 = failure and 0 = pass) to become + * a single bit as part of bitfield with 0 = failure and 1 = pass */ + lbist_stage_status[j] |= ((uint32_t)(testResult + 1) << i); + if (testResult != 0) + { + UART_printf("LBIST functional test failed for %d\n", + lbist_array[i]); + break; + } + } +#if defined(DEBUG) + UART_printf( "Ran LBIST for Stage %d\n", j); +#endif + /* Signal Boot Task that BIST for the stage is completed */ + UART_printf("\n *** Boot stage %d is complete, cores for this stage may now be loaded ***\n\n", j); + } + } + + if (testResult == 0) + { + UART_printf("==========================\n"); + UART_printf("BIST: Example App Summary:\n"); + UART_printf("==========================\n"); + for (i = 0; i < num_pbists_pre_boot; i++) + { + UART_printf("BIST: Pre-boot Stage - Ran negative PBIST ID - %s, Result = %s\n", + pbistName(pbist_pre_boot_stage[i]), + testStatusPrint(pbist_pre_boot_stage_neg_status[i])); + } + UART_printf("Pre-boot stage - Ran %d negative PBIST total sections\n", + num_pbists_pre_boot); + + #if defined (SOC_J7200) || defined (SOC_J721S2) || defined (SOC_J784S4) + for (i = 0; i < num_pbists_pre_boot; i++) + { + UART_printf("BIST: Pre-boot Stage - Ran ROM Test PBIST ID - %s, Result = %s\n", + pbistName(pbist_pre_boot_stage[i]), + testStatusPrint(pbist_pre_boot_stage_rom_test_status[i])); + } + UART_printf("Pre-boot stage - Ran %d ROM Test of PBIST total sections\n", + num_pbists_pre_boot); + #endif + for (i = 0; i < num_pbists_pre_boot; i++) + { + UART_printf("BIST: Pre-boot Stage - Ran PBIST ID - %s, Result = %s\n", + pbistName(pbist_pre_boot_stage[i]), + testStatusPrint(pbist_pre_boot_stage_status[i])); + } + UART_printf("Pre-boot stage - Ran %d PBIST total sections\n", + num_pbists_pre_boot); + for (i = 0; i < num_lbists_pre_boot; i++) + { + UART_printf("BIST: Pre-boot Stage - Ran LBIST ID - %s, Result = %s\n", + lbistName(lbist_pre_boot_stage[i]), + LBIST_hwPostStatusPrint(lbist_pre_boot_stage_status[i])); + } + UART_printf("Pre-boot stage - Ran %d LBIST total sections\n", + num_lbists_pre_boot); + + for (j = 0; j < NUM_BOOT_STAGES; j++) + { + pbist_array = pbist_array_stage[j]; + lbist_array = lbist_array_stage[j]; +#if defined(GATHER_BIST_STAGE_DETAILS) + for (i = 0; i < num_pbists_per_boot_stage[j]; i++) + { + /*MCU instances are not supported for neg and pos test, + So skipped according to the pbist_first_boot_stage array sequence */ + #if defined (SOC_J784S4) + if((i==27)|| (i==28)||(i==29)) + { + continue; + } + #endif + /*MCU instances are not supported for neg and pos test, + So skipped according to the pbist_first_boot_stage array sequence */ + #if defined (SOC_J7200) + if((i== 6U)|| (i==7U)||(i==8U)) + { + continue; + } + #endif + /*MCU instances are not supported for neg and pos test, + So skipped according to the pbist_first_boot_stage array sequence */ + #if defined (SOC_J721S2) + if((i==14)|| (i==15)||(i==16)) + { + continue; + } + #endif + UART_printf("BIST: Stage %d - Ran negative PBIST ID - %s, Result = %s\n", + j, pbistName(pbist_array[i]), + testStatusPrint((pbist_stage_neg_status[j] >> i) & 0x1)); + } + UART_printf("BIST: Stage %d - Ran %d negative PBIST total sections\n", + j, (uint32_t)num_pbists_per_boot_stage[j]); + + #if defined (SOC_J7200) || defined (SOC_J721S2) || defined (SOC_J784S4) + for (i = 0; i < num_pbists_per_boot_stage[j]; i++) + { + UART_printf("BIST: Stage %d - Ran ROM Test PBIST ID - %s, Result = %s\n", + j, pbistName(pbist_array[i]), + testStatusPrint((pbist_stage_rom_test_status[j] >> i) & 0x1)); + } + UART_printf("BIST: Stage %d - Ran %d ROM Test PBIST total sections\n", + j, (uint32_t)num_pbists_per_boot_stage[j]); + + #endif + for (i = 0; i < num_pbists_per_boot_stage[j]; i++) + { + /*MCU instances are not supported for neg and pos test, + So skipped according to the pbist_first_boot_stage array sequence */ + #if defined (SOC_J784S4) + if((i==27)|| (i==28)||(i==29)) + { + continue; + } + #endif + /*MCU instances are not supported for neg and pos test, + So skipped according to the pbist_first_boot_stage array sequence */ + #if defined (SOC_J7200) + if((i== 6U)|| (i==7U)||(i==8U)) + { + continue; + } + #endif + /*MCU instances are not supported for neg and pos test, + So skipped according to the pbist_first_boot_stage array sequence */ + #if defined (SOC_J721S2) + if((i==14)|| (i==15)||(i==16)) + { + continue; + } + #endif + UART_printf("BIST: Stage %d - Ran PBIST ID - %s, Result = %s\n", + j, pbistName(pbist_array[i]), + testStatusPrint((pbist_stage_status[j] >> i) & 0x1)); + } + UART_printf("BIST: Stage %d - Ran %d PBIST total sections\n", + j, (uint32_t)num_pbists_per_boot_stage[j]); + + for (i = 0; i < num_lbists_per_boot_stage[j]; i++) + { + UART_printf("BIST: Stage %d - Ran LBIST ID - %s, Result = %s\n", + j, lbistName(lbist_array[i]), + testStatusPrint((lbist_stage_status[j] >> i) & 0x1)); + } + UART_printf("BIST: Stage %d - Ran %d LBIST sections\n", + j, (uint32_t)num_lbists_per_boot_stage[j]); +#endif + } + } +} + diff --git a/packages/ti/boot/sbl/example/boot_app/bist/bist.h b/packages/ti/boot/sbl/example/boot_app/bist/bist.h new file mode 100644 index 00000000..894e367d --- /dev/null +++ b/packages/ti/boot/sbl/example/boot_app/bist/bist.h @@ -0,0 +1,78 @@ +/* +* +* Copyright (c) 2020 Texas Instruments Incorporated +* +* All rights reserved not granted herein. +* +* Limited License. +* +* Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive +* license under copyrights and patents it now or hereafter owns or controls to make, +* have made, use, import, offer to sell and sell ("Utilize") this software subject to the +* terms herein. With respect to the foregoing patent license, such license is granted +* solely to the extent that any such patent is necessary to Utilize the software alone. +* The patent license shall not apply to any combinations which include this software, +* other than combinations with devices manufactured by or for TI ("TI Devices"). +* No hardware patent is licensed hereunder. +* +* Redistributions must preserve existing copyright notices and reproduce this license +* (including the above copyright notice and the disclaimer and (if applicable) source +* code license limitations below) in the documentation and/or other materials provided +* with the distribution +* +* Redistribution and use in binary form, without modification, are permitted provided +* that the following conditions are met: +* +* * No reverse engineering, decompilation, or disassembly of this software is +* permitted with respect to any software provided in binary form. +* +* * any redistribution and use are licensed by TI for use only with TI Devices. +* +* * Nothing shall obligate TI to provide you with source code for the software +* licensed and provided to you in object code. +* +* If software source code is provided to you, modification and redistribution of the +* source code are permitted provided that the following conditions are met: +* +* * any redistribution and use of the source code, including any resulting derivative +* works, are licensed by TI for use only with TI Devices. +* +* * any redistribution and use of any object code compiled from the source code +* and any resulting derivative works, are licensed by TI for use only with TI Devices. +* +* Neither the name of Texas Instruments Incorporated nor the names of its suppliers +* +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* DISCLAIMER. +* +* THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS +* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED +* OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + +/** + * \file bist.h + * + * \brief This header provides BIST task function. + */ + +#ifndef __BIST__ +#define __BIST__ + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ +/* Function prototypes */ +void bist_TaskFxn(void); + +#endif /* __BIST__ */ diff --git a/packages/ti/boot/sbl/example/boot_app/bist/lbist_utils.c b/packages/ti/boot/sbl/example/boot_app/bist/lbist_utils.c new file mode 100644 index 00000000..1e43eab1 --- /dev/null +++ b/packages/ti/boot/sbl/example/boot_app/bist/lbist_utils.c @@ -0,0 +1,762 @@ +/* +* +* Copyright (c) 2020 Texas Instruments Incorporated +* +* All rights reserved not granted herein. +* +* Limited License. +* +* Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive +* license under copyrights and patents it now or hereafter owns or controls to make, +* have made, use, import, offer to sell and sell ("Utilize") this software subject to the +* terms herein. With respect to the foregoing patent license, such license is granted +* solely to the extent that any such patent is necessary to Utilize the software alone. +* The patent license shall not apply to any combinations which include this software, +* other than combinations with devices manufactured by or for TI ("TI Devices"). +* No hardware patent is licensed hereunder. +* +* Redistributions must preserve existing copyright notices and reproduce this license +* (including the above copyright notice and the disclaimer and (if applicable) source +* code license limitations below) in the documentation and/or other materials provided +* with the distribution +* +* Redistribution and use in binary form, without modification, are permitted provided +* that the following conditions are met: +* +* * No reverse engineering, decompilation, or disassembly of this software is +* permitted with respect to any software provided in binary form. +* +* * any redistribution and use are licensed by TI for use only with TI Devices. +* +* * Nothing shall obligate TI to provide you with source code for the software +* licensed and provided to you in object code. +* +* If software source code is provided to you, modification and redistribution of the +* source code are permitted provided that the following conditions are met: +* +* * any redistribution and use of the source code, including any resulting derivative +* works, are licensed by TI for use only with TI Devices. +* +* * any redistribution and use of any object code compiled from the source code +* and any resulting derivative works, are licensed by TI for use only with TI Devices. +* +* Neither the name of Texas Instruments Incorporated nor the names of its suppliers +* +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* DISCLAIMER. +* +* THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS +* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED +* OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + +/** + * \file lbist_utils.c + * + * \brief LBIST utility functions + */ + +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ +#include +#include +#include +#include +#include +#include + +/* Osal API header files */ +#include +#include + +#include "power_seq.h" + +#include "lbist_utils.h" +#include "lbist_defs.h" + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ + +/* This flag adds more verbose prints */ +/* #define DEBUG */ + +/* This flag enables gathering of profile information for each LBIST test run */ +//#define PROFILE_LBIST_TIMING + +/* ========================================================================== */ +/* Internal Function Declarations */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Structure Declarations */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Function Declarations */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Global Variables */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* External Variables */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Function Definitions */ +/* ========================================================================== */ + +/* This function runs the full LBIST test for a particular core. + * It includes the following steps (each step has many sub-steps specificied + * in more details within the function). + * For HW POST LBIST: + * Step 1: Check POST results (already run at startup) + * + * For SW-initiated LBIST: + * Step 1: Configure processor to correct state + * Step 2: Run LBIST test + * Step 3: Restore cores + * */ +int32_t LBIST_runTest(uint32_t coreIndex) +{ + int32_t testResult = 0; + int32_t status; + bool result; + SDL_LBIST_postResult postResult; + +#if defined(PROFILE_LBIST_TIMING) + uint64_t startTime , testStartTime, testEndTime, endTime; + uint64_t prepTime, diffTime, restoreTime; + + UART_printf("\n Starting LBIST test on %s, index %d...", + LBIST_TestHandleArray[coreIndex].coreName, + coreIndex); +#endif + +#if defined(PROFILE_LBIST_TIMING) + /* Get start time of test */ + startTime = TimerP_getTimeInUsecs(); +#endif + + + if ((testResult == 0) && + (LBIST_TestHandleArray[coreIndex].hwPostCoreCheck == true)) + { + status = SDL_LBIST_getPOSTStatus(&postResult); + if (status != SDL_PASS) + { + testResult = -1; + UART_printf(" SDL_LBIST_getPOSTStatus failed: Status %d \n", status); + } + else + { + LBIST_printPostStatus(&postResult); + } + } + else + { + /* SW-initiated LBIST test flow */ + /*-- Step 1: Configure processor to correct state --*/ + + /**--- Step 1a: Request Primary core ---*/ + if (testResult == 0) + { + if (LBIST_TestHandleArray[coreIndex].tisciProcId != 0u) + { +#ifdef DEBUG + UART_printf(" Primary core: %s: Requesting processor \n", + LBIST_TestHandleArray[coreIndex].coreName); +#endif + /* Request Primary core */ + status = Sciclient_procBootRequestProcessor(LBIST_TestHandleArray[coreIndex].tisciProcId, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Primary core: Sciclient_procBootRequestProcessor, ProcId 0x%x...FAILED \n", + LBIST_TestHandleArray[coreIndex].tisciProcId); + testResult = -1; + } + } + } + + /**--- Step 1b: Request Secondary core ---*/ + if (testResult == 0) + { + if ((LBIST_TestHandleArray[coreIndex].secondaryCoreNeeded) + && (LBIST_TestHandleArray[coreIndex].tisciSecProcId != 0u)) + { +#ifdef DEBUG + UART_printf(" Secondary core: %s: Requesting processor \n", + LBIST_TestHandleArray[coreIndex].secCoreName); +#endif + /* Request secondary core */ + status = Sciclient_procBootRequestProcessor(LBIST_TestHandleArray[coreIndex].tisciSecProcId, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Secondary core: Sciclient_procBootRequestProcessor, ProcId 0x%x...FAILED \n", + LBIST_TestHandleArray[coreIndex].tisciSecProcId); + testResult = -1; + } + } + } + + /**--- Step 1c: Place all Auxilliary modules needed to run test into module reset ---*/ + if (testResult == 0) + { + int i; + + /* Place all Auxilliary modules required for test into module reset */ + for ( i = 0; i < LBIST_TestHandleArray[coreIndex].numAuxDevices; i++) + { +#ifdef DEBUG + UART_printf(" Putting into module reset Device number %d Device Id %x\n", + i, + LBIST_TestHandleArray[coreIndex].auxDeviceIdsP[i]); +#endif + + status = Sciclient_pmSetModuleRst(LBIST_TestHandleArray[coreIndex].auxDeviceIdsP[i], + 0x2, /* Module Reset asserted */ + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Sciclient_pmSetModuleState 0x%x ...FAILED \n", + LBIST_TestHandleArray[coreIndex].auxDeviceIdsP[i]); + testResult = -1; + break; + } + } + } + + /**--- Step 1d: Put Primary core in module reset and local reset ---*/ + if ((testResult == 0) && (LBIST_TestHandleArray[coreIndex].tisciDeviceId != 0U)) + { +#ifdef DEBUG + UART_printf(" Primary core: Putting in module and local reset the core %s \n", + LBIST_TestHandleArray[coreIndex].coreName); +#endif + status = Sciclient_pmSetModuleRst(LBIST_TestHandleArray[coreIndex].tisciDeviceId, + 0x3, /* Module Reset and Local Reset asserted */ + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Sciclient_pmSetModuleRst 0x%x ...FAILED \n", + LBIST_TestHandleArray[coreIndex].tisciDeviceId); + testResult = -1; + } + } + + /**--- Step 1e: Put Secondary core in module reset and local reset ---*/ + if ((testResult == 0) && (LBIST_TestHandleArray[coreIndex].tisciSecDeviceId != 0U)) + { +#ifdef DEBUG + UART_printf(" Secondary core: Putting in module and local reset the core %s \n", + LBIST_TestHandleArray[coreIndex].secCoreName); +#endif + status = Sciclient_pmSetModuleRst(LBIST_TestHandleArray[coreIndex].tisciSecDeviceId, + 0x3, /* Module Reset and Local Reset asserted */ + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Sciclient_pmSetModuleRst 0x%x ...FAILED \n", + LBIST_TestHandleArray[coreIndex].tisciSecDeviceId); + testResult = -1; + } + } + + /**--- Step 1f: Place all Auxilliary modules needed to run test into retention ---*/ + if (testResult == 0) + { + int i; + + /* Place all Auxilliary modules required for test into retention */ + for ( i = 0; i < LBIST_TestHandleArray[coreIndex].numAuxDevices; i++) + { +#ifdef DEBUG + UART_printf(" Putting into Retention Device number %d Device Id %x\n", + i, + LBIST_TestHandleArray[coreIndex].auxDeviceIdsP[i]); +#endif + + status = Sciclient_pmSetModuleState(LBIST_TestHandleArray[coreIndex].auxDeviceIdsP[i], + TISCI_MSG_VALUE_DEVICE_SW_STATE_RETENTION, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Sciclient_pmSetModuleState 0x%x ...FAILED \n", + LBIST_TestHandleArray[coreIndex].auxDeviceIdsP[i]); + testResult = -1; + break; + } + } + } + + /**--- Step 1g: Place Primary core into retention ---*/ + if (testResult == 0) + { + if (LBIST_TestHandleArray[coreIndex].tisciDeviceId != 0u) + { + /* Placing Primary core into Retention */ +#ifdef DEBUG + UART_printf(" Primary core: Putting into Retention %s \n", + LBIST_TestHandleArray[coreIndex].coreName); +#endif + status = Sciclient_pmSetModuleState(LBIST_TestHandleArray[coreIndex].tisciDeviceId, + TISCI_MSG_VALUE_DEVICE_SW_STATE_RETENTION, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Primary core: Sciclient_pmSetModuleState...FAILED \n"); + testResult = -1; + } + } + } + + /**--- Step 1h: Place Secondary core into retention ---*/ + if (testResult == 0) + { + if (LBIST_TestHandleArray[coreIndex].tisciSecDeviceId != 0u) + { + /* Placing Secondary core into Retention */ +#ifdef DEBUG + UART_printf(" Secondary core: Putting into Retention %s \n", + LBIST_TestHandleArray[coreIndex].secCoreName); +#endif + status = Sciclient_pmSetModuleState(LBIST_TestHandleArray[coreIndex].tisciSecDeviceId, + TISCI_MSG_VALUE_DEVICE_SW_STATE_RETENTION, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Secondary core: Sciclient_pmSetModuleState...FAILED \n"); + testResult = -1; + } + } + } + + /**-- Step 2: Run LBIST test --*/ +#if defined(PROFILE_LBIST_TIMING) + /* Get start time for LBIST test */ + testStartTime = TimerP_getTimeInUsecs(); +#endif + + if (testResult == 0) + { + status = SDL_LBIST_selfTest(LBIST_TestHandleArray[coreIndex].instance, SDL_LBIST_TEST, &result); + if ((status != SDL_PASS) || (result == false)) + { + UART_printf(" LBIST selfTest failed \n"); + testResult = -1; + } + } + +#if defined(PROFILE_LBIST_TIMING) + /* Here LBIST test is complete , get end time of test */ + testEndTime = TimerP_getTimeInUsecs(); +#endif + + /**-- Step 3: Restore cores --*/ + /* The following sequence is needed to restore core to normal operation */ + + /**--- Step 3a: Switch off Secondary core ---*/ + if (testResult == 0) + { + if (LBIST_TestHandleArray[coreIndex].secondaryCoreNeeded) + { + /* Power off Secondary core */ +#ifdef DEBUG + UART_printf(" Secondary core: Powering off %s \n", + LBIST_TestHandleArray[coreIndex].secCoreName); +#endif + status = Sciclient_pmSetModuleState(LBIST_TestHandleArray[coreIndex].tisciSecDeviceId, + TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Secondary core: Sciclient_pmSetModuleState: Power off FAILED \n"); + testResult = -1; + } + } + } + + /**--- Step 3b: Switch off Primary core ---*/ + if (testResult == 0) + { + /* Power off Primary core */ +#ifdef DEBUG + UART_printf(" Primary core: Powering off %s \n", + LBIST_TestHandleArray[coreIndex].coreName); +#endif + status = Sciclient_pmSetModuleState(LBIST_TestHandleArray[coreIndex].tisciDeviceId, + TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Primary core: Sciclient_pmSetModuleState: Power off FAILED \n"); + } + } + + /**--- Step 3c: Switch off Auxilliary modules ---*/ + if (testResult == 0) + { + int i; + + /* Place all Auxilliary modules required for test into retention */ + for ( i = 0; i < LBIST_TestHandleArray[coreIndex].numAuxDevices; i++) + { +#ifdef DEBUG + UART_printf(" Powering off Device number %d Device Id %x\n", + i, + LBIST_TestHandleArray[coreIndex].auxDeviceIdsP[i]); +#endif + + status = Sciclient_pmSetModuleState(LBIST_TestHandleArray[coreIndex].auxDeviceIdsP[i], + TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Sciclient_pmSetModuleState 0x%x ...FAILED \n", + LBIST_TestHandleArray[coreIndex].auxDeviceIdsP[i]); + testResult = -1; + break; + } + } + } + + /**--- Step 3d: Disable Isolation ---*/ + if (testResult == 0) + { +#ifdef DEBUG + UART_printf(" Disabling isolation \n"); +#endif + status = SDL_LBIST_selfTest(LBIST_TestHandleArray[coreIndex].instance, SDL_LBIST_TEST_RELEASE, &result); + if (status != SDL_PASS) + { + UART_printf(" SDL_LBIST_disableIsolation ...FAILED \n"); + testResult = -1; + } + } + + /**--- Step 3e: Place all Auxilliary modules into retention ---*/ + if (testResult == 0) + { + int i; + + /* Place all Auxilliary modules required for test into retention */ + for ( i = 0; i < LBIST_TestHandleArray[coreIndex].numAuxDevices; i++) + { +#ifdef DEBUG + UART_printf(" Putting into Retention Device number %d Device Id %x\n", + i, + LBIST_TestHandleArray[coreIndex].auxDeviceIdsP[i]); +#endif + + status = Sciclient_pmSetModuleState(LBIST_TestHandleArray[coreIndex].auxDeviceIdsP[i], + TISCI_MSG_VALUE_DEVICE_SW_STATE_RETENTION, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Sciclient_pmSetModuleState 0x%x ...FAILED \n", + LBIST_TestHandleArray[coreIndex].auxDeviceIdsP[i]); + testResult = -1; + break; + } + } + } + + /**--- Step 3f: Place Primary core into retention ---*/ + if (testResult == 0) + { + /* Placing Primary core into Retention */ +#ifdef DEBUG + UART_printf(" Primary core: Putting into Retention %s \n", + LBIST_TestHandleArray[coreIndex].coreName); +#endif + status = Sciclient_pmSetModuleState(LBIST_TestHandleArray[coreIndex].tisciDeviceId, + TISCI_MSG_VALUE_DEVICE_SW_STATE_RETENTION, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + + if (status != SDL_PASS) + { + UART_printf(" Primary core: Sciclient_pmSetModuleState 0x%x ...FAILED \n", + LBIST_TestHandleArray[coreIndex].tisciDeviceId); + testResult = -1; + } + } + + /**--- Step 3g: Place Secondary core into retention ---*/ + if (testResult == 0) + { + if (LBIST_TestHandleArray[coreIndex].secondaryCoreNeeded) + { + /* Placing Secondary core into Retention */ +#ifdef DEBUG + UART_printf(" Secondary core: Putting into Retention %s \n", + LBIST_TestHandleArray[coreIndex].secCoreName); +#endif + status = Sciclient_pmSetModuleState(LBIST_TestHandleArray[coreIndex].tisciSecDeviceId, + TISCI_MSG_VALUE_DEVICE_SW_STATE_RETENTION, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Secondary core: Sciclient_pmSetModuleState 0x%x ...FAILED \n", + LBIST_TestHandleArray[coreIndex].tisciSecDeviceId); + testResult = -1; + return testResult; + } + } + } + + /**--- Step 3h: Power off Secondary core ---*/ + if (testResult == 0) + { + if (LBIST_TestHandleArray[coreIndex].secondaryCoreNeeded) + { + /* Power off Secondary core */ +#ifdef DEBUG + UART_printf(" Secondary core: Powering off %s \n", + LBIST_TestHandleArray[coreIndex].secCoreName); +#endif + status = Sciclient_pmSetModuleState(LBIST_TestHandleArray[coreIndex].tisciSecDeviceId, + TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Secondary core: Sciclient_pmSetModuleState: Power off FAILED \n"); + testResult = -1; + } + } + } + + /**--- Step 3i: Power off Primary core ---*/ + if (testResult == 0) + { + /* Power off Primary core */ +#ifdef DEBUG + UART_printf(" Primary core: Powering off %s \n", + LBIST_TestHandleArray[coreIndex].coreName); +#endif + status = Sciclient_pmSetModuleState(LBIST_TestHandleArray[coreIndex].tisciDeviceId, + TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Primary core: Sciclient_pmSetModuleState: Power off FAILED \n"); + } + } + + /**--- Step 3j: Power off Auxilliary modules ---*/ + if (testResult == 0) + { + int i; + + /* Place all Auxilliary modules required for test into retention */ + for ( i = 0; i < LBIST_TestHandleArray[coreIndex].numAuxDevices; i++) + { +#ifdef DEBUG + UART_printf(" Powering off Device number %d Device Id %x\n", + i, + LBIST_TestHandleArray[coreIndex].auxDeviceIdsP[i]); +#endif + + status = Sciclient_pmSetModuleState(LBIST_TestHandleArray[coreIndex].auxDeviceIdsP[i], + TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Sciclient_pmSetModuleState 0x%x ...FAILED \n", + LBIST_TestHandleArray[coreIndex].auxDeviceIdsP[i]); + testResult = -1; + break; + } + } + } + + /**--- Step 3k: Take Primary core out of local reset ---*/ + if ((testResult == 0) && (LBIST_TestHandleArray[coreIndex].tisciDeviceId != 0U)) + { +#ifdef DEBUG + UART_printf(" Primary core: Taking out of local reset the core %s \n", + LBIST_TestHandleArray[coreIndex].coreName); +#endif + status = Sciclient_pmSetModuleRst(LBIST_TestHandleArray[coreIndex].tisciDeviceId, + 0x0, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Sciclient_pmSetModuleRst 0x%x ...FAILED \n", + LBIST_TestHandleArray[coreIndex].tisciDeviceId); + testResult = -1; + } + } + + /**--- Step 3l: Take Secondary core out of local reset ---*/ + if ((testResult == 0) && (LBIST_TestHandleArray[coreIndex].tisciSecDeviceId != 0U)) + { +#ifdef DEBUG + UART_printf(" Secondary core: Taking out of local reset the core %s \n", + LBIST_TestHandleArray[coreIndex].secCoreName); +#endif + status = Sciclient_pmSetModuleRst(LBIST_TestHandleArray[coreIndex].tisciSecDeviceId, + 0x0, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Sciclient_pmSetModuleRst 0x%x ...FAILED \n", + LBIST_TestHandleArray[coreIndex].tisciSecDeviceId); + testResult = -1; + } + } + + /**--- Step 3m: Take Auxilliary modules out of module reset ---*/ + if (testResult == 0) + { + int i; + + /* Place all Auxilliary modules required for test into module reset */ + for ( i = 0; i < LBIST_TestHandleArray[coreIndex].numAuxDevices; i++) + { +#ifdef DEBUG + UART_printf(" Putting into module reset Device number %d Device Id %x\n", + i, + LBIST_TestHandleArray[coreIndex].auxDeviceIdsP[i]); +#endif + + status = Sciclient_pmSetModuleRst(LBIST_TestHandleArray[coreIndex].auxDeviceIdsP[i], + 0x0, // Need to keep Local Reset too?? + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Sciclient_pmSetModuleState 0x%x ...FAILED \n", + LBIST_TestHandleArray[coreIndex].auxDeviceIdsP[i]); + testResult = -1; + break; + } + } + } + + /**--- Step 3n: Release Primary core ---*/ + if ((testResult == 0) && (LBIST_TestHandleArray[coreIndex].tisciProcId !=0)) + { + /* release processor Primary core */ +#ifdef DEBUG + UART_printf(" Primary core: Releasing %s \n", + LBIST_TestHandleArray[coreIndex].coreName); +#endif + + status = Sciclient_procBootReleaseProcessor(LBIST_TestHandleArray[coreIndex].tisciProcId, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Primary core: Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n", + LBIST_TestHandleArray[coreIndex].tisciProcId); + testResult = -1; + } + } + + /**--- Step 3o: Release Secondary core ---*/ + if (testResult == 0) + { + if ((LBIST_TestHandleArray[coreIndex].secondaryCoreNeeded) + && (LBIST_TestHandleArray[coreIndex].tisciSecDeviceId != 0u)) + { + /* release processor Secondary core */ +#ifdef DEBUG + UART_printf(" Secondary core: Releasing %s \n", + LBIST_TestHandleArray[coreIndex].secCoreName); +#endif + status = Sciclient_procBootReleaseProcessor(LBIST_TestHandleArray[coreIndex].tisciSecProcId, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Secondary core: Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n", + LBIST_TestHandleArray[coreIndex].tisciSecProcId); + testResult = -1; + } + } + } + +#if defined(PROFILE_LBIST_TIMING) + prepTime = testStartTime - startTime; + diffTime = testEndTime - testStartTime; + restoreTime = endTime - testEndTime; + + UART_printf(" Delta Cores prep time in micro secs %d \n", + (uint32_t)prepTime); + UART_printf(" Delta LBIST execution time in micro secs %d \n", + (uint32_t)diffTime); + UART_printf(" Delta Cores restore time in micro secs %d \n", + (uint32_t)restoreTime); + UART_printf(" LBIST complete for %s \n", + LBIST_TestHandleArray[coreIndex].coreName); +#endif + } /* else clause of "if ((testResult == 0) && + * (LBIST_TestHandleArray[coreIndex].hwPostCoreCheck == true))" */ + + return (testResult); +} + +const char *LBIST_hwPostStatusPrint(int32_t postStatus) +{ + char *name; + + switch(postStatus) + { + case (LBIST_POST_COMPLETED_SUCCESS): + name="LBIST_POST_COMPLETED_SUCCESS"; + break; + case (LBIST_POST_COMPLETED_FAILURE): + name="LBIST_POST_COMPLETED_FAILURE"; + break; + case (LBIST_POST_ATTEMPTED_TIMEOUT): + name="LBIST_POST_ATTEMPTED_TIMEOUT"; + break; + case (LBIST_POST_NOT_RUN): + name="LBIST_POST_NOT_RUN"; + break; + case (LBIST_POST_INVALID_MISR_SEED_INPUT): + name="LBIST_POST_INVALID_MISR_SEED_INPUT"; + break; + default: + name="INVALID ID"; + break; + } + + return name; +} diff --git a/packages/ti/boot/sbl/example/boot_app/bist/lbist_utils.h b/packages/ti/boot/sbl/example/boot_app/bist/lbist_utils.h new file mode 100644 index 00000000..5f80d3ad --- /dev/null +++ b/packages/ti/boot/sbl/example/boot_app/bist/lbist_utils.h @@ -0,0 +1,92 @@ +/* +* +* Copyright (c) 2020 Texas Instruments Incorporated +* +* All rights reserved not granted herein. +* +* Limited License. +* +* Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive +* license under copyrights and patents it now or hereafter owns or controls to make, +* have made, use, import, offer to sell and sell ("Utilize") this software subject to the +* terms herein. With respect to the foregoing patent license, such license is granted +* solely to the extent that any such patent is necessary to Utilize the software alone. +* The patent license shall not apply to any combinations which include this software, +* other than combinations with devices manufactured by or for TI ("TI Devices"). +* No hardware patent is licensed hereunder. +* +* Redistributions must preserve existing copyright notices and reproduce this license +* (including the above copyright notice and the disclaimer and (if applicable) source +* code license limitations below) in the documentation and/or other materials provided +* with the distribution +* +* Redistribution and use in binary form, without modification, are permitted provided +* that the following conditions are met: +* +* * No reverse engineering, decompilation, or disassembly of this software is +* permitted with respect to any software provided in binary form. +* +* * any redistribution and use are licensed by TI for use only with TI Devices. +* +* * Nothing shall obligate TI to provide you with source code for the software +* licensed and provided to you in object code. +* +* If software source code is provided to you, modification and redistribution of the +* source code are permitted provided that the following conditions are met: +* +* * any redistribution and use of the source code, including any resulting derivative +* works, are licensed by TI for use only with TI Devices. +* +* * any redistribution and use of any object code compiled from the source code +* and any resulting derivative works, are licensed by TI for use only with TI Devices. +* +* Neither the name of Texas Instruments Incorporated nor the names of its suppliers +* +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* DISCLAIMER. +* +* THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS +* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED +* OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + +/* Protection against multiple inclusion */ +#ifndef LBIST_UTILS_H_ +#define LBIST_UTILS_H_ + +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ +#include + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ + +#define MSG_NORMAL (APP_UTILS_PRINT_MSG_NORMAL) +#define MSG_STATUS (APP_UTILS_PRINT_MSG_STATUS) + +/* HW POST run status definitions */ +#define LBIST_POST_COMPLETED_SUCCESS (0u) +#define LBIST_POST_COMPLETED_FAILURE (1u) +#define LBIST_POST_ATTEMPTED_TIMEOUT (2u) +#define LBIST_POST_NOT_RUN (3u) +#define LBIST_POST_INVALID_MISR_SEED_INPUT (4u) + +/* ========================================================================== */ +/* Function Declarations */ +/* ========================================================================== */ +int32_t LBIST_runTest(uint32_t coreIndex); +const char *LBIST_hwPostStatusPrint(int32_t postStatus); + +#endif /* LBIST_UTILS_H_ */ diff --git a/packages/ti/boot/sbl/example/boot_app/bist/pbist_utils.c b/packages/ti/boot/sbl/example/boot_app/bist/pbist_utils.c new file mode 100644 index 00000000..ea296890 --- /dev/null +++ b/packages/ti/boot/sbl/example/boot_app/bist/pbist_utils.c @@ -0,0 +1,1640 @@ +/* +* +* Copyright (c) 2022 Texas Instruments Incorporated +* +* All rights reserved not granted herein. +* +* Limited License. +* +* Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive +* license under copyrights and patents it now or hereafter owns or controls to make, +* have made, use, import, offer to sell and sell ("Utilize") this software subject to the +* terms herein. With respect to the foregoing patent license, such license is granted +* solely to the extent that any such patent is necessary to Utilize the software alone. +* The patent license shall not apply to any combinations which include this software, +* other than combinations with devices manufactured by or for TI ("TI Devices"). +* No hardware patent is licensed hereunder. +* +* Redistributions must preserve existing copyright notices and reproduce this license +* (including the above copyright notice and the disclaimer and (if applicable) source +* code license limitations below) in the documentation and/or other materials provided +* with the distribution +* +* Redistribution and use in binary form, without modification, are permitted provided +* that the following conditions are met: +* +* * No reverse engineering, decompilation, or disassembly of this software is +* permitted with respect to any software provided in binary form. +* +* * any redistribution and use are licensed by TI for use only with TI Devices. +* +* * Nothing shall obligate TI to provide you with source code for the software +* licensed and provided to you in object code. +* +* If software source code is provided to you, modification and redistribution of the +* source code are permitted provided that the following conditions are met: +* +* * any redistribution and use of the source code, including any resulting derivative +* works, are licensed by TI for use only with TI Devices. +* +* * any redistribution and use of any object code compiled from the source code +* and any resulting derivative works, are licensed by TI for use only with TI Devices. +* +* Neither the name of Texas Instruments Incorporated nor the names of its suppliers +* +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* DISCLAIMER. +* +* THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS +* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED +* OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + +/** + * \file pbist_utils.c + * + * \brief PBIST utility functions + */ + +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Osal API header files */ +#include + +#include "power_seq.h" + +#include "pbist_utils.h" +#include "pbist_defs.h" + +//#include "app_utils.h" + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ + +/* This flag adds more verbose prints */ +/* #define DEBUG */ + +/* This is to power up the cores before test and power down afterwards */ +#define POWERUP_CORES_BEFORE_TEST + +/* This flag gathers timing information for each PBIST test */ +//#define PROFILE_PBIST_TIMING + + +/* ========================================================================== */ +/* Internal Function Declarations */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Structure Declarations */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Function Declarations */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Global Variables */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* External Variables */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Function Definitions */ +/* ========================================================================== */ + +/* PBIST_setFirewall: Sets firewall settings to be able to access CLEC registers */ + +#if defined(SOC_J721E) || defined(SOC_J721S2)|| defined(SOC_J784S4) + + +static int32_t PBIST_setFirewall(void) +{ + int32_t retVal = CSL_PASS; + uint32_t reqFlag = TISCI_MSG_FLAG_AOP | TISCI_MSG_FLAG_DEVICE_EXCLUSIVE; + uint32_t timeout = SCICLIENT_SERVICE_WAIT_FOREVER; + struct tisci_msg_fwl_set_firewall_region_req request; + Sciclient_ReqPrm_t reqParam = {0}; + Sciclient_RespPrm_t respParam = {0}; + #if defined(SOC_J721E) + request.fwl_id = (uint32_t)CSL_STD_FW_NAVSS0_NAV_SRAM0_ID; + #endif + #if defined(SOC_J721S2) + request.fwl_id = (uint32_t)CSL_STD_FW_NAVSS0_VIRTSS_NB_SLV0_MEM0_ID; + #endif + #if defined(SOC_J784S4) + request.fwl_id = (uint32_t)CSL_STD_FW_NAVSS0_VIRTSS_NB_SLV0_MEM0_ID; + #endif + request.region = (uint32_t) 1U; /* Pick up any unused region : 1 */ + request.n_permission_regs = CSL_FW_NUM_CBASS_FW_EP_REGION_PERMISSION; + request.control = (FW_REGION_ENABLE & CSL_CBASS_ISC_EP_REGION_CONTROL_ENABLE_MASK); + request.permissions[0] = (FW_MCU_R5F0_PRIVID << CSL_CBASS_FW_EP_REGION_PERMISSION_PRIV_ID_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_WRITE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_READ_SHIFT) + | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_CACHEABLE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_DEBUG_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_WRITE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_READ_SHIFT) + | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_CACHEABLE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_DEBUG_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_WRITE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_READ_SHIFT) + | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_CACHEABLE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_DEBUG_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_WRITE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_READ_SHIFT) + | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_CACHEABLE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_DEBUG_SHIFT); + request.permissions[1] = (FW_MCU_R5F0_PRIVID << CSL_CBASS_FW_EP_REGION_PERMISSION_PRIV_ID_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_WRITE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_READ_SHIFT) + | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_CACHEABLE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_DEBUG_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_WRITE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_READ_SHIFT) + | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_CACHEABLE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_DEBUG_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_WRITE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_READ_SHIFT) + | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_CACHEABLE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_DEBUG_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_WRITE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_READ_SHIFT) + | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_CACHEABLE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_DEBUG_SHIFT); + request.permissions[2] = (FW_MCU_R5F0_PRIVID << CSL_CBASS_FW_EP_REGION_PERMISSION_PRIV_ID_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_WRITE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_READ_SHIFT) + | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_CACHEABLE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_DEBUG_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_WRITE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_READ_SHIFT) + | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_CACHEABLE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_DEBUG_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_WRITE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_READ_SHIFT) + | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_CACHEABLE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_DEBUG_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_WRITE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_READ_SHIFT) + | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_CACHEABLE_SHIFT) + | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_DEBUG_SHIFT); + request.start_address = CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE; + request.end_address = CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE + CSL_COMPUTE_CLUSTER0_CLEC_REGS_SIZE; + + reqParam.messageType = (uint16_t) TISCI_MSG_SET_FWL_REGION; + reqParam.flags = (uint32_t) reqFlag; + reqParam.pReqPayload = (const uint8_t *) &request; + reqParam.reqPayloadSize = (uint32_t) sizeof (request); + reqParam.timeout = (uint32_t) timeout; + + respParam.flags = (uint32_t) 0; /* Populated by the API */ + respParam.pRespPayload = (uint8_t *) 0; + respParam.respPayloadSize = (uint32_t) 0; + + + if (((reqFlag & TISCI_MSG_FLAG_AOP) != TISCI_MSG_FLAG_AOP)&& + (reqFlag != 0U)) + { + retVal = CSL_EFAIL; + } + if (retVal == CSL_PASS) + { + retVal = Sciclient_service(&reqParam, &respParam); + } + if ((retVal != CSL_PASS) || + ((reqFlag != 0U) && + ((respParam.flags & TISCI_MSG_FLAG_ACK) != TISCI_MSG_FLAG_ACK))) + { + retVal = CSL_EFAIL; + } + return retVal; +} +#endif +int32_t SDL_OSAL_getClecOutputEvent(uint32_t *clecOutputEvt) +{ + int32_t retVal = SDL_PASS; +#if defined(SOC_J721E) || defined(SOC_J721S2) + *clecOutputEvt = CSLR_COMPUTE_CLUSTER0_CLEC_MSMC_EVENT_IN_COMPUTE_CLUSTER0_CORE_CORE_MSMC_INTR_12; +#endif +#if defined(SOC_J784S4) + *clecOutputEvt = 12; +#endif + return retVal; +} + +int32_t SDL_OSAL_releaseClecOutputEvent(uint32_t clecOutputEvt) +{ + return SDL_PASS; +} + +/* CLEC configuration for C7X and A72 instances */ +int32_t PBIST_clecConfig(uint32_t instance) +{ + #if defined(SOC_J721E) + SDL_ErrType_t status = SDL_EFAIL; + CSL_ClecEventConfig evtCfg; + + evtCfg.secureClaimEnable = 1U; + evtCfg.evtSendEnable = 1U; + evtCfg.rtMap = 2U; + evtCfg.c7xEvtNum = 0U; + + if (PBIST_TestHandleArray[instance].pbistInst == SDL_PBIST_INST_A72) + { + evtCfg.extEvtNum = CSLR_COMPUTE_CLUSTER0_CLEC_MSMC_EVENT_IN_COMPUTE_CLUSTER0_CORE_CORE_MSMC_INTR_12; + /* Configure interrupt router to take care of routing A72 PBIST interrupt event */ + status = CSL_clecConfigEvent((CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE, + CSLR_COMPUTE_CLUSTER0_CLEC_MSMC_EVENT_IN_COMPUTE_CLUSTER0_CORE_CORE_MSMC_INTR_8, + &evtCfg); + if (status != CSL_PASS) + { + UART_printf(" CSL_clecConfigEvent A72 failed \n"); + } + } + else if (PBIST_TestHandleArray[instance].pbistInst == SDL_PBIST_INST_C7X) + { + evtCfg.extEvtNum = CSLR_COMPUTE_CLUSTER0_CLEC_MSMC_EVENT_IN_COMPUTE_CLUSTER0_CORE_CORE_MSMC_INTR_12; + /* Configure interrupt router to take care of routing C7x PBIST interrupt event */ + status = CSL_clecConfigEvent((CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE, + CSLR_COMPUTE_CLUSTER0_CLEC_MSMC_EVENT_IN_COMPUTE_CLUSTER0_CORE_CORE_MSMC_INTR_12, + &evtCfg); + if (status != CSL_PASS) + { + UART_printf(" CSL_clecConfigEvent C7x failed \n"); + } + } + + return status; +#endif + +#if defined(SOC_J7200) + return SDL_PASS; +#endif + +#if defined(SOC_J721S2) + SDL_ErrType_t status = SDL_EFAIL; + CSL_ClecEventConfig evtCfg; + + evtCfg.secureClaimEnable = 1U; + evtCfg.evtSendEnable = 1U; + evtCfg.rtMap = 2U; + evtCfg.c7xEvtNum = 0U; + + + if (PBIST_TestHandleArray[instance].pbistInst == SDL_PBIST_INST_A72) + { + evtCfg.extEvtNum = CSLR_COMPUTE_CLUSTER0_CLEC_MSMC_EVENT_IN_COMPUTE_CLUSTER0_CORE_CORE_MSMC_INTR_12; + /* Configure interrupt router to take care of routing A72 PBIST interrupt event */ + status = CSL_clecConfigEvent((CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE, + CSLR_COMPUTE_CLUSTER0_CLEC_MSMC_EVENT_IN_COMPUTE_CLUSTER0_CORE_CORE_MSMC_INTR_8, + &evtCfg); + if (status != CSL_PASS) + { + UART_printf(" CSL_clecConfigEvent A72 failed \n"); + } + } + else if (PBIST_TestHandleArray[instance].pbistInst == SDL_PBIST_INST_C7X_0) + { + evtCfg.extEvtNum = CSLR_COMPUTE_CLUSTER0_CLEC_MSMC_EVENT_IN_COMPUTE_CLUSTER0_CORE_CORE_MSMC_INTR_12; + /* Configure interrupt router to take care of routing C7x PBIST interrupt event */ + status = CSL_clecConfigEvent((CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE, + CSLR_COMPUTE_CLUSTER0_CLEC_MSMC_EVENT_IN_COMPUTE_CLUSTER0_CORE_CORE_MSMC_INTR_12, + &evtCfg); + if (status != CSL_PASS) + { + UART_printf(" CSL_clecConfigEvent C7x_0 failed \n"); + } + } + else if (PBIST_TestHandleArray[instance].pbistInst == SDL_PBIST_INST_C7X_1) + { + evtCfg.extEvtNum = CSLR_COMPUTE_CLUSTER0_CLEC_MSMC_EVENT_IN_COMPUTE_CLUSTER0_CORE_CORE_MSMC_INTR_12; + /* Configure interrupt router to take care of routing C7x PBIST interrupt event */ + status = CSL_clecConfigEvent((CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE, + CSLR_COMPUTE_CLUSTER0_CLEC_MSMC_EVENT_IN_COMPUTE_CLUSTER0_CORE_CORE_MSMC_INTR_13, + &evtCfg); + if (status != CSL_PASS) + { + UART_printf(" CSL_clecConfigEvent C7x_1 failed \n"); + } + } + return status; +#endif +#if defined(SOC_J784S4) + SDL_ErrType_t status = SDL_EFAIL; + CSL_ClecEventConfig evtCfg; + int32_t retValue = 0; + if (retValue == 0) + { + evtCfg.secureClaimEnable = 1U; + evtCfg.evtSendEnable = 1U; + evtCfg.extEvtNum = 12; + evtCfg.rtMap = 2U; + evtCfg.c7xEvtNum = 0U; + evtCfg.acDru = 0U; + + /* Configure interrupt router to take care of routing A72_0_0 PBIST interrupt event */ + status = CSL_clecConfigEvent((CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE, + 8, + &evtCfg); + if (status != CSL_PASS) + { + UART_printf(" CSL_clecConfigEvent A72_0_0 failed \n"); + retValue = -1; + } + } + + if (retValue == 0) + { + evtCfg.extEvtNum = 12; + /* Configure interrupt router to take care of routing A72_0_1 PBIST interrupt event */ + status = CSL_clecConfigEvent((CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE, + 524, + &evtCfg); + if (status != CSL_PASS) + { + UART_printf(" CSL_clecConfigEvent A72_0_1 failed \n"); + retValue = -1; + } + } + if (retValue == 0) + { + evtCfg.extEvtNum = 12; + /* Configure interrupt router to take care of routing A72_1_0 PBIST interrupt event */ + status = CSL_clecConfigEvent((CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE, + 9, + &evtCfg); + if (status != CSL_PASS) + { + UART_printf(" CSL_clecConfigEvent A72_1_0 failed \n"); + retValue = -1; + } + } + if (retValue == 0) + { + evtCfg.extEvtNum = 12; + /* Configure interrupt router to take care of routing A72_1_1 PBIST interrupt event */ + status = CSL_clecConfigEvent((CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE, + 525, + &evtCfg); + if (status != CSL_PASS) + { + UART_printf(" CSL_clecConfigEvent A72_1_1 failed \n"); + retValue = -1; + } + } + if (retValue == 0) + { + evtCfg.extEvtNum = 12; + /* Configure interrupt router to take care of routing C7X_0 PBIST interrupt event */ + status = CSL_clecConfigEvent((CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE, + 12, + &evtCfg); + if (status != CSL_PASS) + { + UART_printf(" CSL_clecConfigEvent C7X_0 failed \n"); + retValue = -1; + } + } + if (retValue == 0) + { + evtCfg.extEvtNum = 12; + /* Configure interrupt router to take care of routing C7x_1 PBIST interrupt event */ + status = CSL_clecConfigEvent((CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE, + 13, + &evtCfg); + if (status != CSL_PASS) + { + UART_printf(" CSL_clecConfigEvent C7x_1 failed \n"); + retValue = -1; + } + } + if (retValue == 0) + { + evtCfg.extEvtNum = 12; + /* Configure interrupt router to take care of routing C7X_2 PBIST interrupt event */ + status = CSL_clecConfigEvent((CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE, + 14, + &evtCfg); + if (status != CSL_PASS) + { + UART_printf(" CSL_clecConfigEvent C7X_2 failed \n"); + retValue = -1; + } + } + if (retValue == 0) + { + evtCfg.extEvtNum = 12; + /* Configure interrupt router to take care of routing C7x_3 PBIST interrupt event */ + status = CSL_clecConfigEvent((CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE, + 22, + &evtCfg); + if (status != CSL_PASS) + { + UART_printf(" CSL_clecConfigEvent C7x_3 failed \n"); + retValue = -1; + } + } + if (retValue == 0) + { + evtCfg.extEvtNum = 12; + /* Configure interrupt router to take care of routing ANA_0 PBIST interrupt event */ + status = CSL_clecConfigEvent((CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE, + 520, + &evtCfg); + if (status != CSL_PASS) + { + UART_printf(" CSL_clecConfigEvent ANA_0 failed \n"); + retValue = -1; + } + } + if (retValue == 0) + { + evtCfg.extEvtNum = 12; + /* Configure interrupt router to take care of routing ANA_1 PBIST interrupt event */ + status = CSL_clecConfigEvent((CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE, + 521, + &evtCfg); + if (status != CSL_PASS) + { + UART_printf(" CSL_clecConfigEvent ANA_1 failed \n"); + retValue = -1; + } + } + if (retValue == 0) + { + evtCfg.extEvtNum = 12; + /* Configure interrupt router to take care of routing ANA_2 PBIST interrupt event */ + status = CSL_clecConfigEvent((CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE, + 522, + &evtCfg); + if (status != CSL_PASS) + { + UART_printf(" CSL_clecConfigEvent ANA_2 failed \n"); + retValue = -1; + } + } + if (retValue == 0) + { + evtCfg.extEvtNum = 12; + /* Configure interrupt router to take care of routing ANA_3 PBIST interrupt event */ + status = CSL_clecConfigEvent((CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE, + 523, + &evtCfg); + if (status != CSL_PASS) + { + UART_printf(" CSL_clecConfigEvent ANA_3 failed \n"); + retValue = -1; + } + } + + return status; + // return SDL_PASS; +#endif +} + +/* Captures common Initialization: currently initializes CLEC interrupt routing + for C7x & A72 */ +int32_t PBIST_commonInit(void) +{ + #if defined(SOC_J721E) || defined(SOC_J721S2)|| defined(SOC_J784S4) + CSL_ErrType_t status; + /* Add firewall entry to gain access to CLEC registers */ + status = PBIST_setFirewall(); + + if (status != CSL_PASS) + { + UART_printf( " PBIST_setFirewall failed \n"); + } + + return status; +#endif + +#if defined(SOC_J7200) + return SDL_PASS; +#endif +} + + +/* This function runs the full PBIST test for a particular section. + * It includes the following steps (each step has many sub-steps specificied + * in more details within the function). + * For HW POST PBIST: + * Step 1: Configure interrupt handler + * Step 2: Check POST results (already run at startup) + * + * For SW-initiated PBIST: + * Step 1: Configure interrupt handler + * Step 2: Configure processor to correct state + * Step 3: Run PBIST test (includes checking the result) + * Step 4: Restore cores + * */ + +int32_t PBIST_runTest(uint32_t instanceId, uint8_t test) +{ + int32_t testResult = 0; + SDL_ErrType_t status; + bool PBISTResult = true; + SDL_PBIST_testType testType; + uint32_t i = 0; + + uint32_t moduleState = TISCI_MSG_VALUE_DEVICE_HW_STATE_OFF; + uint32_t resetState = 0U; + uint32_t contextLossState = 0U; + +#if defined(PROFILE_PBIST_TIMING) + uint64_t startTime , testStartTime, testEndTime, endTime; + uint64_t prepTime, diffTime, restoreTime; +#endif + + #if defined (SOC_J7200) || defined (SOC_J721S2) || defined (SOC_J784S4) + if (test == PBIST_TEST_NEGATIVE) + { + UART_printf("\n Starting PBIST failure insertion test on %s, index %d...\n", + PBIST_TestHandleArray[instanceId].testName, + instanceId); + testType = SDL_PBIST_NEG_TEST; + } + else if (test == PBIST_TEST_POSITIVE) + { + UART_printf("\n Starting PBIST test on %s, index %d...\n", + PBIST_TestHandleArray[instanceId].testName, + instanceId); + testType = SDL_PBIST_TEST; + } + else + { + UART_printf("\n Starting PBIST Test Of ROM on %s, index %d...\n", + PBIST_TestHandleArray[instanceId].testName, + instanceId); + testType = SDL_PBIST_TEST_OF_ROM; + } + #else + if (test == 1u) + { + UART_printf("\n Starting PBIST failure insertion test on %s, index %d...\n", + PBIST_TestHandleArray[instanceId].testName, + instanceId); + testType = SDL_PBIST_NEG_TEST; + } + else + { + UART_printf("\n Starting PBIST test on %s, index %d...\n", + PBIST_TestHandleArray[instanceId].testName, + instanceId); + testType = SDL_PBIST_TEST; + } + #endif + +#if defined(PROFILE_PBIST_TIMING) + /* Get start time of test */ + startTime = TimerP_getTimeInUsecs(); +#endif + + /* Step 1: (if HW Power-On Self Test, i.e. POST) Check POST results */ + if ((testResult == 0) && + (PBIST_TestHandleArray[instanceId].numPostPbistToCheck > 0)) + { + if (test == 0u) + { +#ifdef DEBUG + UART_printf(" HW POST: Running test on HW POST, %d Instances \n", + PBIST_TestHandleArray[instanceId].numPostPbistToCheck); +#endif + SDL_PBIST_postResult result; + + status = SDL_PBIST_getPOSTStatus(&result); + + if (status != SDL_PASS) + { + testResult = -1; + UART_printf(" SDL_PBIST_getPOSTStatus failed: Status %d \n", status); + } + else + { + PBIST_printPostStatus(&result); + } + } + } + else + { + /* Step 2: (if SW-initiated PBIST) Configure processor to correct state */ + + /**--- Step 2a: Request Primary core ---*/ + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)) + { + if (PBIST_TestHandleArray[instanceId].tisciProcId != 0u) + { +#ifdef DEBUG + UART_printf(" Primary core: %s: Requesting processor \n", + PBIST_TestHandleArray[instanceId].coreName); +#endif + /* Request Primary core */ + status = Sciclient_procBootRequestProcessor(PBIST_TestHandleArray[instanceId].tisciProcId, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != CSL_PASS) + { + UART_printf(" Primary core: Sciclient_procBootRequestProcessor, ProcId 0x%x...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciProcId); + testResult = -1; + } + } + } + + /**--- Step 2b: Request Secondary core ---*/ + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)) + { + if ((PBIST_TestHandleArray[instanceId].secondaryCoreNeeded) + && (PBIST_TestHandleArray[instanceId].tisciSecProcId != 0u)) + { + +#ifdef DEBUG + UART_printf(" Secondary core: %s: Requesting processor \n", + PBIST_TestHandleArray[instanceId].secCoreName); +#endif + /* Request secondary core */ + status = Sciclient_procBootRequestProcessor(PBIST_TestHandleArray[instanceId].tisciSecProcId, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != CSL_PASS) + { + UART_printf(" Secondary core: Sciclient_procBootRequestProcessor, ProcId 0x%x...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciSecProcId); + testResult = -1; + } + } + } + +#if defined (SOC_J784S4) + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)) + { + if ((PBIST_TestHandleArray[instanceId].thirdCoreNeeded) + && (PBIST_TestHandleArray[instanceId].tisciThProcId != 0u)) + { + +#ifdef DEBUG + UART_printf(" Third core: %s: Requesting processor \n", + PBIST_TestHandleArray[instanceId].thCoreName); +#endif + /* Request third core */ + status = Sciclient_procBootRequestProcessor(PBIST_TestHandleArray[instanceId].tisciThProcId, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Third core: Sciclient_procBootRequestProcessor, ProcId 0x%x...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciThProcId); + testResult = -1; + } + } + } + + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)) + { + if ((PBIST_TestHandleArray[instanceId].fourthCoreNeeded) + && (PBIST_TestHandleArray[instanceId].tisciFoProcId != 0u)) + { + +#ifdef DEBUG + UART_printf(" Fourth core: %s: Requesting processor \n", + PBIST_TestHandleArray[instanceId].foCoreName); +#endif + /* Request fourth core */ + status = Sciclient_procBootRequestProcessor(PBIST_TestHandleArray[instanceId].tisciFoProcId, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Fourth core: Sciclient_procBootRequestProcessor, ProcId 0x%x...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciFoProcId); + testResult = -1; + } + } + } +#endif + /**--- Step 2c: Put Primary core in local reset ---*/ + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)) + { + if (PBIST_TestHandleArray[instanceId].tisciDeviceId != 0u) + { + /* Set Local reset for Primary core */ +#ifdef DEBUG + UART_printf(" %s: Primary core: Set module reset \n", + PBIST_TestHandleArray[instanceId].coreName); +#endif + status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciDeviceId, + 0x1, /* Local Reset asserted */ + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != CSL_PASS) + { + UART_printf(" Primary core: Sciclient_pmSetModuleRst...FAILED \n"); + testResult = -1; + } + } + } + + /**--- Step 2d: Put Secondary core in local reset ---*/ + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)) + { + if ((PBIST_TestHandleArray[instanceId].secondaryCoreNeeded) + && (PBIST_TestHandleArray[instanceId].tisciSecDeviceId != 0u)) + { + /* Set Local reset for Secondary core */ +#ifdef DEBUG + UART_printf(" %s: Secondary core: Set Module reset \n", + PBIST_TestHandleArray[instanceId].secCoreName); +#endif + status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciSecDeviceId, + 0x1, /* Local Reset asserted */ + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != CSL_PASS) + { + UART_printf(" Secondary core: Sciclient_pmSetModuleRst...FAILED \n"); + testResult = -1; + } + } + } + +#if defined(SOC_J784S4) + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)) + { + if ((PBIST_TestHandleArray[instanceId].thirdCoreNeeded) + && (PBIST_TestHandleArray[instanceId].tisciThDeviceId != 0u)) + { + /* Set Local reset for Third core */ +#ifdef DEBUG + UART_printf(" %s: Third core: Set Module reset \n", + PBIST_TestHandleArray[instanceId].thCoreName); +#endif + status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciThDeviceId, + 0x1, /* Local Reset asserted */ + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Third core: Sciclient_pmSetModuleRst...FAILED \n"); + testResult = -1; + } + } + } + + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)) + { + if ((PBIST_TestHandleArray[instanceId].fourthCoreNeeded) + && (PBIST_TestHandleArray[instanceId].tisciFoDeviceId != 0u)) + { + /* Set Local reset for Fourth core */ +#ifdef DEBUG + UART_printf(" %s: Fourth core: Set Module reset \n", + PBIST_TestHandleArray[instanceId].foCoreName); +#endif + status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciFoDeviceId, + 0x1, /* Local Reset asserted */ + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Fourth core: Sciclient_pmSetModuleRst...FAILED \n"); + testResult = -1; + } + } + } +#endif +#ifdef POWERUP_CORES_BEFORE_TEST + /**--- Step 2e: Perform any additional power sequencing, if needed ---*/ + /* Custom core power restore sequence - needed to allow core to be powered + * up later by Secondary Bootloader (SBL) */ + if ((testResult == 0) && + (PBIST_TestHandleArray[instanceId].coreCustPwrSeqNeeded) && + (PBIST_TestHandleArray[instanceId].tisciProcId != 0u)) + { + status = customPrepareForPowerUpSequence(PBIST_TestHandleArray[instanceId].tisciProcId); + if (status != CSL_PASS) + { + UART_printf(" Custom core power restore sequence, ProcId 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciProcId); + testResult = -1; + } + } + + /**--- Step 2f: Power up of Auxilliary modules needed to run test */ + if (testResult == 0) + { + /* Power all modules required for test */ + for ( i = 0; i < PBIST_TestHandleArray[instanceId].numAuxDevices; i++) + { +#ifdef DEBUG + UART_printf(" Powering on Device number %d Device Id %x\n", + i, PBIST_TestHandleArray[instanceId].auxDeviceIdsP[i]); +#endif + + status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].auxDeviceIdsP[i], + TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != CSL_PASS) + { + UART_printf(" Sciclient_pmSetModuleState 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].auxDeviceIdsP[i]); + testResult = -1; + break; + } + } + } + + /**--- Step 2g: Power up Primary core */ + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded) + && (PBIST_TestHandleArray[instanceId].tisciDeviceId != 0U)) + { + /* power on Primary core*/ +#ifdef DEBUG + UART_printf(" Primary core: Powering on %s \n", + PBIST_TestHandleArray[instanceId].coreName); +#endif + status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciDeviceId, + TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + + if (status != CSL_PASS) + { + UART_printf(" Primary core: Sciclient_pmSetModuleState 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciDeviceId); + testResult = -1; + } + } + + /**--- Step 2h: Power up Secondary core */ + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded) + && (PBIST_TestHandleArray[instanceId].tisciSecDeviceId != 0U)) + { + if (PBIST_TestHandleArray[instanceId].secondaryCoreNeeded) + { + /* power on Secondary core*/ +#ifdef DEBUG + UART_printf(" Secondary core: Powering on %s \n", + PBIST_TestHandleArray[instanceId].secCoreName); +#endif + status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciSecDeviceId, + TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != CSL_PASS) + { + UART_printf(" Secondary core: Sciclient_pmSetModuleState 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciSecDeviceId); + testResult = -1; + return testResult; + } + } + } + +#if defined(SOC_J784S4) + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded) + && (PBIST_TestHandleArray[instanceId].tisciThDeviceId != 0U)) + { + if (PBIST_TestHandleArray[instanceId].thirdCoreNeeded) + { + /* power on Third core*/ +#ifdef DEBUG + UART_printf(" Third core: Powering on %s \n", + PBIST_TestHandleArray[instanceId].thCoreName); +#endif + status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciThDeviceId, + TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Third core: Sciclient_pmSetModuleState 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciThDeviceId); + testResult = -1; + return testResult; + } + } + } + + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded) + && (PBIST_TestHandleArray[instanceId].tisciFoDeviceId != 0U)) + { + if (PBIST_TestHandleArray[instanceId].fourthCoreNeeded) + { + /* power on Fourth core*/ +#ifdef DEBUG + UART_printf(" Fourth core: Powering on %s \n", + PBIST_TestHandleArray[instanceId].foCoreName); +#endif + status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciFoDeviceId, + TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Fourth core: Sciclient_pmSetModuleState 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciFoDeviceId); + testResult = -1; + return testResult; + } + } + } +#endif + /**--- Step 2i: Double check the Power up of Auxilliary modules needed to run test + * and wait until they are powered up */ + if (testResult == 0) + { + /* Wait for all modules required for test to be powered up */ + for ( i = 0; i < PBIST_TestHandleArray[instanceId].numAuxDevices; i++) + { +#ifdef DEBUG + UART_printf(" Double checking Powering on Device number %d Device Id %x\n", + i, PBIST_TestHandleArray[instanceId].auxDeviceIdsP[i]); +#endif + do + { + status = Sciclient_pmGetModuleState(PBIST_TestHandleArray[instanceId].auxDeviceIdsP[i], + &moduleState, + &resetState, + &contextLossState, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != CSL_PASS) + { + UART_printf(" Sciclient_pmGetModuleState 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].auxDeviceIdsP[i]); + testResult = -1; + break; + } + } while (moduleState != TISCI_MSG_VALUE_DEVICE_HW_STATE_ON); + } + } + + /**--- Step 2j: Double check the Power up of Primary core and wait until it is + * powered up */ + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded) + && (PBIST_TestHandleArray[instanceId].tisciDeviceId != 0U)) + { + /* Double check power on Primary core*/ +#ifdef DEBUG + UART_printf(" Primary core: Double checking Powering on %s \n", + PBIST_TestHandleArray[instanceId].coreName); +#endif + do + { + status = Sciclient_pmGetModuleState(PBIST_TestHandleArray[instanceId].tisciDeviceId, + &moduleState, + &resetState, + &contextLossState, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != CSL_PASS) + { + UART_printf(" Primary core: Sciclient_pmGetModuleState 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciDeviceId); + testResult = -1; + break; + } + } while (moduleState != TISCI_MSG_VALUE_DEVICE_HW_STATE_ON); + } + + /**--- Step 2k: Double check the Power up of Primary core and wait until it is + * powered up */ + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded) + && (PBIST_TestHandleArray[instanceId].tisciSecDeviceId != 0U)) + { + if (PBIST_TestHandleArray[instanceId].secondaryCoreNeeded) + { + /* Double check power on Secondary core*/ +#ifdef DEBUG + UART_printf(" Secondary core: Double checking Powering on %s \n", + PBIST_TestHandleArray[instanceId].coreName); +#endif + do + { + status = Sciclient_pmGetModuleState(PBIST_TestHandleArray[instanceId].tisciSecDeviceId, + &moduleState, + &resetState, + &contextLossState, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != CSL_PASS) + { + UART_printf(" Secondary core: Sciclient_pmGetModuleState 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciSecDeviceId); + testResult = -1; + break; + } + } while (moduleState != TISCI_MSG_VALUE_DEVICE_HW_STATE_ON); + } + } + +#if defined(SOC_J784S4) + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded) + && (PBIST_TestHandleArray[instanceId].tisciThDeviceId != 0U)) + { + if (PBIST_TestHandleArray[instanceId].thirdCoreNeeded) + { + /* Double check power on Third core*/ +#ifdef DEBUG + UART_printf( + " Third core: Double checking Powering on %s \n", + PBIST_TestHandleArray[instanceId].thCoreName); +#endif + do + { + status = Sciclient_pmGetModuleState(PBIST_TestHandleArray[instanceId].tisciThDeviceId, + &moduleState, + &resetState, + &contextLossState, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Third core: Sciclient_pmGetModuleState 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciThDeviceId); + testResult = -1; + break; + } + } while (moduleState != TISCI_MSG_VALUE_DEVICE_HW_STATE_ON); + } + } + + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded) + && (PBIST_TestHandleArray[instanceId].tisciFoDeviceId != 0U)) + { + if (PBIST_TestHandleArray[instanceId].fourthCoreNeeded) + { + /* Double check power on Fourth core*/ +#ifdef DEBUG + UART_printf( + " Fourth core: Double checking Powering on %s \n", + PBIST_TestHandleArray[instanceId].foCoreName); +#endif + do + { + status = Sciclient_pmGetModuleState(PBIST_TestHandleArray[instanceId].tisciFoDeviceId, + &moduleState, + &resetState, + &contextLossState, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Fourth core: Sciclient_pmGetModuleState 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciFoDeviceId); + testResult = -1; + break; + } + } while (moduleState != TISCI_MSG_VALUE_DEVICE_HW_STATE_ON); + } + } +#endif +#endif /* #ifdef POWERUP_CORES_BEFORE_TEST */ + /**--- Step 2l: Power up PBIST */ + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].tisciPBISTDeviceId != 0u)) + { +#ifdef DEBUG + UART_printf(" Powering on PBIST %d \n", + PBIST_TestHandleArray[instanceId].tisciPBISTDeviceId); +#endif + status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciPBISTDeviceId, + TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + + if (status != CSL_PASS) + { + UART_printf(" PBIST Sciclient_pmSetModuleState 0x%x ...FAILED: retValue %d\n", + PBIST_TestHandleArray[instanceId].tisciPBISTDeviceId, status); + testResult = -1; + } + } + + /**--- Step 2m: Execute Auxialliary init function for any final core-internal register + * setup needed for the PBIST test */ + if (testResult == 0) + { + if (PBIST_TestHandleArray[instanceId].auxInitRestoreFunction != 0) + { + status = PBIST_TestHandleArray[instanceId].auxInitRestoreFunction(TRUE); + if (status != CSL_PASS) + { + testResult = -1; + } + } + } + +#if defined(PROFILE_PBIST_TIMING) + /* Get start time for PBIST test */ + testStartTime = TimerP_getTimeInUsecs(); +#endif + + /**-- Step 3: Run PBIST test. --*/ + status = SDL_PBIST_selfTest((SDL_PBIST_inst)PBIST_TestHandleArray[instanceId].pbistInst, testType, NULL, &PBISTResult); + if ((status != SDL_PASS) || (PBISTResult == false)) + { + testResult = -1; + } + +#if defined(PROFILE_PBIST_TIMING) + /* Record test end time */ + testEndTime = TimerP_getTimeInUsecs(); +#endif + + /**-- Step 4: Restore cores --*/ + + /**--- Step 4a: Execute Auxilliary restore function to restore core-internal + * registers to original state */ + if (testResult == 0) + { + + if (PBIST_TestHandleArray[instanceId].auxInitRestoreFunction != 0) + { + status = PBIST_TestHandleArray[instanceId].auxInitRestoreFunction(FALSE); + if (status != CSL_PASS) + { + testResult = -1; + } + } + } + + /**--- Step 4b: Power off PBIST */ + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].tisciPBISTDeviceId != 0u)) + { +#ifdef DEBUG + UART_printf(" Powering off PBIST %d \n", + PBIST_TestHandleArray[instanceId].tisciPBISTDeviceId); +#endif + status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciPBISTDeviceId, + TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + + if (status != CSL_PASS) + { + UART_printf(" PBIST Sciclient_pmSetModuleState 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciPBISTDeviceId); + testResult = -1; + } + } +#ifdef POWERUP_CORES_BEFORE_TEST +#if defined(SOC_J784S4) + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded) + && (PBIST_TestHandleArray[instanceId].tisciFoDeviceId != 0U)) + { + if (PBIST_TestHandleArray[instanceId].fourthCoreNeeded) + { + /* power off Fourth core*/ +#ifdef DEBUG + UART_printf(" Fourth core: Powering off %s \n", + PBIST_TestHandleArray[instanceId].foCoreName); +#endif + status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciFoDeviceId, + TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Fourth core: Sciclient_pmSetModuleState Power off 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciFoDeviceId); + testResult = -1; + return testResult; + } + } + } + + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded) + && (PBIST_TestHandleArray[instanceId].tisciThDeviceId != 0U)) + { + if (PBIST_TestHandleArray[instanceId].thirdCoreNeeded) + { + /* power off Third core*/ +#ifdef DEBUG + UART_printf(" Third core: Powering off %s \n", + PBIST_TestHandleArray[instanceId].thCoreName); +#endif + status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciThDeviceId, + TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Third core: Sciclient_pmSetModuleState Power off 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciThDeviceId); + testResult = -1; + return testResult; + } + } + } +#endif + + /**--- Step 4c: Power off Secondary core */ + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded) + && (PBIST_TestHandleArray[instanceId].tisciSecDeviceId != 0U)) + { + if (PBIST_TestHandleArray[instanceId].secondaryCoreNeeded) + { + /* power off Secondary core*/ +#ifdef DEBUG + UART_printf(" Secondary core: Powering off %s \n", + PBIST_TestHandleArray[instanceId].secCoreName); +#endif + status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciSecDeviceId, + TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != CSL_PASS) + { + UART_printf(" Secondary core: Sciclient_pmSetModuleState Power off 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciSecDeviceId); + testResult = -1; + return testResult; + } + } + } + + /**--- Step 4d: Perform any custom/core-specific power down sequence */ + if ((testResult == 0) && + (PBIST_TestHandleArray[instanceId].coreCustPwrSeqNeeded) && + (PBIST_TestHandleArray[instanceId].tisciProcId != 0u)) + { + status = customPowerDownSequence(PBIST_TestHandleArray[instanceId].tisciProcId); + if (status != CSL_PASS) + { + UART_printf(" Custom core power down sequence, ProcId 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciProcId); + testResult = -1; + } + } + + /**--- Step 4e: Power off Primary core */ + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].tisciProcId != 0u) + && (PBIST_TestHandleArray[instanceId].procRstNeeded)) + { + /* power off Primary core*/ +#ifdef DEBUG + UART_printf(" Primary core: Powering off %s \n", + PBIST_TestHandleArray[instanceId].coreName); +#endif + status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciDeviceId, + TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + + if (status != CSL_PASS) + { + UART_printf(" Primary core: Sciclient_pmSetModuleState Power off 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciDeviceId); + testResult = -1; + } + } + +#ifndef SOC_J784S4 + /**--- Step 4f: Power off of Auxilliary modules needed to run test */ + if (testResult == 0) + { + /* Power all modules required for test */ + for ( i = 0; i < PBIST_TestHandleArray[instanceId].numAuxDevices; i++) + { +#ifdef DEBUG + UART_printf(" Powering off Device number %d Device Id %x\n", + i, PBIST_TestHandleArray[instanceId].auxDeviceIdsP[i]); +#endif + status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].auxDeviceIdsP[i], + TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != CSL_PASS) + { + UART_printf(" Sciclient_pmSetModuleState 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].auxDeviceIdsP[i]); + testResult = -1; + break; + } + } + } +#endif + + /**--- Step 4g: Perform any custom/core-specific power restore sequence needed to + * allow core to be powered up properly later */ + if ((testResult == 0) && + (PBIST_TestHandleArray[instanceId].coreCustPwrSeqNeeded) && + (PBIST_TestHandleArray[instanceId].tisciProcId != 0u)) + { + status = customPrepareForPowerUpSequence(PBIST_TestHandleArray[instanceId].tisciProcId); + if (status != CSL_PASS) + { + UART_printf(" Custom core power restore sequence, ProcId 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciProcId); + testResult = -1; + } + } + + /**--- Step 4h: Take Primary core out of local reset */ + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded) + && (PBIST_TestHandleArray[instanceId].tisciDeviceId != 0U)) + { +#ifdef DEBUG + UART_printf(" Primary core: Taking out of local reset the core %s \n", + PBIST_TestHandleArray[instanceId].coreName); +#endif + status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciDeviceId, + 0x0, /* Local Reset de-asserted */ + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != CSL_PASS) + { + UART_printf(" Sciclient_pmSetModuleRst 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciDeviceId); + testResult = -1; + } + } + + /**--- Step 4i: Take Secondary core out of local reset */ + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded) + && (PBIST_TestHandleArray[instanceId].tisciSecDeviceId != 0U)) + { +#ifdef DEBUG + UART_printf(" Secondary core: Taking out of local reset the core %s \n", + PBIST_TestHandleArray[instanceId].secCoreName); +#endif + status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciSecDeviceId, + 0x0, /* Local Reset de-asserted */ + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != CSL_PASS) + { + UART_printf(" Sciclient_pmSetModuleRst 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciSecDeviceId); + testResult = -1; + } + } +#if defined(SOC_J784S4) + /* Take Third core out of local reset */ + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded) + && (PBIST_TestHandleArray[instanceId].tisciThDeviceId != 0U)) + { +#ifdef DEBUG + UART_printf(" Third core: Taking out of local reset the core %s \n", + PBIST_TestHandleArray[instanceId].thCoreName); +#endif + status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciThDeviceId, + 0x0, /* Local Reset de-asserted */ + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Sciclient_pmSetModuleRst 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciThDeviceId); + testResult = -1; + } + } + + /* Take Fourth core out of local reset */ + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded) + && (PBIST_TestHandleArray[instanceId].tisciFoDeviceId != 0U)) + { +#ifdef DEBUG + UART_printf(" Third core: Taking out of local reset the core %s \n", + PBIST_TestHandleArray[instanceId].foCoreName); +#endif + status = Sciclient_pmSetModuleRst(PBIST_TestHandleArray[instanceId].tisciFoDeviceId, + 0x0, /* Local Reset de-asserted */ + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Sciclient_pmSetModuleRst 0x%x ...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciFoDeviceId); + testResult = -1; + } + } +#endif +#endif /* #ifdef POWERUP_CORES_BEFORE_TEST */ + /* Ensure that cores have been turned off to prepare for booting of the cores */ + + /**--- Step 4j: Power off Primary core */ + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)) + { + if (PBIST_TestHandleArray[instanceId].tisciDeviceId != 0u) + { + /* Set Software Reset Disable State for Primary core */ +#ifdef DEBUG + UART_printf(" %s: Primary core: Put in Software Reset Disable \n", + PBIST_TestHandleArray[instanceId].coreName); +#endif + status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciDeviceId, + TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != CSL_PASS) + { + UART_printf(" Primary core: Sciclient_pmSetModuleState...FAILED \n"); + testResult = -1; + } + } + } + + /**--- Step 4k: Power off Secondary core */ + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)) + { + if ((PBIST_TestHandleArray[instanceId].secondaryCoreNeeded) + && (PBIST_TestHandleArray[instanceId].tisciSecDeviceId != 0u)) + { + /* Set Software Reset Disable State for Secondary core */ +#ifdef DEBUG + UART_printf(" %s: Secondary Core Put in Software Reset Disable \n", + PBIST_TestHandleArray[instanceId].secCoreName); +#endif + status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciSecDeviceId, + TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != CSL_PASS) + { + UART_printf(" Secondary core Sciclient_pmSetModuleState...FAILED \n"); + testResult = -1; + } + } + } + +#if defined(SOC_J784S4) + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)) + { + if ((PBIST_TestHandleArray[instanceId].thirdCoreNeeded) + && (PBIST_TestHandleArray[instanceId].tisciThDeviceId != 0u)) + { + /* Set Software Reset Disable State for Third core */ +#ifdef DEBUG + UART_printf(" %s: Third Core Put in Software Reset Disable \n", + PBIST_TestHandleArray[instanceId].thCoreName); +#endif + status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciThDeviceId, + TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Third core Sciclient_pmSetModuleState...FAILED \n"); + testResult = -1; + } + } + } + + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].procRstNeeded)) + { + if ((PBIST_TestHandleArray[instanceId].fourthCoreNeeded) + && (PBIST_TestHandleArray[instanceId].tisciFoDeviceId != 0u)) + { + /* Set Software Reset Disable State for Fourth core */ +#ifdef DEBUG + UART_printf(" %s: Fourth Core Put in Software Reset Disable \n", + PBIST_TestHandleArray[instanceId].foCoreName); +#endif + status = Sciclient_pmSetModuleState(PBIST_TestHandleArray[instanceId].tisciFoDeviceId, + TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Fourth core Sciclient_pmSetModuleState...FAILED \n"); + testResult = -1; + } + } + } +#endif + + /**--- Step 4m: Release Primary core */ + if ((testResult == 0) && (PBIST_TestHandleArray[instanceId].tisciProcId != 0u) + && (PBIST_TestHandleArray[instanceId].procRstNeeded)) + { + /* release processor Primary core */ +#ifdef DEBUG + UART_printf(" Primary core: Releasing %s \n", + PBIST_TestHandleArray[instanceId].coreName); +#endif + + status = Sciclient_procBootReleaseProcessor(PBIST_TestHandleArray[instanceId].tisciProcId, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != CSL_PASS) + { + UART_printf(" Primary core: Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciProcId); + testResult = -1; + } + } + + /**--- Step 4n: Release Secondary core */ + if (testResult == 0) + { + if ((PBIST_TestHandleArray[instanceId].secondaryCoreNeeded) + && (PBIST_TestHandleArray[instanceId].tisciSecProcId != 0u) + && (PBIST_TestHandleArray[instanceId].procRstNeeded)) + { + /* release processor Secondary core */ +#ifdef DEBUG + UART_printf(" Secondary core: Releasing %s \n", + PBIST_TestHandleArray[instanceId].secCoreName); +#endif + status = Sciclient_procBootReleaseProcessor(PBIST_TestHandleArray[instanceId].tisciSecProcId, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != CSL_PASS) + { + UART_printf(" Secondary core: Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciSecProcId); + testResult = -1; + } + } + } + +#if defined(SOC_J784S4) + if (testResult == 0) + { + if ((PBIST_TestHandleArray[instanceId].thirdCoreNeeded) + && (PBIST_TestHandleArray[instanceId].tisciThProcId != 0u) + && (PBIST_TestHandleArray[instanceId].procRstNeeded)) + { + /* release processor Third core */ +#ifdef DEBUG + UART_printf(" Third core: Releasing %s \n", + PBIST_TestHandleArray[instanceId].thCoreName); +#endif + status = Sciclient_procBootReleaseProcessor(PBIST_TestHandleArray[instanceId].tisciThProcId, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Third core: Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciThProcId); + testResult = -1; + } + } + } + + if (testResult == 0) + { + if ((PBIST_TestHandleArray[instanceId].fourthCoreNeeded) + && (PBIST_TestHandleArray[instanceId].tisciFoProcId != 0u) + && (PBIST_TestHandleArray[instanceId].procRstNeeded)) + { + /* release processor Fourth core */ +#ifdef DEBUG + UART_printf(" Fourth core: Releasing %s \n", + PBIST_TestHandleArray[instanceId].foCoreName); +#endif + status = Sciclient_procBootReleaseProcessor(PBIST_TestHandleArray[instanceId].tisciFoProcId, + TISCI_MSG_FLAG_AOP, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf(" Fourth core: Sciclient_procBootReleaseProcessor, ProcId 0x%x...FAILED \n", + PBIST_TestHandleArray[instanceId].tisciFoProcId); + testResult = -1; + } + } + } +#endif +#if defined(PROFILE_PBIST_TIMING) + /* Record end time */ + endTime = TimerP_getTimeInUsecs(); + + prepTime = testStartTime - startTime; + diffTime = testEndTime - testStartTime; + restoreTime = endTime - testEndTime; + UART_printf(" Delta Cores prep time in micro secs %d \n", + (uint32_t)prepTime); + UART_printf(" Delta PBIST execution time in micro secs %d \n", + (uint32_t)diffTime); + UART_printf(" Delta Cores restore time in micro secs %d \n", + (uint32_t)restoreTime); + UART_printf(" PBIST complete %s, test index %d\n", + PBIST_TestHandleArray[instanceId].testName, + instanceId); +#endif + } + + return (testResult); +} diff --git a/packages/ti/boot/sbl/example/boot_app/bist/pbist_utils.h b/packages/ti/boot/sbl/example/boot_app/bist/pbist_utils.h new file mode 100644 index 00000000..76b6bf21 --- /dev/null +++ b/packages/ti/boot/sbl/example/boot_app/bist/pbist_utils.h @@ -0,0 +1,93 @@ +/* +* +* Copyright (c) 2020 Texas Instruments Incorporated +* +* All rights reserved not granted herein. +* +* Limited License. +* +* Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive +* license under copyrights and patents it now or hereafter owns or controls to make, +* have made, use, import, offer to sell and sell ("Utilize") this software subject to the +* terms herein. With respect to the foregoing patent license, such license is granted +* solely to the extent that any such patent is necessary to Utilize the software alone. +* The patent license shall not apply to any combinations which include this software, +* other than combinations with devices manufactured by or for TI ("TI Devices"). +* No hardware patent is licensed hereunder. +* +* Redistributions must preserve existing copyright notices and reproduce this license +* (including the above copyright notice and the disclaimer and (if applicable) source +* code license limitations below) in the documentation and/or other materials provided +* with the distribution +* +* Redistribution and use in binary form, without modification, are permitted provided +* that the following conditions are met: +* +* * No reverse engineering, decompilation, or disassembly of this software is +* permitted with respect to any software provided in binary form. +* +* * any redistribution and use are licensed by TI for use only with TI Devices. +* +* * Nothing shall obligate TI to provide you with source code for the software +* licensed and provided to you in object code. +* +* If software source code is provided to you, modification and redistribution of the +* source code are permitted provided that the following conditions are met: +* +* * any redistribution and use of the source code, including any resulting derivative +* works, are licensed by TI for use only with TI Devices. +* +* * any redistribution and use of any object code compiled from the source code +* and any resulting derivative works, are licensed by TI for use only with TI Devices. +* +* Neither the name of Texas Instruments Incorporated nor the names of its suppliers +* +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* DISCLAIMER. +* +* THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS +* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED +* OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + +/* Protection against multiple inclusion */ +#ifndef PBIST_UTILS_H_ +#define PBIST_UTILS_H_ + +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ + +#include +#include +#include + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ + +#define MSG_NORMAL (APP_UTILS_PRINT_MSG_NORMAL) +#define MSG_STATUS (APP_UTILS_PRINT_MSG_STATUS) + +#define PBIST_TEST_NEGATIVE 1 +#define PBIST_TEST_POSITIVE 0 +#define PBIST_TEST_ROM 3 + +/* ========================================================================== */ +/* Function Declarations */ +/* ========================================================================== */ +int32_t PBIST_clecConfig(uint32_t instance); +int32_t PBIST_commonInit(void); +int32_t PBIST_runTest(uint32_t instanceId, uint8_t test); + +#endif /* PBIST_UTILS_H_ */ diff --git a/packages/ti/boot/sbl/example/boot_app/bist/power_seq.c b/packages/ti/boot/sbl/example/boot_app/bist/power_seq.c new file mode 100644 index 00000000..e8d581a8 --- /dev/null +++ b/packages/ti/boot/sbl/example/boot_app/bist/power_seq.c @@ -0,0 +1,176 @@ +/* +* +* Copyright (c) 2020 Texas Instruments Incorporated +* +* All rights reserved not granted herein. +* +* Limited License. +* +* Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive +* license under copyrights and patents it now or hereafter owns or controls to make, +* have made, use, import, offer to sell and sell ("Utilize") this software subject to the +* terms herein. With respect to the foregoing patent license, such license is granted +* solely to the extent that any such patent is necessary to Utilize the software alone. +* The patent license shall not apply to any combinations which include this software, +* other than combinations with devices manufactured by or for TI ("TI Devices"). +* No hardware patent is licensed hereunder. +* +* Redistributions must preserve existing copyright notices and reproduce this license +* (including the above copyright notice and the disclaimer and (if applicable) source +* code license limitations below) in the documentation and/or other materials provided +* with the distribution +* +* Redistribution and use in binary form, without modification, are permitted provided +* that the following conditions are met: +* +* * No reverse engineering, decompilation, or disassembly of this software is +* permitted with respect to any software provided in binary form. +* +* * any redistribution and use are licensed by TI for use only with TI Devices. +* +* * Nothing shall obligate TI to provide you with source code for the software +* licensed and provided to you in object code. +* +* If software source code is provided to you, modification and redistribution of the +* source code are permitted provided that the following conditions are met: +* +* * any redistribution and use of the source code, including any resulting derivative +* works, are licensed by TI for use only with TI Devices. +* +* * any redistribution and use of any object code compiled from the source code +* and any resulting derivative works, are licensed by TI for use only with TI Devices. +* +* Neither the name of Texas Instruments Incorporated nor the names of its suppliers +* +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* DISCLAIMER. +* +* THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS +* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED +* OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + +/** + * \file power_seq.c + * + * \brief Custom core power sequence functions needed for proper powering + * beyond just control of SYSFW devices. + */ + +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ + +#include +#include +#include +#include + +#if defined (SOC_J721E) || defined (SOC_J7200) || defined (SOC_J721S2)|| defined (SOC_J784S4) +#include "armv8_power_utils.h" +#include "power_seq.h" +#endif + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Internal Function Declarations */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Structure Declarations */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Function Declarations */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Global Variables */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* External Variables */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Function Definitions */ +/* ========================================================================== */ + +/* Custom core power restore sequence contains any core-custom power steps + * needed prior to powering up, outside of device/power domain controls */ +int32_t customPrepareForPowerUpSequence(uint8_t processorId) +{ + int32_t status = SDL_EFAIL; + + switch(processorId) + { +#if defined (SOC_J721E) || defined (SOC_J7200) || defined (SOC_J721S2) + case (SCICLIENT_PROC_ID_A72SS0_CORE0): + status = armv8_powerPrepareForPowerUpSequence(processorId); + break; +#elif defined (SOC_J784S4) + case (SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE0_0): + case (SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE0_0): + status = armv8_powerPrepareForPowerUpSequence(processorId); + break; +#endif + default: + UART_printf("customPrepareForPowerUpSequence - Invalid ProcId %d\n", + processorId); + break; + } + + return (status); +} + +/* Custom core power down sequence contains any core-custom powerdown steps + * needed to be properly powered down, outside of device/power domain controls */ +int32_t customPowerDownSequence(uint8_t processorId) +{ + int32_t status = SDL_EFAIL; + + switch(processorId) + { +#if defined (SOC_J721E) || defined (SOC_J7200) || defined (SOC_J721S2) + case (SCICLIENT_PROC_ID_A72SS0_CORE0): + status = armv8_powerDownSequence(processorId); + break; +#elif defined (SOC_J784S4) + case (SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE0_0): + case (SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE0_0): + status = armv8_powerDownSequence(processorId); + break; +#endif + default: + UART_printf("customPowerDownSequence - Invalid ProcId %d\n", + processorId); + break; + } + + return (status); +} diff --git a/packages/ti/boot/sbl/example/boot_app/bist/power_seq.h b/packages/ti/boot/sbl/example/boot_app/bist/power_seq.h new file mode 100644 index 00000000..a08f6eb2 --- /dev/null +++ b/packages/ti/boot/sbl/example/boot_app/bist/power_seq.h @@ -0,0 +1,79 @@ +/* +* +* Copyright (c) 2020 Texas Instruments Incorporated +* +* All rights reserved not granted herein. +* +* Limited License. +* +* Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive +* license under copyrights and patents it now or hereafter owns or controls to make, +* have made, use, import, offer to sell and sell ("Utilize") this software subject to the +* terms herein. With respect to the foregoing patent license, such license is granted +* solely to the extent that any such patent is necessary to Utilize the software alone. +* The patent license shall not apply to any combinations which include this software, +* other than combinations with devices manufactured by or for TI ("TI Devices"). +* No hardware patent is licensed hereunder. +* +* Redistributions must preserve existing copyright notices and reproduce this license +* (including the above copyright notice and the disclaimer and (if applicable) source +* code license limitations below) in the documentation and/or other materials provided +* with the distribution +* +* Redistribution and use in binary form, without modification, are permitted provided +* that the following conditions are met: +* +* * No reverse engineering, decompilation, or disassembly of this software is +* permitted with respect to any software provided in binary form. +* +* * any redistribution and use are licensed by TI for use only with TI Devices. +* +* * Nothing shall obligate TI to provide you with source code for the software +* licensed and provided to you in object code. +* +* If software source code is provided to you, modification and redistribution of the +* source code are permitted provided that the following conditions are met: +* +* * any redistribution and use of the source code, including any resulting derivative +* works, are licensed by TI for use only with TI Devices. +* +* * any redistribution and use of any object code compiled from the source code +* and any resulting derivative works, are licensed by TI for use only with TI Devices. +* +* Neither the name of Texas Instruments Incorporated nor the names of its suppliers +* +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* DISCLAIMER. +* +* THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS +* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED +* OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + +/** + * \file power_seq.h + * + * \brief This header provides core-specific power sequence functions. + */ + +#ifndef __POWER_SEQ_H__ +#define __POWER_SEQ_H__ + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ +/* Function prototypes */ +int32_t customPrepareForPowerUpSequence(uint8_t processorId); +int32_t customPowerDownSequence(uint8_t processorId); + +#endif /* __POWER_SEQ_H__ */ diff --git a/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/armv8_power_utils.c b/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/armv8_power_utils.c new file mode 100755 index 00000000..63afe311 --- /dev/null +++ b/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/armv8_power_utils.c @@ -0,0 +1,233 @@ +/* +* +* Copyright (c) 2020 Texas Instruments Incorporated +* +* All rights reserved not granted herein. +* +* Limited License. +* +* Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive +* license under copyrights and patents it now or hereafter owns or controls to make, +* have made, use, import, offer to sell and sell ("Utilize") this software subject to the +* terms herein. With respect to the foregoing patent license, such license is granted +* solely to the extent that any such patent is necessary to Utilize the software alone. +* The patent license shall not apply to any combinations which include this software, +* other than combinations with devices manufactured by or for TI ("TI Devices"). +* No hardware patent is licensed hereunder. +* +* Redistributions must preserve existing copyright notices and reproduce this license +* (including the above copyright notice and the disclaimer and (if applicable) source +* code license limitations below) in the documentation and/or other materials provided +* with the distribution +* +* Redistribution and use in binary form, without modification, are permitted provided +* that the following conditions are met: +* +* * No reverse engineering, decompilation, or disassembly of this software is +* permitted with respect to any software provided in binary form. +* +* * any redistribution and use are licensed by TI for use only with TI Devices. +* +* * Nothing shall obligate TI to provide you with source code for the software +* licensed and provided to you in object code. +* +* If software source code is provided to you, modification and redistribution of the +* source code are permitted provided that the following conditions are met: +* +* * any redistribution and use of the source code, including any resulting derivative +* works, are licensed by TI for use only with TI Devices. +* +* * any redistribution and use of any object code compiled from the source code +* and any resulting derivative works, are licensed by TI for use only with TI Devices. +* +* Neither the name of Texas Instruments Incorporated nor the names of its suppliers +* +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* DISCLAIMER. +* +* THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS +* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED +* OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ +/** + * \file armv8_power_utils.c + * + * \brief This file defines functions to specifically handle + * proper power sequencing for the armv8 cores/cluster. + */ + +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ +#include +#include +#include + +#include + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ + +/* This flag adds more verbose prints */ +//#define DEBUG + +/* ========================================================================== */ +/* Global Variables */ +/* ========================================================================== */ + +/* ========================================================================== */ +/* External Variables */ +/* ========================================================================== */ + + +/* ========================================================================== */ +/* Function Definitions */ +/* ========================================================================== */ + +/* The following steps in the armv8_powerDownSequence() function are needed + * to ensure proper shutdown of the L2 system with ARMv8: + * 1. Assert AINACTS first (to idle the ACP) + * 2. Ensure system interrupts are disabled (N/A because this is boot sequence only) + * 3. Assert L2FLUSHREQ, and then check L2FLUSH_DONE status flag has been asserted + * 4. Deassert L2FLUSHREQ, and then check L2FLUSH_DONE status flag has been deasserted + * 5. Assert ACINACTM (to idle the AXI master interface) + * 6. Wait for STANDBY_WFI_L2 (STANDBYWFIL2) bit to be asserted + */ +int32_t armv8_powerDownSequence(uint8_t processorId) +{ + int32_t status = SDL_EFAIL; + +#ifdef DEBUG + UART_printf(" Running custom powerdown sequence for ARMv8 core\n"); +#endif + + /* Assert AINACTS first (to idle the ACP) - Set Bit 1 to 1 for asserting AINACTS */ + status = Sciclient_procBootSetSequenceCtrl(processorId, 0x00000002, 0x0, 0, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf("Sciclient_procBootSetSequenceCtrl...FAILED for AINACTS assert\n"); + } + + /* Assert L2FLUSHREQ - Set Bit 8 to 1 for asserting L2FLUSHREQ */ + if (status == SDL_PASS) { + status = Sciclient_procBootSetSequenceCtrl(processorId, 0x00000100, 0x0, 0, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf("Sciclient_procBootSetSequenceCtrl...FAILED for " \ + "L2FLUSHREQ assert/set\n"); + } + } + /* Check L2FLUSH_DONE has been asserted - Ensure that Bit 4 has been set to 1 */ + if (status == SDL_PASS) { + + status = Sciclient_procBootWaitProcessorState(processorId, 1, 1, + 0x00000010, 0x0, + 0x0, 0x0, 0, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf("Sciclient_procBootWaitProcessorState...FAILED for " \ + "L2FLUSH_DONE set\n"); + } + } + /* Deassert L2FLUSHREQ - Clear Bit 8 to 0 for deasserting L2FLUSHREQ */ + if (status == SDL_PASS) { + status = Sciclient_procBootSetSequenceCtrl(processorId, 0x0, 0x00000100, 0, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf("Sciclient_procBootSetSequenceCtrl...FAILED for " \ + "L2FLUSHREQ deassert/clear\n"); + } + } + + /* Check L2FLUSH_DONE has been deasserted - Ensure that Bit 4 has been cleared to 0 */ + if (status == SDL_PASS) { + + status = Sciclient_procBootWaitProcessorState(processorId, 1, 1, + 0x0, 0x0, + 0x00000010, 0x0, 0, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf("Sciclient_procBootWaitProcessorState...FAILED for " \ + "L2FLUSH_DONE clear \n"); + } + } + /* Assert ACINACTM (to idle the AXI master interface) - Set Bit 0 to 1 for asserting ACINACTM */ + if (status == SDL_PASS) { + status = Sciclient_procBootSetSequenceCtrl(processorId, 0x00000001, 0x0, 0, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf("Sciclient_procBootSetSequenceCtrl...FAILED for " \ + "ACINACTM assert/set \n"); + } + } + + return (status); +} + +/* The following steps in the armv8_powerPrepareForPowerUpSequence() function are needed + * to ensure the L2 system within ARMv8 is in a state where proper startup + * can occur from SBL calls: + * 1. Deassert L2FLUSHREQ. + * 2. Deassert AINACTS (to enable the ACP) + * 3. Deassert ACINACTM (to enable the AXI master interface) + * This sequence should be run when the cluster is powered down + * before any power up sequence. + */ +int32_t armv8_powerPrepareForPowerUpSequence(uint8_t processorId) +{ + int32_t status = SDL_EFAIL; + +#ifdef DEBUG + UART_printf(" Running custom power restore sequence for ARMv8 core\n"); +#endif + + /* Deassert L2FLUSHREQ - Clear Bit 8 to 0 for deasserting L2FLUSHREQ */ + if (status == SDL_PASS) { + status = Sciclient_procBootSetSequenceCtrl(processorId, 0x0, 0x00000100, 0, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf("Sciclient_procBootSetSequenceCtrl...FAILED for " \ + "L2FLUSHREQ deassert/clear\n"); + } + } + /* Deassert AINACTS - Clear Bit 1 to 0 for deasserting AINACTS */ + status = Sciclient_procBootSetSequenceCtrl(processorId, 0x0, 0x00000002, 0, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf("Sciclient_procBootSetSequenceCtrl...FAILED for AINACTS " \ + "deassert\n"); + } + + /* Deassert ACINACTM - Clear Bit 0 to 0 for deasserting ACINACTM */ + if (status == SDL_PASS) { + status = Sciclient_procBootSetSequenceCtrl(processorId, 0x0, 0x00000001, 0, + SCICLIENT_SERVICE_WAIT_FOREVER); + if (status != SDL_PASS) + { + UART_printf("Sciclient_procBootSetSequenceCtrl...FAILED for " \ + "ACINACTM deassert/clear \n"); + } + } + + + return (status); +} diff --git a/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/armv8_power_utils.h b/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/armv8_power_utils.h new file mode 100755 index 00000000..38dbe974 --- /dev/null +++ b/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/armv8_power_utils.h @@ -0,0 +1,64 @@ +/******************************************************************** + * Copyright (C) 2020 Texas Instruments Incorporated. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Name : armv8_power_utils.h +*/ +#ifndef ARMV8_POWER_UTILS_H_ +#define ARMV8_POWER_UTILS_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Function Declarations */ +/* ========================================================================== */ + +int32_t armv8_powerDownSequence(uint8_t processorId); +int32_t armv8_powerPrepareForPowerUpSequence(uint8_t processorId); + +#ifdef __cplusplus +} +#endif +#endif /* ARMV8_POWER_UTILS_H_ */ diff --git a/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/bist_core_defs.c b/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/bist_core_defs.c new file mode 100755 index 00000000..d88f5fab --- /dev/null +++ b/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/bist_core_defs.c @@ -0,0 +1,432 @@ +/* +* +* Copyright (c) 2020 Texas Instruments Incorporated +* +* All rights reserved not granted herein. +* +* Limited License. +* +* Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive +* license under copyrights and patents it now or hereafter owns or controls to make, +* have made, use, import, offer to sell and sell ("Utilize") this software subject to the +* terms herein. With respect to the foregoing patent license, such license is granted +* solely to the extent that any such patent is necessary to Utilize the software alone. +* The patent license shall not apply to any combinations which include this software, +* other than combinations with devices manufactured by or for TI ("TI Devices"). +* No hardware patent is licensed hereunder. +* +* Redistributions must preserve existing copyright notices and reproduce this license +* (including the above copyright notice and the disclaimer and (if applicable) source +* code license limitations below) in the documentation and/or other materials provided +* with the distribution +* +* Redistribution and use in binary form, without modification, are permitted provided +* that the following conditions are met: +* +* * No reverse engineering, decompilation, or disassembly of this software is +* permitted with respect to any software provided in binary form. +* +* * any redistribution and use are licensed by TI for use only with TI Devices. +* +* * Nothing shall obligate TI to provide you with source code for the software +* licensed and provided to you in object code. +* +* If software source code is provided to you, modification and redistribution of the +* source code are permitted provided that the following conditions are met: +* +* * any redistribution and use of the source code, including any resulting derivative +* works, are licensed by TI for use only with TI Devices. +* +* * any redistribution and use of any object code compiled from the source code +* and any resulting derivative works, are licensed by TI for use only with TI Devices. +* +* Neither the name of Texas Instruments Incorporated nor the names of its suppliers +* +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* DISCLAIMER. +* +* THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS +* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED +* OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ +/** + * \file bist_core_defs.c + * + * \brief This file defines available main domain bist modules and order of bist per stage + */ + +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ +#include +#include "bist_core_defs.h" + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Global Variables */ +/* ========================================================================== */ + +/* NOTE: The PBIST and LBIST tests that are run in each stage on this SOC are + * defined in this file. To make modifications, the user simply can add/remove/move + * ID's in the following arrays. + * Run before any booting of cores: + * pbist_pre_boot_stage + * lbist_pre_boot_stage + * Run before the first boot stage: + * pbist_first_boot_stage + * lbist_first_boot_stage + * Run before the second boot stage: + * pbist_second_boot_stage + * lbist_second_boot_stage + * Run before the third boot stage: + * pbist_third_boot_stage + * lbist_third_boot_stage + * Care should be taken to ensure that BIST sections for particular cores match + * the boot cores selected for each boot stage in soc//boot_core_defs.c. + * */ + + +/* Defines PBIST's needed for all cores before the first stage of the Main Domain + * boot sequence for J784S4 SOC */ +int pbist_pre_boot_stage[] = +{ + PBIST_HWPOST_MCU_INDEX, /* Read results of HW POST MCU PBIST */ + +}; + +int pbist_pre_boot_stage_status[] = +{ + 0, /* HW Post status */ +}; + +int pbist_pre_boot_stage_neg_status[] = +{ + 0, /* HW Post status */ +}; +int pbist_pre_boot_stage_rom_test_status[] = +{ + 0, /* HW Post status */ +}; + +/* Defines LBIST's needed for all cores before the first stage of the Main Domain + * boot sequence for J784S4 SOC */ +int lbist_pre_boot_stage[] = +{ + LBIST_HWPOST_INST_SMS_INDEX, /* Read results of HW POST SMS LBIST */ + LBIST_HWPOST_INST_MCU_INDEX /* Read results of HW POST MCU LBIST */ +}; + +int lbist_pre_boot_stage_status[] = +{ + 0, /* HW POST SMS LBIST */ + 0, /* HW POST MCU LBIST */ +}; + +/* Defines PBIST's for the first stage of the Main Domain + * boot sequence for J784S4 SOC */ +int pbist_first_boot_stage[] = +{ + PBIST_INSTANCE_MAINR5F0, + PBIST_INSTANCE_CODEC, + PBIST_INSTANCE_MAININFRA_1, + PBIST_INSTANCE_VPAC_0, + PBIST_INSTANCE_DSS, + PBIST_INSTANCE_DMPAC, + PBIST_INSTANCE_NAVSS, + PBIST_INSTANCE_MAININFRA_0, + PBIST_INSTANCE_GPU, + PBIST_INSTANCE_HC, + PBIST_INSTANCE_VPAC_1, + PBIST_INSTANCE_MAINR5F2, + PBIST_INSTANCE_CODEC_1, + PBIST_INSTANCE_A72_0_0, + PBIST_INSTANCE_A72_0_1, + PBIST_INSTANCE_A72_1_0, + PBIST_INSTANCE_A72_1_1, + PBIST_INSTANCE_C7X_0, + PBIST_INSTANCE_C7X_1, + PBIST_INSTANCE_C7X_2, + PBIST_INSTANCE_C7X_3, + PBIST_INSTANCE_ANA_0, + PBIST_INSTANCE_ANA_1, + PBIST_INSTANCE_ANA_2, + PBIST_INSTANCE_ANA_3, + PBIST_INSTANCE_MSMC, + PBIST_INSTANCE_MAINR5F1, + PBIST_INSTANCE_MCU_PSROM, + PBIST_INSTANCE_MCU_1, + PBIST_INSTANCE_MCU_PULSAR + +}; + +/* Defines LBIST's for the first stage of the Main Domain + * boot sequence for J784S4 SOC */ +int lbist_first_boot_stage[] = +{ + LBIST_INST_MAINR5F0_INDEX, + LBIST_INST_MAINR5F2_INDEX +}; +/* Defines LBIST's for the second stage of the Main Domain + * boot sequence for J784S4 SOC */ +int lbist_second_boot_stage[] = +{ + LBIST_INST_MAINR5F1_INDEX, + LBIST_INST_C7X0_INDEX, + LBIST_INST_C7X1_INDEX, + LBIST_INST_C7X2_INDEX, + LBIST_INST_C7X3_INDEX, + LBIST_INST_VPAC0_INDEX, + LBIST_INST_DMPAC_INDEX, + LBIST_INST_A72_0_INDEX, + LBIST_INST_A72_1_INDEX +}; + +/* Defines LBIST's for the third stage of the Main Domain + * boot sequence for J784S4 SOC */ +int lbist_third_boot_stage[] = +{ + LBIST_INST_A72SS0_CORE0_INDEX, + LBIST_INST_A72SS0_CORE1_INDEX, + LBIST_INST_A72SS0_CORE2_INDEX, + LBIST_INST_A72SS0_CORE3_INDEX, + LBIST_INST_A72SS1_CORE0_INDEX, + LBIST_INST_A72SS1_CORE1_INDEX, + LBIST_INST_A72SS1_CORE2_INDEX, + LBIST_INST_A72SS1_CORE3_INDEX + +}; + +/* Points to pbist arrays for each of the boot stages */ +int *pbist_array_stage[NUM_BOOT_STAGES] = +{ + pbist_first_boot_stage, +}; + +/* Points to lbist arrays for each of the boot stages */ +int *lbist_array_stage[NUM_BOOT_STAGES] = +{ + lbist_first_boot_stage, + lbist_second_boot_stage, + lbist_third_boot_stage +}; + +/* Defines number of LBIST's run in each stage */ +uint8_t num_lbists_per_boot_stage[NUM_BOOT_STAGES] = +{ + sizeof(lbist_first_boot_stage) / sizeof(int), + sizeof(lbist_second_boot_stage) / sizeof(int), + sizeof(lbist_third_boot_stage) / sizeof(int) +}; + +/* Defines number of PBIST's run in each stage */ +uint8_t num_pbists_per_boot_stage[NUM_BOOT_STAGES] = +{ + sizeof(pbist_first_boot_stage) / sizeof(int), +}; + +uint8_t num_lbists_pre_boot = sizeof(lbist_pre_boot_stage) / sizeof(int); +uint8_t num_pbists_pre_boot = sizeof(pbist_pre_boot_stage) / sizeof(int); + +const char *pbistName(uint32_t pbistID) +{ + char *name; + + switch(pbistID) + { + case (PBIST_HWPOST_MCU_INDEX): + name="PBIST_HWPOST_MCU_INDEX"; + break; + case (PBIST_INSTANCE_MAINR5F0): + name="PBIST_INSTANCE_MAINR5F0"; + break; + case (PBIST_INSTANCE_CODEC): + name="PBIST_INSTANCE_CODEC"; + break; + case (PBIST_INSTANCE_MAININFRA_1): + name="PBIST_INSTANCE_MAININFRA_1"; + break; + case (PBIST_INSTANCE_VPAC_0): + name="PBIST_INSTANCE_VPAC_0"; + break; + case (PBIST_INSTANCE_DSS): + name="PBIST_INSTANCE_DSS"; + break; + case (PBIST_INSTANCE_DMPAC): + name="PBIST_INSTANCE_DMPAC"; + break; + case (PBIST_INSTANCE_NAVSS): + name="PBIST_INSTANCE_NAVSS"; + break; + case (PBIST_INSTANCE_MAININFRA_0): + name="PBIST_INSTANCE_MAININFRA_0"; + break; + case (PBIST_INSTANCE_GPU): + name="PBIST_INSTANCE_GPU"; + break; + case (PBIST_INSTANCE_HC): + name="PBIST_INSTANCE_HC"; + break; + case (PBIST_INSTANCE_VPAC_1): + name="PBIST_INSTANCE_VPAC_1"; + break; + case (PBIST_INSTANCE_MAINR5F2): + name="PBIST_INSTANCE_MAINR5F2"; + break; + case (PBIST_INSTANCE_CODEC_1): + name="PBIST_INSTANCE_CODEC_1"; + break; + case (PBIST_INSTANCE_A72_0_0): + name="PBIST_INSTANCE_A72_0_0"; + break; + case (PBIST_INSTANCE_A72_0_1): + name="PBIST_INSTANCE_A72_0_1"; + break; + case (PBIST_INSTANCE_A72_1_0): + name="PBIST_INSTANCE_A72_1_0"; + break; + case (PBIST_INSTANCE_A72_1_1): + name="PBIST_INSTANCE_A72_1_1"; + break; + case (PBIST_INSTANCE_C7X_0): + name="PBIST_INSTANCE_C7X_0"; + break; + case (PBIST_INSTANCE_C7X_1): + name="PBIST_INSTANCE_C7X_1"; + break; + case (PBIST_INSTANCE_C7X_2): + name="PBIST_INSTANCE_C7X_2"; + break; + case (PBIST_INSTANCE_C7X_3): + name="PBIST_INSTANCE_C7X_3"; + break; + case (PBIST_INSTANCE_ANA_0): + name="PBIST_INSTANCE_ANA_0"; + break; + case (PBIST_INSTANCE_ANA_1): + name="PBIST_INSTANCE_ANA_1"; + break; + case (PBIST_INSTANCE_ANA_2): + name="PBIST_INSTANCE_ANA_2"; + break; + case (PBIST_INSTANCE_ANA_3): + name="PBIST_INSTANCE_ANA_3"; + break; + case (PBIST_INSTANCE_MSMC): + name="PBIST_INSTANCE_MSMC"; + break; + case (PBIST_INSTANCE_MAINR5F1): + name="PBIST_INSTANCE_MAINR5F1"; + break; + case (PBIST_INSTANCE_MCU_PSROM): + name="PBIST_INSTANCE_MCU_PSROM"; + break; + case (PBIST_INSTANCE_MCU_1): + name="PBIST_INSTANCE_MCU_1"; + break; + case (PBIST_INSTANCE_MCU_PULSAR): + name="PBIST_INSTANCE_MCU_PULSAR"; + break; + default: + name="INVALID ID"; + break; + } + + return name; +} + + +const char *lbistName(uint32_t lbistID) +{ + char *name; + + switch(lbistID) + { + case (LBIST_HWPOST_INST_SMS_INDEX): + name="LBIST_HWPOST_INST_SMS_INDEX"; + break; + case (LBIST_HWPOST_INST_MCU_INDEX): + name="LBIST_HWPOST_INST_MCU_INDEX"; + break; + case (LBIST_INST_MAINR5F0_INDEX): + name="LBIST_INST_MAINR5F0_INDEX"; + break; + case (LBIST_INST_MAINR5F1_INDEX): + name="LBIST_INST_MAINR5F1_INDEX"; + break; + case (LBIST_INST_C7X0_INDEX): + name="LBIST_INST_C7X0_INDEX"; + break; + case (LBIST_INST_C7X1_INDEX): + name="LBIST_INST_C7X1_INDEX"; + break; + case (LBIST_INST_VPAC0_INDEX): + name="LBIST_INST_VPAC0_INDEX"; + break; + case (LBIST_INST_DMPAC_INDEX): + name="LBIST_INST_DMPAC_INDEX"; + break; + case (LBIST_INST_A72_0_INDEX): + name="LBIST_INST_A72_0_INDEX"; + break; + case (LBIST_INST_VPAC1_INDEX): + name="LBIST_INST_VPAC1_INDEX"; + break; + case (LBIST_INST_A72_1_INDEX): + name="LBIST_INST_A72_1_INDEX"; + break; + case (LBIST_INST_C7X2_INDEX): + name="LBIST_INST_C7X2_INDEX"; + break; + case (LBIST_INST_C7X3_INDEX): + name="LBIST_INST_C7X3_INDEX"; + break; + case (LBIST_INST_A72SS0_CORE0_INDEX): + name="LBIST_INST_A72SS0_CORE0_INDEX"; + break; + case (LBIST_INST_A72SS0_CORE1_INDEX): + name="LBIST_INST_A72SS0_CORE1_INDEX"; + break; + case (LBIST_INST_A72SS0_CORE2_INDEX): + name="LBIST_INST_A72SS0_CORE2_INDEX"; + break; + case (LBIST_INST_A72SS0_CORE3_INDEX): + name="LBIST_INST_A72SS0_CORE3_INDEX"; + break; + case (LBIST_INST_A72SS1_CORE0_INDEX): + name="LBIST_INST_A72SS1_CORE0_INDEX"; + break; + case (LBIST_INST_A72SS1_CORE1_INDEX): + name="LBIST_INST_A72SS1_CORE1_INDEX"; + break; + case (LBIST_INST_A72SS1_CORE2_INDEX): + name="LBIST_INST_A72SS1_CORE2_INDEX"; + break; + case (LBIST_INST_A72SS1_CORE3_INDEX): + name="LBIST_INST_A72SS1_CORE3_INDEX"; + break; + case (LBIST_INST_MAINR5F2_INDEX): + name="LBIST_INST_MAINR5F2_INDEX"; + break; + default: + name="INVALID ID"; + break; + } + + return name; +} + diff --git a/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/bist_core_defs.h b/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/bist_core_defs.h new file mode 100755 index 00000000..fc693e38 --- /dev/null +++ b/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/bist_core_defs.h @@ -0,0 +1,176 @@ +/******************************************************************** + * Copyright (C) 2020 Texas Instruments Incorporated. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Name : bist_core_defs.h +*/ +#ifndef BIST_CORE_DEFS_H_ +#define BIST_CORE_DEFS_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ +/* Defines total number of Boot Stages for the Main Domain + * multi-stage boot sequence for J784S4 SOC */ +#define NUM_BOOT_STAGES 3 + +#define PBIST_HWPOST_MCU_INDEX (0U) +#define PBIST_INSTANCE_MAINR5F0 (1U) +#define PBIST_INSTANCE_CODEC (2U) +#define PBIST_INSTANCE_MAININFRA_1 (3U) +#define PBIST_INSTANCE_VPAC_0 (4U) +#define PBIST_INSTANCE_DSS (5U) +#define PBIST_INSTANCE_DMPAC (6U) +#define PBIST_INSTANCE_NAVSS (7U) +#define PBIST_INSTANCE_MAININFRA_0 (8U) +#define PBIST_INSTANCE_GPU (9U) +#define PBIST_INSTANCE_HC (10U) +#define PBIST_INSTANCE_VPAC_1 (11U) +#define PBIST_INSTANCE_MAINR5F2 (12U) +#define PBIST_INSTANCE_CODEC_1 (13U) +#define PBIST_INSTANCE_A72_0_0 (14U) +#define PBIST_INSTANCE_A72_0_1 (15U) +#define PBIST_INSTANCE_A72_1_0 (16U) +#define PBIST_INSTANCE_A72_1_1 (17U) +#define PBIST_INSTANCE_C7X_0 (18U) +#define PBIST_INSTANCE_C7X_1 (19U) +#define PBIST_INSTANCE_C7X_2 (20U) +#define PBIST_INSTANCE_C7X_3 (21U) +#define PBIST_INSTANCE_ANA_0 (22U) +#define PBIST_INSTANCE_ANA_1 (23U) +#define PBIST_INSTANCE_ANA_2 (24U) +#define PBIST_INSTANCE_ANA_3 (25U) +#define PBIST_INSTANCE_MSMC (26U) +#define PBIST_INSTANCE_MAINR5F1 (27U) +#define PBIST_INSTANCE_MCU_PSROM (28U) +#define PBIST_INSTANCE_MCU_1 (29U) +#define PBIST_INSTANCE_MCU_PULSAR (30U) + + +#define PBIST_MAX_INSTANCE (PBIST_INSTANCE_MCU_PULSAR+1) + +#define PBIST_INSTANCE_NAME_MAX_LENGTH 20 + +#define LBIST_HWPOST_INST_SMS_INDEX 0 +#define LBIST_HWPOST_INST_MCU_INDEX 1 +#define LBIST_INST_MAINR5F0_INDEX 2 +#define LBIST_INST_MAINR5F1_INDEX 3 +#define LBIST_INST_C7X0_INDEX 4 +#define LBIST_INST_C7X1_INDEX 5 +#define LBIST_INST_VPAC0_INDEX 6 +#define LBIST_INST_DMPAC_INDEX 7 +#define LBIST_INST_A72_0_INDEX 8 +#define LBIST_INST_VPAC1_INDEX 9 +#define LBIST_INST_A72_1_INDEX 10 +#define LBIST_INST_C7X2_INDEX 11 +#define LBIST_INST_C7X3_INDEX 12 +#define LBIST_INST_A72SS0_CORE0_INDEX 13 +#define LBIST_INST_A72SS0_CORE1_INDEX 14 +#define LBIST_INST_A72SS0_CORE2_INDEX 15 +#define LBIST_INST_A72SS0_CORE3_INDEX 16 +#define LBIST_INST_A72SS1_CORE0_INDEX 17 +#define LBIST_INST_A72SS1_CORE1_INDEX 18 +#define LBIST_INST_A72SS1_CORE2_INDEX 19 +#define LBIST_INST_A72SS1_CORE3_INDEX 20 +#define LBIST_INST_MAINR5F2_INDEX 21 + +#define LBIST_MAX_CORE_INDEX (LBIST_INST_MAINR5F2_INDEX+1) + +/* HW POST core definitions */ +#define LBIST_POST_CORE_SMS LBIST_HWPOST_INST_SMS_INDEX +#define LBIST_POST_CORE_MCU LBIST_HWPOST_INST_MCU_INDEX +#define LBIST_POST_CORE_MAX LBIST_HWPOST_INST_MCU_INDEX + +/* ========================================================================== */ +/* External Dependencies */ +/* ========================================================================== */ + +/* Number of PBIST sections run in the pre-boot stage, i.e. before any Main Domain + * cores are booted */ +extern uint8_t num_pbists_pre_boot; + +/* Defines PBIST sections run in the pre-boot stage, i.e. before any Main Domain + * cores are booted */ +extern int pbist_pre_boot_stage[]; + +/* Structure to save the status of the PBIST tests run as part of the pre-boot stage */ +extern int pbist_pre_boot_stage_status[]; + +/* Structure to save the status of the PBIST negative tests run as part of the pre-boot stage */ +extern int pbist_pre_boot_stage_neg_status[]; + +/* Structure to save the status of the PBIST rom tests run as part of the pre-boot stage */ +extern int pbist_pre_boot_stage_rom_test_status[]; + +/* Number of LBIST tests run in the pre-boot stage, i.e. before any Main Domain + * cores are booted */ +extern int lbist_pre_boot_stage[]; + +/* Defines LBIST tests run in the pre-boot stage, i.e. before any Main Domain + * cores are booted */ +extern int lbist_pre_boot_stage_status[]; + +/* Points to PBIST arrays that are run right before each of the boot stages */ +extern int *pbist_array_stage[NUM_BOOT_STAGES]; + +/* Points to LBIST arrays that are run right before each of the boot stages */ +extern int *lbist_array_stage[NUM_BOOT_STAGES]; + +/* Number of LBIST sections run in the pre-boot stage, i.e. before any Main Domain + * cores are booted */ +extern uint8_t num_lbists_pre_boot; + +/* Number of LBIST sections run before each of the boot stages */ +extern uint8_t num_lbists_per_boot_stage[NUM_BOOT_STAGES]; + +/* Number of PBIST sections run before each of the boot stages */ +extern uint8_t num_pbists_per_boot_stage[NUM_BOOT_STAGES]; + +/* Function to return PBIST section name based on PBIST ID number */ +const char *pbistName(uint32_t pbistID); + +/* Function to return LBIST section name based on LBIST ID number */ +const char *lbistName(uint32_t lbistID); + +#ifdef __cplusplus +} +#endif +#endif /* BIST_CORE_DEFS_H_ */ diff --git a/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/lbist_defs.c b/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/lbist_defs.c new file mode 100755 index 00000000..2f77524a --- /dev/null +++ b/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/lbist_defs.c @@ -0,0 +1,474 @@ +/* +* +* Copyright (c) 2020 Texas Instruments Incorporated +* +* All rights reserved not granted herein. +* +* Limited License. +* +* Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive +* license under copyrights and patents it now or hereafter owns or controls to make, +* have made, use, import, offer to sell and sell ("Utilize") this software subject to the +* terms herein. With respect to the foregoing patent license, such license is granted +* solely to the extent that any such patent is necessary to Utilize the software alone. +* The patent license shall not apply to any combinations which include this software, +* other than combinations with devices manufactured by or for TI ("TI Devices"). +* No hardware patent is licensed hereunder. +* +* Redistributions must preserve existing copyright notices and reproduce this license +* (including the above copyright notice and the disclaimer and (if applicable) source +* code license limitations below) in the documentation and/or other materials provided +* with the distribution +* +* Redistribution and use in binary form, without modification, are permitted provided +* that the following conditions are met: +* +* * No reverse engineering, decompilation, or disassembly of this software is +* permitted with respect to any software provided in binary form. +* +* * any redistribution and use are licensed by TI for use only with TI Devices. +* +* * Nothing shall obligate TI to provide you with source code for the software +* licensed and provided to you in object code. +* +* If software source code is provided to you, modification and redistribution of the +* source code are permitted provided that the following conditions are met: +* +* * any redistribution and use of the source code, including any resulting derivative +* works, are licensed by TI for use only with TI Devices. +* +* * any redistribution and use of any object code compiled from the source code +* and any resulting derivative works, are licensed by TI for use only with TI Devices. +* +* Neither the name of Texas Instruments Incorporated nor the names of its suppliers +* +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* DISCLAIMER. +* +* THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS +* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED +* OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + +/** + * \file lbist_defs.c + * + * \brief LBIST SOC-specific structures and functions + */ + +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ +#include +#include +#include +#include +#include +#include +#include + +#include "lbist_utils.h" +#include "lbist_defs.h" + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ + +#define A72_NUM_AUX_DEVICES 3 + +/* HW POST run status definitions */ +#define LBIST_POST_COMPLETED_SUCCESS_STR "SDL_LBIST_POST_COMPLETED_SUCCESS" +#define LBIST_POST_COMPLETED_FAILURE_STR "SDL_LBIST_POST_COMPLETED_FAILURE" +#define LBIST_POST_ATTEMPTED_TIMEOUT_STR "SDL_LBIST_POST_TIMEOUT" +#define LBIST_POST_NOT_RUN_STR "SDL_LBIST_POST_NOT_RUN" + +/* ========================================================================== */ +/* Internal Function Declarations */ +/* ========================================================================== */ + +/* ========================================================================== */ +/* Structure Declarations */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Function Declarations */ +/* ========================================================================== */ +char * LBIST_getPostStatusString(SDL_LBIST_postStatus postStatus); + +/* ========================================================================== */ +/* Global Variables */ +/* ========================================================================== */ + +uint32_t LBIST_A72AuxDevList[A72_NUM_AUX_DEVICES] = +{ + TISCI_DEV_A72SS0, + TISCI_DEV_A72SS0_CORE0, + TISCI_DEV_A72SS0_CORE1 +}; + + +LBIST_TestHandle_t LBIST_TestHandleArray[LBIST_MAX_CORE_INDEX+1] = +{ + /* HW POST - SMS - Checks MISR results only */ + + { + .coreName = "HWPOST - SMS", + .numAuxDevices = 0u, /* No Aux devices */ + .hwPostCoreCheck = true, + .hwPostCoreNum = LBIST_POST_CORE_SMS, + }, + /* HW POST - MCU - Checks MISR results only */ + { + .coreName = "HWPOST - MCU", + .numAuxDevices = 0u, /* No Aux devices */ + .hwPostCoreCheck = true, + .hwPostCoreNum = LBIST_POST_CORE_MCU, + }, /* LBIST event handler */ + + /* Main R5F 0 */ + { + .coreName = "Main R5F0-0", + .instance = SDL_LBIST_INST_MAINR5F0, + .secondaryCoreNeeded = true, /* Secondary core needed */ + .wfiCheckNeeded = false, /* wfi check needed */ + .secCoreName = "Main R5F1-0", /* Secondary core */ + .cpuStatusFlagMask = TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI, /* Expected boot status value for wfi */ + .tisciProcId = SCICLIENT_PROC_ID_R5FSS0_CORE0, /* Main R5F core 0 Proc Id */ + .tisciSecProcId = SCICLIENT_PROC_ID_R5FSS0_CORE1, /* Main R5F core 1 Proc Id */ + .tisciDeviceId = TISCI_DEV_R5FSS0_CORE0, /* Main R5F core 0 Device Id */ + .tisciSecDeviceId = TISCI_DEV_R5FSS0_CORE1, /* Main R5F core 1 Device Id */ + .numAuxDevices = 0u, /* No Aux devices */ + }, + /* Main R5F 1 */ + { + .coreName = "Main R5F1-0", + .instance = SDL_LBIST_INST_MAINR5F1, + .secondaryCoreNeeded = true, /* Secondary core needed */ + .wfiCheckNeeded = false, /* wfi check needed */ + .secCoreName = "Main R5F1-1", /* Secondary core */ + .cpuStatusFlagMask = TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI, /* Expected boot status value for wfi */ + .tisciProcId = SCICLIENT_PROC_ID_R5FSS1_CORE0, /* Main R5F core 0 Proc Id */ + .tisciSecProcId = SCICLIENT_PROC_ID_R5FSS1_CORE1, /* Main R5F core 1 Proc Id */ + .tisciDeviceId = TISCI_DEV_R5FSS1_CORE0, /* Main R5F core 0 Device id */ + .tisciSecDeviceId = TISCI_DEV_R5FSS1_CORE1, /* Main R5F core 1 Device id */ + .numAuxDevices = 0u, /* No Aux devices */ + }, + /* C7x0 */ + { + .coreName = "C7x0 ", + .instance = SDL_LBIST_INST_C7X0, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .wfiCheckNeeded = false, /* wfi check needed */ + .secCoreName = "None", /* Secondary core */ + .cpuStatusFlagMask = TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI, /* Expected boot status value for wfi */ + .tisciProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_C71SS0_CORE0_0, /* C7x Proc Id */ + .tisciSecProcId = 0u, + .tisciDeviceId = TISCI_DEV_COMPUTE_CLUSTER0_C71SS0, /* C7x Device Id */ + .tisciSecDeviceId = 0u, + .numAuxDevices = 0u, /* No Aux devices */ + }, + /* C7x1 */ + { + .coreName = "C7x1 ", + .instance = SDL_LBIST_INST_C7X1, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .wfiCheckNeeded = false, /* wfi check needed */ + .secCoreName = "None", /* Secondary core */ + .cpuStatusFlagMask = TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI, /* Expected boot status value for wfi */ + .tisciProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_C71SS1_CORE0_0, /* C7x Proc Id */ + .tisciSecProcId = 0u, + .tisciDeviceId = TISCI_DEV_COMPUTE_CLUSTER0_C71SS1, /* C7x Device Id */ + .tisciSecDeviceId = 0u, + .numAuxDevices = 0u, /* No Aux devices */ + }, + /* VPAC0 */ + { + .coreName = "VPAC0", + .instance = SDL_LBIST_INST_VPAC0, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .wfiCheckNeeded = false, /* wfi check needed */ + .secCoreName = "None", /* Secondary core */ + .cpuStatusFlagMask = TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI, /* Expected boot status value for wfi */ + .tisciProcId = 0, /* No proc id */ + .tisciSecProcId = 0, /* No Proc Id */ + .tisciDeviceId = TISCI_DEV_VPAC0, /* VPAC Device Id */ + .tisciSecDeviceId = 0, + .numAuxDevices = 0u, /* No Aux devices */ + }, + + /* DMPAC */ + { + .coreName = "DMPAC", + .instance = SDL_LBIST_INST_DMPAC, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .wfiCheckNeeded = false, /* wfi check needed */ + .secCoreName = "None", /* Secondary core */ + .cpuStatusFlagMask = TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI, /* Expected boot status value for wfi */ + .tisciProcId = 0, /* No proc id */ + .tisciSecProcId = 0, /* No Proc Id */ + .tisciDeviceId = TISCI_DEV_DMPAC0, /* DMPAC Device Id */ + .tisciSecDeviceId = 0, + .numAuxDevices = 0u, /* No Aux devices */ + }, + + /* A72_0*/ + { + .coreName = "A72 core 0", + .instance = SDL_LBIST_INST_A72, + .secondaryCoreNeeded = true, /* Secondary core needed */ + .wfiCheckNeeded = false, /* wfi check needed */ + .secCoreName = "A72 core 1", /* Secondary core */ + .cpuStatusFlagMask = TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI, /* Expected boot status value for wfi */ + .tisciProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE0_0, /* A72 core 0 Proc Id */ + .tisciSecProcId = 0u, /* A72 core 1 Proc Id */ + .tisciDeviceId = TISCI_DEV_A72SS0, /* A72 core 0 Device Id */ + .tisciSecDeviceId = 0u, /* A72 core 1 Device Id */ + .numAuxDevices = A72_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &LBIST_A72AuxDevList[0], /* Array of Aux device ids */ + }, + + /* VPAC1 */ + { + .coreName = "VPAC1", + .instance = SDL_LBIST_INST_VPAC1, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .wfiCheckNeeded = false, /* wfi check needed */ + .secCoreName = "None", /* Secondary core */ + .cpuStatusFlagMask = TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI, /* Expected boot status value for wfi */ + .tisciProcId = 0, /* No proc id */ + .tisciSecProcId = 0, /* No Proc Id */ + .tisciDeviceId = TISCI_DEV_VPAC1, /* VPAC Device Id */ + .tisciSecDeviceId = 0, + .numAuxDevices = 0u, /* No Aux devices */ + }, + + /* A72_1*/ + { + .coreName = "A72 core 1", + .instance = SDL_LBIST_INST_A72_1, + .secondaryCoreNeeded = true, /* Secondary core needed */ + .wfiCheckNeeded = false, /* wfi check needed */ + .secCoreName = "A72 core 1", /* Secondary core */ + .cpuStatusFlagMask = TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI, /* Expected boot status value for wfi */ + .tisciProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE0_0, /* A72 core 0 Proc Id */ + .tisciSecProcId = 0u, /* A72 core 1 Proc Id */ + .tisciDeviceId = TISCI_DEV_A72SS1, /* A72 core 0 Device Id */ + .tisciSecDeviceId = 0u, /* A72 core 1 Device Id */ + .numAuxDevices = A72_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &LBIST_A72AuxDevList[0], /* Array of Aux device ids */ + }, + + /* C7x2 */ + { + .coreName = "C7x2 ", + .instance = SDL_LBIST_INST_C7X2, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .wfiCheckNeeded = false, /* wfi check needed */ + .secCoreName = "None", /* Secondary core */ + .cpuStatusFlagMask = TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI, /* Expected boot status value for wfi */ + .tisciProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_C71SS2_CORE0_0, /* C7x Proc Id */ + .tisciSecProcId = 0u, + .tisciDeviceId = TISCI_DEV_COMPUTE_CLUSTER0_C71SS2, /* C7x Device Id */ + .tisciSecDeviceId = 0u, + .numAuxDevices = 0u, /* No Aux devices */ + }, + /* C7x3 */ + { + .coreName = "C7x3 ", + .instance = SDL_LBIST_INST_C7X3, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .wfiCheckNeeded = false, /* wfi check needed */ + .secCoreName = "None", /* Secondary core */ + .cpuStatusFlagMask = TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI, /* Expected boot status value for wfi */ + .tisciProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_C71SS3_CORE0_0, /* C7x Proc Id */ + .tisciSecProcId = 0u, + .tisciDeviceId = TISCI_DEV_COMPUTE_CLUSTER0_C71SS3, /* C7x Device Id */ + .tisciSecDeviceId = 0u, + .numAuxDevices = 0u, /* No Aux devices */ + }, + /* A72SS0_CORE0*/ + { + .coreName = "A72SS0 core 0", + .instance = SDL_LBIST_INST_A72SS0_CORE0, + .secondaryCoreNeeded = true, /* Secondary core needed */ + .wfiCheckNeeded = false, /* wfi check needed */ + .secCoreName = "A72SS1 core 0", /* Secondary core */ + .cpuStatusFlagMask = TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI, /* Expected boot status value for wfi */ + .tisciProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE0_0, /* A72 core 0 Proc Id */ + .tisciSecProcId = 0u, /* A72 core 1 Proc Id */ + .tisciDeviceId = TISCI_DEV_A72SS0_CORE0, /* A72 core 0 Device Id */ + .tisciSecDeviceId = 0u, /* A72 core 1 Device Id */ + .numAuxDevices = A72_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &LBIST_A72AuxDevList[0], /* Array of Aux device ids */ + }, + /* A72SS0_CORE1*/ + { + .coreName = "A72SS0 core 1", + .instance = SDL_LBIST_INST_A72SS0_CORE1, + .secondaryCoreNeeded = true, /* Secondary core needed */ + .wfiCheckNeeded = false, /* wfi check needed */ + .secCoreName = "A72SS1 core 1", /* Secondary core */ + .cpuStatusFlagMask = TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI, /* Expected boot status value for wfi */ + .tisciProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE1_0, /* A72 core 0 Proc Id */ + .tisciSecProcId = 0u, /* A72 core 1 Proc Id */ + .tisciDeviceId = TISCI_DEV_A72SS0_CORE1, /* A72 core 0 Device Id */ + .tisciSecDeviceId = 0u, /* A72 core 1 Device Id */ + .numAuxDevices = A72_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &LBIST_A72AuxDevList[0], /* Array of Aux device ids */ + }, + /* A72SS0_CORE2*/ + { + .coreName = "A72SS0 core 2", + .instance = SDL_LBIST_INST_A72SS0_CORE2, + .secondaryCoreNeeded = true, /* Secondary core needed */ + .wfiCheckNeeded = false, /* wfi check needed */ + .secCoreName = "A72SS1 core 2", /* Secondary core */ + .cpuStatusFlagMask = TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI, /* Expected boot status value for wfi */ + .tisciProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE2_0, /* A72 core 0 Proc Id */ + .tisciSecProcId = 0u, /* A72 core 1 Proc Id */ + .tisciDeviceId = TISCI_DEV_A72SS0_CORE2, /* A72 core 0 Device Id */ + .tisciSecDeviceId = 0u, /* A72 core 1 Device Id */ + .numAuxDevices = A72_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &LBIST_A72AuxDevList[0], /* Array of Aux device ids */ + }, + /* A72SS0_CORE3*/ + { + .coreName = "A72SS0 core 3", + .instance = SDL_LBIST_INST_A72SS0_CORE3, + .secondaryCoreNeeded = true, /* Secondary core needed */ + .wfiCheckNeeded = false, /* wfi check needed */ + .secCoreName = "A72SS1 core 3", /* Secondary core */ + .cpuStatusFlagMask = TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI, /* Expected boot status value for wfi */ + .tisciProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE3_0, /* A72 core 0 Proc Id */ + .tisciSecProcId = 0u, /* A72 core 1 Proc Id */ + .tisciDeviceId = TISCI_DEV_A72SS0_CORE3, /* A72 core 0 Device Id */ + .tisciSecDeviceId = 0u, /* A72 core 1 Device Id */ + .numAuxDevices = A72_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &LBIST_A72AuxDevList[0], /* Array of Aux device ids */ + }, + /* A72SS1_CORE0*/ + { + .coreName = "A72SS1 core0 ", + .instance = SDL_LBIST_INST_A72SS1_CORE0, + .secondaryCoreNeeded = true, /* Secondary core needed */ + .wfiCheckNeeded = false, /* wfi check needed */ + .secCoreName = "A72SS0 core0", /* Secondary core */ + .cpuStatusFlagMask = TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI, /* Expected boot status value for wfi */ + .tisciProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE0_0, /* A72 core 0 Proc Id */ + .tisciSecProcId = 0u, /* A72 core 1 Proc Id */ + .tisciDeviceId = TISCI_DEV_A72SS1_CORE0, /* A72 core 0 Device Id */ + .tisciSecDeviceId = 0u, /* A72 core 1 Device Id */ + .numAuxDevices = A72_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &LBIST_A72AuxDevList[0], /* Array of Aux device ids */ + }, + /* A72SS1_CORE1*/ + { + .coreName = "A72SS1 core 1", + .instance = SDL_LBIST_INST_A72SS1_CORE1, + .secondaryCoreNeeded = true, /* Secondary core needed */ + .wfiCheckNeeded = false, /* wfi check needed */ + .secCoreName = "A72SS0 core 1", /* Secondary core */ + .cpuStatusFlagMask = TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI, /* Expected boot status value for wfi */ + .tisciProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE1_0, /* A72 core 0 Proc Id */ + .tisciSecProcId = 0u, /* A72 core 1 Proc Id */ + .tisciDeviceId = TISCI_DEV_A72SS1_CORE1, /* A72 core 0 Device Id */ + .tisciSecDeviceId = 0u, /* A72 core 1 Device Id */ + .numAuxDevices = A72_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &LBIST_A72AuxDevList[0], /* Array of Aux device ids */ + }, + /* A72SS1_CORE2*/ + { + .coreName = "A72SS1 core 2", + .instance = SDL_LBIST_INST_A72SS1_CORE2, + .secondaryCoreNeeded = true, /* Secondary core needed */ + .wfiCheckNeeded = false, /* wfi check needed */ + .secCoreName = "A72SS0 core 2", /* Secondary core */ + .cpuStatusFlagMask = TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI, /* Expected boot status value for wfi */ + .tisciProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE2_0, /* A72 core 0 Proc Id */ + .tisciSecProcId = 0u, /* A72 core 1 Proc Id */ + .tisciDeviceId = TISCI_DEV_A72SS1_CORE2, /* A72 core 0 Device Id */ + .tisciSecDeviceId = 0u, /* A72 core 1 Device Id */ + .numAuxDevices = A72_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &LBIST_A72AuxDevList[0], /* Array of Aux device ids */ + }, + /* A72SS1_CORE3*/ + { + .coreName = "A72SS1 core 3", + .instance = SDL_LBIST_INST_A72SS1_CORE3, + .secondaryCoreNeeded = true, /* Secondary core needed */ + .wfiCheckNeeded = false, /* wfi check needed */ + .secCoreName = "A72SS0 core 3", /* Secondary core */ + .cpuStatusFlagMask = TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI, /* Expected boot status value for wfi */ + .tisciProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE3_0, /* A72 core 0 Proc Id */ + .tisciSecProcId = 0u, /* A72 core 1 Proc Id */ + .tisciDeviceId = TISCI_DEV_A72SS1_CORE3, /* A72 core 0 Device Id */ + .tisciSecDeviceId = 0u, /* A72 core 1 Device Id */ + .numAuxDevices = A72_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &LBIST_A72AuxDevList[0], /* Array of Aux device ids */ + }, + /* Main R5F 2 */ + { + .coreName = "Main R5F2-0", + .instance = SDL_LBIST_INST_MAINR5F2, + .secondaryCoreNeeded = true, /* Secondary core needed */ + .wfiCheckNeeded = false, /* wfi check needed */ + .secCoreName = "Main R5F2-1", /* Secondary core */ + .cpuStatusFlagMask = TISCI_MSG_VAL_PROC_BOOT_STATUS_FLAG_R5_WFI, /* Expected boot status value for wfi */ + .tisciProcId = SCICLIENT_PROC_ID_R5FSS2_CORE0, /* Main R5F core 0 Proc Id */ + .tisciSecProcId = 0u, /* Main R5F core 1 Proc Id */ + .tisciDeviceId = TISCI_DEV_R5FSS2_CORE0, /* Main R5F core 0 Device Id */ + .tisciSecDeviceId = 0u, /* Main R5F core 1 Device Id */ + .numAuxDevices = 0u, /* No Aux devices */ + }, +}; + +/* ========================================================================== */ +/* External Variables */ +/* ========================================================================== */ + + +/* ========================================================================== */ +/* Function Definitions */ +/* ========================================================================== */ + +char * LBIST_getPostStatusString(SDL_LBIST_postStatus postStatus) +{ + if (postStatus == SDL_LBIST_POST_NOT_RUN) + { + return LBIST_POST_NOT_RUN_STR; + } + else if (postStatus == SDL_LBIST_POST_TIMEOUT) + { + return LBIST_POST_ATTEMPTED_TIMEOUT_STR; + } + else if (postStatus == SDL_LBIST_POST_COMPLETED_FAILURE) + { + return LBIST_POST_COMPLETED_FAILURE_STR; + } + else if (postStatus == SDL_LBIST_POST_COMPLETED_SUCCESS) + { + return LBIST_POST_COMPLETED_SUCCESS_STR; + } + return NULL; +} + +void LBIST_printPostStatus(SDL_LBIST_postResult *result) +{ + UART_printf(" HW POST MCU Status : %s\n", (LBIST_getPostStatusString(result->mcuPostStatus)) ? : "Invalid"); + UART_printf(" HW POST DMSC Status : %s\n", (LBIST_getPostStatusString(result->smsPostStatus)) ? : "Invalid"); + + return; +} + diff --git a/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/lbist_defs.h b/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/lbist_defs.h new file mode 100755 index 00000000..5f5b1693 --- /dev/null +++ b/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/lbist_defs.h @@ -0,0 +1,99 @@ +/******************************************************************** + * Copyright (C) 2020 Texas Instruments Incorporated. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Name : lbist_defs.h +*/ +#ifndef LBIST_DEFS_H_ +#define LBIST_DEFS_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ +#include +#include + +#include "bist_core_defs.h" + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ +typedef void (*LBIST_handlerPtr)(uint32_t coreIndex); + +typedef struct LBIST_TestHandle_s +{ + /** Core name */ + char coreName[16]; + /** Core instance */ + SDL_LBIST_inst instance; + /** Indicate secondary core need to be handled */ + bool secondaryCoreNeeded; + bool wfiCheckNeeded; + /** Secondary core name */ + char secCoreName[16]; + /** Mask used to check CPU Status */ + uint32_t cpuStatusFlagMask; + /** Core Processor Id */ + uint32_t tisciProcId; + /** Secondary Core Processor Id */ + uint32_t tisciSecProcId; + /** Core Device Id */ + uint32_t tisciDeviceId; + /** Secondary Core Device Id */ + uint32_t tisciSecDeviceId; + /** Number of Auxiliary devices needed for the test */ + uint32_t numAuxDevices; + /** List of Auxiliary devices needed for the test */ + uint32_t *auxDeviceIdsP; + /** Indicates if test is just checking output MISR values for + * already-completed test. If true, it is not a SW-initiated test */ + bool hwPostCoreCheck; + /** If test is just HW POST result check, this designates + * the core for which the logic result is being checked, + * i.e. LBIST_POST_CORE_XXX */ + uint32_t hwPostCoreNum; +} LBIST_TestHandle_t; + +extern LBIST_TestHandle_t LBIST_TestHandleArray[LBIST_MAX_CORE_INDEX+1]; + +/* ========================================================================== */ +/* Function Declarations */ +/* ========================================================================== */ +void LBIST_printPostStatus(SDL_LBIST_postResult *result); + +#ifdef __cplusplus +} +#endif +#endif /* LBIST_DEFS_H_ */ diff --git a/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/pbist_defs.c b/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/pbist_defs.c new file mode 100755 index 00000000..f2833faf --- /dev/null +++ b/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/pbist_defs.c @@ -0,0 +1,1438 @@ +/* +* +* Copyright (c) 2020 Texas Instruments Incorporated +* +* All rights reserved not granted herein. +* +* Limited License. +* +* Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive +* license under copyrights and patents it now or hereafter owns or controls to make, +* have made, use, import, offer to sell and sell ("Utilize") this software subject to the +* terms herein. With respect to the foregoing patent license, such license is granted +* solely to the extent that any such patent is necessary to Utilize the software alone. +* The patent license shall not apply to any combinations which include this software, +* other than combinations with devices manufactured by or for TI ("TI Devices"). +* No hardware patent is licensed hereunder. +* +* Redistributions must preserve existing copyright notices and reproduce this license +* (including the above copyright notice and the disclaimer and (if applicable) source +* code license limitations below) in the documentation and/or other materials provided +* with the distribution +* +* Redistribution and use in binary form, without modification, are permitted provided +* that the following conditions are met: +* +* * No reverse engineering, decompilation, or disassembly of this software is +* permitted with respect to any software provided in binary form. +* +* * any redistribution and use are licensed by TI for use only with TI Devices. +* +* * Nothing shall obligate TI to provide you with source code for the software +* licensed and provided to you in object code. +* +* If software source code is provided to you, modification and redistribution of the +* source code are permitted provided that the following conditions are met: +* +* * any redistribution and use of the source code, including any resulting derivative +* works, are licensed by TI for use only with TI Devices. +* +* * any redistribution and use of any object code compiled from the source code +* and any resulting derivative works, are licensed by TI for use only with TI Devices. +* +* Neither the name of Texas Instruments Incorporated nor the names of its suppliers +* +* may be used to endorse or promote products derived from this software without +* specific prior written permission. +* +* DISCLAIMER. +* +* THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS +* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED +* OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + +/** + * \file pbist_defs.c + * + * \brief PBIST SOC-specific structures and functions + */ + +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* SCI Client */ +#include + +#include "pbist_utils.h" +#include "pbist_defs.h" + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ + +#define MSMC_NUM_AUX_DEVICES 2 + +#define A72_NUM_AUX_DEVICES 1 + +#define MAIN_INFRA0_NUM_AUX_DEVICES 4 + +#define MAIN_R5F1_NUM_AUX_DEVICES 4 + +#define MAIN_INFRA1_NUM_AUX_DEVICES 18 + +#define HC_NUM_AUX_DEVICES 12 + +#define CODEC_NUM_AUX_DEVICES 1 + +#define GPU_NUM_AUX_DEVICES 3 + +#define DSS_NUM_AUX_DEVICES 8 + +#define C7X0_NUM_AUX_DEVICES 1 + +#define C7X1_NUM_AUX_DEVICES 1 + +#define C7X2_NUM_AUX_DEVICES 1 + +#define C7X3_NUM_AUX_DEVICES 1 + +#define ANA_NUM_AUX_DEVICES 2 + +/* This macro defined by default to indicate only a select memory section can + * be run on the MCU memory PBIST instances to ensure test application running + * on MCU is not corrupted. */ +#define PBIST_MCU_SELECTED_MEMORY + +/* HW POST run status definitions */ +#define PBIST_POST_COMPLETED_SUCCESS_STR "SDL_PBIST_POST_COMPLETED_SUCCESS" +#define PBIST_POST_COMPLETED_FAILURE_STR "SDL_PBIST_POST_COMPLETED_FAILURE" +#define PBIST_POST_ATTEMPTED_TIMEOUT_STR "SDL_PBIST_POST_TIMEOUT" +#define PBIST_POST_NOT_RUN_STR "SDL_PBIST_POST_NOT_RUN" + +#define PBIST_RAT_CFG_BASE SDL_MCU_R5FSS0_RAT_CFG_BASE + +/* ========================================================================== */ +/* Internal Function Declarations */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Local function prototypes */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Structure Declarations */ +/* ========================================================================== */ + +/* None */ + +/* ========================================================================== */ +/* Function Declarations */ +/* ========================================================================== */ + +/* + InitRestore functions : Initialize or Restore based on init flag + init : TRUE --> Initialize + init : FALSE --> Restore +*/ +int32_t PBIST_VPAC0AuxInitRestore(bool init); +int32_t PBIST_VPAC1AuxInitRestore(bool init); +int32_t PBIST_HCAuxInitRestore(bool init); +int32_t PBIST_MainInfra0AuxInitRestore(bool init); +int32_t PBIST_NAVSSAuxInitRestore(bool init); +int32_t PBIST_CodecAuxInitRestore(bool init); +int32_t PBIST_GPUAuxInitRestore(bool init); +int32_t PBIST_DSSAuxInitRestore(bool init); +int32_t PBIST_A720_0AuxInitRestore(bool init); +int32_t PBIST_A720_1AuxInitRestore(bool init); +int32_t PBIST_A721_0AuxInitRestore(bool init); +int32_t PBIST_A721_1AuxInitRestore(bool init); +/* ========================================================================== */ +/* Global Variables */ +/* ========================================================================== */ +uint32_t PBIST_MainInfra0AuxDevList[MAIN_INFRA0_NUM_AUX_DEVICES] = +{ + TISCI_DEV_MMCSD0, + TISCI_DEV_MMCSD1, + TISCI_DEV_CPSW1, + TISCI_DEV_DEBUGSS_WRAP0, +}; + +uint32_t PBIST_MainInfra1AuxDevList[MAIN_INFRA1_NUM_AUX_DEVICES] = +{ + TISCI_DEV_MCAN0, + TISCI_DEV_MCAN1, + TISCI_DEV_MCAN2, + TISCI_DEV_MCAN3, + TISCI_DEV_MCAN4, + TISCI_DEV_MCAN5, + TISCI_DEV_MCAN6, + TISCI_DEV_MCAN7, + TISCI_DEV_MCAN8, + TISCI_DEV_MCAN9, + TISCI_DEV_MCAN10, + TISCI_DEV_MCAN11, + TISCI_DEV_MCAN12, + TISCI_DEV_MCAN13, + TISCI_DEV_MCAN14, + TISCI_DEV_MCAN15, + TISCI_DEV_MCAN16, + TISCI_DEV_MCAN17 +}; + +uint32_t PBIST_HCAuxDevList[HC_NUM_AUX_DEVICES] = +{ + TISCI_DEV_DEBUGSS_WRAP0, + TISCI_DEV_UFS0, + TISCI_DEV_PCIE0, + TISCI_DEV_PCIE1, + TISCI_DEV_PCIE2, + TISCI_DEV_PCIE3, + TISCI_DEV_USB0, + TISCI_DEV_MMCSD0, + TISCI_DEV_MMCSD1, + TISCI_DEV_SA2_UL0, + TISCI_DEV_VUSR_DUAL0, + TISCI_DEV_CPSW_9XUSS_J7AM0, +}; + +uint32_t PBIST_CodecAuxDevList[CODEC_NUM_AUX_DEVICES] = +{ + TISCI_DEV_CODEC0 +}; + +uint32_t PBIST_GPUAuxDevList[GPU_NUM_AUX_DEVICES] = +{ + TISCI_DEV_J7AEP_GPU_BXS464_WRAP0, + TISCI_DEV_J7AEP_GPU_BXS464_WRAP0_GPU_SS_0, + TISCI_DEV_J7AEP_GPU_BXS464_WRAP0_GPUCORE_0, +}; + +uint32_t PBIST_DSSAuxDevList[DSS_NUM_AUX_DEVICES] = +{ + TISCI_DEV_DSS0, + TISCI_DEV_DSS_EDP0, + TISCI_DEV_DSS_DSI0, + TISCI_DEV_CSI_TX_IF0, + TISCI_DEV_CSI_TX_IF1, + TISCI_DEV_CSI_RX_IF0, + TISCI_DEV_CSI_RX_IF1, + TISCI_DEV_CSI_RX_IF2, +}; + +uint32_t PBIST_C7X0_AuxDevList[C7X0_NUM_AUX_DEVICES] = +{ + TISCI_DEV_COMPUTE_CLUSTER0_C71SS0, +}; + +uint32_t PBIST_C7X1_AuxDevList[C7X1_NUM_AUX_DEVICES] = +{ + TISCI_DEV_COMPUTE_CLUSTER0_C71SS1, +}; + +uint32_t PBIST_C7X2_AuxDevList[C7X2_NUM_AUX_DEVICES] = +{ + TISCI_DEV_COMPUTE_CLUSTER0_C71SS2, +}; + +uint32_t PBIST_C7X3_AuxDevList[C7X3_NUM_AUX_DEVICES] = +{ + TISCI_DEV_COMPUTE_CLUSTER0_C71SS3, +}; + +uint32_t PBIST_MSMCAuxDevList[MSMC_NUM_AUX_DEVICES] = +{ + TISCI_DEV_COMPUTE_CLUSTER0_DIVH2_DIVH_0, + TISCI_DEV_COMPUTE_CLUSTER0_DIVP_TFT_0, +}; + +uint32_t PBIST_A720AuxDevList[A72_NUM_AUX_DEVICES] = +{ + TISCI_DEV_A72SS0, +}; + +uint32_t PBIST_A721AuxDevList[A72_NUM_AUX_DEVICES] = +{ + TISCI_DEV_A72SS1, +}; + +uint32_t PBIST_ANA0AuxDevList[ANA_NUM_AUX_DEVICES] = +{ + TISCI_DEV_COMPUTE_CLUSTER0_C71SS0, + TISCI_DEV_COMPUTE_CLUSTER0_DRU4, +}; + +uint32_t PBIST_ANA1AuxDevList[ANA_NUM_AUX_DEVICES] = +{ + TISCI_DEV_COMPUTE_CLUSTER0_C71SS1, + TISCI_DEV_COMPUTE_CLUSTER0_DRU5, +}; + +uint32_t PBIST_ANA2AuxDevList[ANA_NUM_AUX_DEVICES] = +{ + TISCI_DEV_COMPUTE_CLUSTER0_C71SS2, + TISCI_DEV_COMPUTE_CLUSTER0_DRU6, +}; + +uint32_t PBIST_ANA3AuxDevList[ANA_NUM_AUX_DEVICES] = +{ + TISCI_DEV_COMPUTE_CLUSTER0_C71SS3, + TISCI_DEV_COMPUTE_CLUSTER0_DRU7, +}; + +PBIST_TestHandle_t PBIST_TestHandleArray[PBIST_MAX_INSTANCE+1] = + { + /* HW POST - Used to check the status of HW POST MCU PBIST */ + { + .testName = "PBIST HWPOST MCU", + .pbistInst = SDL_PBIST_INST_MCUR5F0, + .numPostPbistToCheck = 1u, + }, + /* Main R5F 0 */ + { + .tisciPBISTDeviceId = TISCI_DEV_PBIST2, /* PBIST device id */ + .testName = "Main R5F 0 PBIST", + .pbistInst = SDL_PBIST_INST_MAINR5F0, + .numPostPbistToCheck = 0u, + .procRstNeeded = true, + .secondaryCoreNeeded = true, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "Main R5F0 core0", /* Primary core */ + .secCoreName = "Main R5F0 core1", /* Secondary core */ + .tisciProcId = SCICLIENT_PROC_ID_R5FSS0_CORE0, /* Main R5F core 0 Proc Id */ + .tisciSecProcId = SCICLIENT_PROC_ID_R5FSS0_CORE1, /* Main R5F core 1 Proc Id */ + .tisciDeviceId = TISCI_DEV_R5FSS0_CORE0, /* Main R5F core 0 Device Id */ + .tisciSecDeviceId = TISCI_DEV_R5FSS0_CORE1, /* Main R5F core 1 Device Id */ + .coreCustPwrSeqNeeded = false, + .numAuxDevices = 0u, /* No Aux devices */ + .auxInitRestoreFunction = NULL, /* Auxilliary init function */ + }, + /* Codec_0 */ + { + .testName = "Codec PBIST", + .pbistInst = SDL_PBIST_INST_CODEC, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_PBIST11, /* PBIST device id */ + .procRstNeeded = false, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "Encoder", /* Primary core */ + .tisciProcId = 0x0u, /* No ProcId for Encoder */ + .tisciDeviceId = TISCI_DEV_CODEC0, /* Encoder Device Id */ + .coreCustPwrSeqNeeded = false, + .numAuxDevices = CODEC_NUM_AUX_DEVICES, /* No Aux devices */ + .auxDeviceIdsP = &PBIST_CodecAuxDevList[0], /* Array of Aux device ids */ + .auxInitRestoreFunction = PBIST_CodecAuxInitRestore, /* Auxilliary init function */ + }, + /* Main Infra 1 */ + { + .testName = "Main Infra1 PBIST", + .pbistInst = SDL_PBIST_INST_MAININFRA1, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_PBIST1, /* PBIST device id */ + .procRstNeeded = false, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "", /* No coreName */ + .tisciProcId = 0x0u, /* No Proc Id needed for Main Intrastructure */ + .tisciDeviceId = 0x0u, /* No Device Id needed for Main infrastructure */ + .coreCustPwrSeqNeeded = false, + .numAuxDevices = MAIN_INFRA1_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &PBIST_MainInfra1AuxDevList[0], /* Array of Aux device ids */ + .auxInitRestoreFunction = NULL, /* Auxilliary init function */ + }, + /* VPAC */ + { + .testName = "VPAC PBIST", + .pbistInst = SDL_PBIST_INST_VPAC_0, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_PBIST8, /* PBIST device id */ + .procRstNeeded = true, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "VPAC core", /* Primary core */ + .tisciProcId = 0x0u, /* No ProcId for VPAC */ + .tisciDeviceId = TISCI_DEV_VPAC0, /* VPAC core Device Id */ + .coreCustPwrSeqNeeded = false, + .numAuxDevices = 0u, /* No Aux devices */ + .auxInitRestoreFunction = PBIST_VPAC0AuxInitRestore, /* Auxilliary init function */ + }, + + /* DSS EDP DSI */ + { + .testName = "DSS EDP PBIST", + .pbistInst = SDL_PBIST_INST_DSS, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_PBIST5, /* PBIST device id */ + .procRstNeeded = false, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "DSS", /* Primary core */ + .tisciProcId = 0x0u, /* No ProcId for MSMC */ + .tisciDeviceId = TISCI_DEV_DSS_DSI0, /* DSS Device Id */ + .coreCustPwrSeqNeeded = false, + .numAuxDevices = DSS_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &PBIST_DSSAuxDevList[0], /* Array of Aux device ids */ + .auxInitRestoreFunction = PBIST_DSSAuxInitRestore, /* Auxilliary init function */ + }, + /* DMPAC */ + { + .testName = "DMPAC PBIST", + .pbistInst = SDL_PBIST_INST_DMPAC, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_PBIST7, /* PBIST device id */ + .procRstNeeded = true, + .secondaryCoreNeeded = true, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "DMPAC core", /* Primary core */ + .secCoreName = "DMPAC SDE core", /* Secondary core */ + .tisciProcId = 0x0u, /* No ProcId for DMPAC */ + .tisciSecProcId = 0x0u, /* No Sec ProcId for DMPAC */ + .tisciDeviceId = TISCI_DEV_DMPAC0, /* DMPAC Core Device Id */ + .tisciSecDeviceId = TISCI_DEV_DMPAC0_SDE_0, /* DMPAC_SDE Device Id */ + .coreCustPwrSeqNeeded = false, + .numAuxDevices = 0u, /* No Aux devices */ + .auxInitRestoreFunction = NULL, /* Auxilliary init function */ + }, + /* NAVSS */ + { + .testName = "NAVSS PBIST", + .pbistInst = SDL_PBIST_INST_NAVSS, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_PBIST4, /* PBIST device id */ + .procRstNeeded = true, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "NAVSS", /* Primary core */ + .tisciProcId = 0x0u, /* No ProcId for NAVSS */ + .tisciDeviceId = TISCI_DEV_NAVSS0, /* NAVSS Device Id */ + .coreCustPwrSeqNeeded = false, + .numAuxDevices = 0u, /* No Aux devices */ + .auxInitRestoreFunction = PBIST_NAVSSAuxInitRestore, /* Auxilliary init function */ + }, + /* Main Infra 0 */ + { + .testName = "Main Infra0 PBIST", + .pbistInst = SDL_PBIST_INST_MAININFRA0, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_PBIST0, /* PBIST device id */ + .procRstNeeded = false, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "", /* No coreName */ + .tisciProcId = 0x0u, /* No Proc Id needed for Main Intrastructure */ + .tisciDeviceId = 0x0u, /* No Device Id needed for Main infrastructure */ + .coreCustPwrSeqNeeded = false, + .numAuxDevices = MAIN_INFRA0_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &PBIST_MainInfra0AuxDevList[0], /* Array of Aux device ids */ + .auxInitRestoreFunction = NULL, /* Auxilliary init function */ + }, + /* GPU */ + { + .testName = "GPU PBIST", + .pbistInst = SDL_PBIST_INST_GPU, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_J7AEP_GPU_BXS464_WRAP0_DFT_EMBED_PBIST_0, /* PBIST device id */ + .procRstNeeded = false, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "GPU", /* Primary core */ + .tisciProcId = 0x0u, /* No ProcId for GPU */ + .tisciDeviceId = TISCI_DEV_J7AEP_GPU_BXS464_WRAP0_GPUCORE_0, /* GPU Device Id */ + .coreCustPwrSeqNeeded = false, + .numAuxDevices = GPU_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &PBIST_GPUAuxDevList[0], /* Array of Aux device ids */ + .auxInitRestoreFunction = PBIST_GPUAuxInitRestore, /* Auxilliary init function */ + }, + /* HC */ + { + .testName = "HC PBIST", + .pbistInst = SDL_PBIST_INST_HC, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_PBIST3, /* PBIST device id */ + .procRstNeeded = false, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .coreName = "", /* No coreName */ + .tisciProcId = 0x0u, /* No ProcId for HC */ + .tisciDeviceId = 0x0u, /* No Device Id */ + .coreCustPwrSeqNeeded = false, + .numAuxDevices = HC_NUM_AUX_DEVICES, /* No Aux devices */ + .auxDeviceIdsP = &PBIST_HCAuxDevList[0], /* Array of Aux device ids */ + .auxInitRestoreFunction = PBIST_HCAuxInitRestore, /* Auxilliary init function */ + }, + + /* VPAC 1 */ + { + .testName = "VPAC_1 PBIST", + .pbistInst = SDL_PBIST_INST_VPAC_1, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_PBIST13, /* PBIST device id */ + .procRstNeeded = false, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "VPAC", /* Primary core */ + .tisciProcId = 0x0u, /* No ProcId for GPU */ + .tisciDeviceId = TISCI_DEV_VPAC1, /* GPU Device Id */ + .coreCustPwrSeqNeeded = false, + .numAuxDevices = 0u, /* Number of Aux devices */ + .auxInitRestoreFunction = PBIST_VPAC1AuxInitRestore, /* Auxilliary init function */ + }, + /* Main R5F 2 */ + { + .testName = "Main R5F 2 PBIST", + .pbistInst = SDL_PBIST_INST_MAINR5F2, + .tisciPBISTDeviceId = TISCI_DEV_PBIST14, /* PBIST device id */ + .procRstNeeded = true, + .secondaryCoreNeeded = true, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "Main R5F0 core0", /* Primary core */ + .secCoreName = "Main R5F0 core1", /* Secondary core */ + .tisciProcId = SCICLIENT_PROC_ID_R5FSS2_CORE0, /* Main R5F core 0 Proc Id */ + .tisciSecProcId = SCICLIENT_PROC_ID_R5FSS2_CORE1, /* Main R5F core 1 Proc Id */ + .tisciDeviceId = TISCI_DEV_R5FSS2_CORE0, /* Main R5F core 0 Device Id */ + .tisciSecDeviceId = TISCI_DEV_R5FSS2_CORE1, /* Main R5F core 1 Device Id */ + .coreCustPwrSeqNeeded = false, + .numAuxDevices = 0u, /* No Aux devices */ + .auxInitRestoreFunction = NULL, /* Auxilliary init function */ + }, + /* Codec_1 */ + { + .testName = "Codec 1 PBIST", + .pbistInst = SDL_PBIST_INST_CODEC_1, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_PBIST15, /* PBIST device id */ + .procRstNeeded = false, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "CODEC", /* Primary core */ + .tisciProcId = 0x0u, /* No ProcId for Encoder */ + .tisciDeviceId = TISCI_DEV_CODEC1, /* Encoder Device Id */ + .coreCustPwrSeqNeeded = false, + .numAuxDevices = CODEC_NUM_AUX_DEVICES, + .auxDeviceIdsP = &PBIST_CodecAuxDevList[0], /* Array of Aux device ids */ + .auxInitRestoreFunction = PBIST_CodecAuxInitRestore, /* Auxilliary init function */ + }, + /* A72_0 0 */ + { + .testName = "A72_0_0 PBIST", + .pbistInst = PBIST_INSTANCE_A72_0_0, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_COMPUTE_CLUSTER0_ARM0_DFT_EMBED_PBIST_0, /* Device Id for A72 PBIST */ + .procRstNeeded = true, + .secondaryCoreNeeded = true, /* Secondary core needed */ + .thirdCoreNeeded = true, + .fourthCoreNeeded = true, + .coreName = "A72 core 0", /* Primary core */ + .secCoreName = "A72 core 1", /* Secondary core */ + .thCoreName = "A72 core 2", + .foCoreName = "A72 core 3", + .tisciProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE0_0, /* A72 core 0 Proc Id */ + .tisciSecProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE1_0, /* A72 core 1 Proc Id */ + .tisciThProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE2_0, + .tisciFoProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE3_0, + .tisciDeviceId = TISCI_DEV_A72SS0_CORE0, /* A72 core 0 Device Id */ + .tisciSecDeviceId = TISCI_DEV_A72SS0_CORE1, /* A72 core 1 Device Id */ + .tisciThDeviceId = TISCI_DEV_A72SS0_CORE2, /* A72 core 2 Device Id */ + .tisciFoDeviceId = TISCI_DEV_A72SS0_CORE3, /* A72 core 3 Device Id */ + .coreCustPwrSeqNeeded = true, /* A72 needs custom powerdown sequence steps */ + .numAuxDevices = A72_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &PBIST_A720AuxDevList[0], /* Array of Aux device ids */ + .auxInitRestoreFunction = PBIST_A720_0AuxInitRestore, /* Auxilliary init function */ + }, + /* A72_0_1 */ + { + .testName = "A72_0_1 PBIST", + .pbistInst = SDL_PBIST_INST_A72_0_1, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_COMPUTE_CLUSTER0_ARM0_DFT_EMBED_PBIST_1, /* Device Id for A72 PBIST */ + .procRstNeeded = true, + .secondaryCoreNeeded = true, /* Secondary core needed */ + .thirdCoreNeeded = true, + .fourthCoreNeeded = true, + .procRstNeeded = true, + .secondaryCoreNeeded = true, /* Secondary core needed */ + .thirdCoreNeeded = true, + .fourthCoreNeeded = true, + .coreName = "A72 core 0", /* Primary core */ + .secCoreName = "A72 core 1", /* Secondary core */ + .thCoreName = "A72 core 2", + .foCoreName = "A72 core 3", + .tisciProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE0_0, /* A72 core 0 Proc Id */ + .tisciSecProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE1_0, /* A72 core 1 Proc Id */ + .tisciThProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE2_0, + .tisciFoProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE3_0, + .tisciDeviceId = TISCI_DEV_A72SS0_CORE0, /* A72 core 0 Device Id */ + .tisciSecDeviceId = TISCI_DEV_A72SS0_CORE1, /* A72 core 1 Device Id */ + .tisciThDeviceId = TISCI_DEV_A72SS0_CORE2, /* A72 core 2 Device Id */ + .tisciFoDeviceId = TISCI_DEV_A72SS0_CORE3, /* A72 core 3 Device Id */ + .coreCustPwrSeqNeeded = true, /* A72 needs custom powerdown sequence steps */ + .numAuxDevices = A72_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &PBIST_A720AuxDevList[0], /* Array of Aux device ids */ + .auxInitRestoreFunction = PBIST_A720_1AuxInitRestore, /* Auxilliary init function */ + }, + /* A72_1_0 */ + { + .testName = "A72_1_0 PBIST", + .pbistInst = SDL_PBIST_INST_A72_1_0, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_COMPUTE_CLUSTER0_ARM1_DFT_EMBED_PBIST_0, /* Device Id for A72 PBIST */ + .procRstNeeded = true, + .secondaryCoreNeeded = true, /* Secondary core needed */ + .thirdCoreNeeded = true, + .fourthCoreNeeded = true, + .coreName = "A721 core 0", /* Primary core */ + .secCoreName = "A721 core 1", /* Secondary core */ + .thCoreName = "A721 core 2", + .foCoreName = "A721 core 3", + .tisciProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE0_0, /* A72 core 0 Proc Id */ + .tisciSecProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE1_0, /* A72 core 1 Proc Id */ + .tisciThProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE2_0, /* A72 core 2 Proc Id */ + .tisciFoProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE3_0, /* A72 core 3 Proc Id */ + .tisciDeviceId = TISCI_DEV_A72SS1_CORE0, /* A72 core 0 Device Id */ + .tisciSecDeviceId = TISCI_DEV_A72SS1_CORE1, /* A72 core 1 Device Id */ + .tisciThDeviceId = TISCI_DEV_A72SS1_CORE2, /* A72 core 2 Device Id */ + .tisciFoDeviceId = TISCI_DEV_A72SS1_CORE3, /* A72 core 3 Device Id */ + .coreCustPwrSeqNeeded = true, /* A72 needs custom powerdown sequence steps */ + .numAuxDevices = A72_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &PBIST_A721AuxDevList[0], /* Array of Aux device ids */ + .auxInitRestoreFunction = PBIST_A721_0AuxInitRestore, /* Auxilliary init function */ + }, + /* A72_1_1 */ + { + .testName = "A72_1_1 PBIST", + .pbistInst = SDL_PBIST_INST_A72_1_1, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_COMPUTE_CLUSTER0_ARM1_DFT_EMBED_PBIST_1, /* Device Id for A72 PBIST */ + .procRstNeeded = true, + .secondaryCoreNeeded = true, /* Secondary core needed */ + .thirdCoreNeeded = true, + .fourthCoreNeeded = true, + .coreName = "A721 core 0", /* Primary core */ + .secCoreName = "A721 core 1", /* Secondary core */ + .thCoreName = "A721 core 2", + .foCoreName = "A721 core 3", + .tisciProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE0_0, /* A72 core 0 Proc Id */ + .tisciSecProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE1_0, /* A72 core 1 Proc Id */ + .tisciThProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE2_0, /* A72 core 2 Proc Id */ + .tisciFoProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE3_0, /* A72 core 3 Proc Id */ + .tisciDeviceId = TISCI_DEV_A72SS1_CORE0, /* A72 core 0 Device Id */ + .tisciSecDeviceId = TISCI_DEV_A72SS1_CORE1, /* A72 core 1 Device Id */ + .tisciThDeviceId = TISCI_DEV_A72SS1_CORE2, /* A72 core 2 Device Id */ + .tisciFoDeviceId = TISCI_DEV_A72SS1_CORE3, /* A72 core 3 Device Id */ + .coreCustPwrSeqNeeded = true, /* A72 needs custom powerdown sequence steps */ + .numAuxDevices = A72_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &PBIST_A721AuxDevList[0], /* Array of Aux device ids */ + .auxInitRestoreFunction = PBIST_A721_1AuxInitRestore, /* Auxilliary init function */ + }, + /* C7X_0 */ + { + .testName = "C7X_0 PBIST", + .pbistInst = SDL_PBIST_INST_C7X_0, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_C71X_0_PBIST_VD, /* PBIST device id */ + .procRstNeeded = true, /* Initialize done flag */ + .secondaryCoreNeeded = false, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "C7x 0", /* Primary core */ + .tisciProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_C71SS0_CORE0_0, /* C6x core0 Proc Id */ + .tisciDeviceId = TISCI_DEV_COMPUTE_CLUSTER0_C71SS0_CORE0, /* C6x Core 0 Device Id */ + .coreCustPwrSeqNeeded = false, + .numAuxDevices = C7X0_NUM_AUX_DEVICES, /* No Aux devices */ + .auxDeviceIdsP = &PBIST_C7X0_AuxDevList[0], + .auxInitRestoreFunction = NULL, /* Auxilliary init function */ + }, + /* C7X_1 */ + { + .testName = "C7X_1 PBIST", + .pbistInst = SDL_PBIST_INST_C7X_1, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_C71X_1_PBIST_VD, /* PBIST device id */ + .procRstNeeded = true, /* Initialize done flag */ + .secondaryCoreNeeded = false, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "C7x 1", /* Primary core */ + .tisciProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_C71SS1_CORE0_0, /* C7x core0 Proc Id */ + .tisciDeviceId = TISCI_DEV_COMPUTE_CLUSTER0_C71SS1_CORE0, /* C7x Core 0 Device Id */ + .coreCustPwrSeqNeeded = false, + .numAuxDevices = C7X1_NUM_AUX_DEVICES, /* No Aux devices */ + .auxDeviceIdsP = &PBIST_C7X1_AuxDevList[0], + .auxInitRestoreFunction = NULL, /* Auxilliary init function */ + }, + /* C7X_2 */ + { + .testName = "C7X_2 PBIST", + .pbistInst = SDL_PBIST_INST_C7X_2, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_COMPUTE_CLUSTER0_AC71_6_DFT_EMBED_PBIST_0, /* PBIST device id */ + .procRstNeeded = true, /* Initialize done flag */ + .secondaryCoreNeeded = false, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "C7x 2", /* Primary core */ + .tisciProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_C71SS2_CORE0_0, /* C6x core0 Proc Id */ + .tisciDeviceId = TISCI_DEV_COMPUTE_CLUSTER0_C71SS2_CORE0, /* C6x Core 0 Device Id */ + .coreCustPwrSeqNeeded = false, + .numAuxDevices = C7X2_NUM_AUX_DEVICES, /* No Aux devices */ + .auxDeviceIdsP = &PBIST_C7X2_AuxDevList[0], + .auxInitRestoreFunction = NULL, /* Auxilliary init function */ + }, + /* C7X_3*/ + { + .testName = "C7X_3 PBIST", + .pbistInst = SDL_PBIST_INST_C7X_3, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_COMPUTE_CLUSTER0_AC71_7_DFT_EMBED_PBIST_0, /* PBIST device id */ + .procRstNeeded = true, /* Initialize done flag */ + .secondaryCoreNeeded = false, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "C7x 3", /* Primary core */ + .tisciProcId = SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_C71SS3_CORE0_0, /* C6x core0 Proc Id */ + .tisciDeviceId = TISCI_DEV_COMPUTE_CLUSTER0_C71SS3_CORE0, /* C6x Core 0 Device Id */ + .coreCustPwrSeqNeeded = false, + .numAuxDevices = C7X3_NUM_AUX_DEVICES, /* No Aux devices */ + .auxDeviceIdsP = &PBIST_C7X3_AuxDevList[0], + .auxInitRestoreFunction = NULL, /* Auxilliary init function */ + }, + /* ANA_0 */ + { + .testName = "ANA_0 PBIST", + .pbistInst = SDL_PBIST_INST_ANA_0, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_COMPUTE_CLUSTER0_AW4_MSMC_DFT_EMBED_PBIST_0, /* PBIST device id */ + .procRstNeeded = false, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "ANA_0", /* Primary core */ + .tisciProcId = 0x0u, /* No ProcId for ANA */ + .tisciDeviceId = 0x0u, /* ANA Device Id */ + .coreCustPwrSeqNeeded = false, + .numAuxDevices = ANA_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &PBIST_ANA0AuxDevList[0], /* Array of Aux device ids */ + .auxInitRestoreFunction = NULL, /* Auxilliary init function */ + }, + /* ANA_1 */ + { + .testName = "ANA_1 PBIST", + .pbistInst = SDL_PBIST_INST_ANA_1, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_COMPUTE_CLUSTER0_AW5_MSMC_DFT_EMBED_PBIST_0, /* PBIST device id */ + .procRstNeeded = false, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "ANA_1", /* Primary core */ + .tisciProcId = 0x0u, /* No ProcId for ANA */ + .tisciDeviceId = 0x0u, /* ANA Device Id */ + .coreCustPwrSeqNeeded = false, + .numAuxDevices = ANA_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &PBIST_ANA1AuxDevList[0], /* Array of Aux device ids */ + .auxInitRestoreFunction = NULL, /* Auxilliary init function */ + }, + /* ANA_2 */ + { + .testName = "ANA_2 PBIST", + .pbistInst = SDL_PBIST_INST_ANA_2, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_COMPUTE_CLUSTER0_AW6_MSMC_DFT_EMBED_PBIST_0, /* PBIST device id */ + .procRstNeeded = false, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "ANA_2", /* Primary core */ + .tisciProcId = 0x0u, /* No ProcId for ANA */ + .tisciDeviceId = 0x0u, /* ANA Device Id */ + .coreCustPwrSeqNeeded = false, + .numAuxDevices = ANA_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &PBIST_ANA2AuxDevList[0], /* Array of Aux device ids */ + .auxInitRestoreFunction = NULL, /* Auxilliary init function */ + }, + /* ANA_3 */ + { + .testName = "ANA_3 PBIST", + .pbistInst = SDL_PBIST_INST_ANA_3, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_COMPUTE_CLUSTER0_AW7_MSMC_DFT_EMBED_PBIST_0, /* PBIST device id */ + .procRstNeeded = false, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "ANA_3", /* Primary core */ + .tisciProcId = 0x0u, /* No ProcId for ANA */ + .tisciDeviceId = 0x0u, /* ANA Device Id */ + .coreCustPwrSeqNeeded = false, + .numAuxDevices = ANA_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &PBIST_ANA3AuxDevList[0], /* Array of Aux device ids */ + .auxInitRestoreFunction = NULL, /* Auxilliary init function */ + }, + /* MSMC */ + { + .testName = "MSMC PBIST", + .pbistInst = SDL_PBIST_INST_MSMC, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_COMPUTE_CLUSTER0_MSMC_DFT_EMBED_PBIST_0, /* PBIST device id */ + .procRstNeeded = false, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "", /* Primary core */ + .tisciProcId = 0x0u, + .tisciDeviceId = 0x0u, + .coreCustPwrSeqNeeded = false, /* A72 needs custom powerdown sequence steps */ + .numAuxDevices = MSMC_NUM_AUX_DEVICES, /* Number of Aux devices */ + .auxDeviceIdsP = &PBIST_MSMCAuxDevList[0], /* Array of Aux device ids */ + .auxInitRestoreFunction = NULL, + }, + /* Main R5F 1 */ + { + .testName = "Main R5F 1 PBIST", + .pbistInst = SDL_PBIST_INST_MAINR5F1, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_PBIST10, /* PBIST device id */ + .procRstNeeded = true, + .secondaryCoreNeeded = true, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "Main R5F1 core0", /* Primary core */ + .secCoreName = "Main R5F1 core1", /* Secondary core */ + .tisciProcId = SCICLIENT_PROC_ID_R5FSS0_CORE0, /* Main R5F core 0 Proc Id */ + .tisciSecProcId = SCICLIENT_PROC_ID_R5FSS0_CORE1, /* Main R5F core 1 Proc Id */ + .tisciDeviceId = TISCI_DEV_R5FSS0_CORE0, /* Main R5F core 0 Device id */ + .tisciSecDeviceId = TISCI_DEV_R5FSS0_CORE1, /* Main R5F core 1 Device id */ + .coreCustPwrSeqNeeded = false, + .numAuxDevices = 0u, /* No Aux devices */ + .auxInitRestoreFunction = NULL, /* Auxilliary init function */ + }, + /* MCU PSROM*/ + { + .testName = "PBIST MCU PSROM", + .pbistInst = SDL_PBIST_INST_MCUR5F0, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_MCU_PBIST0, /* PBIST device id */ + .procRstNeeded = false, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "", /* Primary core */ + .tisciProcId = 0x0u, + .tisciDeviceId = 0x0u, + .coreCustPwrSeqNeeded = false, /* A72 needs custom powerdown sequence steps */ + .numAuxDevices = 0x0, /* Number of Aux devices */ + .auxDeviceIdsP = 0x0, /* Array of Aux device ids */ + .auxInitRestoreFunction = NULL, + }, + /* MCU_1*/ + { + .testName = "PBIST MCU_1", + .pbistInst = SDL_PBIST_INST_MCUR5F1, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_MCU_PBIST1, /* PBIST device id */ + .procRstNeeded = false, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "", /* Primary core */ + .tisciProcId = 0x0u, + .tisciDeviceId = 0x0u, + .coreCustPwrSeqNeeded = false, /* A72 needs custom powerdown sequence steps */ + .numAuxDevices = 0x0, /* Number of Aux devices */ + .auxDeviceIdsP = 0x0, /* Array of Aux device ids */ + .auxInitRestoreFunction = NULL, + }, + /* MCU PULSAR*/ + { + .testName = "PBIST MCU PULSAR", + .pbistInst = SDL_PBIST_INST_MCU_PULSAR, + .numPostPbistToCheck = 0u, + .tisciPBISTDeviceId = TISCI_DEV_MCU_PBIST2, /* PBIST device id */ + .procRstNeeded = false, + .secondaryCoreNeeded = false, /* Secondary core needed */ + .thirdCoreNeeded = false, + .fourthCoreNeeded = false, + .coreName = "", /* Primary core */ + .tisciProcId = 0x0u, + .tisciDeviceId = 0x0u, + .coreCustPwrSeqNeeded = false, /* A72 needs custom powerdown sequence steps */ + .numAuxDevices = 0x0, /* Number of Aux devices */ + .auxDeviceIdsP = 0x0, /* Array of Aux device ids */ + .auxInitRestoreFunction = NULL, + }, + + + +}; + +/* ========================================================================== */ +/* External Variables */ +/* ========================================================================== */ + + +/* ========================================================================== */ +/* Function Definitions */ +/* ========================================================================== */ + +/* + InitRestore functions : Initialize or Restore based on init flag + init : TRUE --> Initialize + init : FALSE --> Restore +*/ +int32_t PBIST_A720_0AuxInitRestore(bool init) +{ + int32_t testResult = 0; + bool result; + + CSL_RatTranslationCfgInfo translationCfg; + uint32_t *localP = (uint32_t *)PBIST_REGION2_LOCAL_BASE; + + /* Add RAT configuration to access address > 32bit address range */ + translationCfg.translatedAddress = CSL_COMPUTE_CLUSTER0_CC_BASE; + translationCfg.sizeInBytes = PBIST_REG_REGION_SIZE; + translationCfg.baseAddress = (uint32_t)PBIST_REGION2_LOCAL_BASE; + + /* Set up RAT translation */ + result = CSL_ratConfigRegionTranslation((CSL_ratRegs *)PBIST_RAT_CFG_BASE, + PBIST_RAT_REGION2_INDEX, &translationCfg); + if (result == false) { + UART_printf(" CSL_ratConfigRegionTranslation...FAILED \n"); + testResult = -1; + } + + if (testResult == 0) + { + if (init) + { + *((uint32_t *)(((uint32_t)localP) + 0x100)) = 0x1; + } + else + { + *((uint32_t *)(((uint32_t)localP) + 0x100)) = 0x0; + } + } + + if (testResult == 0) + { + /* Disable RAT translation */ + result = CSL_ratDisableRegionTranslation((CSL_ratRegs *)PBIST_RAT_CFG_BASE, + PBIST_RAT_REGION2_INDEX); + if (result == false) { + UART_printf(" CSL_ratDisableRegionTranslation...FAILED \n"); + testResult = -1; + } + } + + return testResult; +} + +int32_t PBIST_A720_1AuxInitRestore(bool init) +{ + int32_t testResult = 0; + bool result; + + CSL_RatTranslationCfgInfo translationCfg; + uint32_t *localP = (uint32_t *)PBIST_REGION2_LOCAL_BASE; + + /* Add RAT configuration to access address > 32bit address range */ + translationCfg.translatedAddress = CSL_COMPUTE_CLUSTER0_CC_BASE; + translationCfg.sizeInBytes = PBIST_REG_REGION_SIZE; + translationCfg.baseAddress = (uint32_t)PBIST_REGION2_LOCAL_BASE; + + /* Set up RAT translation */ + result = CSL_ratConfigRegionTranslation((CSL_ratRegs *)PBIST_RAT_CFG_BASE, + PBIST_RAT_REGION2_INDEX, &translationCfg); + if (result == false) { + UART_printf(" CSL_ratConfigRegionTranslation...FAILED \n"); + testResult = -1; + } + + if (testResult == 0) + { + if (init) + { + *((uint32_t *)(((uint32_t)localP) + 0x100)) = 0x2; + } + else + { + *((uint32_t *)(((uint32_t)localP) + 0x100)) = 0x0; + } + } + + if (testResult == 0) + { + /* Disable RAT translation */ + result = CSL_ratDisableRegionTranslation((CSL_ratRegs *)PBIST_RAT_CFG_BASE, + PBIST_RAT_REGION2_INDEX); + if (result == false) { + UART_printf(" CSL_ratDisableRegionTranslation...FAILED \n"); + testResult = -1; + } + } + + return testResult; +} + +int32_t PBIST_A721_0AuxInitRestore(bool init) +{ + int32_t testResult = 0; + bool result; + + CSL_RatTranslationCfgInfo translationCfg; + uint32_t *localP = (uint32_t *)PBIST_REGION2_LOCAL_BASE; + + /* Add RAT configuration to access address > 32bit address range */ + translationCfg.translatedAddress = CSL_COMPUTE_CLUSTER0_CC_BASE; + translationCfg.sizeInBytes = PBIST_REG_REGION_SIZE; + translationCfg.baseAddress = (uint32_t)PBIST_REGION2_LOCAL_BASE; + + /* Set up RAT translation */ + result = CSL_ratConfigRegionTranslation((CSL_ratRegs *)PBIST_RAT_CFG_BASE, + PBIST_RAT_REGION2_INDEX, &translationCfg); + if (result == false) { + UART_printf(" CSL_ratConfigRegionTranslation...FAILED \n"); + testResult = -1; + } + + if (testResult == 0) + { + if (init) + { + *((uint32_t *)(((uint32_t)localP) + 0x104)) = 0x1; + } + else + { + *((uint32_t *)(((uint32_t)localP) + 0x104)) = 0x0; + } + } + + if (testResult == 0) + { + /* Disable RAT translation */ + result = CSL_ratDisableRegionTranslation((CSL_ratRegs *)PBIST_RAT_CFG_BASE, + PBIST_RAT_REGION2_INDEX); + if (result == false) { + UART_printf(" CSL_ratDisableRegionTranslation...FAILED \n"); + testResult = -1; + } + } + + return testResult; +} + +int32_t PBIST_A721_1AuxInitRestore(bool init) +{ + int32_t testResult = 0; + bool result; + + CSL_RatTranslationCfgInfo translationCfg; + uint32_t *localP = (uint32_t *)PBIST_REGION2_LOCAL_BASE; + + /* Add RAT configuration to access address > 32bit address range */ + translationCfg.translatedAddress = CSL_COMPUTE_CLUSTER0_CC_BASE; + translationCfg.sizeInBytes = PBIST_REG_REGION_SIZE; + translationCfg.baseAddress = (uint32_t)PBIST_REGION2_LOCAL_BASE; + + /* Set up RAT translation */ + result = CSL_ratConfigRegionTranslation((CSL_ratRegs *)PBIST_RAT_CFG_BASE, + PBIST_RAT_REGION2_INDEX, &translationCfg); + if (result == false) { + UART_printf(" CSL_ratConfigRegionTranslation...FAILED \n"); + testResult = -1; + } + + if (testResult == 0) + { + if (init) + { + *((uint32_t *)(((uint32_t)localP) + 0x104)) = 0x2; + } + else + { + *((uint32_t *)(((uint32_t)localP) + 0x104)) = 0x0; + } + } + + if (testResult == 0) + { + /* Disable RAT translation */ + result = CSL_ratDisableRegionTranslation((CSL_ratRegs *)PBIST_RAT_CFG_BASE, + PBIST_RAT_REGION2_INDEX); + if (result == false) { + UART_printf(" CSL_ratDisableRegionTranslation...FAILED \n"); + testResult = -1; + } + } + + return testResult; +} + +/* define the unlock and lock values */ +#define KICK0_UNLOCK_VAL 0x68EF3490 +#define KICK1_UNLOCK_VAL 0xD172BC5A +#define KICK_LOCK_VAL 0x00000000 + +int32_t PBIST_VPAC0AuxInitRestore(bool init) +{ + int32_t testResult = 0; + CSL_viss_topRegs *vissTopRegsP; + + *((uint32_t *)(SDL_WKUP_CTRL_MMR0_CFG0_BASE + SDL_WKUP_CTRL_MMR_CFG0_LOCK6_KICK0)) = KICK0_UNLOCK_VAL; + *((uint32_t *)(SDL_WKUP_CTRL_MMR0_CFG0_BASE + SDL_WKUP_CTRL_MMR_CFG0_LOCK6_KICK1)) = KICK1_UNLOCK_VAL; + *((uint32_t *)(SDL_WKUP_CTRL_MMR0_CFG0_BASE + SDL_WKUP_CTRL_MMR_CFG0_MAIN_CLKGATE_CTRL1)) = 0xFFFFFFFF; + + vissTopRegsP = (CSL_viss_topRegs *)CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE; + if (init) + { + *((uint32_t *)(CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE + CSL_VISS_TOP_TEST_CNTL)) = 0x1; + *((uint32_t *)(CSL_VPAC0_VPAC_REGS_VPAC_REGS_CFG_IP_MMRS_BASE + CSL_VPAC_CNTL_VPAC_TEST_CTRL)) = 0x00000003; + vissTopRegsP->VISS_CNTL = CSL_VISS_TOP_VISS_CNTL_NSF4V_EN_MASK + | CSL_VISS_TOP_VISS_CNTL_GLBCE_EN_MASK; + } + else + { + vissTopRegsP->VISS_CNTL &= (~(CSL_VISS_TOP_VISS_CNTL_NSF4V_EN_MASK + | CSL_VISS_TOP_VISS_CNTL_GLBCE_EN_MASK)); + } + + return testResult; +} + +int32_t PBIST_VPAC1AuxInitRestore(bool init) +{ + int32_t testResult = 0; + CSL_viss_topRegs *vissTopRegsP; + + *((uint32_t *)(SDL_WKUP_CTRL_MMR0_CFG0_BASE + SDL_WKUP_CTRL_MMR_CFG0_LOCK6_KICK0)) = KICK0_UNLOCK_VAL; + *((uint32_t *)(SDL_WKUP_CTRL_MMR0_CFG0_BASE + SDL_WKUP_CTRL_MMR_CFG0_LOCK6_KICK1)) = KICK1_UNLOCK_VAL; + *((uint32_t *)(SDL_WKUP_CTRL_MMR0_CFG0_BASE + SDL_WKUP_CTRL_MMR_CFG0_MAIN_CLKGATE_CTRL1)) = 0xFFFFFFFF; + + vissTopRegsP = (CSL_viss_topRegs *)CSL_VPAC1_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE; + if (init) + { + *((uint32_t *)(CSL_VPAC1_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE + CSL_VISS_TOP_TEST_CNTL)) = 0x1; + *((uint32_t *)(CSL_VPAC1_VPAC_REGS_VPAC_REGS_CFG_IP_MMRS_BASE + CSL_VPAC_CNTL_VPAC_TEST_CTRL)) = 0x00000003; + vissTopRegsP->VISS_CNTL = CSL_VISS_TOP_VISS_CNTL_NSF4V_EN_MASK + | CSL_VISS_TOP_VISS_CNTL_GLBCE_EN_MASK; + } + else + { + vissTopRegsP->VISS_CNTL &= (~(CSL_VISS_TOP_VISS_CNTL_NSF4V_EN_MASK + | CSL_VISS_TOP_VISS_CNTL_GLBCE_EN_MASK)); + } + + return testResult; +} + +void ecc_ufs_config(void) +{ + uint32_t retval; + + retval = *((uint32_t *)(SDL_UFS0_P2A_WRAP_CFG_VBP_UFSHCI_BASE + 0x34)) | 0x00000001; + *((uint32_t *)(SDL_UFS0_P2A_WRAP_CFG_VBP_UFSHCI_BASE + 0x34)) = retval; + retval = *((uint32_t *)(SDL_UFS0_P2A_WRAP_CFG_VBP_UFSHCI_BASE + 0x34)) & 0x00000001; + while (retval == 0) + { + retval = *((uint32_t *)(SDL_UFS0_P2A_WRAP_CFG_VBP_UFSHCI_BASE + 0x34)) & 0x00000001; + } + + retval = *((uint32_t *)(SDL_UFS0_P2A_WRAP_CFG_VBP_UFSHCI_BASE + 0xC8)) | 0x000000F8; + *((uint32_t *)(SDL_UFS0_P2A_WRAP_CFG_VBP_UFSHCI_BASE + 0xC8)) = retval; +} + +int32_t PBIST_HCAuxInitRestore(bool init) +{ + int32_t testResult = 0; + + CSL_Cp_aceRegs *SA2ULRegsP; + + SA2ULRegsP = (CSL_Cp_aceRegs *)CSL_SA2_UL0_BASE; + + *((uint32_t *)(SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_LOCK3_KICK0)) = KICK0_UNLOCK_VAL; + *((uint32_t *)(SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_LOCK3_KICK1)) = KICK1_UNLOCK_VAL; + *((uint32_t *)(SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_PBIST_EN)) = 0xFFFFFFFF; + + if (init) + { + ecc_ufs_config(); + *((uint32_t *)(0x4E01000)) = 0xA9B; + + SA2ULRegsP->UPDATES.ENGINE_ENABLE |= CSL_CP_ACE_UPDATES_ENGINE_ENABLE_PKA_EN_MASK; + } + else + { + SA2ULRegsP->UPDATES.ENGINE_ENABLE &= (~CSL_CP_ACE_UPDATES_ENGINE_ENABLE_PKA_EN_MASK); + } + + return testResult; +} + +int32_t PBIST_MainInfra0AuxInitRestore(bool init) +{ + int32_t testResult = 0; + + *((uint32_t *)(SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_LOCK3_KICK0)) = KICK0_UNLOCK_VAL; + *((uint32_t *)(SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_LOCK3_KICK1)) = KICK1_UNLOCK_VAL; + *((uint32_t *)(SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_PBIST_EN)) = 0xFFFFFFFF; + + return testResult; +} + +int32_t PBIST_NAVSSAuxInitRestore(bool init) +{ + *((uint32_t *)(SDL_WKUP_CTRL_MMR0_CFG0_BASE + SDL_WKUP_CTRL_MMR_CFG0_LOCK6_KICK0)) = KICK0_UNLOCK_VAL; + *((uint32_t *)(SDL_WKUP_CTRL_MMR0_CFG0_BASE + SDL_WKUP_CTRL_MMR_CFG0_LOCK6_KICK1)) = KICK1_UNLOCK_VAL; + *((uint32_t *)(SDL_WKUP_CTRL_MMR0_CFG0_BASE + SDL_WKUP_CTRL_MMR_CFG0_MAIN_CLKGATE_CTRL1)) = 0xFFFFFFFF; + + return 0; +} + +int32_t PBIST_CodecAuxInitRestore(bool init) +{ + int32_t testResult = 0; + *((uint32_t *)(SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_LOCK3_KICK0)) = KICK0_UNLOCK_VAL; + *((uint32_t *)(SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_LOCK3_KICK1)) = KICK1_UNLOCK_VAL; + *((uint32_t *)(SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_PBIST_EN)) = 0xFFFFFFFF; + return testResult; +} + + +int32_t PBIST_GPUAuxInitRestore(bool init) +{ + int32_t testResult = 0; + bool result; + int32_t i = 0; + uint32_t timeoutCnt; + + CSL_RatTranslationCfgInfo translationCfg; + + uint32_t localP = (uint32_t)PBIST_REGION2_LOCAL_BASE; + + /* Add RAT configuration to access address > 32bit address range */ + translationCfg.translatedAddress = SDL_AEP_GPU_BXS464_WRAP0_CORE_MMRS_BASE; + translationCfg.sizeInBytes = PBIST_REG_REGION2_SIZE; + translationCfg.baseAddress = (uint32_t)PBIST_REGION2_LOCAL_BASE; + + /* Set up RAT translation */ + result = CSL_ratConfigRegionTranslation((CSL_ratRegs *)PBIST_RAT_CFG_BASE, + PBIST_RAT_REGION2_INDEX, &translationCfg); + if (result == false) { + UART_printf(" CSL_ratConfigRegionTranslation...FAILED \n"); + testResult = -1; + } + + if (testResult == 0) + { + if (init) + { + *((uint32_t *)(localP + 0xA100)) = 0x0; + timeoutCnt = 100000U; + while (timeoutCnt-- > 0) + { + if (*((uint32_t *)(localP + 0xA100)) == (uint32_t)0x0) + { + break; + } + } + if (timeoutCnt == 0) + { + UART_printf("timeout in GPUAuxInitRestore [1]\n"); + } + + /* Force all GPU clocks on */ + *((uint64_t *)(localP)) = 0x0015550015115555; + + /* Force the FW Processor clocks to ON to enable testing of mars memories */ + *((uint32_t *)(localP + 0x3090)) = 0x00000001; + i = 1000; + while(i--); + *((uint32_t *)(localP + 0x3480)) = 0x00000001; + timeoutCnt = 100000U; + while (timeoutCnt-- > 0) + { + if((*(uint32_t *)(localP + 0x3488) & 0x400) == (uint32_t)0x400) + { + break; + } + } + if (timeoutCnt == 0) + { + UART_printf("timeout in GPUAuxInitRestore [2]\n"); + } + *((uint32_t *)(localP + 0x3480)) = 0x80000001; + i = 1000; + while(i--); + timeoutCnt = 100000U; + while (timeoutCnt-- > 0) + { + if((*((uint32_t *)(((uint32_t)localP) + 0x3488)) & 0x200) == (uint32_t)0x200) + { + break; + } + } + if (timeoutCnt == 0) + { + UART_printf("timeout in GPUAuxInitResotre [3]\n"); + } + *((uint32_t *)(localP + 0x3420)) = 0x000001FF; + *((uint32_t *)(localP + 0x34B8)) = 0x002307F8; + timeoutCnt = 100000U; + while (timeoutCnt-- > 0) + { + if((*((uint32_t *)(localP + 0x34B0)) & 0x1700) == (uint32_t)0x0000) + { + break; + } + } + if (timeoutCnt == 0) + { + UART_printf("timeout in GPUAuxInitRestore [4]\n"); + } + i = 1000; + while(i--); + *((uint32_t *)(((uint32_t)localP) + 0x3480)) = 0x00; + i = 1000; + while(i--); + } + else + { + /* TODO: Need to see how to revert */ + } + } + if (testResult == 0) + { + /* Disable RAT translation */ + result = CSL_ratDisableRegionTranslation((CSL_ratRegs *)PBIST_RAT_CFG_BASE, + PBIST_RAT_REGION2_INDEX); + if (result == false) { + UART_printf(" CSL_ratDisableRegionTranslation...FAILED \n"); + testResult = -1; + } + } + + return testResult; +} + +int32_t PBIST_DSSAuxInitRestore(bool init) +{ + int32_t testResult = 0; + uint32_t value; + + uint32_t *common_m = (uint32_t *)(CSL_DSS0_DISPC_0_COMMON_M_BASE); + + uint32_t *vp2 = (uint32_t *)(CSL_DSS0_VP2_BASE); + + uint32_t *ovr2 = (uint32_t *)(SDL_DSS0_OVR2_BASE); + + uint32_t *vid1 = (uint32_t *)(SDL_DSS0_VID1_BASE); + uint32_t *vid2 = (uint32_t *)(SDL_DSS0_VIDL1_BASE); + uint32_t *vid3 = (uint32_t *)(SDL_DSS0_VID2_BASE); + uint32_t *vid4 = (uint32_t *)(SDL_DSS0_VIDL2_BASE); + + + if (init) + { + *((uint32_t *)(SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_LOCK3_KICK0)) = KICK0_UNLOCK_VAL; + *((uint32_t *)(SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_LOCK3_KICK1)) = KICK1_UNLOCK_VAL; + *((uint32_t *)(SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_PBIST_EN)) = 0xFFFFFFFF; + + *((uint32_t *)(SDL_WKUP_CTRL_MMR0_CFG0_BASE + SDL_WKUP_CTRL_MMR_CFG0_LOCK6_KICK0)) = KICK0_UNLOCK_VAL; + *((uint32_t *)(SDL_WKUP_CTRL_MMR0_CFG0_BASE + SDL_WKUP_CTRL_MMR_CFG0_LOCK6_KICK1)) = KICK1_UNLOCK_VAL; + *((uint32_t *)(SDL_WKUP_CTRL_MMR0_CFG0_BASE + SDL_WKUP_CTRL_MMR_CFG0_MAIN_CLKGATE_CTRL2)) = 0xFFFFFFFF; + + CSL_REG32_WR(&((CSL_dss_vid1Regs*)(vid1))->FBDC_ATTRIBUTES, 1); + CSL_REG32_WR(&((CSL_dss_vidl1Regs*)(vid2))->FBDC_ATTRIBUTES, 1); + CSL_REG32_WR(&((CSL_dss_vid1Regs*)(vid3))->FBDC_ATTRIBUTES, 1); + CSL_REG32_WR(&((CSL_dss_vidl1Regs*)(vid4))->FBDC_ATTRIBUTES, 1); + + CSL_REG32_FINS(&((CSL_dss_vidl1Regs*)(vid2))->ATTRIBUTES, DSS_VIDL1_ATTRIBUTES_ENABLE, 1); + + value = CSL_FMK(DSS_OVR1_ATTRIBUTES_ENABLE, 1) | CSL_FMK(DSS_OVR1_ATTRIBUTES_CHANNELIN, 1); + CSL_REG32_WR(&((CSL_dss_ovr1Regs *)(ovr2))->ATTRIBUTES, value); + + { + uint32_t division = 2400 / 100; + + uint32_t divfactor = 0x8000 | (division-1); + + *((uint32_t *)(SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_LOCK2_KICK0)) = KICK0_UNLOCK_VAL; + *((uint32_t *)(SDL_CTRL_MMR0_CFG0_BASE + SDL_MAIN_CTRL_MMR_CFG0_LOCK2_KICK1)) = KICK1_UNLOCK_VAL; + + *((uint32_t *)(SDL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_DSS_DISPC0_CLKSEL1)) = 0x1; + *((uint32_t *)(CSL_PLL0_CFG_BASE + CSL_MAIN_PLL_MMR_CFG_PLL19_PID + CSL_MAIN_PLL_MMR_CFG_PLL0_HSDIV_CTRL0)) = divfactor; + } + + CSL_REG32_FINS(&((CSL_dss_common_mRegs*)(common_m))->DISPC_CONNECTIONS, DSS_COMMON_M_DISPC_CONNECTIONS_DPI_0_CONN, 4); + + CSL_REG32_FINS(&((CSL_dss_vp1Regs*)(vp2))->CONTROL, DSS_VP1_CONTROL_ENABLE, 1); + } + + return testResult; +} +char * PBIST_getPostStatusString(SDL_PBIST_postStatus postStatus) +{ + if (postStatus == SDL_PBIST_POST_NOT_RUN) + { + return PBIST_POST_NOT_RUN_STR; + } + else if (postStatus == SDL_PBIST_POST_TIMEOUT) + { + return PBIST_POST_ATTEMPTED_TIMEOUT_STR; + } + else if (postStatus == SDL_PBIST_POST_COMPLETED_FAILURE) + { + return PBIST_POST_COMPLETED_FAILURE_STR; + } + else if (postStatus == SDL_PBIST_POST_COMPLETED_SUCCESS) + { + return PBIST_POST_COMPLETED_SUCCESS_STR; + } + return NULL; +} + +void PBIST_printPostStatus(SDL_PBIST_postResult *result) +{ + UART_printf(" HW POST MCU Status : %s\n", (PBIST_getPostStatusString(result->mcuPostStatus)) ? : "Invalid"); + + return; +} \ No newline at end of file diff --git a/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/pbist_defs.h b/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/pbist_defs.h new file mode 100755 index 00000000..1dc5da71 --- /dev/null +++ b/packages/ti/boot/sbl/example/boot_app/bist/soc/j784s4/pbist_defs.h @@ -0,0 +1,118 @@ +/******************************************************************** + * Copyright (C) 2022 Texas Instruments Incorporated. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Name : pbist_defs.h +*/ +#ifndef PBIST_DEFS_H_ +#define PBIST_DEFS_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* ========================================================================== */ +/* Include Files */ +/* ========================================================================== */ +#include +#include +#include +#include + +#include "bist_core_defs.h" + +/* ========================================================================== */ +/* Macros & Typedefs */ +/* ========================================================================== */ + +#define PBIST_REGION_LOCAL_BASE (0x60000000u) + +#define PBIST_REGION2_LOCAL_BASE (0x68000000u) + +#define PBIST_RAT_REGION_INDEX 0 +#define PBIST_RAT_REGION2_INDEX 1 + +#define PBIST_REG_REGION_SIZE (0x400u) +#define PBIST_REG_REGION2_SIZE (0x10000u) + +/* Firewall definitions */ +#define FW_REGION_ENABLE (0xAU) +#define FW_MCU_R5F0_PRIVID (96U) + +typedef void (*PBIST_handlerPtr)(uint32_t instanceId); + +/* + InitRestore function : Initialize or Restore based on init flag + init : TRUE --> Initialize + init : FALSE --> Restore +*/ +typedef int32_t (*PBIST_auxInitRestoreFunctionPtr)(bool init); + +typedef struct PBIST_TestHandle_s +{ + char testName[PBIST_INSTANCE_NAME_MAX_LENGTH]; + SDL_PBIST_inst pbistInst; + uint32_t tisciPBISTDeviceId; + bool procRstNeeded; + bool secondaryCoreNeeded; + bool thirdCoreNeeded; + bool fourthCoreNeeded; + char coreName[16]; + char secCoreName[16]; + char thCoreName[16]; + char foCoreName[16]; + uint32_t tisciProcId; + uint32_t tisciSecProcId; + uint32_t tisciThProcId; + uint32_t tisciFoProcId; + uint32_t tisciDeviceId; + uint32_t tisciSecDeviceId; + uint32_t tisciThDeviceId; + uint32_t tisciFoDeviceId; + bool coreCustPwrSeqNeeded; + uint8_t numPostPbistToCheck; + uint32_t numAuxDevices; + uint32_t *auxDeviceIdsP; + PBIST_auxInitRestoreFunctionPtr auxInitRestoreFunction; +} PBIST_TestHandle_t; + +extern PBIST_TestHandle_t PBIST_TestHandleArray[PBIST_MAX_INSTANCE+1]; + +/* ========================================================================== */ +/* Function Declarations */ +/* ========================================================================== */ + +void PBIST_printPostStatus(SDL_PBIST_postResult *result); + +#ifdef __cplusplus +} +#endif +#endif /* PBIST_DEFS_H_ */ diff --git a/packages/ti/boot/sbl/example/boot_app/boot_app_main.c b/packages/ti/boot/sbl/example/boot_app/boot_app_main.c index 4c0c4995..73231700 100644 --- a/packages/ti/boot/sbl/example/boot_app/boot_app_main.c +++ b/packages/ti/boot/sbl/example/boot_app/boot_app_main.c @@ -81,7 +81,10 @@ #elif defined(BOOT_OSPI) #include "boot_app_ospi.h" #endif - +#if defined(BIST_TASK_ENABLED) +#include "bist.h" +#include "test/osal/osal_interface.h" +#endif /* ========================================================================== */ /* Macros & Typedefs */ /* ========================================================================== */ @@ -91,6 +94,11 @@ /**< Task Priority Levels */ #define BOOT_TASK_PRIORITY (2) +#if defined(BIST_TASK_ENABLED) +#define BIST_TASK_PRIORITY (3) +#define BIST_TASK_STACKSIZE (16U * 1024U) +#endif + /* uncomment the following for debug logs */ // #define UART_PRINT_DEBUG @@ -104,6 +112,9 @@ /* Function Declarations */ /* ========================================================================== */ static void BootApp_TaskFxn(void* a0, void* a1); +#if defined(BIST_TASK_ENABLED) +static void BistApp_TaskFxn(void* a0, void* a1); +#endif static uint32_t Boot_App(); static void BootApp_AppSetup(); static int32_t BootApp_RequestStageCores(uint8_t stageNum); @@ -125,6 +136,14 @@ static uint8_t gBootAppTaskStack[APP_TASK_STACK] __attribute__((aligned(32))); TaskP_Handle gbootTask; static uint64_t gtimeBootAppStart, gtimeBootAppFinish; +#if defined(BIST_TASK_ENABLED) +static uint8_t gBist_TaskStack[BIST_TASK_STACKSIZE] __attribute__((aligned(32))); +TaskP_Handle gbistTask; +static uint64_t gtimeBistAppStart, gtimeBistAppFinish; +/* Semaphore to indicate BIST Task completion */ +static SemaphoreP_Handle gBistTaskCompletedSem = NULL; +#endif + int32_t main(void) { Board_initCfg boardCfg; @@ -158,7 +177,30 @@ int32_t main(void) UART_printf("\nBoot Task creation failed\r\n"); OS_stop(); } +#if defined(BIST_TASK_ENABLED) + /* initializing the semaphores*/ + SemaphoreP_Params semParams; + SemaphoreP_Params_init(&semParams); + gBistTaskCompletedSem = SemaphoreP_create(0, &semParams); + if(NULL == gBistTaskCompletedSem) + { + UART_printf("\n Semaphore create failed\r\n"); + } + /* Initialize the task params */ + TaskP_Params bistTaskParams; + TaskP_Params_init(&bistTaskParams); + bistTaskParams.priority = BIST_TASK_PRIORITY; + bistTaskParams.stack = gBist_TaskStack; + bistTaskParams.stacksize = sizeof (gBist_TaskStack); + + gbistTask = TaskP_create(&BistApp_TaskFxn, &bistTaskParams); + if (NULL == gbistTask) + { + UART_printf("\nBist Task creation failed\r\n"); + OS_stop(); + } +#endif OS_start(); /* does not return */ return(0); @@ -166,6 +208,10 @@ int32_t main(void) static void BootApp_TaskFxn(void* a0, void* a1) { +#if defined(BIST_TASK_ENABLED) + /* Wait for the BIST task completion */ + SemaphoreP_pend(gBistTaskCompletedSem, SemaphoreP_WAIT_FOREVER); +#endif gtimeBootAppStart = BootApp_GetTimeInMicroSec(CSL_armR5PmuReadCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM)); Boot_App(); @@ -177,6 +223,27 @@ static void BootApp_TaskFxn(void* a0, void* a1) return; } +#if defined(BIST_TASK_ENABLED) +static void BistApp_TaskFxn(void* a0, void* a1) +{ + /* Initialize the SDL osal */ + SDL_TEST_osalInit(); + + gtimeBistAppStart = BootApp_GetTimeInMicroSec(CSL_armR5PmuReadCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM)); + + bist_TaskFxn(); + + gtimeBistAppFinish = BootApp_GetTimeInMicroSec(CSL_armR5PmuReadCntr(CSL_ARM_R5_PMU_CYCLE_COUNTER_NUM)); + + UART_printf("\nMCU Bist Task started at %d usecs and finished at %d usecs\r\n", (uint32_t)gtimeBistAppStart, (uint32_t)gtimeBistAppFinish); + + /* Post semaphore after BIST task completion so other tasks could start execution */ + SemaphoreP_post(gBistTaskCompletedSem); + + return; +} +#endif + uint32_t Boot_App() { uint32_t retVal; diff --git a/packages/ti/boot/sbl/sbl_component.mk b/packages/ti/boot/sbl/sbl_component.mk index 2477c722..76c9a16c 100644 --- a/packages/ti/boot/sbl/sbl_component.mk +++ b/packages/ti/boot/sbl/sbl_component.mk @@ -1350,6 +1350,7 @@ SBL_CFLAGS += -DSBL_LOG_LEVEL=2 SBL_CFLAGS += -DSBL_ENABLE_PLL SBL_CFLAGS += -DSBL_ENABLE_CLOCKS SBL_CFLAGS += -DSBL_ENABLE_DDR +SBL_CFLAGS += -DSBL_ENABLE_BIST ifeq ($(SOC), $(filter $(SOC), j721e)) SBL_CFLAGS += -DSBL_ENABLE_SERDES diff --git a/packages/ti/drv/sciclient/src/rm_pm_hal/pm/soc/j784s4/dmsc.c b/packages/ti/drv/sciclient/src/rm_pm_hal/pm/soc/j784s4/dmsc.c index 748a295e..ba3f6d31 100644 --- a/packages/ti/drv/sciclient/src/rm_pm_hal/pm/soc/j784s4/dmsc.c +++ b/packages/ti/drv/sciclient/src/rm_pm_hal/pm/soc/j784s4/dmsc.c @@ -95,7 +95,12 @@ static s32 wait_reset_done_with_timeout(domgrp_t domain) if (timeout == 0U) { ret = -ETIMEDOUT; } - + else + { + /* Delay to allow access Main domain */ + osal_delay(250); + } + return ret; } -- 2.34.1