From 9af6b92b30fc65e6a701f7f6172017b620d36e2d Mon Sep 17 00:00:00 2001
From: Doredla Sudheer Kumar <s-doredla@ti.com>
Date: Thu, 1 Jun 2023 23:55:46 +0530
Subject: [PATCH] Ported MCAL EthVirtMAC supported in MCU2_1 core to MCU1_0
 core. Made revalent changes in Ethfw and mcusw example application.

Signed-off-by: Doredla Sudheer Kumar <s-doredla@ti.com>

diff --git a/ethfw/apps/app_remoteswitchcfg_server/mcu_2_0/main.c b/ethfw/apps/app_remoteswitchcfg_server/mcu_2_0/main.c
index 75f18755..8a61070b 100644
--- a/ethfw/apps/app_remoteswitchcfg_server/mcu_2_0/main.c
+++ b/ethfw/apps/app_remoteswitchcfg_server/mcu_2_0/main.c
@@ -462,7 +462,7 @@ static EthFw_VirtPortCfg gEthApp_virtPortCfg[] =
 static EthFw_VirtPortCfg gEthApp_autosarVirtPortCfg[] =
 {
     {
-        .remoteCoreId = IPC_MCU2_1,
+        .remoteCoreId = IPC_MCU1_0,
         .portId       = ETHREMOTECFG_SWITCH_PORT_1,
     },
 };
diff --git a/ethfw/apps/common/r5f_mpu_j721e_default.c b/ethfw/apps/common/r5f_mpu_j721e_default.c
index 1a3d40bf..5a05ab90 100644
--- a/ethfw/apps/common/r5f_mpu_j721e_default.c
+++ b/ethfw/apps/common/r5f_mpu_j721e_default.c
@@ -170,4 +170,18 @@ const CSL_ArmR5MpuRegionCfg  gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
         .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
         .memAttr          = 4U,
     },
+	{
+        /* Region 9 configuration: DDR_MCU1_0_IPC_ADDR as non-cache */
+        .regionId         = 9U,
+        .enable           = 1U,
+        .baseAddr         = 0xA0000000,
+        .size             = CSL_ARM_R5_MPU_REGION_SIZE_1MB,
+        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
+        .exeNeverControl  = 1U,
+        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
+        .shareable        = 0U,
+        .cacheable        = (uint32_t)FALSE,
+        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
+        .memAttr          = 4U,
+    },
 };
diff --git a/ethfw/apps/common/r5f_mpu_j721e_safertos.c b/ethfw/apps/common/r5f_mpu_j721e_safertos.c
index d868382a..f2dc817d 100644
--- a/ethfw/apps/common/r5f_mpu_j721e_safertos.c
+++ b/ethfw/apps/common/r5f_mpu_j721e_safertos.c
@@ -197,6 +197,21 @@ xMPU_CONFIG_PARAMETERS  gMPUConfigParms[CSL_ARM_R5F_MPU_REGIONS_MAX] =
         .ulRegionSize           = (2U * 1024U * 1024U), /* 2 MB */
         .ulSubRegionDisable     = mpuREGION_ALL_SUB_REGIONS_ENABLED,
     },
+    {
+        /* Region 8 configuration: DDR_MCU1_0_IPC */
+        .ulRegionNumber         = 8U,
+        .ulRegionBeginAddress   = 0xA0000000,
+        {
+            .ulexeNeverControl  = 1U,
+            .ulaccessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
+            .ulshareable        = 0U,
+            .ulcacheable        = 0U,
+            .ulcachePolicy      = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
+            .ulmemAttr          = 4U,
+        },
+        .ulRegionSize           = (1U * 1024U * 1024U), /* 1 MB */
+        .ulSubRegionDisable     = mpuREGION_ALL_SUB_REGIONS_ENABLED,
+    },
 };
 
 
diff --git a/mcusw/mcal_drv/mcal/Eth/makefile b/mcusw/mcal_drv/mcal/Eth/makefile
index ed519fe1..1fe2c6d9 100644
--- a/mcusw/mcal_drv/mcal/Eth/makefile
+++ b/mcusw/mcal_drv/mcal/Eth/makefile
@@ -26,7 +26,11 @@ INCDIR += $(MCUSW_INSTALL_PATH)/mcal_drv/mcal/examples_config/EthTrcv_Demo_Cfg/o
 
 BUILD_VARIANT ?= PreCompile
 ifeq ($(BUILD_VARIANT), PreCompile)
+  ifeq ($(BUILD_APP), eth_virtmac_app)
+  INCDIR += $(MCUSW_INSTALL_PATH)/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/$(SOC)/$(CORE)_cpswng/include
+  else
   INCDIR += $(MCUSW_INSTALL_PATH)/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/$(SOC)/$(CORE)/include
+  endif
 else
 ifeq ($(BUILD_VARIANT), LinkTime)
   INCDIR += $(MCUSW_INSTALL_PATH)/mcal_drv/mcal/examples_config/Eth_Demo_Lcfg/output/generated/soc/$(SOC)/$(CORE)/include
diff --git a/mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/CddIpc_Demo_Cfg/output/generated/soc/j721e/mcu2_1/include/Cdd_IpcCfg.h b/mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/CddIpc_Demo_Cfg/output/generated/soc/j721e/mcu1_0/include/Cdd_IpcCfg.h
similarity index 100%
rename from mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/CddIpc_Demo_Cfg/output/generated/soc/j721e/mcu2_1/include/Cdd_IpcCfg.h
rename to mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/CddIpc_Demo_Cfg/output/generated/soc/j721e/mcu1_0/include/Cdd_IpcCfg.h
diff --git a/mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/CddIpc_Demo_Cfg/output/generated/soc/j721e/mcu2_1/src/Cdd_IpcCfg.c b/mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/CddIpc_Demo_Cfg/output/generated/soc/j721e/mcu1_0/src/Cdd_IpcCfg.c
similarity index 99%
rename from mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/CddIpc_Demo_Cfg/output/generated/soc/j721e/mcu2_1/src/Cdd_IpcCfg.c
rename to mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/CddIpc_Demo_Cfg/output/generated/soc/j721e/mcu1_0/src/Cdd_IpcCfg.c
index 43358bf1..dad4e33e 100755
--- a/mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/CddIpc_Demo_Cfg/output/generated/soc/j721e/mcu2_1/src/Cdd_IpcCfg.c
+++ b/mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/CddIpc_Demo_Cfg/output/generated/soc/j721e/mcu1_0/src/Cdd_IpcCfg.c
@@ -261,7 +261,7 @@ CDD_IPC_CONFIG_DATA_SECTION CONST(Cdd_IpcConfigType, CDD_IPC_CONFIG_DATA)
 {
     .coreIds =
     {
-        .ownProcID = CDD_IPC_CORE_MCU2_1,
+        .ownProcID = CDD_IPC_CORE_MCU1_0,
         /**< Defines processor ID on which MCAL/AUTOSAR is being hosted */
         .numProcs = 1,
         /**< Number of processor which with IPC is desired */
diff --git a/mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/EthVirtmacApp.c b/mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/EthVirtmacApp.c
index a1be0700..f077b34e 100755
--- a/mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/EthVirtmacApp.c
+++ b/mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/EthVirtmacApp.c
@@ -91,9 +91,11 @@
 #include <EthUtils.h>
 
 #include <ti/csl/arch/csl_arch.h>
+#include <ti/csl/cslr.h>
 #include <ti/csl/soc.h>
 #include <ti/csl/hw_types.h>
 #include <ti/osal/osal.h>
+#include <ti/osal/TaskP.h>
 #include <ti/osal/SemaphoreP.h>
 #include <ti/osal/TimerP.h>
 
@@ -109,6 +111,11 @@
 #include "IntRtr_Cfg.h"
 #endif
 
+#if (defined (BUILD_MCU1_0) && (defined (SOC_J721E) || defined (SOC_J7200) || defined (SOC_J784S4)))
+#include <ti/drv/sciclient/sciserver_tirtos.h>
+#include <ti/drv/sciclient/examples/common/sciclient_appCommon.h>
+#endif
+
 /* ========================================================================== */
 /*                           Macros & Typedefs                                */
 /* ========================================================================== */
@@ -173,6 +180,18 @@
 #define ETH_TX_IRQ_PACING_HW_TIMER_IRQ_NUM              (INTRTR_CFG_MAIN_DOMAIN_TIMER_4_OUT_INT_NO + INTRTR_CFG_START_LEVEL_INT_NUMBER) /* GP timer 3 */
 #endif
 
+/* Test application stack size */
+#define APP_TASK_STACK                  (32U * 1024U)
+/**< Stack required for the stack */
+#define VIRTETH_PROFILE_DEMO_TASK_NAME  ("VirEth PROFILE")
+/**< Task names */
+#define VIRTETH_TASK_PRIORITY           (3)
+/**< Task Priority Levels */
+
+#if (defined (BUILD_MCU1_0))
+#define freertos
+#endif
+
 /* ========================================================================== */
 /*                         Structures and Enums                               */
 /* ========================================================================== */
@@ -629,6 +648,14 @@ void EthVirtmacApp_freeEthResources(void);
 static void EthVirtmacApp_addVlanId(uint32 vlanId);
 static void EthVirtmacApp_delVlanId(uint32 vlanId);
 
+/**
+ * \brief Setup SciServer
+ *
+ * \return PASS or FAIL of SciServer setup
+ */
+sint32 SetupSciServer(void);
+static uint8_t Sciserver_TaskStack[APP_TASK_STACK] __attribute__((aligned(32)));
+static uint8_t VirtEthApp_TaskStack[APP_TASK_STACK] __attribute__((aligned(32)));
 
 static inline void EthVirtmacAppUtils_assertLocal(boolean condition,
                                             const char *str,
@@ -713,7 +740,11 @@ static uint8 gCntrlBuf[RPMSG_DATA_SIZE] __attribute__ ((section("ipc_data_buffer
 
 static uint8 g_vringMemBuf[IPC_VRING_MEM_SIZE] __attribute__ ((section(".bss:ipc_vring_mem"), aligned(8192)));
 
+#if (defined (BUILD_MCU1_0))
+static uint32 selfProcId = IPC_MCU1_0;
+#else
 static uint32 selfProcId = IPC_MCU2_1;
+#endif
 static uint32 gRemoteProc[] =
 {
     IPC_MPU1_0,
@@ -804,11 +835,28 @@ static const uint16 ipc_map_dst_id[] =
 #endif
 };
 
+#if (defined (BUILD_MCU1_0))
+const Ipc_ResourceTable ti_ipc_remoteproc_ResourceTable __attribute__ ((section (".resource_table"), aligned (4096))) = 
+{
+    {
+        1U,                   /* we're the first version that implements this */
+        2U,         /* number of entries in the table */
+        {
+            0U, 
+            0U,                /* reserved, must be zero */
+        }
+    },
+};
+#endif
+
 /* ========================================================================== */
 /*                          Function Definitions                              */
 /* ========================================================================== */
-
+#if defined (freertos)
+int VirtEthmain(void)
+#else
 int main(void)
+#endif
 {
     uint32 i;
     boolean status;
@@ -932,6 +980,90 @@ int main(void)
     return 0;
 }
 
+#if defined (freertos)
+static void Taskfnx(void* a0, void* a1)
+{
+     /* Initialize SCI Client Server */
+    SetupSciServer();
+}
+
+static void mainTask(void* a0, void* a1)
+{
+    Std_ReturnType retVal;
+
+    retVal = VirtEthmain();
+
+    if (E_OK == retVal)
+    {
+        EthVirtmac_printf("Eth VirtApp task Completed\n");
+    }
+    else
+    {
+        EthVirtmac_printf("Eth VirtApp task Failed\n");
+    }
+}
+
+int main(void)
+{
+    sint32 ret = CSL_PASS;
+    char *version_str = NULL;
+    char *rmpmhal_version_str = NULL;
+
+    TaskP_Handle VirtEthTask;
+    TaskP_Params VirtEthTaskParams;
+
+    TaskP_Handle SciserverTask;
+    TaskP_Params SciserverTaskParams;
+
+    /* Relocate FreeRTOS Reset Vectors from BTCM*/
+    void _freertosresetvectors (void);  
+    memcpy((void *)0x0, (void *)_freertosresetvectors, 0x40);
+
+    OS_init();
+
+    /* Initialize the task params */
+	TaskP_Params_init(&SciserverTaskParams);
+	SciserverTaskParams.priority       = 6;
+	SciserverTaskParams.stack          = Sciserver_TaskStack;
+	SciserverTaskParams.stacksize      = sizeof (Sciserver_TaskStack);
+
+	SciserverTask = TaskP_create(&Taskfnx, &SciserverTaskParams);
+
+    if (NULL == SciserverTask)
+    {
+        OS_stop();
+        return(0);
+    }
+
+	/* Initialize the task params */
+	TaskP_Params_init(&VirtEthTaskParams);
+    //VirtEthTaskParams.instance->name = VIRTETH_PROFILE_DEMO_TASK_NAME;
+	VirtEthTaskParams.priority       = VIRTETH_TASK_PRIORITY;
+	VirtEthTaskParams.stack          = VirtEthApp_TaskStack;
+	VirtEthTaskParams.stacksize      = sizeof (VirtEthApp_TaskStack);
+
+	VirtEthTask = TaskP_create(&mainTask, &VirtEthTaskParams);
+
+    if (NULL == VirtEthTask)
+    {
+        OS_stop();
+        return(0);
+    }
+
+    version_str = Sciserver_getVersionStr();
+    rmpmhal_version_str = Sciserver_getRmPmHalVersionStr();
+
+    EthVirtmac_printf("Sciserver Testapp Built On: %s %s\n", __DATE__, __TIME__);
+    EthVirtmac_printf("Sciserver Version: %s\n", version_str);
+    EthVirtmac_printf("RM_PM_HAL Version: %s\n", rmpmhal_version_str);
+
+    OS_start();    /* does not return */
+
+    return(0);
+    
+}
+#endif
+
 static void EthVirtmacApp_delay(uint32 msecs)
 {
     TickType count = 1000000U * msecs;
@@ -3095,6 +3227,51 @@ void Cdd_IpcNewCtrlMessageNotify(uint32 remoteProcId)
 
 }
 
+#if defined (freertos)
+sint32 SetupSciServer(void)
+{
+	sint32 ret = CSL_PASS;
+    Sciserver_TirtosCfgPrms_t appPrms;
+    Sciclient_ConfigPrms_t clientPrms;
+
+    appPrms.taskPriority[SCISERVER_TASK_USER_LO] = 4;
+    appPrms.taskPriority[SCISERVER_TASK_USER_HI] = 5;
+
+    /* Sciclient needs to be initialized before Sciserver. Sciserver depends on
+     * Sciclient API to execute message forwarding */
+    ret = Sciclient_configPrmsInit(&clientPrms);
+
+	if (ret == CSL_PASS)
+    {
+        ret = Sciclient_boardCfgParseHeader(
+            (uint8_t *) SCISERVER_COMMON_X509_HEADER_ADDR,
+            &clientPrms.inPmPrms, &clientPrms.inRmPrms);
+    }
+
+    if (ret == CSL_PASS)
+    {
+        ret = Sciclient_init(&clientPrms);
+    }
+
+    if (ret == CSL_PASS)
+    {
+        ret = Sciserver_tirtosInit(&appPrms);
+    }
+
+    if (ret == CSL_PASS)
+    {
+        EthVirtmac_printf("Starting Sciserver..... PASSED\n");
+    }
+    else
+    {
+        EthVirtmac_printf("Starting Sciserver..... FAILED\n");
+    }
+
+	return ret;
+}
+#endif
+
+
 #if 0
 /**< Sections defined in linker command file for ADC module */
 extern uint32 __linker_cdd_ipc_text_start, __linker_cdd_ipc_text_end,
diff --git a/mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/build/j721e/mcu1_0/linker_r5_freertos.lds b/mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/build/j721e/mcu1_0/linker_r5_freertos.lds
new file mode 100755
index 00000000..d84cf60f
--- /dev/null
+++ b/mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/build/j721e/mcu1_0/linker_r5_freertos.lds
@@ -0,0 +1,617 @@
+/*----------------------------------------------------------------------------*/
+/* File: k3m4_r5f_linker.cmd                                                  */
+/* Description:																  */
+/*    Link command file for j721e M4 MCU 0 view							  */
+/*	  TI ARM Compiler version 15.12.3 LTS or later							  */
+/*                                                                            */
+/*    Platform: QT                                                            */
+/* (c) Texas Instruments 2017, All rights reserved.                           */
+/*----------------------------------------------------------------------------*/
+/*  History:								      */
+/*    Aug 26th, 2016 Original version .......................... Loc Truong   */
+/*    Aug 01th, 2017 new TCM mem map  .......................... Loc Truong   */
+/*    Nov 07th, 2017 Changes for R5F Init Code.................. Vivek Dhande */
+/*----------------------------------------------------------------------------*/
+/* Linker Settings                                                            */
+/* Standard linker options													  */
+--retain="*(.bootCode)"
+--retain="*(.startupCode)"
+--retain="*(.startupData)"
+--retain="*(.irqStack)"
+--retain="*(.fiqStack)"
+--retain="*(.abortStack)"
+--retain="*(.undStack)"
+--retain="*(.svcStack)"
+--retain="*(.resource_table)"
+
+--fill_value=0
+--stack_size=0x4000
+--heap_size=0x8000
+--entry_point=_freertosresetvectors
+
+-stack  0x4000  /* SOFTWARE STACK SIZE */
+-heap   0x8000  /* HEAP AREA SIZE      */
+
+/*-------------------------------------------*/
+/*       Stack Sizes for various modes       */
+/*-------------------------------------------*/
+__IRQ_STACK_SIZE   = 0x1000;
+__FIQ_STACK_SIZE   = 0x0100;
+__ABORT_STACK_SIZE = 0x0100;
+__UND_STACK_SIZE   = 0x0100;
+__SVC_STACK_SIZE   = 0x0100;
+
+--define FILL_PATTERN=0xFEAA55EF
+--define FILL_LENGTH=0x100
+
+/*--------------------------------------------------------------------------*/
+/*                               Memory Map                                 */
+/*--------------------------------------------------------------------------*/
+MEMORY
+{
+    VECTORS (X)                 : origin = 0x00000000   length = 0x00000040
+
+    /* MCU0_R5F_0 local view */
+    MCU0_R5F_TCMA (X)           : origin=0x00000040     length=0x00007FC0
+    MCU0_R5F_TCMB0_VECS (RWIX)	: origin=0x41010000		length=0x100
+    MCU0_R5F_TCMB0(RWIX)        : origin=0x41010100     length=0x00008000-0x100
+
+    /* Refer the user guide for details on persistence of these sections */
+    OCMC_RAM_BOARD_CFG (RWIX)   : origin=0x41C80000 length=0x2000
+    RESET_VECTORS (X)           : origin=0x41C82000 length=0x100
+    OCMC_RAM (RWIX)             : origin=0x41C82100 length=0x7DA00
+    OCMC_RAM_X509_HEADER (RWIX) : origin=0x41CFFB00 length=0x500
+
+    OCMC_RAM_SBL_RUNTIME (RWIX) : origin=0x41C00000 length=0x80000
+
+    /* j721e MCMS3 locations */
+    /* j721e Reserved Memory for ARM Trusted Firmware */
+    MSMC3_ARM_FW   (RWIX)   : origin=0x70000000 length=0x40000         /* 256KB */
+    MSMC3   (RWIX)          : origin=0x70040000 length=0x7B0000        /* 8MB - 320KB */
+    /* j721e Reserved Memory for DMSC Firmware */
+    MSMC3_DMSC_FW  (RWIX)   : origin=0x707F0000 length=0x10000         /* 64KB */
+
+
+    /* DDR for MCU1_0 for Linux IPC [ size 1024.00 KB ] */
+    DDR_MCU1_0_IPC           ( RWIX ) : ORIGIN = 0xA0000000 , LENGTH = 0x00100000
+    /* DDR for MCU1_0 for Linux resource table [ size 1024 B ] */
+    DDR_MCU1_0_RESOURCE_TABLE ( RWIX ) : ORIGIN = 0xA0100000 , LENGTH = 0x00000400
+    /* DDR for MCU1_0 for code/data [ size 63.00 MB ] */
+    DDR_MCU1_0               ( RWIX ) : ORIGIN = 0xA0100400 , LENGTH = 0x00EFFC00
+
+    /* Memory for remote core logging [ size 256.00 KB ] */
+    APP_LOG_MEM                       : ORIGIN = 0xB8000000 , LENGTH = 0x00040000
+    /* Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent [ size 31.75 MB ] */
+    TIOVX_OBJ_DESC_MEM                : ORIGIN = 0xB8040000 , LENGTH = 0x01FC0000
+    /* Memory for IPC Vring's. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
+    IPC_VRING_MEM                     : ORIGIN = 0xAA000000 , LENGTH = 0x02000000
+    /* Memory for shared memory buffers in DDR [ size 576.00 MB ] */
+    DDR_SHARED_MEM                    : ORIGIN = 0xBC000000 , LENGTH = 0x24000000
+
+}  /* end of MEMORY */
+
+/*----------------------------------------------------------------------------*/
+/* Section Configuration                                                      */
+
+SECTIONS
+{
+    .freertosrstvectors      : {} palign(8)      > MCU0_R5F_TCMB0_VECS
+    .bootCode        : {} palign(8)      > MCU0_R5F_TCMB0
+    .startupCode     : {} palign(8)      > MCU0_R5F_TCMB0
+    .startupData     : {} palign(8)      > MCU0_R5F_TCMB0, type = NOINIT
+
+    .stack  	: {} align(4)		> DDR_MCU1_0 (HIGH)  fill=FILL_PATTERN
+
+    .irqStack   : {. = . + __IRQ_STACK_SIZE;} align(4)      > DDR_MCU1_0  (HIGH)
+    RUN_START(__IRQ_STACK_START)
+    RUN_END(__IRQ_STACK_END)
+
+    .fiqStack   : {. = . + __FIQ_STACK_SIZE;} align(4)      > DDR_MCU1_0  (HIGH)
+    RUN_START(__FIQ_STACK_START)
+    RUN_END(__FIQ_STACK_END)
+
+    .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)    > DDR_MCU1_0  (HIGH)
+    RUN_START(__ABORT_STACK_START)
+    RUN_END(__ABORT_STACK_END)
+
+    .undStack   : {. = . + __UND_STACK_SIZE;} align(4)      > DDR_MCU1_0  (HIGH)
+    RUN_START(__UND_STACK_START)
+    RUN_END(__UND_STACK_END)
+
+    .svcStack   : {. = . + __SVC_STACK_SIZE;} align(4)      > DDR_MCU1_0  (HIGH)
+    RUN_START(__SVC_STACK_START)
+    RUN_END(__SVC_STACK_END)
+
+    .text    	     : {} palign(8) > DDR_MCU1_0
+    GROUP {
+        .text.hwi    : palign(8)
+        .text.cache  : palign(8)
+        .text.mpu    : palign(8)
+        .text.boot   : palign(8)
+    }                             > DDR_MCU1_0
+    .const   	: {} palign(8)    > DDR_MCU1_0
+    .rodata     : {} palign(8)    > DDR_MCU1_0
+    .cinit   	: {} palign(8)	  > DDR_MCU1_0
+    .pinit   	: {} palign(8) 	  > DDR_MCU1_0
+
+    /* For NDK packet memory, we need to map this sections before .bss*/
+    //.bss:NDK_MMBUFFER  (NOLOAD) {} ALIGN (128) > MCU0_DDR_SPACE
+    //.bss:NDK_PACKETMEM (NOLOAD) {} ALIGN (128) > MCU0_DDR_SPACE
+
+    .bss:app_log_mem        (NOLOAD) : {} > APP_LOG_MEM
+    .bss:ipc_vring_mem      (NOLOAD) : {} > IPC_VRING_MEM
+    .bss:ddr_shared_mem     (NOLOAD) : {} > DDR_SHARED_MEM
+
+    /* For bss we are using the OCMC_RAM_SBL_RUNTIME since by the time SBL loads
+     BootApp there is no need of SBL so we can overwrite SBL. */
+    .bss     	    : {} align(4)  	> DDR_MCU1_0
+    .far     	    : {} align(4)  	> DDR_MCU1_0
+    .data    	    : {} palign(128) 	> DDR_MCU1_0
+    .data_buffer    : {} palign(128) 	> DDR_MCU1_0
+    .sysmem  	    : {}                > DDR_MCU1_0
+    .bss.devgroup*  : {} align(4)       > DDR_MCU1_0
+    .const.devgroup*: {} align(4)       > DDR_MCU1_0
+    .data_user      : {} align(4)       > DDR_MCU1_0
+    .boardcfg_data  : {} align(4)       > DDR_MCU1_0
+
+    .resource_table          :
+    {
+        __RESOURCE_TABLE = .;
+    }                                   > DDR_MCU1_0_RESOURCE_TABLE
+
+
+    .CDD_IPC_MPU_CFG : {} palign(8)      > DDR_MCU1_0
+
+    /* Additional sections settings 	*/
+    .sysfw_data_cfg_board      : {} palign(128) > DDR_MCU1_0
+    .sysfw_data_cfg_board_rm   : {} palign(128) > DDR_MCU1_0
+    .sysfw_data_cfg_board_sec  : {} palign(128) > DDR_MCU1_0
+
+    .tracebuf   : {} > DDR_MCU1_0
+
+    .benchmark_buffer : {} > DDR_MCU1_0
+
+    /* Additional sections settings     */
+    McalTextSection : fill=FILL_PATTERN, align=4, load > DDR_MCU1_0
+    {
+        .=align(4);
+        __linker_spi_text_start = .;
+        . += FILL_LENGTH;
+        *(SPI_TEXT_SECTION)
+        *(SPI_ISR_TEXT_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_spi_text_end = .;
+
+        .=align(4);
+        __linker_gpt_text_start = .;
+        . += FILL_LENGTH;
+        *(GPT_TEXT_SECTION)
+        *(GPT_ISR_TEXT_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_gpt_text_end = .;
+
+        .=align(4);
+        __linker_dio_text_start = .;
+        . += FILL_LENGTH;
+        *(DIO_TEXT_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_dio_text_end = .;
+
+        .=align(4);
+        __linker_eth_text_start = .;
+        . += FILL_LENGTH;
+        *(ETH_TEXT_SECTION)
+        *(ETH_ISR_TEXT_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_eth_text_end = .;
+
+        .=align(4);
+        __linker_ethtrcv_text_start = .;
+        . += FILL_LENGTH;
+        *(ETHTRCV_TEXT_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_ethtrcv_text_end = .;
+
+        .=align(4);
+        __linker_can_text_start = .;
+        . += FILL_LENGTH;
+        *(CAN_TEXT_SECTION)
+        *(CAN_ISR_TEXT_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_can_text_end = .;
+
+        .=align(4);
+        __linker_wdg_text_start = .;
+        . += FILL_LENGTH;
+        *(WDG_TEXT_SECTION)
+        *(WDG_ISR_TEXT_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_wdg_text_end = .;
+
+        .=align(4);
+        __linker_pwm_text_start = .;
+        . += FILL_LENGTH;
+        *(PWM_TEXT_SECTION)
+        *(PWM_ISR_TEXT_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_pwm_text_end = .;
+
+        __linker_adc_text_start = .;
+        . += FILL_LENGTH;
+        *(ADC_TEXT_SECTION)
+        *(ADC_ISR_TEXT_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_adc_text_end = .;
+
+        .=align(4);
+        __linker_cdd_ipc_text_start = .;
+        . += FILL_LENGTH;
+        *(CDD_IPC_TEXT_SECTION)
+        *(CDD_IPC_ISR_TEXT_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_cdd_ipc_text_end = .;
+
+    }
+    McalConstSection : fill=FILL_PATTERN, align=4, load > DDR_MCU1_0
+    {
+        .=align(4);
+        __linker_spi_const_start = .;
+        . += FILL_LENGTH;
+        *(SPI_CONST_32_SECTION)
+        *(SPI_CONFIG_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_spi_const_end = .;
+
+        .=align(4);
+        __linker_gpt_const_start = .;
+        . += FILL_LENGTH;
+        *(GPT_CONST_32_SECTION)
+        *(GPT_CONFIG_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_gpt_const_end = .;
+
+        .=align(4);
+        __linker_dio_const_start = .;
+        . += FILL_LENGTH;
+        *(DIO_CONST_32_SECTION)
+        *(DIO_CONST_UNSPECIFIED_SECTION)
+        *(DIO_CONFIG_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_dio_const_end = .;
+
+        .=align(4);
+        __linker_can_const_start = .;
+        . += FILL_LENGTH;
+        *(CAN_CONST_8_SECTION)
+        *(CAN_CONST_32_SECTION)
+        *(CAN_CONFIG_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_can_const_end = .;
+
+        .=align(4);
+        __linker_eth_const_start = .;
+        . += FILL_LENGTH;
+        *(ETH_CONST_32_SECTION)
+        *(ETH_CONFIG_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_eth_const_end = .;
+
+        .=align(4);
+        __linker_ethtrcv_const_start = .;
+        . += FILL_LENGTH;
+        *(ETHTRCV_CONST_32_SECTION)
+        *(ETHTRCV_CONFIG_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_ethtrcv_const_end = .;
+
+        .=align(4);
+        __linker_wdg_const_start = .;
+        . += FILL_LENGTH;
+        *(WDG_CONST_32_SECTION)
+        *(WDG_CONFIG_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_wdg_const_end = .;
+
+        .=align(4);
+        __linker_pwm_const_start = .;
+        . += FILL_LENGTH;
+        *(PWM_CONST_32_SECTION)
+        *(PWM_CONFIG_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_pwm_const_end = .;
+
+        .=align(4);
+        __linker_adc_const_start = .;
+        . += FILL_LENGTH;
+        *(ADC_CONST_32_SECTION)
+        *(ADC_CONFIG_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_adc_const_end = .;
+
+        .=align(4);
+        __linker_cdd_ipc_const_start = .;
+        . += FILL_LENGTH;
+        *(CDD_IPC_CONST_32_SECTION)
+        *(CDD_IPC_CONFIG_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_cdd_ipc_const_end = .;
+    }
+
+    McalInitSection : fill=FILL_PATTERN, align=4, load > DDR_MCU1_0
+    {
+        .=align(4);
+        __linker_spi_init_start = .;
+        . += FILL_LENGTH;
+        *(SPI_DATA_INIT_UNSPECIFIED_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_spi_init_end = .;
+
+        .=align(4);
+        __linker_gpt_init_start = .;
+        . += FILL_LENGTH;
+        *(GPT_DATA_INIT_32_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_gpt_init_end = .;
+
+        .=align(4);
+        __linker_pwm_init_start = .;
+        . += FILL_LENGTH;
+        *(PWM_DATA_INIT_32_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_pwm_init_end = .;
+
+        .=align(4);
+        __linker_dio_init_start = .;
+        . += FILL_LENGTH;
+        *(DIO_DATA_INIT_32_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_dio_init_end = .;
+
+        .=align(4);
+        __linker_eth_init_start = .;
+        . += FILL_LENGTH;
+        *(ETH_DATA_INIT_UNSPECIFIED_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_eth_init_end = .;
+
+        .=align(4);
+        __linker_ethtrcv_init_start = .;
+        . += FILL_LENGTH;
+        *(ETHTRCV_DATA_INIT_UNSPECIFIED_SECTION)
+        *(ETHTRCV_DATA_INIT_32_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_ethtrcv_init_end = .;
+
+        .=align(4);
+        __linker_can_init_start = .;
+        . += FILL_LENGTH;
+        *(CAN_DATA_INIT_8_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_can_init_end = .;
+
+        .=align(4);
+        __linker_wdg_init_start = .;
+        . += FILL_LENGTH;
+        *(WDG_DATA_INIT_UNSPECIFIED_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_wdg_init_end = .;
+
+        .=align(4);
+        __linker_adc_init_start = .;
+        . += FILL_LENGTH;
+        *(ADC_DATA_INIT_UNSPECIFIED_SECTION)
+        *(ADC_DATA_INIT_32_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_adc_init_end = .;
+
+        .=align(4);
+        __linker_cdd_ipc_init_start = .;
+        . += FILL_LENGTH;
+        *(CDD_IPC_DATA_INIT_UNSPECIFIED_SECTION)
+        *(CDD_IPC_DATA_INIT_32_SECTION)
+        *(CDD_IPC_DATA_INIT_8_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_cdd_ipc_init_end = .;
+    }
+    McalNoInitSection : fill=FILL_PATTERN, align=4, load > DDR_MCU1_0, type = NOINIT
+    {
+        .=align(4);
+        __linker_spi_no_init_start = .;
+        . += FILL_LENGTH;
+        *(SPI_DATA_NO_INIT_UNSPECIFIED_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_spi_no_init_end = .;
+
+        .=align(4);
+        __linker_gpt_no_init_start = .;
+        . += FILL_LENGTH;
+        *(GPT_DATA_NO_INIT_UNSPECIFIED_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_gpt_no_init_end = .;
+
+        .=align(4);
+        __linker_dio_no_init_start = .;
+        . += FILL_LENGTH;
+        *(DIO_DATA_NO_INIT_UNSPECIFIED_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_dio_no_init_end = .;
+
+        .=align(4);
+        __linker_eth_no_init_start = .;
+        . += FILL_LENGTH;
+        *(ETH_DATA_NO_INIT_UNSPECIFIED_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_eth_no_init_end = .;
+
+        .=align(128);
+        __linker_eth_no_init_128_start = .;
+        . += FILL_LENGTH;
+        *(ETH_DATA_NO_INIT_UNSPECIFIED_SECTION_128)
+        .=align(128);
+        . += FILL_LENGTH;
+        __linker_eth_no_init_128_end = .;
+
+
+        .=align(4);
+        __linker_ethtrcv_no_init_start = .;
+        . += FILL_LENGTH;
+        *(ETHTRCV_DATA_NO_INIT_UNSPECIFIED_SECTION)
+        *(ETHTRCV_DATA_NO_INIT_16_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_ethtrcv_no_init_end = .;
+
+        .=align(4);
+        __linker_can_no_init_start = .;
+        . += FILL_LENGTH;
+        *(CAN_DATA_NO_INIT_UNSPECIFIED_SECTION)
+        *(CAN_DATA_NO_INIT_32_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_can_no_init_end = .;
+
+        .=align(4);
+        __linker_wdg_no_init_start = .;
+        . += FILL_LENGTH;
+        *(WDG_DATA_NO_INIT_UNSPECIFIED_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_wdg_no_init_end = .;
+
+        .=align(4);
+        __linker_pwm_no_init_start = .;
+        . += FILL_LENGTH;
+        *(PWM_DATA_NO_INIT_UNSPECIFIED_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_pwm_no_init_end = .;
+
+        __linker_adc_no_init_start = .;
+        . += FILL_LENGTH;
+        *(ADC_DATA_NO_INIT_UNSPECIFIED_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_adc_no_init_end = .;
+
+        __linker_cdd_ipc_no_init_start = .;
+        . += FILL_LENGTH;
+        *(CDD_IPC_DATA_NO_INIT_UNSPECIFIED_SECTION)
+        *(CDD_IPC_DATA_NO_INIT_8_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_cdd_ipc_no_init_end = .;
+
+    }
+    /* Example Utility specifics */
+    VariablesAlignedNoInitSection : align=8, load > DDR_MCU1_0, type = NOINIT
+    {
+        .=align(8);
+        __linker_cdd_ipc_no_init_align_8b_start = .;
+        . += FILL_LENGTH;
+        *(CDD_IPC_DATA_NO_INIT_8_ALIGN_8B_SECTION)
+        .=align(8);
+        . += FILL_LENGTH;
+        __linker_cdd_ipc_no_init_align_8b_end = .;
+    }
+    /* Example Utility specifics */
+    UtilityNoInitSection : align=4, load > DDR_MCU1_0, type = NOINIT
+    {
+        .=align(4);
+        __linker_utility_no_init_start = .;
+        . += FILL_LENGTH;
+        *(EG_TEST_RESULT_32_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_utility_no_init_end = .;
+    }
+    SciClientBoardCfgSection : align=128, load > DDR_MCU1_0, type = NOINIT
+    {
+        .=align(128);
+        __linker_boardcfg_data_start = .;
+        . += FILL_LENGTH;
+        *(.boardcfg_data)
+        .=align(128);
+        . += FILL_LENGTH;
+        __linker_boardcfg_data_end = .;
+    }
+    /* This section is used for descs and ring mems. It's best to have
+     * it in OCMRAM or MSMC3 */
+    McalUdmaSection : fill=FILL_PATTERN, align=128, load > DDR_MCU1_0
+    {
+        .=align(128);
+        __linker_eth_udma_desc_start = .;
+        . += FILL_LENGTH;
+        *(ETH_UDMA_DESC_SECTION)
+        .=align(128);
+        . += FILL_LENGTH;
+        __linker_eth_udma_desc_end = .;
+
+        .=align(128);
+        __linker_eth_udma_ring_start = .;
+        . += FILL_LENGTH;
+        *(ETH_UDMA_RING_SECTION)
+        .=align(128);
+        . += FILL_LENGTH;
+        __linker_eth_udma_ring_end = .;
+    }
+    McalTxDataSection : fill=FILL_PATTERN, align=128, load > DDR_MCU1_0, type = NOINIT
+    {
+        .=align(128);
+        __linker_eth_tx_data_start = .;
+        . += FILL_LENGTH;
+        *(ETH_TX_DATA_SECTION)
+        .=align(128);
+        . += FILL_LENGTH;
+        __linker_eth_tx_data_end = .;
+    }
+    McalRxDataSection : fill=FILL_PATTERN, align=128, load > DDR_MCU1_0, type = NOINIT
+    {
+        .=align(128);
+        __linker_eth_rx_data_start = .;
+        . += FILL_LENGTH;
+        *(ETH_RX_DATA_SECTION)
+        .=align(128);
+        . += FILL_LENGTH;
+        __linker_eth_rx_data_end = .;
+    }
+}  /* end of SECTIONS */
+
+/*----------------------------------------------------------------------------*/
+/* Misc linker settings                                                       */
+
+
+/*-------------------------------- END ---------------------------------------*/
diff --git a/mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/makeethvirtmac b/mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/makeethvirtmac
index 96ca5d2d..153f59fc 100644
--- a/mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/makeethvirtmac
+++ b/mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/makeethvirtmac
@@ -1,7 +1,13 @@
 include $(MCUSW_INSTALL_PATH)/build/Rules.make
 
+ifeq ($(CORE), mcu1_0)
+BUILD_OS_TYPE = freertos
+endif
+
 APP_NAME = eth_virtmac_app
 
+export BUILD_APP = eth_virtmac_app
+
 SRCDIR = . ../utils
 #SRCDIR += $(eth_virtmac_app_PATH)/Eth_Demo_Cfg/output/generated/soc/$(SOC)/$(CORE)/src
 SRCDIR += $(eth_virtmac_app_PATH)/CddIpc_Demo_Cfg/output/generated/soc/$(SOC)/$(CORE)/src
@@ -22,8 +28,8 @@ INCDIR += $(MCUSW_INSTALL_PATH)/mcal_drv/mcal/examples_config/IntRtr_Cfg/soc/$(S
 
 BUILD_VARIANT ?= PreCompile
 ifeq ($(BUILD_VARIANT), PreCompile)
-  INCDIR += $(MCUSW_INSTALL_PATH)/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/$(SOC)/$(CORE)/include
-  SRCDIR += $(MCUSW_INSTALL_PATH)/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/$(SOC)/$(CORE)/src
+  INCDIR += $(MCUSW_INSTALL_PATH)/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/$(SOC)/$(CORE)_cpswng/include
+  SRCDIR += $(MCUSW_INSTALL_PATH)/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/$(SOC)/$(CORE)_cpswng/src
 else
 ifeq ($(BUILD_VARIANT), LinkTime)
   INCDIR += $(MCUSW_INSTALL_PATH)/mcal_drv/mcal/examples_config/Eth_Demo_Lcfg/output/generated/soc/$(SOC)/$(CORE)/include
@@ -46,12 +52,21 @@ COMP_LIST_COMMON = eth bsw_stubs app_utils cdd_ipc
 EXT_LIB_LIST_COMMON = $(csl_LIBPATH)/$(SOC)/$(ISA_EXT)/$(BUILD_PROFILE_$(CORE))/$(csl_LIBNAME).$(LIBEXT)
 EXT_LIB_LIST_COMMON += $(csl_init_LIBPATH)/$(SOC)/$(ISA_EXT)/$(BUILD_PROFILE_$(CORE))/$(csl_init_LIBNAME).$(LIBEXT)
 EXT_LIB_LIST_COMMON += $(udma_LIBPATH)/$(SOC)/$(CORE)/$(BUILD_PROFILE_$(CORE))/$(udma_LIBNAME).$(LIBEXT)
+
+ifeq ($(BUILD_OS_TYPE), freertos)
+INCLUDE_EXTERNAL_INTERFACES += freertos
+EXT_LIB_LIST_COMMON += $(osal_freertos_LIBPATH)/$(SOC)/$(ISA_EXT)/$(BUILD_PROFILE_$(CORE))/$(osal_freertos_LIBNAME).$(LIBEXT)
+EXT_LIB_LIST_COMMON += $(freertos_LIBPATH)/$(SOC)/$(CORE)/$(BUILD_PROFILE_$(CORE))/$(freertos_LIBNAME).$(LIBEXT)
+else
 EXT_LIB_LIST_COMMON += $(osal_nonos_LIBPATH)/$(SOC)/$(ISA_EXT)/$(BUILD_PROFILE_$(CORE))/$(osal_nonos_LIBNAME).$(LIBEXT)
+endif
+
 ifeq ($(SOC),$(filter $(SOC), j721e j7200))
   ifeq ($(CORE),mcu1_0)
     EXT_LIB_LIST_COMMON += $(sciclient_direct_LIBPATH)/$(SOC)/$(CORE)/$(BUILD_PROFILE_$(CORE))/$(sciclient_direct_LIBNAME).$(LIBEXT)
     EXT_LIB_LIST_COMMON += $(sciserver_tirtos_LIBPATH)/$(SOC)/$(CORE)/$(BUILD_PROFILE_$(CORE))/$(sciserver_tirtos_LIBNAME).$(LIBEXT)
     EXT_LIB_LIST_COMMON += $(rm_pm_hal_LIBPATH)/$(SOC)/$(CORE)/$(BUILD_PROFILE_$(CORE))/$(rm_pm_hal_LIBNAME).$(LIBEXT)
+	EXT_LIB_LIST_COMMON += $(pm_lib_LIBPATH)/$(SOC)/$(ISA_EXT)/$(BUILD_PROFILE_$(CORE))/$(pm_lib_LIBNAME).$(LIBEXT)
   else
     EXT_LIB_LIST_COMMON += $(sciclient_LIBPATH)/$(SOC)/$(CORE)/$(BUILD_PROFILE_$(CORE))/$(sciclient_LIBNAME).$(LIBEXT)
   endif
@@ -79,6 +94,8 @@ SRCS_COMMON += app_utils_cdd_ipc.c
 
 ifeq ($(BUILD_OS_TYPE),tirtos)
 EXTERNAL_LNKCMD_FILE_LOCAL = $(eth_virtmac_app_PATH)/build/$(SOC)/$(CORE)/linker_r5_sysbios.lds
+else ifeq ($(BUILD_OS_TYPE),freertos)
+EXTERNAL_LNKCMD_FILE_LOCAL = $(eth_virtmac_app_PATH)/build/$(SOC)/$(CORE)/linker_r5_freertos.lds
 else
 EXTERNAL_LNKCMD_FILE_LOCAL = $(eth_virtmac_app_PATH)/build/$(SOC)/$(CORE)/linker_r5.lds
 endif
diff --git a/mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/soc/j721e/mcu2_1/CddIpcR5Mpu.c b/mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/soc/j721e/mcu1_0/CddIpcR5Mpu.c
similarity index 96%
rename from mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/soc/j721e/mcu2_1/CddIpcR5Mpu.c
rename to mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/soc/j721e/mcu1_0/CddIpcR5Mpu.c
index 7995135b..eeaba70e 100644
--- a/mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/soc/j721e/mcu2_1/CddIpcR5Mpu.c
+++ b/mcusw/mcal_drv/mcal/examples/Eth/eth_app/target/soc/j721e/mcu1_0/CddIpcR5Mpu.c
@@ -104,8 +104,8 @@ const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX]
         .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
         .shareable        = 0U,
         .cacheable        = (uint32_t)FALSE,
-        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
-        .memAttr          = CSL_ARM_R5_MEM_ATTR_STRONGLY_ORDERED,
+        .cachePolicy      = 0U,
+        .memAttr          = 0U,
     },
     {
         .regionId         = 1U,
@@ -117,8 +117,8 @@ const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX]
         .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
         .shareable        = 0U,
         .cacheable        = (uint32_t)TRUE,
-        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
-        .memAttr          = CSL_ARM_R5_MEM_ATTR_NON_SHAREABLE,
+        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,
+        .memAttr          = 0U,
     },
     {
         .regionId         = 2U,
@@ -150,7 +150,7 @@ const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX]
         .regionId         = 4U,
         .enable           = 1U,
         .baseAddr         = 0x41C00000,
-        .size             = CSL_ARM_R5_MPU_REGION_SIZE_512KB,
+        .size             = CSL_ARM_R5_MPU_REGION_SIZE_1MB,
         .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
         .exeNeverControl  = 0U,
         .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
@@ -240,7 +240,7 @@ const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX]
     {
         .regionId         = 11U,
         .enable           = 1U,
-        .baseAddr         = 0xA3000000,
+        .baseAddr         = 0xA0000000,
         .size             = CSL_ARM_R5_MPU_REGION_SIZE_1MB,
         .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
         .exeNeverControl  = 1U,
diff --git a/mcusw/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/j721e/mcu2_1/include/Eth_Cfg.h b/mcusw/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/j721e/mcu1_0_cpswng/include/Eth_Cfg.h
similarity index 97%
rename from mcusw/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/j721e/mcu2_1/include/Eth_Cfg.h
rename to mcusw/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/j721e/mcu1_0_cpswng/include/Eth_Cfg.h
index 8ab04c37..fcb6be66 100644
--- a/mcusw/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/j721e/mcu2_1/include/Eth_Cfg.h
+++ b/mcusw/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/j721e/mcu1_0_cpswng/include/Eth_Cfg.h
@@ -67,7 +67,7 @@
  *
  */
 /*******************************************************************************
-    Project         : J721E_mcu2_1
+    Project         : J721E_mcu1_0
     Date            : 2023-02-14 09:12:40
     SW Ver          : 2.1.0
     Module Rele Ver : AUTOSAR 4.3.1 0
@@ -236,7 +236,7 @@ extern "C" {
 #define UDMA_DEVICE_ID_PSIL                                                (199U)
 #define UDMA_DEVICE_ID_IA                                                  (209U)
 #define UDMA_DEVICE_ID_IR                                                  (213U)
-#define UDMA_DEVICE_ID_CORE                                                (246U)
+#define UDMA_DEVICE_ID_CORE                                                (250U)
 /* @} */
 
 /**
@@ -360,7 +360,7 @@ extern "C" {
 #define Eth_Cpsw_GetMdioOpMode(CtrlIndex)                                  ( ETH_MDIO_OPMODE_MANUAL )
 
 #define Eth_GetRxMtuLength(CtrlIndex)                                      ( 1522U )
-#define Eth_GetTxChanStartNum(CtrlIndex)                                   ( 133U )
+#define Eth_GetTxChanStartNum(CtrlIndex)                                   ( 24U )
 #define Eth_GetRxChanStartNum(CtrlIndex)                                   ( 0U )
 #define Eth_GetEgressFifoTotalNum(CtrlIndex)                               ( 1U )
 #define Eth_GetIngressFifoTotalNum(CtrlIndex)                              ( 1U )
@@ -396,7 +396,7 @@ extern "C" {
 #define Eth_GetIngressFifoCqIdx(CtrlIndex, FifoIdx)                        ( 1U )
 #define Eth_GetIngressFifoFqIdx(CtrlIndex, FifoIdx)                        ( 3U )
 
-#define Eth_GetTxChanId(CtrlIndex, ChIdx)                                  ( 133U )
+#define Eth_GetTxChanId(CtrlIndex, ChIdx)                                  ( 24U )
 #define Eth_GetTxChanTdCqRingIdx(CtrlIndex, ChIdx)                         ( 4U )
 #define Eth_GetTxChanDepth(CtrlIndex, ChIdx)                               ( 128U )
 
@@ -425,8 +425,8 @@ extern "C" {
 #define Eth_GetEventCoreIntrNum(CtrlIndex, EvtIdx)                         ( Eth_EventCfg_Ctrl_0[(EvtIdx)].coreIntrNum )
 #define Eth_GetEventVirtIntrNum(CtrlIndex, EvtIdx)                         ( Eth_EventCfg_Ctrl_0[(EvtIdx)].virtIntrNum )
 #define Eth_GetEventIrIntrNum(CtrlIndex, EvtIdx)                           ( Eth_EventCfg_Ctrl_0[(EvtIdx)].IrIntrNum )
-#define Eth_GetTxEventCoreIntrNum(CtrlIndex)                               ( 238U )
-#define Eth_GetRxEventCoreIntrNum(CtrlIndex)                               ( 239U )
+#define Eth_GetTxEventCoreIntrNum(CtrlIndex)                               ( 377U )
+#define Eth_GetRxEventCoreIntrNum(CtrlIndex)                               ( 378U )
 
 #define Eth_GetHwTimerTotalNum(CtrlIndex)                                  ( 0U )
 #define Eth_GetHwTimerId(CtrlIndex, Index)                                 ( 0xFFU )
diff --git a/mcusw/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/j721e/mcu2_1/src/Eth_Cfg.c b/mcusw/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/j721e/mcu1_0_cpswng/src/Eth_Cfg.c
similarity index 90%
rename from mcusw/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/j721e/mcu2_1/src/Eth_Cfg.c
rename to mcusw/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/j721e/mcu1_0_cpswng/src/Eth_Cfg.c
index e2662e06..e8f49dd6 100644
--- a/mcusw/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/j721e/mcu2_1/src/Eth_Cfg.c
+++ b/mcusw/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/j721e/mcu1_0_cpswng/src/Eth_Cfg.c
@@ -67,7 +67,7 @@
  *            for ETH MCAL driver
  */
 /*******************************************************************************
-    Project         : J721E_mcu2_1
+    Project         : J721E_mcu1_0
     Date            : 2023-02-14 09:12:40
     SW Ver          : 2.1.0
     Module Rele Ver : AUTOSAR 4.3.1 0
@@ -222,31 +222,31 @@ CONST(Eth_Udma_RingCfgType, ETH_VAR_NO_INIT) Eth_Udma_RingCfg_0[5U] =
 {
     {
         /* memPtr               */ Eth_RingMem_Ctrl_0_Cq_Egress_0,
-        /* hwId                 */ 926U,
+        /* hwId                 */ 630U,
         /* size                 */ 128U,
         /* priority             */ 0U
     },
     {
         /* memPtr               */ Eth_RingMem_Ctrl_0_Cq_Ingress_0,
-        /* hwId                 */ 927U,
+        /* hwId                 */ 631U,
         /* size                 */ 128U,
         /* priority             */ 0U
     },
     {
         /* memPtr               */ Eth_RingMem_Ctrl_0_Fq_Egress_0,
-        /* hwId                 */ 133U,
+        /* hwId                 */ 24U,
         /* size                 */ 128U,
         /* priority             */ 0U
     },
     {
         /* memPtr               */ Eth_RingMem_Ctrl_0_Fq_Ingress_0,
-        /* hwId                 */ 928U,
+        /* hwId                 */ 632U,
         /* size                 */ 128U,
         /* priority             */ 0U
     },
     {
         /* memPtr               */ Eth_RingMem_Ctrl_0_TdCq_Egress_Ch_0,
-        /* hwId                 */ 929U,
+        /* hwId                 */ 633U,
         /* size                 */ 1U,
         /* priority             */ 0U
     },
@@ -258,14 +258,14 @@ CONST(Eth_Udma_RingCfgType, ETH_VAR_NO_INIT) Eth_Udma_RingCfg_0[5U] =
 CONST(Eth_Udma_EventCfgType, ETH_VAR_NO_INIT) Eth_EventCfg_Ctrl_0[2U] =
 {
     {
-        /* coreIntrNum          */ 238U,
-        /* virtIntrNum          */ 244U,
-        /* IrIntrNum            */ 238U
+        /* coreIntrNum          */ 377U,
+        /* virtIntrNum          */ 252U,
+        /* IrIntrNum            */ 401U
     },
     {
-        /* coreIntrNum          */ 239U,
-        /* virtIntrNum          */ 245U,
-        /* IrIntrNum            */ 239U
+        /* coreIntrNum          */ 378U,
+        /* virtIntrNum          */ 253U,
+        /* IrIntrNum            */ 402U
     }
 };
 
@@ -278,14 +278,14 @@ CONST(Eth_Udma_RingEventCfgType, ETH_VAR_NO_INIT) Eth_RingEventCfg_Ctrl_0[2U] =
         /* ringIdx              */ 0U,
         /* eventIdx             */ 0U,
         /* virtBitNum           */ 0U,
-        /* globalEvent          */ 3430U,
+        /* globalEvent          */ 1574U,
         /* srcOffset            */ 0U
     },
     {
         /* ringIdx              */ 1U,
         /* eventIdx             */ 1U,
         /* virtBitNum           */ 0U,
-        /* globalEvent          */ 3431U,
+        /* globalEvent          */ 1575U,
         /* srcOffset            */ 0U
     },
 };
diff --git a/mcusw/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/j721e/mcu2_1/src/Eth_Lcfg.c b/mcusw/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/j721e/mcu1_0_cpswng/src/Eth_Lcfg.c
similarity index 100%
rename from mcusw/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/j721e/mcu2_1/src/Eth_Lcfg.c
rename to mcusw/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/j721e/mcu1_0_cpswng/src/Eth_Lcfg.c
diff --git a/mcusw/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/j721e/mcu2_1/src/Eth_PBcfg.c b/mcusw/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/j721e/mcu1_0_cpswng/src/Eth_PBcfg.c
similarity index 100%
rename from mcusw/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/j721e/mcu2_1/src/Eth_PBcfg.c
rename to mcusw/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/soc/j721e/mcu1_0_cpswng/src/Eth_PBcfg.c
diff --git a/mcusw/mcal_drv/mcal/mcusw_mcal_component.mk b/mcusw/mcal_drv/mcal/mcusw_mcal_component.mk
index 3bd0886b..8e45cb69 100755
--- a/mcusw/mcal_drv/mcal/mcusw_mcal_component.mk
+++ b/mcusw/mcal_drv/mcal/mcusw_mcal_component.mk
@@ -681,7 +681,7 @@ eth_virtmac_app_INCLUDE = $(eth_virtmac_app_PATH)
 eth_virtmac_app_BOARDLIST = j721e_sim j721e_evm j7200_evm j784s4_evm
 export eth_virtmac_app_BOARDLIST
 ifeq ($(BOARD),$(filter $(BOARD), j721e_evm j7200_evm j784s4_evm))
-eth_virtmac_app_$(SOC)_CORELIST = mcu2_1
+eth_virtmac_app_$(SOC)_CORELIST = mcu1_0 mcu2_1
 endif
 export eth_virtmac_app_$(SOC)_CORELIST
 eth_virtmac_app_SBL_APPIMAGEGEN = yes
-- 
2.17.1

