From d10f7d1930eaeb7e797804e7b1c01b9e32ac9568 Mon Sep 17 00:00:00 2001
From: Puranjay Mohan <p-mohan@ti.com>
Date: Thu, 26 May 2022 14:37:33 +0530
Subject: [tiL5.10-CON PATCH] arm64: dts: ti: k3-am65: Add support for MII

Change the pinctrl and phy-mode to support MII mode for the icssg.

Signed-off-by: Puranjay Mohan <p-mohan@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am654-idk.dts | 80 +++++++++++++++++++++++--
 1 file changed, 74 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am654-idk.dts b/arch/arm64/boot/dts/ti/k3-am654-idk.dts
index 6170d7ea0f0c..07209caf8bda 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-idk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-idk.dts
@@ -45,7 +45,7 @@
 			icssg0_eth: icssg0-eth {
 				compatible = "ti,am654-icssg-prueth";
 				pinctrl-names = "default";
-				pinctrl-0 = <&icssg0_rgmii_pins_default>;
+				pinctrl-0 = <&icssg0_mii_pins_default>;
 				sram = <&msmc_ram>;
 				ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
 				firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
@@ -90,7 +90,7 @@
 
 				icssg0_emac0: ethernet-mii0 {
 					phy-handle = <&icssg0_phy0>;
-					phy-mode = "rgmii-rxid";
+					phy-mode = "mii";
 					syscon-rgmii-delay = <&scm_conf 0x4100>;
 					/* Filled in by bootloader */
 					local-mac-address = [00 00 00 00 00 00];
@@ -98,7 +98,7 @@
 
 				icssg0_emac1: ethernet-mii1 {
 					phy-handle = <&icssg0_phy1>;
-					phy-mode = "rgmii-rxid";
+					phy-mode = "mii";
 					syscon-rgmii-delay = <&scm_conf 0x4104>;
 					/* Filled in by bootloader */
 					local-mac-address = [00 00 00 00 00 00];
@@ -109,7 +109,7 @@
 			icssg1_eth: icssg1-eth {
 				compatible = "ti,am654-icssg-prueth";
 				pinctrl-names = "default";
-				pinctrl-0 = <&icssg1_rgmii_pins_default>;
+				pinctrl-0 = <&icssg1_mii_pins_default>;
 				sram = <&msmc_ram>;
 				ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
 				firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
@@ -155,7 +155,7 @@
 
 				icssg1_emac0: ethernet-mii0 {
 					phy-handle = <&icssg1_phy0>;
-					phy-mode = "rgmii-rxid";
+					phy-mode = "mii";
 					syscon-rgmii-delay = <&scm_conf 0x4110>;
 					/* Filled in by bootloader */
 					local-mac-address = [00 00 00 00 00 00];
@@ -163,7 +163,7 @@
 
 				icssg1_emac1: ethernet-mii1 {
 					phy-handle = <&icssg1_phy1>;
-					phy-mode = "rgmii-rxid";
+					phy-mode = "mii";
 					syscon-rgmii-delay = <&scm_conf 0x4114>;
 					/* Filled in by bootloader */
 					local-mac-address = [00 00 00 00 00 00];
@@ -223,6 +223,40 @@
 		>;
 	};
 
+	icssg0_mii_pins_default: icssg0-mii-pins-default {
+		pinctrl-single,pins = <
+			AM65X_IOPAD(0x0284, PIN_INPUT, 1) /* (AC24) PRG0_PRU1_GPO16.pr0_mii_mt0_clk */
+			AM65X_IOPAD(0x0280, PIN_OUTPUT, 0) /* (AE27) PRG0_PRU1_GPO15.pr0_mii0_txen */
+			AM65X_IOPAD(0x027c, PIN_OUTPUT, 0) /* (AD24) PRG0_PRU1_GPO14.pr0_mii0_txd3 */
+			AM65X_IOPAD(0x0278, PIN_OUTPUT, 0) /* (AD25) PRG0_PRU1_GPO13.pr0_mii0_txd2 */
+			AM65X_IOPAD(0x0274, PIN_OUTPUT, 0) /* (AC25) PRG0_PRU1_GPO12.pr0_mii0_txd1 */
+			AM65X_IOPAD(0x0270, PIN_OUTPUT, 0) /* (AB24) PRG0_PRU1_GPO11.pr0_mii0_txd0 */
+			AM65X_IOPAD(0x0204, PIN_INPUT, 1) /* (Y24) PRG0_PRU0_GPO4.pr0_mii0_rxdv */
+			AM65X_IOPAD(0x020c, PIN_INPUT, 1) /* (Y25) PRG0_PRU0_GPO6.pr0_mii_mr0_clk */
+			AM65X_IOPAD(0x0200, PIN_INPUT, 1) /* (AA27) PRG0_PRU0_GPO3.pr0_mii0_rxd3 */
+			AM65X_IOPAD(0x01fc, PIN_INPUT, 1) /* (W24) PRG0_PRU0_GPO2.pr0_mii0_rxd2 */
+			AM65X_IOPAD(0x0208, PIN_INPUT, 1) /* (V28) PRG0_PRU0_GPO5.pr0_mii0_rxer */
+			AM65X_IOPAD(0x01f8, PIN_INPUT, 1) /* (W25) PRG0_PRU0_GPO1.pr0_mii0_rxd1 */
+			AM65X_IOPAD(0x01f4, PIN_INPUT, 1) /* (V24) PRG0_PRU0_GPO0.pr0_mii0_rxd0 */
+			AM65X_IOPAD(0x0214, PIN_INPUT, 1) /* (V27) PRG0_PRU0_GPO8.pr0_mii0_rxlink */
+
+			AM65X_IOPAD(0x0234, PIN_INPUT, 1) /* (AD28) PRG0_PRU0_GPO16.pr0_mii_mt1_clk */
+			AM65X_IOPAD(0x0230, PIN_OUTPUT, 0) /* (AA24) PRG0_PRU0_GPO15.pr0_mii1_txen */
+			AM65X_IOPAD(0x022c, PIN_OUTPUT, 0) /* (AD26) PRG0_PRU0_GPO14.pr0_mii1_txd3 */
+			AM65X_IOPAD(0x0228, PIN_OUTPUT, 0) /* (AC26) PRG0_PRU0_GPO13.pr0_mii1_txd2 */
+			AM65X_IOPAD(0x0224, PIN_OUTPUT, 0) /* (AD27) PRG0_PRU0_GPO12.pr0_mii1_txd1 */
+			AM65X_IOPAD(0x0220, PIN_OUTPUT, 0) /* (AB25) PRG0_PRU0_GPO11.pr0_mii1_txd0 */
+			AM65X_IOPAD(0x0254, PIN_INPUT, 1) /* (AA25) PRG0_PRU1_GPO4.pr0_mii1_rxdv */
+			AM65X_IOPAD(0x025c, PIN_INPUT, 1) /* (AB27) PRG0_PRU1_GPO6.pr0_mii_mr1_clk */
+			AM65X_IOPAD(0x0250, PIN_INPUT, 1) /* (AB26) PRG0_PRU1_GPO3.pr0_mii1_rxd3 */
+			AM65X_IOPAD(0x024c, PIN_INPUT, 1) /* (AC27) PRG0_PRU1_GPO2.pr0_mii1_rxd2 */
+			AM65X_IOPAD(0x0258, PIN_INPUT, 1) /* (U23) PRG0_PRU1_GPO5.pr0_mii1_rxer */
+			AM65X_IOPAD(0x0248, PIN_INPUT, 1) /* (AC28) PRG0_PRU1_GPO1.pr0_mii1_rxd1 */
+			AM65X_IOPAD(0x0244, PIN_INPUT, 1) /* (AB28) PRG0_PRU1_GPO0.pr0_mii1_rxd0 */
+			AM65X_IOPAD(0x0264, PIN_INPUT, 1) /* (W27) PRG0_PRU1_GPO8.pr0_mii1_rxlink */
+		>;
+	};
+
 	icssg0_iep0_pins_default: icssg0-iep0-pins-default {
 		pinctrl-single,pins = <
 			AM65X_IOPAD(0x0240, PIN_INPUT, 2) /* (U24) PRG0_PRU0_GPO19.PRG0_IEP0_EDC_SYNC_OUT0 */
@@ -266,6 +300,40 @@
 		>;
 	};
 
+	icssg1_mii_pins_default: icssg1-mii-pins-default {
+		pinctrl-single,pins = <
+			AM65X_IOPAD(0x0170, PIN_INPUT, 1) /* (AE19) PRG1_PRU1_GPO16.pr1_mii_mt0_clk */
+			AM65X_IOPAD(0x016c, PIN_OUTPUT, 0) /* (AG19) PRG1_PRU1_GPO15.pr1_mii0_txen */
+			AM65X_IOPAD(0x0168, PIN_OUTPUT, 0) /* (AH19) PRG1_PRU1_GPO14.pr1_mii0_txd3 */
+			AM65X_IOPAD(0x0164, PIN_OUTPUT, 0) /* (AF19) PRG1_PRU1_GPO13.pr1_mii0_txd2 */
+			AM65X_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AE20) PRG1_PRU1_GPO12.pr1_mii0_txd1 */
+			AM65X_IOPAD(0x015c, PIN_OUTPUT, 0) /* (AC20) PRG1_PRU1_GPO11.pr1_mii0_txd0 */
+			AM65X_IOPAD(0x00f0, PIN_INPUT, 1) /* (AG23) PRG1_PRU0_GPO4.pr1_mii0_rxdv */
+			AM65X_IOPAD(0x00f8, PIN_INPUT, 1) /* (AF22) PRG1_PRU0_GPO6.pr1_mii_mr0_clk */
+			AM65X_IOPAD(0x00ec, PIN_INPUT, 1) /* (AD21) PRG1_PRU0_GPO3.pr1_mii0_rxd3 */
+			AM65X_IOPAD(0x00e8, PIN_INPUT, 1) /* (AF23) PRG1_PRU0_GPO2.pr1_mii0_rxd2 */
+			AM65X_IOPAD(0x00f4, PIN_INPUT, 1) /* (AF27) PRG1_PRU0_GPO5.pr1_mii0_rxer */
+			AM65X_IOPAD(0x00e4, PIN_INPUT, 1) /* (AG24) PRG1_PRU0_GPO1.pr1_mii0_rxd1 */
+			AM65X_IOPAD(0x00e0, PIN_INPUT, 1) /* (AE22) PRG1_PRU0_GPO0.pr1_mii0_rxd0 */
+			AM65X_IOPAD(0x0100, PIN_INPUT, 1) /* (AF28) PRG1_PRU0_GPO8.pr1_mii0_rxlink */
+
+			AM65X_IOPAD(0x0120, PIN_INPUT, 1) /* (AD20) PRG1_PRU0_GPO16.pr1_mii_mt1_clk */
+			AM65X_IOPAD(0x011c, PIN_OUTPUT, 0) /* (AD19) PRG1_PRU0_GPO15.pr1_mii1_txen */
+			AM65X_IOPAD(0x0118, PIN_OUTPUT, 0) /* (AG20) PRG1_PRU0_GPO14.pr1_mii1_txd3 */
+			AM65X_IOPAD(0x0114, PIN_OUTPUT, 0) /* (AH21) PRG1_PRU0_GPO13.pr1_mii1_txd2 */
+			AM65X_IOPAD(0x0110, PIN_OUTPUT, 0) /* (AH20) PRG1_PRU0_GPO12.pr1_mii1_txd1 */
+			AM65X_IOPAD(0x010c, PIN_OUTPUT, 0) /* (AF21) PRG1_PRU0_GPO11.pr1_mii1_txd0 */
+			AM65X_IOPAD(0x0140, PIN_INPUT, 1) /* (AE21) PRG1_PRU1_GPO4.pr1_mii1_rxdv */
+			AM65X_IOPAD(0x0148, PIN_INPUT, 1) /* (AG22) PRG1_PRU1_GPO6.pr1_mii_mr1_clk */
+			AM65X_IOPAD(0x013c, PIN_INPUT, 1) /* (AH22) PRG1_PRU1_GPO3.pr1_mii1_rxd3 */
+			AM65X_IOPAD(0x0138, PIN_INPUT, 1) /* (AG21) PRG1_PRU1_GPO2.pr1_mii1_rxd2 */
+			AM65X_IOPAD(0x0144, PIN_INPUT, 1) /* (AC22) PRG1_PRU1_GPO5.pr1_mii1_rxer */
+			AM65X_IOPAD(0x0134, PIN_INPUT, 1) /* (AH23) PRG1_PRU1_GPO1.pr1_mii1_rxd1 */
+			AM65X_IOPAD(0x0130, PIN_INPUT, 1) /* (AH24) PRG1_PRU1_GPO0.pr1_mii1_rxd0 */
+			AM65X_IOPAD(0x0150, PIN_INPUT, 1) /* (AE24) PRG1_PRU1_GPO8.pr1_mii1_rxlink */
+		>;
+	};
+
 	icssg1_iep0_pins_default: icssg1-iep0-pins-default {
 		pinctrl-single,pins = <
 			AM65X_IOPAD(0x012c, PIN_INPUT, 2) /* (AG26) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */
-- 
2.17.1

