From 82036fb1d6ddfcb234e85bc7887b207a9c006517 Mon Sep 17 00:00:00 2001 From: Bin Liu Date: Wed, 11 Feb 2026 10:30:58 -0600 Subject: [PATCH 4/4] mmc: dump mmc registers Signed-off-by: Bin Liu --- common/spl/spl_mmc.c | 2 ++ drivers/mmc/am654_sdhci.c | 26 +++++++++++++++++++++++++- drivers/mmc/mmc.c | 34 +++++++++++++++++++++++++++++++++- 3 files changed, 60 insertions(+), 2 deletions(-) diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 3d032bb27ce3..836ed696ed63 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -5,6 +5,8 @@ * * Aneesh V */ +#define DEBUG + #include #include #include diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c index 8f1095539746..e019ece2db20 100644 --- a/drivers/mmc/am654_sdhci.c +++ b/drivers/mmc/am654_sdhci.c @@ -313,12 +313,32 @@ static int am654_sdhci_set_ios_post(struct sdhci_host *host) return 0; } +void sdhci_dump_phy_regs(void *base) +{ + u32 ctrl[6]; + + regmap_read(base, 0x100, &ctrl[0]); + regmap_read(base, 0x104, &ctrl[1]); + regmap_read(base, 0x108, &ctrl[2]); + regmap_read(base, 0x10c, &ctrl[3]); + regmap_read(base, 0x110, &ctrl[4]); + regmap_read(base, 0x114, &ctrl[5]); + + pr_info("phy_ctrl1 0x%08x, phy_ctrl2 0x%08x, phy_ctrl3 0x%08x\n", + ctrl[0], ctrl[1], ctrl[2]); + pr_info("phy_ctrl4 0x%08x, phy_ctrl5 0x%08x, phy_ctrl6 0x%08x\n\n", + ctrl[3], ctrl[4], ctrl[5]); +} + int am654_sdhci_init(struct am654_sdhci_plat *plat) { u32 ctl_cfg_2 = 0; u32 mask, val; int ret; + pr_info("before am654_sdhci init:\n"); + sdhci_dump_phy_regs(plat->base); + /* Reset OTAP to default value */ mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0); @@ -374,7 +394,11 @@ static int am654_sdhci_deferred_probe(struct sdhci_host *host) am654_sdhci_init(plat); - return sdhci_probe(dev); + val = sdhci_probe(dev); + pr_info("after sdhci SDHCI_RESET_ALL:\n"); + sdhci_dump_phy_regs(plat->base); + + return val; } static void am654_sdhci_write_b(struct sdhci_host *host, u8 val, int reg) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index d96db7a0f836..cbc3f1d408e6 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -6,6 +6,7 @@ * * Based vaguely on the Linux code */ +#define DEBUG #include #include @@ -26,6 +27,7 @@ #include #include #include "mmc_private.h" +#include #define DEFAULT_CMD6_TIMEOUT_MS 500 @@ -162,6 +164,25 @@ const char *mmc_mode_name(enum bus_mode mode) } #endif +void mmc_dump_regs(struct mmc *mmc) +{ + struct sdhci_host *host = mmc->priv; + void *plat = host->ioaddr + 0x8000; + + pr_debug("PHY_CTRL1 0x%08x, PHY_CTRL2 0x%08x, PHY_CTRL3 0x%08x\n", + readl(plat + 0x100), + readl(plat + 0x104), + readl(plat + 0x108)); + pr_debug("PHY_CTRL4 0x%08x, PHY_CTRL5 0x%08x, PHY_CTRL6 0x%08x\n", + readl(plat + 0x10c), + readl(plat + 0x110), + readl(plat + 0x114)); + pr_debug("HOST_CONTROL 0x%01x, HOST_CONTROL2 0x%02x, CLOCK_CONTROL 0x%02x\n\n", + sdhci_readb(host, SDHCI_HOST_CONTROL), + sdhci_readw(host, SDHCI_HOST_CONTROL2), + sdhci_readw(host, SDHCI_CLOCK_CONTROL)); +} + static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode) { static const int freqs[] = { @@ -1627,6 +1648,7 @@ static int mmc_set_ios(struct mmc *mmc) if (mmc->cfg->ops->set_ios) ret = mmc->cfg->ops->set_ios(mmc); + mmc_dump_regs(mmc); return ret; } @@ -1644,6 +1666,8 @@ static int mmc_host_power_cycle(struct mmc *mmc) int mmc_set_clock(struct mmc *mmc, uint clock, bool disable) { + int ret; + if (!disable) { if (clock > mmc->cfg->f_max) clock = mmc->cfg->f_max; @@ -1655,9 +1679,13 @@ int mmc_set_clock(struct mmc *mmc, uint clock, bool disable) mmc->clock = clock; mmc->clk_disable = disable; + mmc_dump_regs(mmc); debug("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock); - return mmc_set_ios(mmc); + ret = mmc_set_ios(mmc); + mmc_dump_regs(mmc); + + return ret; } static int mmc_set_bus_width(struct mmc *mmc, uint width) @@ -2895,6 +2923,7 @@ retry: goto retry; } + mmc_dump_regs(mmc); /* If the command timed out, we check for an MMC card */ if (err == -ETIMEDOUT) { err = mmc_send_op_cond(mmc); @@ -2907,6 +2936,9 @@ retry: return -EOPNOTSUPP; } } +#if !defined(CONFIG_CPU_V7R) + pr_err("___ pass failure point\n"); +#endif return err; } -- 2.34.1