/*
 *  Copyright (C) 2021 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */

//#include <board/ethphy/ethphy_DP83822.h>
#include <ethphy_dp83822.h>
#include <drivers/mdio.h>

/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */

#define ETHPHY_DP83822_BMCR_REG                                     (0x0000)
#define ETHPHY_DP83822_BMSR_REG                                     (0x0001)
#define ETHPHY_DP83822_PHYIDR1_REG                                  (0x0002)
#define ETHPHY_DP83822_PHYIDR2_REG                                  (0x0003)
#define ETHPHY_DP83822_ANAR_REG                                     (0x0004)
#define ETHPHY_DP83822_ANLPAR_REG                                   (0x0005)
#define ETHPHY_DP83822_ANER_REG                                     (0x0006)
#define ETHPHY_DP83822_ANNPTR_REG                                   (0x0007)
#define ETHPHY_DP83822_ANLNPTR_REG                                  (0x0008)
#define ETHPHY_DP83822_GEN_CFG1_REG                                 (0x0009)
#define ETHPHY_DP83822_CR2_REG                                      (0x000A)
#define ETHPHY_DP83822_CR3_REG                                      (0x000B)

#define ETHPHY_DP83822_REGCR_REG                                    (0x000D)

#define ETHPHY_DP83822_FLDS_REG                                    (0x000F)

#define ETHPHY_DP83822_PHY_CONTROL_REG                              (0x0011)    //(0x0010)
#define ETHPHY_DP83822_PHY_STATUS_REG                               (0x0010)    //(0x0011)
#define ETHPHY_DP83822_MISR1_REG                                    (0x0012)
#define ETHPHY_DP83822_MISR2_REG                                    (0x0013)

#define ETHPHY_DP83822_FCSCR_REG                                    (0x0014)
#define ETHPHY_DP83822_RECR_REG                                    (0x0015)
#define ETHPHY_DP83822_BISCR_REG                                    (0x0016)
#define ETHPHY_DP83822_RCSR_REG                                     (0x0017)

#define ETHPHY_DP83822_LEDS_CFG1_REG                                (0x0018)
//#define ETHPHY_DP83822_LEDS_CFG2_REG                                (0x0019)
#define ETHPHY_DP83822_PHYCR                                        (0x0019)
#define ETHPHY_DP83822_LEDS_CFG3_REG                                (0x001A)
#define ETHPHY_DP83822_GEN_CFG4_REG                                 (0x001E)
//below check later
#define ETHPHY_DP83822_PHYRCR_CTRL_REG                              (0x001F)
#define ETHPHY_DP83822_MLED_REG                                     (0x0025)

#define ETHPHY_DP83822_GENCFG_REG                                     (0x0456)
#define ETHPHY_DP83822_LEDCFG1_REG                                     (0x0460)
#define ETHPHY_DP83822_SOR1_REG                                     (0x0467)
#define ETHPHY_DP83822_LEDCFG2_REG                                  (0x0469)

#define ETHPHY_DP83822_GEN_CFG_FLD_REG                              (0x002D)
#define ETHPHY_DP83822_RGMII_CTRL_REG                               (0x0032)
#define ETHPHY_DP83822_RGMII_CTRL2_REG                              (0x0033)
#define ETHPHY_DP83822_G_100BT_REG0_REG                             (0x0043)
#define ETHPHY_DP83822_OP_MODE_DECODE_REG                           (0x01DF)

#define ETHPHY_DP83822_BMCR_IEEE_POWER_DOWN_ENABLE_MASK             (0x0800)
#define ETHPHY_DP83822_BMCR_AUTO_NEGOTIATE_ENABLE_MASK              (0x1000)
#define ETHPHY_DP83822_BMCR_SPEED_SEL_LSB_MASK                      (0x2000)
//#define ETHPHY_DP83822_BMCR_SPEED_SEL_MSB_MASK                      (0x0040) //not available n 83822
#define ETHPHY_DP83822_BMCR_DUPLEX_EN_MASK                          (0x0100)
#define ETHPHY_DP83822_BMSR_AUTONEG_COMP_MASK                       (0x0020)
#define ETHPHY_DP83822_ANER_LP_AUTONEG_ABLE_MASK                    (0x0001)
//#define ETHPHY_DP83822_GEN_CFG1_G_1000BT_FD_ADV_MASK                (0x0200)  //not available n 83822
//#define ETHPHY_DP83822_GEN_CFG1_G_1000BT_HD_ADV_MASK                (0x0100)  //not available n 83822
#define ETHPHY_DP83822_PHY_CONTROL_AUTOMDIX_ENABLE_MASK             (0x8000)        //(0x0040)
#define ETHPHY_DP83822_PHY_CONTROL_LEDConfiguration_MASK            (0x0020)
#define ETHPHY_DP83822_PHY_STATUS_SPEED_MASK                        (0x0002)    //(0xC000)
#define ETHPHY_DP83822_PHY_STATUS_DUPLEX_MASK                       (0x0004)    //(0x2000)
///////////////////////////////////////////////////////////////////////////CHECK LATER
#define ETHPHY_DP83822_LEDS_CFG1_LED_SEL_MASK                       (0x000F)
#define ETHPHY_DP83822_LEDS_CFG3_LEDS_BLINK_RATE_MASK               (0x0003)
#define ETHPHY_DP83822_CR2_EXT_FD_ENABLE_MASK                       (0x0030)    //Enhanced LED Link:bit4  Extended Full-Duplex Ability:bit5
////////////////////////////////////////////////////////////////////////////
//#define ETHPHY_DP83822_GEN_CTRL_SW_RESTART_MASK                     (0x4000)
#define ETHPHY_DP83822_PHYRCR_SW_RESTART_MASK                       (0x4000)
#define ETHPHY_DP83822_PHYRCR_SW_RESET_MASK                         (0x8000)

//#define ETHPHY_DP83822_GEN_CFG_FLD_FAST_LINK_DOWN_MODES_MASK        (0x001F)
#define ETHPHY_DP83822_CR3_FLD_FAST_LINK_DOWN_MODES_MASK            (0x000F)
#define ETHPHY_DP83822_RGMII_CTRL_RX_HALF_FULL_THR_LSB_MASK         (0x0060)
#define ETHPHY_DP83822_RGMII_CTRL_TX_HALF_FULL_THR_LSB_MASK         (0x0018)
#define ETHPHY_DP83822_RGMII_CTRL2_RX_HALF_FULL_THR_MSB_MASK        (0x0002)
#define ETHPHY_DP83822_RGMII_CTRL2_TX_HALF_FULL_THR_MSB_MASK        (0x0001)

#define ETHPHY_DP83822_RGMII_CTRL2_LOW_LATENCY_10_100_EN_MASK       (0x0004)
#define ETHPHY_DP83822_G_100BT_REG0_ENHANCED_IPG_DET_ENABLE_MASK    (0x0010)
#define ETHPHY_DP83822_G_100BT_REG0_ODDNIBBLE_DET_ENABLE_MASK       (0x0002)
#define ETHPHY_DP83822_OP_MODE_DECODE_RGMII_MII_SEL_MASK            (0x0020)

#define ETHPHY_DP83822_RGMII_CTRL_RX_HALF_FULL_THR_LSB_SHIFT        (0x0005)
#define ETHPHY_DP83822_RGMII_CTRL_TX_HALF_FULL_THR_LSB_SHIFT        (0x0003)
#define ETHPHY_DP83822_RGMII_CTRL2_RX_HALF_FULL_THR_MSB_SHIFT       (0x0001)
#define ETHPHY_DP83822_RGMII_CTRL2_TX_HALF_FULL_THR_MSB_SHIFT       (0x0000)

#define ETHPHY_DP83822_PHYIDR1_REG_VALUE                            (0x2000)

#define ETHPHY_DP83822_PHY_STATUS_SPEED_10M                         (0x0000)
#define ETHPHY_DP83822_PHY_STATUS_SPEED_100M                        (0x4000)
#define ETHPHY_DP83822_PHY_STATUS_SPEED_1000M                       (0xC000)

/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */

int32_t ETHPHY_DP83822_open(ETHPHY_Config *config, const ETHPHY_Params *params);

int32_t ETHPHY_DP83822_command(ETHPHY_Config *config,
                               uint32_t command,
                               void *data,
                               uint32_t dataSize);

static int32_t ETHPHY_DP83822_enableMii(ETHPHY_Attrs *attrs);

static int32_t ETHPHY_DP83822_softRestart(ETHPHY_Attrs *attrs);

static int32_t ETHPHY_DP83822_enableAutoMdix(ETHPHY_Attrs *attrs);

static int32_t ETHPHY_DP83822_verifyIdentifierRegister(ETHPHY_Attrs *attrs);

static int32_t ETHPHY_DP83822_disable1000mAdvertisement(ETHPHY_Attrs *attrs);

static int32_t ETHPHY_DP83822_enableFastLinkDownDetection(ETHPHY_Attrs *attrs,
                                                          void         *data,
                                                          uint32_t     dataSize);

static int32_t ETHPHY_DP83822_configureLedSource(ETHPHY_Attrs *attrs,
                                                 void         *data,
                                                 uint32_t     dataSize);

static int32_t ETHPHY_DP83822_configureLedBlinkRate(ETHPHY_Attrs *attrs,
                                                    void         *data,
                                                    uint32_t     dataSize);

static int32_t ETHPHY_DP83822_enableExtendedFdAbility(ETHPHY_Attrs *attrs);

static int32_t ETHPHY_DP83822_enableOddNibbleDetection(ETHPHY_Attrs *attrs);

static int32_t ETHPHY_DP83822_enableEnhancedIpgDetection(ETHPHY_Attrs *attrs);

static int32_t ETHPHY_DP83822_getSpeedDuplex(ETHPHY_Attrs *attrs,
                                                void         *data,
                                                uint32_t     dataSize);

static int32_t ETHPHY_DP83822_setSpeedDuplex(ETHPHY_Attrs *attrs,
                                                void         *data,
                                                uint32_t     dataSize);

static int32_t ETHPHY_DP83822_enableLowLatencyRgmii(ETHPHY_Attrs *attrs);

static int32_t ETHPHY_DP83822_setRxHalfFullThresholdRgmii(ETHPHY_Attrs *attrs,
                                                          void         *data,
                                                          uint32_t     dataSize);

static int32_t ETHPHY_DP83822_setTxHalfFullThresholdRgmii(ETHPHY_Attrs *attrs,
                                                          void         *data,
                                                          uint32_t     dataSize);

static int32_t ETHPHY_DP83822_getAutonegCompleteStatus(ETHPHY_Attrs *attrs,
                                                       void         *data,
                                                       uint32_t     dataSize);


static int32_t ETHPHY_DP83822_getLinkPartnerAutonegAbility(ETHPHY_Attrs *attrs,
                                                           void         *data,
                                                           uint32_t     dataSize);

static int32_t ETHPHY_DP83822_enableIeeePowerDownMode(ETHPHY_Attrs *attrs);

static int32_t ETHPHY_DP83822_disableIeeePowerDownMode(ETHPHY_Attrs *attrs);

static void Dp83822_printRegs(ETHPHY_Attrs *attrs,uint32_t RegAddr);
static int32_t ETHPHY_DP83822_RegDump(ETHPHY_Attrs *attrs);
static int32_t ETHPHY_DP83822_Ecat_init(ETHPHY_Attrs *attrs);
/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

ETHPHY_Fxns gEthPhyFxns_DP83822 =
{
    .openFxn    = ETHPHY_DP83822_open,
    .closeFxn   = NULL,
    .commandFxn = ETHPHY_DP83822_command,
};

/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */

int32_t ETHPHY_DP83822_open(ETHPHY_Config *config, const ETHPHY_Params *params)
{
    int32_t         status = SystemP_SUCCESS;
    ETHPHY_Attrs    *attrs;

    //DebugP_log("%s\n\r",__func__);

    if((NULL == config) || (NULL == params) || (NULL == config->attrs)) {
        status = SystemP_FAILURE;
    }
    else
    {
        attrs = config->attrs;
        status = MDIO_initClock(attrs->mdioBaseAddress);
    }

    return status;
}

int32_t ETHPHY_DP83822_command(ETHPHY_Config *config,
                               uint32_t command,
                               void *data,
                               uint32_t dataSize)
{
    int32_t         status = SystemP_SUCCESS;
    ETHPHY_Attrs    *attrs;

    //DebugP_log("%s command [%#x] data[%#x] dataSize[%d]\n\r",__func__,command,data,dataSize);

    if(NULL == config) {
        status = SystemP_FAILURE;
    }

    if(status == SystemP_SUCCESS)
    {
        attrs = config->attrs;
        switch (command)
        {
            case ETHPHY_CMD_ENABLE_MII :
                status = ETHPHY_DP83822_enableMii(attrs);
                break;

            case ETHPHY_CMD_SOFT_RESTART :
                status = ETHPHY_DP83822_softRestart(attrs);
                break;

            case ETHPHY_CMD_ENABLE_AUTO_MDIX :
                //status = ETHPHY_DP83822_enableAutoMdix(attrs);
                status = ETHPHY_DP83822_Ecat_init(attrs);
                break;

            case ETHPHY_CMD_VERIFY_IDENTIFIER_REGISTER :
                status = ETHPHY_DP83822_verifyIdentifierRegister(attrs);
                break;

            case ETHPHY_CMD_DISABLE_1000M_ADVERTISEMENT :
                status = ETHPHY_DP83822_disable1000mAdvertisement(attrs);
                break;

            case ETHPHY_CMD_ENABLE_FAST_LINK_DOWN_DETECTION :
                status = ETHPHY_DP83822_enableFastLinkDownDetection(attrs, data, dataSize);
                break;

            case ETHPHY_CMD_CONFIGURE_LED_SOURCE :
                status = ETHPHY_DP83822_configureLedSource(attrs, data, dataSize);
                break;

            case ETHPHY_CMD_CONFIGURE_LED_BLINK_RATE :
                status = ETHPHY_DP83822_configureLedBlinkRate(attrs, data, dataSize);
                break;

            case ETHPHY_CMD_ENABLE_EXTENDED_FD_ABILITY :
                status = ETHPHY_DP83822_enableExtendedFdAbility(attrs);
                break;

            case ETHPHY_CMD_ENABLE_ODD_NIBBLE_DETECTION :
                status = ETHPHY_DP83822_enableOddNibbleDetection(attrs);
                break;

            case ETHPHY_CMD_ENABLE_ENHANCED_IPG_DETECTION :
                status = ETHPHY_DP83822_enableEnhancedIpgDetection(attrs);
                break;

            case ETHPHY_CMD_GET_LINK_STATUS :
                status = MDIO_phyLinkStatus(attrs->mdioBaseAddress, attrs->phyAddress);

                //#ifdef Debug_Verbose
                    if(status == SystemP_SUCCESS) {
                        DebugP_log("MDIO_phyLinkStatus : mdioBaseAddress [%#x] PHY[%d] Link Ok\r\n",attrs->mdioBaseAddress , attrs->phyAddress);
                    }
                    else {
                        DebugP_log("MDIO_phyLinkStatus : mdioBaseAddress [%#x] PHY[%d] No Link\r\n",attrs->mdioBaseAddress , attrs->phyAddress);
                    }
                //#endif
                break;

            case ETHPHY_CMD_GET_SPEED_AND_DUPLEX_CONFIG :
                status = ETHPHY_DP83822_getSpeedDuplex(attrs, data, dataSize);
                break;

            case ETHPHY_CMD_SET_SPEED_AND_DUPLEX_CONFIG :
                status = ETHPHY_DP83822_setSpeedDuplex(attrs, data, dataSize);
                break;

            case ETHPHY_CMD_ENABLE_LOW_LATENCY_10M_100M_RGMII:
                status = ETHPHY_DP83822_enableLowLatencyRgmii(attrs);
                break;

            case ETHPHY_CMD_SET_RX_HALF_FULL_THRESHOLD_RGMII:
                status = ETHPHY_DP83822_setRxHalfFullThresholdRgmii(attrs, data, dataSize);
                break;

            case ETHPHY_CMD_SET_TX_HALF_FULL_THRESHOLD_RGMII:
                //status = ETHPHY_DP83822_setTxHalfFullThresholdRgmii(attrs, data, dataSize);
                status = ETHPHY_DP83822_RegDump(attrs);
                break;

            case ETHPHY_CMD_GET_AUTONEG_COMPLETE_STATUS:
                status = ETHPHY_DP83822_getAutonegCompleteStatus(attrs, data, dataSize);
                break;

            case ETHPHY_CMD_GET_LINK_PARTNER_AUTONEG_ABILITY:
                status = ETHPHY_DP83822_getLinkPartnerAutonegAbility(attrs, data, dataSize);
                break;

            case ETHPHY_CMD_ENABLE_IEEE_POWER_DOWN:
                status = ETHPHY_DP83822_enableIeeePowerDownMode(attrs);
                break;

            case ETHPHY_CMD_DISABLE_IEEE_POWER_DOWN:
                status = ETHPHY_DP83822_disableIeeePowerDownMode(attrs);
                break;

            default:
                status = SystemP_FAILURE;
                break;
        }
    }

    return status;
}

static int32_t ETHPHY_DP83822_enableMii(ETHPHY_Attrs *attrs)
{
    int32_t status = SystemP_FAILURE;
    uint16_t phyRegVal = 0;

    //DebugP_log("%s phyAddress[%#x] Required 0x0041\n\r",__func__,attrs->phyAddress);
    Dp83822_printRegs(attrs, ETHPHY_DP83822_RCSR_REG);

    status = MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_RCSR_REG, &phyRegVal);

       if(status == SystemP_SUCCESS) {
           phyRegVal = 0x0041; //ETHPHY_DP83822_PHYRCR_SW_RESTART_MASK;
           status = MDIO_phyRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_RCSR_REG, phyRegVal);
       }


    /*
    status = MDIO_phyExtRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_RCSR_REG, &phyRegVal);

    if(status == SystemP_SUCCESS)
    {
        //phyRegVal |= ETHPHY_DP83822_OP_MODE_DECODE_RGMII_MII_SEL_MASK;
        phyRegVal &= ~0x0220;     //0000 0010 0010 0000 = 0x0220
        status = MDIO_phyExtRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_RCSR_REG, phyRegVal);
    }
    //Below For debug only
    status = MDIO_phyExtRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_RCSR_REG, &phyRegVal);
    if(status == SystemP_SUCCESS)
    {
        DebugP_log("%s phyAddress[%#x] MII Enabled : %#x bi5/9  should be 0 for MII\n\r",__func__,attrs->phyAddress,phyRegVal);
    }
    //For debug only
     */

    Dp83822_printRegs(attrs, ETHPHY_DP83822_RCSR_REG);
    return status;
}

static int32_t ETHPHY_DP83822_softRestart(ETHPHY_Attrs *attrs)
{
    int32_t status = SystemP_FAILURE;
    uint16_t phyRegVal = 0;

    //DebugP_log("%s phyAddress[%#x]\n\r",__func__,attrs->phyAddress);
    Dp83822_printRegs(attrs, ETHPHY_DP83822_PHYRCR_CTRL_REG);

    status = MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_PHYRCR_CTRL_REG, &phyRegVal);

    if(status == SystemP_SUCCESS) {
        phyRegVal |= ETHPHY_DP83822_PHYRCR_SW_RESTART_MASK;
        status = MDIO_phyRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_PHYRCR_CTRL_REG, phyRegVal);
    }
    Dp83822_printRegs(attrs, ETHPHY_DP83822_PHYRCR_CTRL_REG);

    return status;
}

static int32_t ETHPHY_DP83822_enableAutoMdix(ETHPHY_Attrs *attrs)
{
    int32_t status = SystemP_FAILURE;
    uint16_t phyRegVal = 0;

    //DebugP_log("%s phyAddress[%#x]\n\r",__func__,attrs->phyAddress);
    Dp83822_printRegs(attrs, ETHPHY_DP83822_PHYCR);

    status = MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_PHYCR, &phyRegVal);

    if(status == SystemP_SUCCESS) {
        phyRegVal |= ETHPHY_DP83822_PHY_CONTROL_AUTOMDIX_ENABLE_MASK | ETHPHY_DP83822_PHY_CONTROL_LEDConfiguration_MASK;
        status = MDIO_phyRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_PHYCR, phyRegVal);
    }
    Dp83822_printRegs(attrs, ETHPHY_DP83822_PHYCR);
    return status;
}

static int32_t ETHPHY_DP83822_verifyIdentifierRegister(ETHPHY_Attrs *attrs)
{
    int32_t status = SystemP_FAILURE;
    uint16_t phyRegVal = 0;

    //DebugP_log("%s phyAddress[%#x]\n\r",__func__,attrs->phyAddress);

    status = MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_PHYIDR1_REG, &phyRegVal);

    if(status == SystemP_SUCCESS)
    {
        if(phyRegVal == ETHPHY_DP83822_PHYIDR1_REG_VALUE) {
            status = SystemP_SUCCESS;
        }
        else {
            status = SystemP_FAILURE;
        }
    }
    return status;
}

static int32_t ETHPHY_DP83822_disable1000mAdvertisement(ETHPHY_Attrs *attrs)
{
    int32_t status = SystemP_FAILURE;
    //uint16_t phyRegVal = 0;

    status = SystemP_SUCCESS;

    //DebugP_log("%s phyAddress[%#x]\n\r",__func__,attrs->phyAddress);
/*
    status = MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_GEN_CFG1_REG, &phyRegVal);

    if(status == SystemP_SUCCESS)
    {
        phyRegVal &= ~ETHPHY_DP83822_GEN_CFG1_G_1000BT_FD_ADV_MASK;
        phyRegVal &= ~ETHPHY_DP83822_GEN_CFG1_G_1000BT_HD_ADV_MASK;
        status = MDIO_phyRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_GEN_CFG1_REG, phyRegVal);
    }*/
    return status;
}

static int32_t ETHPHY_DP83822_enableFastLinkDownDetection(ETHPHY_Attrs *attrs,
                                                          void         *data,
                                                          uint32_t     dataSize)
{
    int32_t status = SystemP_SUCCESS;
    uint16_t phyRegVal = 0;
    uint32_t mode;

    //DebugP_log("%s phyAddress[%#x] data[%#x]\n\r",__func__,attrs->phyAddress,((ETHPHY_DP83822_FastLinkDownDetectionConfig *)data)->mode);
    Dp83822_printRegs(attrs, ETHPHY_DP83822_CR3_REG);

    if((data == NULL) || (dataSize != sizeof(ETHPHY_DP83822_FastLinkDownDetectionConfig))) {
        status = SystemP_FAILURE;
    }

    if(status == SystemP_SUCCESS) {
        status = MDIO_phyExtRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_CR3_REG, &phyRegVal);
    }
    if(status == SystemP_SUCCESS)
    {
        mode = ((ETHPHY_DP83822_FastLinkDownDetectionConfig *)data)->mode;

        mode = 0x180c;
        //DebugP_log("mode [%#x]\n\r",mode);

        phyRegVal &= ~(ETHPHY_DP83822_CR3_FLD_FAST_LINK_DOWN_MODES_MASK);
        //phyRegVal |= (mode & ETHPHY_DP83822_CR3_FLD_FAST_LINK_DOWN_MODES_MASK);
        phyRegVal |= mode;
        status = MDIO_phyExtRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_CR3_REG, phyRegVal);
    }
    Dp83822_printRegs(attrs, ETHPHY_DP83822_CR3_REG);
    return status;
}

static int32_t ETHPHY_DP83822_configureLedSource(ETHPHY_Attrs *attrs,
                                                 void         *data,
                                                 uint32_t     dataSize)
{
    int32_t status = SystemP_SUCCESS;
    uint16_t phyRegVal = 0;
    uint32_t ledNum;
    uint32_t mode;

   // DebugP_log("%s phyAddress[%#x]\n\r",__func__,attrs->phyAddress);
    Dp83822_printRegs(attrs, ETHPHY_DP83822_LEDS_CFG1_REG);

    if((data == NULL) || (dataSize != sizeof(ETHPHY_DP83822_LedSourceConfig))) {
        status = SystemP_FAILURE;
    }

    if(status == SystemP_SUCCESS) {
        status = MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_LEDS_CFG1_REG, &phyRegVal);
    }

    if(status == SystemP_SUCCESS)
    {
        ledNum = ((ETHPHY_DP83822_LedSourceConfig *)data)->ledNum;
        mode = ((ETHPHY_DP83822_LedSourceConfig *)data)->mode;

        switch(ledNum)
        {
            case ETHPHY_DP83822_LED0:
                //phyRegVal &= ~(ETHPHY_DP83822_LEDS_CFG1_LED_SEL_MASK << 0);
                //phyRegVal |= (mode << 0);
                phyRegVal = 0x0000;    //0x0080;
                break;
/*
            case ETHPHY_DP83822_LED1:
                //phyRegVal &= ~(ETHPHY_DP83822_LEDS_CFG1_LED_SEL_MASK << 4);
                //phyRegVal |= (mode << 4);
                break;

            case ETHPHY_DP83822_LED2:
                //phyRegVal &= ~(ETHPHY_DP83822_LEDS_CFG1_LED_SEL_MASK << 8);
                //phyRegVal |= (mode << 8);
                break;

            case ETHPHY_DP83822_LED_GPIO:
                //phyRegVal &= ~(ETHPHY_DP83822_LEDS_CFG1_LED_SEL_MASK << 12);
                //phyRegVal |= (mode << 12);
                break;*/

        }

        status = MDIO_phyRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_LEDS_CFG1_REG, phyRegVal);
    }
    Dp83822_printRegs(attrs, ETHPHY_DP83822_LEDS_CFG1_REG);

    (void)mode;
    return status;
}

static int32_t ETHPHY_DP83822_configureLedBlinkRate(ETHPHY_Attrs *attrs,
                                                    void         *data,
                                                    uint32_t     dataSize)
{
    int32_t status = SystemP_SUCCESS;
    uint16_t phyRegVal = 0;
    uint32_t blinkRate;

    //DebugP_log("%s phyAddress[%#x]\n\r",__func__,attrs->phyAddress);
    return status;

    if((data == NULL) || (dataSize != sizeof(ETHPHY_DP83822_LedBlinkRateConfig))) {
        status = SystemP_FAILURE;
    }

    if(status == SystemP_SUCCESS) {
        status = MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_LEDS_CFG3_REG, &phyRegVal);
    }

    if(status == SystemP_SUCCESS)
    {
        blinkRate = ((ETHPHY_DP83822_LedBlinkRateConfig *)data)->rate;

        phyRegVal &= ~(ETHPHY_DP83822_LEDS_CFG3_LEDS_BLINK_RATE_MASK);
        phyRegVal |= blinkRate;

        status = MDIO_phyRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_LEDS_CFG3_REG, phyRegVal);
    }
    return status;
}

static int32_t ETHPHY_DP83822_enableExtendedFdAbility(ETHPHY_Attrs *attrs)
{
    int32_t status = SystemP_FAILURE;
    uint16_t phyRegVal = 0;

    //DebugP_log("%s phyAddress[%#x]\n\r",__func__,attrs->phyAddress);

    status = MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_CR2_REG, &phyRegVal);

    if(status == SystemP_SUCCESS) {
        phyRegVal |= ETHPHY_DP83822_CR2_EXT_FD_ENABLE_MASK;
        status = MDIO_phyRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_CR2_REG, phyRegVal);
    }
    return status;
}

static int32_t ETHPHY_DP83822_enableOddNibbleDetection(ETHPHY_Attrs *attrs)
{
    int32_t status = SystemP_FAILURE;
    uint16_t phyRegVal = 0;

   // DebugP_log("%s phyAddress[%#x]\n\r",__func__,attrs->phyAddress);

    status = MDIO_phyExtRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_CR2_REG, &phyRegVal);

    if(status == SystemP_SUCCESS) {
        phyRegVal |= (ETHPHY_DP83822_G_100BT_REG0_ODDNIBBLE_DET_ENABLE_MASK);
        status = MDIO_phyExtRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_CR2_REG, phyRegVal);
    }

    return status;
}

static int32_t ETHPHY_DP83822_enableEnhancedIpgDetection(ETHPHY_Attrs *attrs)
{
    int32_t status = SystemP_FAILURE;
    uint16_t phyRegVal = 0;

    //DebugP_log("%s phyAddress[%#x]\n\r",__func__,attrs->phyAddress);

    status = MDIO_phyExtRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_CR2_REG, &phyRegVal);

    if(status == SystemP_SUCCESS) {
        phyRegVal |= 0x0004;        //(ETHPHY_DP83822_G_100BT_REG0_ENHANCED_IPG_DET_ENABLE_MASK);    enable RX_ER During IDLE
        status = MDIO_phyExtRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_CR2_REG, phyRegVal);
    }

    return status;
}

static int32_t ETHPHY_DP83822_getSpeedDuplex(ETHPHY_Attrs *attrs,
                                                void         *data,
                                                uint32_t     dataSize)
{
    uint16_t phyRegVal = 0;
    int32_t status = SystemP_SUCCESS;
    ETHPHY_SpeedDuplexConfig *pSpeedDuplex = NULL;

    //DebugP_log("%s phyAddress[%#x]\n\r",__func__,attrs->phyAddress);

    if((data == NULL) || (dataSize != sizeof(ETHPHY_DP83822_LedBlinkRateConfig))) {
        status = SystemP_FAILURE;
    }

    if(status == SystemP_SUCCESS) {
        status = MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_PHY_STATUS_REG, &phyRegVal);
        pSpeedDuplex = (ETHPHY_SpeedDuplexConfig *)data;
    }

    if(status == SystemP_SUCCESS)
    {
        if((phyRegVal & ETHPHY_DP83822_PHY_STATUS_SPEED_MASK) == ETHPHY_DP83822_PHY_STATUS_SPEED_10M)  /*Speed is 10*/
        {
            if(phyRegVal & ETHPHY_DP83822_PHY_STATUS_DUPLEX_MASK) {
                pSpeedDuplex->config = ETHPHY_SPEED_DUPLEX_CONFIG_10FD;
            }
            else {
                pSpeedDuplex->config = ETHPHY_SPEED_DUPLEX_CONFIG_10HD;
            }
        }
        else if((phyRegVal & ETHPHY_DP83822_PHY_STATUS_SPEED_MASK) == ETHPHY_DP83822_PHY_STATUS_SPEED_100M)/*Speed is 100*/
        {
            if(phyRegVal & ETHPHY_DP83822_PHY_STATUS_DUPLEX_MASK) {
                pSpeedDuplex->config = ETHPHY_SPEED_DUPLEX_CONFIG_100FD;
            }
            else {
                pSpeedDuplex->config = ETHPHY_SPEED_DUPLEX_CONFIG_100HD;
            }
        }
        else if((phyRegVal & ETHPHY_DP83822_PHY_STATUS_SPEED_MASK) == ETHPHY_DP83822_PHY_STATUS_SPEED_1000M)/*Speed is 1000*/
        {
            if(phyRegVal & ETHPHY_DP83822_PHY_STATUS_DUPLEX_MASK) {
                pSpeedDuplex->config = ETHPHY_SPEED_DUPLEX_CONFIG_1000FD;
            }
            else {
                pSpeedDuplex->config = ETHPHY_SPEED_DUPLEX_CONFIG_1000HD;
            }
        }
        else {
            pSpeedDuplex->config = ETHPHY_SPEED_DUPLEX_CONFIG_INVALID;
        }
    }

    return status;
}

static int32_t ETHPHY_DP83822_setSpeedDuplex(ETHPHY_Attrs *attrs,
                                                void         *data,
                                                uint32_t     dataSize)
{
    uint16_t phyRegVal = 0;
    int32_t status = SystemP_SUCCESS;
    uint32_t config;

    //DebugP_log("%s phyAddress[%#x] DupSpeed[%#x]\n\r",__func__,attrs->phyAddress,((ETHPHY_SpeedDuplexConfig *)data)->config);

    if((data == NULL) || (dataSize != sizeof(ETHPHY_DP83822_LedBlinkRateConfig))) {
        status = SystemP_FAILURE;
    }

    if(status == SystemP_SUCCESS) {
        status = MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_BMCR_REG, &phyRegVal);
    }

    if(status == SystemP_SUCCESS)
    {
        config = ((ETHPHY_SpeedDuplexConfig *)data)->config;

        switch(config)
        {
            case ETHPHY_SPEED_DUPLEX_CONFIG_AUTONEG:
                phyRegVal |= ETHPHY_DP83822_BMCR_AUTO_NEGOTIATE_ENABLE_MASK;
                break;

            case ETHPHY_SPEED_DUPLEX_CONFIG_10FD:
                phyRegVal &= ~(ETHPHY_DP83822_BMCR_AUTO_NEGOTIATE_ENABLE_MASK);
                phyRegVal &= ~(ETHPHY_DP83822_BMCR_SPEED_SEL_LSB_MASK);
                //phyRegVal &= ~(ETHPHY_DP83822_BMCR_SPEED_SEL_MSB_MASK);
                phyRegVal |= ETHPHY_DP83822_BMCR_DUPLEX_EN_MASK;
                break;

            case ETHPHY_SPEED_DUPLEX_CONFIG_100FD:
                phyRegVal &= ~(ETHPHY_DP83822_BMCR_AUTO_NEGOTIATE_ENABLE_MASK);
                //phyRegVal &= ~(ETHPHY_DP83822_BMCR_SPEED_SEL_MSB_MASK);
                phyRegVal |= ETHPHY_DP83822_BMCR_SPEED_SEL_LSB_MASK;
                phyRegVal |= ETHPHY_DP83822_BMCR_DUPLEX_EN_MASK;
                break;

           /* case ETHPHY_SPEED_DUPLEX_CONFIG_1000FD:
                phyRegVal &= ~(ETHPHY_DP83822_BMCR_AUTO_NEGOTIATE_ENABLE_MASK);
                phyRegVal |= ETHPHY_DP83822_BMCR_SPEED_SEL_MSB_MASK;
                phyRegVal |= ETHPHY_DP83822_BMCR_SPEED_SEL_LSB_MASK;
                phyRegVal |= ETHPHY_DP83822_BMCR_DUPLEX_EN_MASK;
                break;*/

            case ETHPHY_SPEED_DUPLEX_CONFIG_10HD:
                phyRegVal &= ~(ETHPHY_DP83822_BMCR_AUTO_NEGOTIATE_ENABLE_MASK);
                phyRegVal &= ~(ETHPHY_DP83822_BMCR_SPEED_SEL_LSB_MASK);
                //phyRegVal &= ~(ETHPHY_DP83822_BMCR_SPEED_SEL_MSB_MASK);
                phyRegVal &= ~(ETHPHY_DP83822_BMCR_DUPLEX_EN_MASK);
                break;

            case ETHPHY_SPEED_DUPLEX_CONFIG_100HD:
                phyRegVal &= ~(ETHPHY_DP83822_BMCR_AUTO_NEGOTIATE_ENABLE_MASK);
                //phyRegVal &= ~(ETHPHY_DP83822_BMCR_SPEED_SEL_MSB_MASK);
                phyRegVal |= ETHPHY_DP83822_BMCR_SPEED_SEL_LSB_MASK;
                phyRegVal &= ~(ETHPHY_DP83822_BMCR_DUPLEX_EN_MASK);
                break;

  /*          case ETHPHY_SPEED_DUPLEX_CONFIG_1000HD:
                phyRegVal &= ~(ETHPHY_DP83822_BMCR_AUTO_NEGOTIATE_ENABLE_MASK);
                phyRegVal |= ETHPHY_DP83822_BMCR_SPEED_SEL_MSB_MASK;
                phyRegVal |= ETHPHY_DP83822_BMCR_SPEED_SEL_LSB_MASK;
                phyRegVal &= ~(ETHPHY_DP83822_BMCR_DUPLEX_EN_MASK);
                break;*/

            default:
                status = SystemP_FAILURE;
                break;
        }
    }

    if(status == SystemP_SUCCESS) {
        status = MDIO_phyRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_BMCR_REG, phyRegVal);
    }
    return status;
}

static int32_t ETHPHY_DP83822_enableLowLatencyRgmii(ETHPHY_Attrs *attrs)
{
    int32_t status = SystemP_FAILURE;
    uint16_t phyRegVal = 0;

    //DebugP_log("%s phyAddress[%#x]\n\r",__func__,attrs->phyAddress);

    status = MDIO_phyExtRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_RGMII_CTRL2_REG, &phyRegVal);

    if(status == SystemP_SUCCESS) {
        phyRegVal |= (ETHPHY_DP83822_RGMII_CTRL2_LOW_LATENCY_10_100_EN_MASK);
        status = MDIO_phyExtRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_RGMII_CTRL2_REG, phyRegVal);
    }

    return status;
}

static int32_t ETHPHY_DP83822_setRxHalfFullThresholdRgmii(ETHPHY_Attrs *attrs,
                                                          void         *data,
                                                          uint32_t     dataSize)
{
    int32_t status = SystemP_SUCCESS;
    uint16_t phyRegVal = 0;
    uint16_t phyRegVal2 = 0;
    uint8_t value;
    uint8_t valueLsbs;
    uint8_t valueMsb;

    //DebugP_log("%s phyAddress[%#x]\n\r",__func__,attrs->phyAddress);

    if((data == NULL) || (dataSize != sizeof(uint8_t))) {
        status = SystemP_FAILURE;
    }

    if(status == SystemP_SUCCESS) {
        status = MDIO_phyExtRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_RGMII_CTRL_REG, &phyRegVal);
        status = MDIO_phyExtRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_RGMII_CTRL2_REG, &phyRegVal2);
    }

    if(status == SystemP_SUCCESS)
    {
        value = (uint8_t)(*(uint8_t *)data);

        /*Store 2 LSBs from value(Bits[1:0]) into Bits[1:0] of valueLsbs*/
        valueLsbs = (value & 0x03);

        /*Store MSB from value(Bit[2]) into Bit[0] of valueMsb*/
        valueMsb = (value & 0x04);
        valueMsb >>= 2;

        /* Set lower 2 bits in Bits[6:5] of RGMII_CTRL and MSB in Bit[1] of RGMII_CTRL2*/
        phyRegVal &= ~(ETHPHY_DP83822_RGMII_CTRL_RX_HALF_FULL_THR_LSB_MASK);
        phyRegVal |= (valueLsbs << ETHPHY_DP83822_RGMII_CTRL_RX_HALF_FULL_THR_LSB_SHIFT);
        phyRegVal2 &= ~(ETHPHY_DP83822_RGMII_CTRL2_RX_HALF_FULL_THR_MSB_MASK);
        phyRegVal2 |= (valueMsb << ETHPHY_DP83822_RGMII_CTRL2_RX_HALF_FULL_THR_MSB_SHIFT);

        status = MDIO_phyExtRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_RGMII_CTRL_REG, phyRegVal);
    }

    if(status == SystemP_SUCCESS) {
        status = MDIO_phyExtRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_RGMII_CTRL2_REG, phyRegVal2);
    }

    return status;
}

static int32_t ETHPHY_DP83822_setTxHalfFullThresholdRgmii(ETHPHY_Attrs *attrs,
                                                          void         *data,
                                                          uint32_t     dataSize)
{
    int32_t status = SystemP_SUCCESS;
    uint16_t phyRegVal = 0;
    uint16_t phyRegVal2 = 0;
    uint8_t value;
    uint8_t valueLsbs;
    uint8_t valueMsb;

    //DebugP_log("%s phyAddress[%#x]\n\r",__func__,attrs->phyAddress);

    if((data == NULL) || (dataSize != sizeof(uint8_t))) {
        status = SystemP_FAILURE;
    }

    if(status == SystemP_SUCCESS) {
        status = MDIO_phyExtRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_RGMII_CTRL_REG, &phyRegVal);
        status = MDIO_phyExtRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_RGMII_CTRL2_REG, &phyRegVal2);
    }

    if(status == SystemP_SUCCESS)
    {
        value = (uint8_t)(*(uint8_t *)data);

        /*Store 2 LSBs from value(Bits[1:0]) into Bits[1:0] of valueLsbs*/
        valueLsbs = (value & 0x03);

        /*Store MSB from value(Bit[2]) into Bit[0] of valueMsb*/
        valueMsb = (value & 0x04);
        valueMsb >>= 2;

        /* Set lower 2 bits in Bits[4:3] of RGMII_CTRL and MSB in Bit[0] of RGMII_CTRL2*/
        phyRegVal &= ~(ETHPHY_DP83822_RGMII_CTRL_TX_HALF_FULL_THR_LSB_MASK);
        phyRegVal |= (valueLsbs << ETHPHY_DP83822_RGMII_CTRL_TX_HALF_FULL_THR_LSB_SHIFT);
        phyRegVal2 &= ~(ETHPHY_DP83822_RGMII_CTRL2_TX_HALF_FULL_THR_MSB_MASK);
        phyRegVal2 |= (valueMsb << ETHPHY_DP83822_RGMII_CTRL2_TX_HALF_FULL_THR_MSB_SHIFT);

        status = MDIO_phyExtRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_RGMII_CTRL_REG, phyRegVal);
    }

    if(status == SystemP_SUCCESS) {
        status = MDIO_phyExtRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_RGMII_CTRL2_REG, phyRegVal2);
    }

    return status;
}

static int32_t ETHPHY_DP83822_getAutonegCompleteStatus(ETHPHY_Attrs *attrs,
                                                       void         *data,
                                                       uint32_t     dataSize)
{
    int32_t status = SystemP_SUCCESS;
    uint16_t phyRegVal = 0;
    uint8_t *value = (uint8_t *)data;

    //DebugP_log("%s phyAddress[%#x]\n\r",__func__,attrs->phyAddress);

    if((data == NULL) || (dataSize != sizeof(uint8_t))) {
        status = SystemP_FAILURE;
    }

    if(status == SystemP_SUCCESS) {
        status = MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_BMSR_REG, &phyRegVal);
    }

    if(status == SystemP_SUCCESS)
    {
        if(phyRegVal & ETHPHY_DP83822_BMSR_AUTONEG_COMP_MASK) {
            *value = 1;
        }
        else {
            *value = 0;
        }
    }

    return status;
}

static int32_t ETHPHY_DP83822_getLinkPartnerAutonegAbility(ETHPHY_Attrs *attrs,
                                                           void         *data,
                                                           uint32_t     dataSize)
{
    int32_t status = SystemP_SUCCESS;
    uint16_t phyRegVal = 0;
    uint8_t *value = (uint8_t *)data;

    //DebugP_log("%s phyAddress[%#x]\n\r",__func__,attrs->phyAddress);

    if((data == NULL) || (dataSize != sizeof(uint8_t))) {
        status = SystemP_FAILURE;
    }

    if(status == SystemP_SUCCESS) {
        status = MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_ANER_REG, &phyRegVal);
    }

    if(status == SystemP_SUCCESS)
    {
        if(phyRegVal & ETHPHY_DP83822_ANER_LP_AUTONEG_ABLE_MASK) {
            *value = 1;
        }
        else {
            *value = 0;
        }
    }

    return status;
}

static int32_t ETHPHY_DP83822_enableIeeePowerDownMode(ETHPHY_Attrs *attrs)
{
    int32_t status = SystemP_FAILURE;
    uint16_t phyRegVal = 0;

    //DebugP_log("%s phyAddress[%#x]\n\r",__func__,attrs->phyAddress);
    Dp83822_printRegs(attrs, ETHPHY_DP83822_BMCR_REG);

    status = MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_BMCR_REG, &phyRegVal);

    if(status == SystemP_SUCCESS)
    {
        phyRegVal |= (ETHPHY_DP83822_BMCR_IEEE_POWER_DOWN_ENABLE_MASK);
        status = MDIO_phyRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_BMCR_REG, phyRegVal);
    }

    Dp83822_printRegs(attrs, ETHPHY_DP83822_BMCR_REG);

    return status;
}

static int32_t ETHPHY_DP83822_disableIeeePowerDownMode(ETHPHY_Attrs *attrs)
{
    int32_t status = SystemP_FAILURE;
    uint16_t phyRegVal = 0;

    //DebugP_log("%s phyAddress[%#x]\n\r",__func__,attrs->phyAddress);
    Dp83822_printRegs(attrs, ETHPHY_DP83822_BMCR_REG);

    status = MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_BMCR_REG, &phyRegVal);

    if(status == SystemP_SUCCESS)
    {
        phyRegVal &= ~(ETHPHY_DP83822_BMCR_IEEE_POWER_DOWN_ENABLE_MASK);
        status = MDIO_phyRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_BMCR_REG, phyRegVal);
    }
    Dp83822_printRegs(attrs, ETHPHY_DP83822_BMCR_REG);

    return status;
}


static int32_t ETHPHY_DP83822_Ecat_init(ETHPHY_Attrs *attrs)
{
    int32_t status = SystemP_FAILURE;
    uint16_t phyRegVal = 0;

    //DebugP_log("%s phyAddress[%#x]\r\n",__func__,attrs->phyAddress);

    //LED0
    //DebugP_log("Auto-MDIX enable and enable LED0 config Required 0x8020\r\n");
    Dp83822_printRegs(attrs, ETHPHY_DP83822_PHYCR);

    status = MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_PHYCR, &phyRegVal);
    if(status == SystemP_SUCCESS)
    {
        phyRegVal = 0x8020;        //ETHPHY_DP83822_PHY_CONTROL_AUTOMDIX_ENABLE_MASK | ETHPHY_DP83822_PHY_CONTROL_LEDConfiguration_MASK;
        status = MDIO_phyRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_PHYCR, phyRegVal);
    }
    Dp83822_printRegs(attrs, ETHPHY_DP83822_PHYCR);


    //DebugP_log("LED0 Active High polarity  Required 0x0080\r\n");
    Dp83822_printRegs(attrs, ETHPHY_DP83822_LEDS_CFG1_REG);

    status = MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_LEDS_CFG1_REG, &phyRegVal);
    if(status == SystemP_SUCCESS)
    {
        phyRegVal = 0x0000;     //0x0080;        //ETHPHY_DP83822_PHY_CONTROL_AUTOMDIX_ENABLE_MASK | ETHPHY_DP83822_PHY_CONTROL_LEDConfiguration_MASK;
        status = MDIO_phyRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_LEDS_CFG1_REG, phyRegVal);
    }
    Dp83822_printRegs(attrs, ETHPHY_DP83822_LEDS_CFG1_REG);

    //led1
    Dp83822_printRegs(attrs, ETHPHY_DP83822_LEDCFG1_REG);

    status = MDIO_phyExtRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_LEDCFG1_REG, &phyRegVal);
    if(status == SystemP_SUCCESS)
    {
        phyRegVal &= 0xF0FF;     //0x0080;
        phyRegVal |= 0x0A00;        //1010 = MII LINK (100BT+FD)  0000 = LINK OK
        status = MDIO_phyExtRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_LEDCFG1_REG, phyRegVal);
    }
    Dp83822_printRegs(attrs, ETHPHY_DP83822_LEDCFG1_REG);


    //DebugP_log("LED1 Active High polarity  Required 0x0440\r\n");

    Dp83822_printRegs(attrs, ETHPHY_DP83822_LEDCFG2_REG);
    status = MDIO_phyExtRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_LEDCFG2_REG, &phyRegVal);

    if(status == SystemP_SUCCESS)
    {
        //phyRegVal |= ETHPHY_DP83822_OP_MODE_DECODE_RGMII_MII_SEL_MASK;
        phyRegVal = 0x0440;     //0000 0010 0010 0000 = 0x0220
        status = MDIO_phyExtRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_LEDCFG2_REG, phyRegVal);
    }
    Dp83822_printRegs(attrs, ETHPHY_DP83822_LEDCFG2_REG);



    //Auto negotiate enable configuration:
    //DebugP_log("Auto negotiate enable configuration  Required 0x01E1\r\n");
    Dp83822_printRegs(attrs, ETHPHY_DP83822_ANAR_REG);

    status = MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_ANAR_REG, &phyRegVal);
    if(status == SystemP_SUCCESS)
    {
       phyRegVal = 0x01E1;        //ETHPHY_DP83822_PHY_CONTROL_AUTOMDIX_ENABLE_MASK | ETHPHY_DP83822_PHY_CONTROL_LEDConfiguration_MASK;
       status = MDIO_phyRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_ANAR_REG, phyRegVal);
    }
    Dp83822_printRegs(attrs, ETHPHY_DP83822_ANAR_REG);

    //Enable Robust Auto MDIX
    //DebugP_log("Enable Robust Auto MDIX Required 0x0020\r\n");
    Dp83822_printRegs(attrs, ETHPHY_DP83822_GEN_CFG1_REG);

    status = MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_GEN_CFG1_REG, &phyRegVal);
    if(status == SystemP_SUCCESS)
    {
       phyRegVal = 0x0020;        //ETHPHY_DP83822_PHY_CONTROL_AUTOMDIX_ENABLE_MASK | ETHPHY_DP83822_PHY_CONTROL_LEDConfiguration_MASK;
       status = MDIO_phyRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_GEN_CFG1_REG, phyRegVal);
    }
    Dp83822_printRegs(attrs, ETHPHY_DP83822_GEN_CFG1_REG);


    //(Enable Auto negotiate and restart process)
    //DebugP_log("Enable Auto negotiate and restart process Required 0x3300\r\n");
    Dp83822_printRegs(attrs, ETHPHY_DP83822_BMCR_REG);

    status = MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_BMCR_REG, &phyRegVal);
    if(status == SystemP_SUCCESS)
    {
       phyRegVal = 0x3300;       //ETHPHY_DP83822_PHY_CONTROL_AUTOMDIX_ENABLE_MASK | ETHPHY_DP83822_PHY_CONTROL_LEDConfiguration_MASK;
       status = MDIO_phyRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_BMCR_REG, phyRegVal);
    }
    Dp83822_printRegs(attrs, ETHPHY_DP83822_BMCR_REG);

    //Odd-nibble Detection Disable Configuration
    //DebugP_log("Disable Odd-nibble detection Required 0x0102\r\n");
    Dp83822_printRegs(attrs, ETHPHY_DP83822_CR2_REG);

    status = MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_CR2_REG, &phyRegVal);
    if(status == SystemP_SUCCESS)
    {
       phyRegVal = 0x0102;       //ETHPHY_DP83822_PHY_CONTROL_AUTOMDIX_ENABLE_MASK | ETHPHY_DP83822_PHY_CONTROL_LEDConfiguration_MASK;
       status = MDIO_phyRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_CR2_REG, phyRegVal);
    }
    Dp83822_printRegs(attrs, ETHPHY_DP83822_CR2_REG);

    //Fast Link-Drop Enable
    //DebugP_log("Fast Link-Drop Enable(RX Error count) Required 0x0008\r\n");
    Dp83822_printRegs(attrs, ETHPHY_DP83822_CR3_REG);

    status = MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_CR3_REG, &phyRegVal);
    if(status == SystemP_SUCCESS)
    {
       phyRegVal = 0x0008;       //ETHPHY_DP83822_PHY_CONTROL_AUTOMDIX_ENABLE_MASK | ETHPHY_DP83822_PHY_CONTROL_LEDConfiguration_MASK;
       status = MDIO_phyRegWrite(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_CR3_REG, phyRegVal);
    }
    Dp83822_printRegs(attrs, ETHPHY_DP83822_CR3_REG);

    return SystemP_SUCCESS;

}


static int32_t ETHPHY_DP83822_RegDump(ETHPHY_Attrs *attrs)
{
   // uint32_t phyAddr = attrs->phyAddress;
    //uint16_t phyRegVal = 0u;
//return SystemP_SUCCESS;
    //DebugP_log(" %s : After Reset Phy[%d]\r\n",__func__,attrs->phyAddress);

    for(uint8_t i =0; i<= 0x1f; i++)
    {
        if((i==0x0c) ||(i==0x0e)||(i==0x1a)||(i==0x1b)||(i==0x1c)||(i==0x1d)||(i==0x1e)) {
            continue;
        }
        Dp83822_printRegs(attrs, i);
    }

    Dp83822_printRegs(attrs, 0x25);
    //Dp83822_printRegs(attrs, 0x56);
    Dp83822_printRegs(attrs, 0x456);

    Dp83822_printRegs(attrs, 0x460);

    Dp83822_printRegs(attrs, 0x467);

    Dp83822_printRegs(attrs, 0x469);

    return SystemP_SUCCESS;

}

static void Dp83822_printRegs(ETHPHY_Attrs *attrs,uint32_t RegAddr)
{
    uint32_t phyAddr = attrs->phyAddress;
    uint16_t phyRegVal = 0u;
return;
    if( (RegAddr != ETHPHY_DP83822_LEDCFG1_REG) && ( RegAddr != ETHPHY_DP83822_LEDCFG2_REG)) {
                        return;
    }
    switch(RegAddr)
    {
        case    ETHPHY_DP83822_BMCR_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_BMCR_REG, &phyRegVal);
                                    DebugP_log("PHY %u: BMCR[%#x]    = 0x%04x\n", phyAddr,ETHPHY_DP83822_BMCR_REG , phyRegVal);
                                    break;
        case    ETHPHY_DP83822_BMSR_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_BMSR_REG, &phyRegVal);
                                    DebugP_log("PHY %u: BMSR[%#x]    = 0x%04x\n", phyAddr,ETHPHY_DP83822_BMSR_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_PHYIDR1_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_PHYIDR1_REG, &phyRegVal);
                                    DebugP_log("PHY %u: PHYIDR1[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_PHYIDR1_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_PHYIDR2_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_PHYIDR2_REG, &phyRegVal);
                                    DebugP_log("PHY %u: PHYIDR2[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_PHYIDR2_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_ANAR_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_ANAR_REG, &phyRegVal);
                                    DebugP_log("PHY %u: ANAR[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_ANAR_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_ANLPAR_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_ANLPAR_REG, &phyRegVal);
                                    DebugP_log("PHY %u: ANLPAR[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_ANLPAR_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_ANER_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_ANER_REG, &phyRegVal);
                                    DebugP_log("PHY %u: ANER[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_ANER_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_ANNPTR_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_ANNPTR_REG, &phyRegVal);
                                    DebugP_log("PHY %u: ANPTR[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_ANNPTR_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_ANLNPTR_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_ANLNPTR_REG, &phyRegVal);
                                    DebugP_log("PHY %u: ANLNPTR[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_ANLNPTR_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_GEN_CFG1_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_GEN_CFG1_REG, &phyRegVal);
                                    DebugP_log("PHY %u: CR1[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_GEN_CFG1_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_CR2_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_CR2_REG, &phyRegVal);
                                    DebugP_log("PHY %u: CR2[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_CR2_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_CR3_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_CR3_REG, &phyRegVal);
                                    DebugP_log("PHY %u: CR3[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_CR3_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_REGCR_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_REGCR_REG, &phyRegVal);
                                    DebugP_log("PHY %u: REGCR[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_REGCR_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_FLDS_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_FLDS_REG, &phyRegVal);
                                    DebugP_log("PHY %u: FLDS[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_FLDS_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_PHY_STATUS_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_PHY_STATUS_REG, &phyRegVal);
                                    DebugP_log("PHY %u: PHYSTS[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_PHY_STATUS_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_PHY_CONTROL_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_PHY_CONTROL_REG, &phyRegVal);
                                    DebugP_log("PHY %u: PHYSCR[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_PHY_CONTROL_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_MISR1_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_MISR1_REG, &phyRegVal);
                                    DebugP_log("PHY %u: MISR1[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_MISR1_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_MISR2_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_MISR2_REG, &phyRegVal);
                                    DebugP_log("PHY %u: MISR2[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_MISR2_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_FCSCR_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_FCSCR_REG, &phyRegVal);
                                    DebugP_log("PHY %u: FCSCR[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_FCSCR_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_RECR_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_RECR_REG, &phyRegVal);
                                    DebugP_log("PHY %u: RECR[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_RECR_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_BISCR_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_BISCR_REG, &phyRegVal);
                                    DebugP_log("PHY %u: BISCR[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_BISCR_REG, phyRegVal);
                                    break;

        case    ETHPHY_DP83822_RCSR_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_RCSR_REG, &phyRegVal);
                                    DebugP_log("PHY %u: RCSR[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_RCSR_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_LEDS_CFG1_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_LEDS_CFG1_REG, &phyRegVal);
                                    DebugP_log("PHY %u: LEDCR[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_LEDS_CFG1_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_PHYCR:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_PHYCR, &phyRegVal);
                                    DebugP_log("PHY %u: PHYCR[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_PHYCR, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_PHYRCR_CTRL_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_PHYRCR_CTRL_REG, &phyRegVal);
                                    DebugP_log("PHY %u: PHYRCR[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_PHYRCR_CTRL_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_MLED_REG:
                                    MDIO_phyRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_MLED_REG, &phyRegVal);
                                    DebugP_log("PHY %u: MLEDCR[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_MLED_REG, phyRegVal);
                                    break;

        case    ETHPHY_DP83822_GENCFG_REG:
                                    MDIO_phyExtRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_GENCFG_REG, &phyRegVal);
                                    DebugP_log("PHY %u: GENCFG[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_GENCFG_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_LEDCFG1_REG:
                                    MDIO_phyExtRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_LEDCFG1_REG, &phyRegVal);
                                    DebugP_log("PHY %u: LEDCFG1[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_LEDCFG1_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_SOR1_REG:
                                    MDIO_phyExtRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_SOR1_REG, &phyRegVal);
                                    DebugP_log("PHY %u: SOR1[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_SOR1_REG, phyRegVal);
                                    break;
        case    ETHPHY_DP83822_LEDCFG2_REG:
                                    MDIO_phyExtRegRead(attrs->mdioBaseAddress, NULL, attrs->phyAddress, ETHPHY_DP83822_LEDCFG2_REG, &phyRegVal);
                                    DebugP_log("PHY %u: LEDCFG2[%#x] = 0x%04x\n", phyAddr,ETHPHY_DP83822_LEDCFG2_REG, phyRegVal);
                                    break;

        default:
                                    DebugP_log("PHY [%u]: RegAddress[%#x] Not Handled\r\n", phyAddr,RegAddr);

                                    break;
    }


    /*
    EnetPhy_readReg(hPhy, PHY_ANNPRR, &val);
    DebugP_log("PHY %u: ANNPRR[%#x]  = 0x%04x\n", phyAddr,PHY_ANNPRR, val);
    EnetPhy_readReg(hPhy, DP83822_CR1, &val);
    DebugP_log("PHY %u: CR1[%#x]     = 0x%04x\n", phyAddr,DP83822_CR1, val);
    EnetPhy_readReg(hPhy, PHY_GIGSR, &val);
    DebugP_log("PHY %u: STS1[%#x]    = 0x%04x\n", phyAddr,PHY_GIGSR, val);
    EnetPhy_readReg(hPhy, DP83822_PHYSTS, &val);
    DebugP_log("PHY %u: PHYSTS[%#x]    = 0x%04x\n", phyAddr,DP83822_PHYSTS, val);



    EnetPhy_readReg(hPhy, DP83822_BISCR, &val);
    DebugP_log("PHY %u: BISCR[%#x]    = 0x%04x\n", phyAddr,DP83822_BISCR, val);
    EnetPhy_readReg(hPhy, PHY_GIGESR, &val);
    DebugP_log("PHY %u: 1KSCR[%#x]   = 0x%04x\n", phyAddr,PHY_GIGESR, val);
    EnetPhy_readReg(hPhy, DP83822_RCSR, &val);
    DebugP_log("PHY %u: RCSR[%#x]   = 0x%04x\n", phyAddr,DP83822_RCSR, val);

    EnetPhy_readReg(hPhy, DP83822_PHYCR, &val);
    DebugP_log("PHY %u: PHYCR[%#x]   = 0x%04x\n", phyAddr,DP83822_PHYCR, val);
    */
}
