diff --git a/build/build_cdd_ipc_profile_app_mcu1-0_debug.sh b/build/build_cdd_ipc_profile_app_mcu1-0_debug.sh
new file mode 100755
index 0000000..fe38549
--- /dev/null
+++ b/build/build_cdd_ipc_profile_app_mcu1-0_debug.sh
@@ -0,0 +1 @@
+make cdd_ipc_profile_app CORE=mcu1_0 BUILD_OS_TYPE=tirtos BUILD_PROFILE=debug -sj
diff --git a/mcuss_demos/mcal_config/CddIpc_Demo_Cfg/output/generated/soc/j721e/mcu1_0/src/Cdd_IpcCfg.c b/mcuss_demos/mcal_config/CddIpc_Demo_Cfg/output/generated/soc/j721e/mcu1_0/src/Cdd_IpcCfg.c
index 734050f..2368166 100755
--- a/mcuss_demos/mcal_config/CddIpc_Demo_Cfg/output/generated/soc/j721e/mcu1_0/src/Cdd_IpcCfg.c
+++ b/mcuss_demos/mcal_config/CddIpc_Demo_Cfg/output/generated/soc/j721e/mcu1_0/src/Cdd_IpcCfg.c
@@ -1,64 +1,64 @@
-/*
-*
-* Copyright (c) 2019 Texas Instruments Incorporated
-*
-* All rights reserved not granted herein.
-*
-* Limited License.
-*
-* Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
-* license under copyrights and patents it now or hereafter owns or controls to make,
-* have made, use, import, offer to sell and sell ("Utilize") this software subject to the
-* terms herein.  With respect to the foregoing patent license, such license is granted
-* solely to the extent that any such patent is necessary to Utilize the software alone.
-* The patent license shall not apply to any combinations which include this software,
-* other than combinations with devices manufactured by or for TI ("TI Devices").
-* No hardware patent is licensed hereunder.
-*
-* Redistributions must preserve existing copyright notices and reproduce this license
-* (including the above copyright notice and the disclaimer and (if applicable) source
-* code license limitations below) in the documentation and/or other materials provided
-* with the distribution
-*
-* Redistribution and use in binary form, without modification, are permitted provided
-* that the following conditions are met:
-*
-* *       No reverse engineering, decompilation, or disassembly of this software is
-* permitted with respect to any software provided in binary form.
-*
-* *       any redistribution and use are licensed by TI for use only with TI Devices.
-*
-* *       Nothing shall obligate TI to provide you with source code for the software
-* licensed and provided to you in object code.
-*
-* If software source code is provided to you, modification and redistribution of the
-* source code are permitted provided that the following conditions are met:
-*
-* *       any redistribution and use of the source code, including any resulting derivative
-* works, are licensed by TI for use only with TI Devices.
-*
-* *       any redistribution and use of any object code compiled from the source code
-* and any resulting derivative works, are licensed by TI for use only with TI Devices.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of its suppliers
-*
-* may be used to endorse or promote products derived from this software without
-* specific prior written permission.
-*
-* DISCLAIMER.
-*
-* THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS
-* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-* IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
-* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
-* OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-*/
+/*
+*
+* Copyright (c) 2019 Texas Instruments Incorporated
+*
+* All rights reserved not granted herein.
+*
+* Limited License.
+*
+* Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
+* license under copyrights and patents it now or hereafter owns or controls to make,
+* have made, use, import, offer to sell and sell ("Utilize") this software subject to the
+* terms herein.  With respect to the foregoing patent license, such license is granted
+* solely to the extent that any such patent is necessary to Utilize the software alone.
+* The patent license shall not apply to any combinations which include this software,
+* other than combinations with devices manufactured by or for TI ("TI Devices").
+* No hardware patent is licensed hereunder.
+*
+* Redistributions must preserve existing copyright notices and reproduce this license
+* (including the above copyright notice and the disclaimer and (if applicable) source
+* code license limitations below) in the documentation and/or other materials provided
+* with the distribution
+*
+* Redistribution and use in binary form, without modification, are permitted provided
+* that the following conditions are met:
+*
+* *       No reverse engineering, decompilation, or disassembly of this software is
+* permitted with respect to any software provided in binary form.
+*
+* *       any redistribution and use are licensed by TI for use only with TI Devices.
+*
+* *       Nothing shall obligate TI to provide you with source code for the software
+* licensed and provided to you in object code.
+*
+* If software source code is provided to you, modification and redistribution of the
+* source code are permitted provided that the following conditions are met:
+*
+* *       any redistribution and use of the source code, including any resulting derivative
+* works, are licensed by TI for use only with TI Devices.
+*
+* *       any redistribution and use of any object code compiled from the source code
+* and any resulting derivative works, are licensed by TI for use only with TI Devices.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of its suppliers
+*
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* DISCLAIMER.
+*
+* THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS
+* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+* OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
 
 /**
  *  \file     Cdd_IpcCfg.c
@@ -209,9 +209,9 @@ CDD_IPC_CONFIG_DATA_SECTION CONST(struct Cdd_IpcChannelType_s,
     {
         .id = CddIpcConf_IpcComChanId_Cdd_IpcMcu21,
         /**< Unique identifiers for a channel */
-        .localEp = 21U,
+        .localEp = 41U,
         /**< Local End Point identifier, on which MCAL/AUTOSAR is hosted */
-        .remoteEp = 21U,
+        .remoteEp = 61U,
         /**< Remote End Point identifier, on remote cores */
         .remoteProcId = CDD_IPC_CORE_MCU2_1,
         /**< Remote Processor Identifier */
@@ -270,9 +270,9 @@ CDD_IPC_CONFIG_DATA_SECTION CONST(Cdd_IpcConfigType, CDD_IPC_CONFIG_DATA)
 
     .vertIoCfg =
     {
-        .vertIoRingAddr = (void *)0xaa000000U,
+        .vertIoRingAddr = (void *)0xB0000000U,
         /**< Defines address that shall be shared between cores */
-        .vertIoRingSize = 0x1c00000U,
+        .vertIoRingSize = 0x02000000U,
         /**< Size of the shared memory */
         .reserved = 0U,
         /**< Future use if any */
diff --git a/mcuss_demos/profiling/cddIpc/cddIpc_profile.c b/mcuss_demos/profiling/cddIpc/cddIpc_profile.c
index 139f05b..fe9f0da 100755
--- a/mcuss_demos/profiling/cddIpc/cddIpc_profile.c
+++ b/mcuss_demos/profiling/cddIpc/cddIpc_profile.c
@@ -109,6 +109,7 @@ void Cdd_IpcProfilePrepareTxBufs(void);
 void Cdd_IpcProfilePrintProfiledValues(uint32 itr, uint32 rxLength,
                                         uint64_t cumlativeRxIsrTime);
 uint32 Cdd_IpcProfileCore(uint32 commId, SemaphoreP_Handle newIpcRxMsgRcvd);
+uint32 Cdd_IpcPingRemoteCore(uint32 commId, SemaphoreP_Handle newIpcRxMsgRcvd);
 void Cdd_IpcProfileCheckCtrlMsg(uint32 *pMcu21Flag, uint32 *pMpu10Flag);
 
 /* ========================================================================== */
@@ -202,7 +203,7 @@ uint32 Cdd_IpcProfileTest(void)
     ctrlMsgFromMpu10Valid = 0U;
 
 #if (STD_ON == CDD_IPC_ANNOUNCE_API)
-    const char announceMsg[CDD_IPC_MAX_CTRL_MSG_LEN] = "ti.ipc4.ping-pong";
+    const char announceMsg[CDD_IPC_MAX_CTRL_MSG_LEN] = "ti.ipc4.cdd-ipc";
 #endif
 
     Cdd_IpcProfilePrepareTxBufs();
@@ -250,7 +251,7 @@ uint32 Cdd_IpcProfileTest(void)
                 AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME "\n");
                 AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME " Starting Profiling"
                                                             " for MCU 2 1 \n");
-                rtnVal = Cdd_IpcProfileCore(
+                rtnVal = Cdd_IpcPingRemoteCore(
                                     CddIpcConf_IpcComChanId_Cdd_IpcMcu21,
                                     Cdd_NewIpcRxMsgRcvd);
                 AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME "\n");
@@ -377,6 +378,64 @@ uint32 Cdd_IpcProfileCore(uint32 commId, SemaphoreP_Handle newIpcRxMsgRcvd)
     return rtnVal;
 }
 
+#define NUMMSGS  2   /* number of message sent per task */
+#define MSGSIZE  512
+
+uint32 Cdd_IpcPingRemoteCore(uint32 commId, SemaphoreP_Handle newIpcRxMsgRcvd)
+{
+    volatile uint64_t   preTimeStamp, postTimeStamp;
+    int32_t             i;
+    char                buf[MSGSIZE];
+    uint32 rtnVal = E_OK;
+    uint32              len;
+
+    for (i = 0; i < NUMMSGS; i++)
+    {
+        /* Send data to remote endPt: */
+        len = snprintf(buf, MSGSIZE-1, "ping %d", i);
+        buf[len++] = '\0';
+
+        rtnVal = Cdd_IpcSendMsg(commId, &buf[0U], len);
+        if (E_OK == rtnVal)
+        {
+            AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME
+            " sent %s MSG to comm[%d]\n",
+            &buf[0U], commId);
+        }
+        else
+        {
+            AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME
+            " failed to send to comm[%d]\n", commId);
+            break;
+        }
+
+        SemaphoreP_pend(Cdd_NewIpcRxMsgRcvd, SemaphoreP_WAIT_FOREVER);
+
+        rtnVal = Cdd_IpcReceiveMsg(commId, &buf[0U], &len);
+        if (E_NOT_OK == rtnVal)
+        {
+            AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME
+            " failed to receive from comm[%d]\n", commId);
+            break;
+        }
+
+        /* Make it NULL terminated string */
+        if(len >= MSGSIZE)
+        {
+            buf[MSGSIZE-1] = '\0';
+        }
+        else
+        {
+            buf[len] = '\0';
+        }
+        AppUtils_Printf(MSG_NORMAL, MSG_APP_NAME
+            " Received %s MSG from comm[%d]\n",
+            &buf[0U], commId);
+    }
+
+    return rtnVal;
+}
+
 void Cdd_IpcProfileCheckCtrlMsg(uint32 *pMcu21Flag, uint32 *pMpu10Flag)
 {
 #if (STD_ON == CDD_IPC_ANNOUNCE_API)
diff --git a/mcuss_demos/profiling/cddIpc/main_tirtos.c b/mcuss_demos/profiling/cddIpc/main_tirtos.c
index 384264a..d20bec1 100755
--- a/mcuss_demos/profiling/cddIpc/main_tirtos.c
+++ b/mcuss_demos/profiling/cddIpc/main_tirtos.c
@@ -125,6 +125,13 @@ static uint8_t Cdd_IpcProfile_TaskStack[APP_TASK_STACK] __attribute__((aligned(3
 /* ========================================================================== */
 /*                          Function Definitions                              */
 /* ========================================================================== */
+void StartupEmulatorWaitFxn (void)
+{
+    volatile uint32_t enableDebug = 0;
+    do
+    {
+    }while (enableDebug);
+}
 
 int main(void)
 {
@@ -133,6 +140,9 @@ int main(void)
     Task_Params taskParams;
     sint32 ret = CSL_PASS;
 
+    /* This is for debug purpose - see the description of function header */
+    StartupEmulatorWaitFxn();
+
 #ifdef UART_ENABLED
     AppUtils_Init();
 #endif
@@ -224,8 +234,8 @@ sint32 SetupSciServer(void)
     Sciserver_TirtosCfgPrms_t appPrms;
     Sciclient_ConfigPrms_t clientPrms;
 
-    appPrms.taskPriority[SCISERVER_TASK_USER_LO] = 1;
-    appPrms.taskPriority[SCISERVER_TASK_USER_HI] = 4;
+    appPrms.taskPriority[SCISERVER_TASK_USER_LO] = 4;
+    appPrms.taskPriority[SCISERVER_TASK_USER_HI] = 5;
 
     /* Sciclient needs to be initialized before Sciserver. Sciserver depends on
      * Sciclient API to execute message forwarding */
diff --git a/mcuss_demos/profiling/cddIpc/makefile b/mcuss_demos/profiling/cddIpc/makefile
index 03ce507..bfbe7a0 100755
--- a/mcuss_demos/profiling/cddIpc/makefile
+++ b/mcuss_demos/profiling/cddIpc/makefile
@@ -44,8 +44,8 @@ INCLUDE_EXTERNAL_INTERFACES += xdc bios
 SRCS_COMMON = main_tirtos.c cddIpc_profile.c
 EXT_LIB_LIST_COMMON += $(osal_tirtos_LIBPATH)/$(SOC)/$(ISA_EXT)/$(BUILD_PROFILE_$(CORE))/$(osal_tirtos_LIBNAME).$(LIBEXT)
 # Enable XDC build for application by providing XDC CFG File per core
-XDC_CFG_FILE_$(CORE) = $(PDK_INSTALL_PATH)/ti/build/$(SOC)/sysbios_$(ISA).cfg
-XDC_CFG_UPDATE_$(CORE)=$(MCUSW_INSTALL_PATH)/mcuss_demos/profiling/cddIpc/overrides/$(SOC)/ipc_addendum.cfg
+XDC_CFG_FILE_$(CORE) = $(MCUSW_INSTALL_PATH)/mcuss_demos/profiling/cddIpc/overrides/$(SOC)/sysbios_r5f.cfg
+#XDC_CFG_UPDATE_$(CORE)=$(MCUSW_INSTALL_PATH)/mcuss_demos/profiling/cddIpc/overrides/$(SOC)/ipc_addendum.cfg
 export XDC_CFG_UPDATE_$(CORE)
 
 # Common source files and CFLAGS across all platforms and cores
@@ -57,7 +57,7 @@ SRCS_COMMON += app_utils_cdd_ipc.c
 
 # Enable copy of vectors
 ifeq ($(ISA),$(filter $(ISA), r5f))
-  SRCS_ASM_COMMON += utilsCopyVecs2ATcm.asm
+  SRCS_ASM_COMMON += ipcCopyVecs2Exc.asm
 endif
 
 PACKAGE_SRCS_COMMON = .
@@ -72,6 +72,8 @@ endif
 # SRCS_<core/SoC/platform-name> =
 # CFLAGS_LOCAL_<core/SoC/platform-name> =
 
+EXTERNAL_LNKCMD_FILE_LOCAL = $(MCUSW_INSTALL_PATH)/mcuss_demos/profiling/cddIpc/soc/$(SOC)/$(CORE)/linker_r5_sysbios.lds
+
 # Include common make files
 ifeq ($(MAKERULEDIR), )
 #Makerule path not defined, define this and assume relative path from ROOTDIR
diff --git a/mcuss_demos/profiling/cddIpc/overrides/j721e/r5_mpu.xs b/mcuss_demos/profiling/cddIpc/overrides/j721e/r5_mpu.xs
new file mode 100755
index 0000000..d0f627f
--- /dev/null
+++ b/mcuss_demos/profiling/cddIpc/overrides/j721e/r5_mpu.xs
@@ -0,0 +1,190 @@
+/*
+ *
+ * Copyright (c) 2018 Texas Instruments Incorporated
+ *
+ * All rights reserved not granted herein.
+ *
+ * Limited License.
+ *
+ * Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
+ * license under copyrights and patents it now or hereafter owns or controls to make,
+ * have made, use, import, offer to sell and sell ("Utilize") this software subject to the
+ * terms herein.  With respect to the foregoing patent license, such license is granted
+ * solely to the extent that any such patent is necessary to Utilize the software alone.
+ * The patent license shall not apply to any combinations which include this software,
+ * other than combinations with devices manufactured by or for TI ("TI Devices").
+ * No hardware patent is licensed hereunder.
+ *
+ * Redistributions must preserve existing copyright notices and reproduce this license
+ * (including the above copyright notice and the disclaimer and (if applicable) source
+ * code license limitations below) in the documentation and/or other materials provided
+ * with the distribution
+ *
+ * Redistribution and use in binary form, without modification, are permitted provided
+ * that the following conditions are met:
+ *
+ * *       No reverse engineering, decompilation, or disassembly of this software is
+ * permitted with respect to any software provided in binary form.
+ *
+ * *       any redistribution and use are licensed by TI for use only with TI Devices.
+ *
+ * *       Nothing shall obligate TI to provide you with source code for the software
+ * licensed and provided to you in object code.
+ *
+ * If software source code is provided to you, modification and redistribution of the
+ * source code are permitted provided that the following conditions are met:
+ *
+ * *       any redistribution and use of the source code, including any resulting derivative
+ * works, are licensed by TI for use only with TI Devices.
+ *
+ * *       any redistribution and use of any object code compiled from the source code
+ * and any resulting derivative works, are licensed by TI for use only with TI Devices.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of its suppliers
+ *
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * DISCLAIMER.
+ *
+ * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * Note: Marking a region as shareable will cause the region to behave as outer shareable with write through
+ *       no write-allocate caching policy irrespective of the actual cache policy set. Therefore, only select
+ *       regions that are actually shared outside the R5 CPUSS must be marked as shared.
+ */
+
+var MPU = xdc.useModule('ti.sysbios.family.arm.MPU');
+MPU.enableMPU = true;
+MPU.enableBackgroundRegion = true;
+
+var attrs = new MPU.RegionAttrs();
+MPU.initRegionAttrsMeta(attrs);
+
+var index = 0;
+
+/* make all 4G as strongly ordered, non-cacheable */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = true;
+attrs.noExecute = true;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 0;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(index++, 0x00000000, MPU.RegionSize_4G, attrs);
+
+/* make ATCM as cacheable */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(index++, 0x00000000, MPU.RegionSize_32K, attrs);
+
+/* make ATCM as cacheable */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(index++, 0x41000000, MPU.RegionSize_32K, attrs);
+
+/* make BTCM as cacheable */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0x0;
+MPU.setRegionMeta(index++, 0x41010000, MPU.RegionSize_32K, attrs);
+
+/* MCU OCSRAM as cacheable */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(index++, 0x41C00000, MPU.RegionSize_1M, attrs);
+
+/* make all MSMC as cacheable */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(index++, 0x70000000, MPU.RegionSize_8M, attrs);
+
+/* make all 2G DDR as cacheable */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(index++, 0x80000000, MPU.RegionSize_2G, attrs);
+
+/* Note: the next 4 MPU regions start address (second argument of MPU.setRegionMeta)
+   must cover the address range of APP_LOG_MEM, TIOVX_OBJ_DESC_MEM, IPC_VRING_MEM,
+   TIOVX_LOG_RT_MEM_ADDR in system_memory_map.html and MUST be 16M aligned
+ */
+var non_cache_base_addr = 0xB0000000;
+var MB = 0x100000;
+
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = true;
+attrs.noExecute = true;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 0;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(index++, non_cache_base_addr + 0*32*MB, MPU.RegionSize_32M, attrs);
+MPU.setRegionMeta(index++, non_cache_base_addr + 1*32*MB, MPU.RegionSize_32M, attrs);
+MPU.setRegionMeta(index++, non_cache_base_addr + 2*32*MB, MPU.RegionSize_32M, attrs);
+MPU.setRegionMeta(index++, non_cache_base_addr + 3*32*MB, MPU.RegionSize_32M, attrs);
+
+/* make DDR_MCU1_0_IPC_ADDR as non-cache */
+/* Note: the next MPU regions start address (second argument of MPU.setRegionMeta)
+   must cover the address range of DDR_MCU1_0_IPC_ADDR
+   in system_memory_map.html and MUST be 1M aligned
+ */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = true;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 0;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(index++, 0xA0000000, MPU.RegionSize_1M, attrs);
+
+xdc.print("# MPU setup for " + index + " entries !!!");
diff --git a/mcuss_demos/profiling/cddIpc/overrides/j721e/sysbios_r5f.cfg b/mcuss_demos/profiling/cddIpc/overrides/j721e/sysbios_r5f.cfg
new file mode 100644
index 0000000..ff23dab
--- /dev/null
+++ b/mcuss_demos/profiling/cddIpc/overrides/j721e/sysbios_r5f.cfg
@@ -0,0 +1,162 @@
+/*
+ *
+ * Copyright (c) 2018 Texas Instruments Incorporated
+ *
+ * All rights reserved not granted herein.
+ *
+ * Limited License.
+ *
+ * Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
+ * license under copyrights and patents it now or hereafter owns or controls to make,
+ * have made, use, import, offer to sell and sell ("Utilize") this software subject to the
+ * terms herein.  With respect to the foregoing patent license, such license is granted
+ * solely to the extent that any such patent is necessary to Utilize the software alone.
+ * The patent license shall not apply to any combinations which include this software,
+ * other than combinations with devices manufactured by or for TI ("TI Devices").
+ * No hardware patent is licensed hereunder.
+ *
+ * Redistributions must preserve existing copyright notices and reproduce this license
+ * (including the above copyright notice and the disclaimer and (if applicable) source
+ * code license limitations below) in the documentation and/or other materials provided
+ * with the distribution
+ *
+ * Redistribution and use in binary form, without modification, are permitted provided
+ * that the following conditions are met:
+ *
+ * *       No reverse engineering, decompilation, or disassembly of this software is
+ * permitted with respect to any software provided in binary form.
+ *
+ * *       any redistribution and use are licensed by TI for use only with TI Devices.
+ *
+ * *       Nothing shall obligate TI to provide you with source code for the software
+ * licensed and provided to you in object code.
+ *
+ * If software source code is provided to you, modification and redistribution of the
+ * source code are permitted provided that the following conditions are met:
+ *
+ * *       any redistribution and use of the source code, including any resulting derivative
+ * works, are licensed by TI for use only with TI Devices.
+ *
+ * *       any redistribution and use of any object code compiled from the source code
+ * and any resulting derivative works, are licensed by TI for use only with TI Devices.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of its suppliers
+ *
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * DISCLAIMER.
+ *
+ * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+var Program     = xdc.useModule("xdc.cfg.Program");
+
+var Startup     = xdc.useModule("xdc.runtime.Startup");
+var SysStd      = xdc.useModule("xdc.runtime.SysStd");
+var System      = xdc.useModule("xdc.runtime.System");
+var Log         = xdc.useModule("xdc.runtime.Log");
+var Assert      = xdc.useModule("xdc.runtime.Assert");
+var Defaults    = xdc.useModule('xdc.runtime.Defaults');
+var Error       = xdc.useModule('xdc.runtime.Error');
+var Registry    = xdc.useModule('xdc.runtime.Registry');
+var Main        = xdc.useModule("xdc.runtime.Main");
+var Memory      = xdc.useModule("xdc.runtime.Memory");
+var Diags       = xdc.useModule("xdc.runtime.Diags");
+var Timestamp   = xdc.useModule("xdc.runtime.Timestamp");
+
+var BIOS        = xdc.useModule("ti.sysbios.BIOS");
+var Task        = xdc.useModule("ti.sysbios.knl.Task");
+var Idle        = xdc.useModule("ti.sysbios.knl.Idle");
+var Semaphore   = xdc.useModule("ti.sysbios.knl.Semaphore");
+var Clock       = xdc.useModule("ti.sysbios.knl.Clock");
+var Queue       = xdc.useModule('ti.sysbios.knl.Queue');
+var GateH       = xdc.useModule('xdc.runtime.knl.GateH');
+var Event       = xdc.useModule('ti.sysbios.knl.Event');
+var Hwi         = xdc.useModule('ti.sysbios.hal.Hwi');
+var Cache       = xdc.useModule('ti.sysbios.hal.Cache');
+var halCore     = xdc.useModule('ti.sysbios.hal.Core');
+var HeapMem     = xdc.useModule("ti.sysbios.heaps.HeapMem");
+var HeapBuf     = xdc.useModule("ti.sysbios.heaps.HeapBuf");
+var SyncSem     = xdc.useModule('ti.sysbios.syncs.SyncSem');
+var biosGates   = xdc.useModule('ti.sysbios.gates.GateTask');
+var GateSwi     = xdc.useModule('ti.sysbios.gates.GateSwi');
+var Load        = xdc.useModule('ti.sysbios.utils.Load');
+
+/* BIOS library type */
+BIOS.libType = BIOS.LibType_Custom;
+
+/* Clock tick in microseconds */
+Clock.tickPeriod    = 1000;
+
+/* Stack size when NULL is passed as stack during TSK create    */
+Task.defaultStackSize   = 16*1024;
+Task.enableIdleTask = true;
+Task.checkStackFlag = true;
+
+/* Idle.addFunc('&appIdleLoop'); */
+
+Hwi.checkStackFlag = false;
+
+/* malloc heap size */
+Memory.defaultHeapSize = 768*1024;
+
+/* set input Hz to all timers */
+var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+for (var i=0; i < DMTimer.numTimerDevices; i++) {
+    DMTimer.intFreqs[i].lo = 19200000;
+    DMTimer.intFreqs[i].hi = 0;
+}
+
+Load.swiEnabled   = true;
+Load.hwiEnabled   = true;
+Load.taskEnabled  = true;
+Load.updateInIdle = true;
+Load.windowInMs   = 500;
+Load.postUpdate   = '&Utils_prfLoadUpdate';
+
+/* Set the proxy for System module.
+ * This enables print statements at runtime in the application
+ */
+var SysMin = xdc.module('xdc.runtime.SysMin');
+SysMin.bufSize = 0x80000; 
+
+System.SupportProxy = SysMin;
+
+var Core         = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Core');
+Core.id = 0;
+
+var Cache = xdc.useModule('ti.sysbios.family.arm.v7r.Cache');
+Cache.enableCache = true;
+
+var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
+Hwi.vimBaseAddress = 0x40F80000;
+
+/* DMTimer #x - in general, address is 0x024x0000 where x is timer # */
+var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+Timer.checkFrequency = false;
+
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+Clock.timerId = 1;
+
+var Reset = xdc.useModule("xdc.runtime.Reset");
+Reset.fxns[Reset.fxns.length++] = "&ipcCopyVecs2Exc";
+
+/*
+ * Initialize MPU and enable it
+ *
+ * Note: MPU must be enabled and properly configured for caching to work.
+ */
+xdc.loadCapsule("r5_mpu.xs");
+
+
diff --git a/mcuss_demos/profiling/cddIpc/soc/j721e/mcu1_0/ipcCopyVecs2Exc.asm b/mcuss_demos/profiling/cddIpc/soc/j721e/mcu1_0/ipcCopyVecs2Exc.asm
new file mode 100644
index 0000000..d740900
--- /dev/null
+++ b/mcuss_demos/profiling/cddIpc/soc/j721e/mcu1_0/ipcCopyVecs2Exc.asm
@@ -0,0 +1,59 @@
+;
+;  Copyright (c) 2020, Texas Instruments Incorporated
+;  All rights reserved.
+; 
+;  Redistribution and use in source and binary forms, with or without
+;  modification, are permitted provided that the following conditions
+;  are met:
+; 
+;  *  Redistributions of source code must retain the above copyright
+;     notice, this list of conditions and the following disclaimer.
+; 
+;  *  Redistributions in binary form must reproduce the above copyright
+;     notice, this list of conditions and the following disclaimer in the
+;     documentation and/or other materials provided with the distribution.
+; 
+;  *  Neither the name of Texas Instruments Incorporated nor the names of
+;     its contributors may be used to endorse or promote products derived
+;     from this software without specific prior written permission.
+; 
+;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+;  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+;  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+;  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+;  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+;  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+;  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+;  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+;  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+;  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;
+; ======== ipcCopyVecs2Exc.asm ========
+; Copies sysbios defined vector to Exception Handler area
+;
+    .text
+    .sect   ".ipcCopyVecsToExc"
+;==============================================================================
+;   void ipcCopyVecs2Exc( void )
+;==============================================================================
+    .global ti_sysbios_family_arm_v7r_keystone3_Hwi_vectors
+
+    .global ipcCopyVecs2Exc
+ipcCopyVecs2Exc:
+        .asmfunc
+        movw    r0, ti_sysbios_family_arm_v7r_keystone3_Hwi_vectors
+        movt    r0, ti_sysbios_family_arm_v7r_keystone3_Hwi_vectors
+        mov     r1, #0                  ; Exeception Handler address
+        mov	r2, #64			; 64 bytes
+loop:
+        ldr	r3, [r0], #4
+        str     r3, [r1], #4
+        subs    r2, r2, #4
+        bgt     loop
+exit:
+        bx      lr
+        .endasmfunc
+
+        .end
diff --git a/mcuss_demos/profiling/cddIpc/soc/j721e/mcu1_0/linker_r5_sysbios.lds b/mcuss_demos/profiling/cddIpc/soc/j721e/mcu1_0/linker_r5_sysbios.lds
new file mode 100755
index 0000000..a686d55
--- /dev/null
+++ b/mcuss_demos/profiling/cddIpc/soc/j721e/mcu1_0/linker_r5_sysbios.lds
@@ -0,0 +1,198 @@
+/*----------------------------------------------------------------------------*/
+/* File: k3m4_r5f_linker.cmd                                                  */
+/* Description:																  */
+/*    Link command file for j721e M4 MCU 0 view							  */
+/*	  TI ARM Compiler version 15.12.3 LTS or later							  */
+/*                                                                            */
+/*    Platform: QT                                                            */
+/* (c) Texas Instruments 2017, All rights reserved.                           */
+/*----------------------------------------------------------------------------*/
+/*  History:															      *'
+/*    Aug 26th, 2016 Original version .......................... Loc Truong   */
+/*    Aug 01th, 2017 new TCM mem map  .......................... Loc Truong   */
+/*    Nov 07th, 2017 Changes for R5F Init Code.................. Vivek Dhande */
+/*----------------------------------------------------------------------------*/
+/* Linker Settings                                                            */
+/* Standard linker options													  */
+--retain="*(.bootCode)"
+--retain="*(.startupCode)"
+--retain="*(.startupData)"
+--retain="*(.ipcCopyVecsToExc)"
+--fill_value=0
+/*----------------------------------------------------------------------------*/
+/* Memory Map                                                                 */
+
+--define FILL_PATTERN=0xFEAA55EF
+--define FILL_LENGTH=0x100
+
+/* 1 MB of MCU Domain MSRAM is split as shown below */
+/* Size used  F0000 Number of slices 4 */
+/*                                  Rounding Offset */
+/*SBL?      Start   41C00000    245760  0   */
+/*          End     41C3C000                */
+/*MCU 10    Start   41C3C100    245760  100 */
+/*          End     41C78100                */
+/*MCU 11    Start   41C78200    245760  100 */
+/*          End     41CB4200                */
+
+MEMORY
+{
+    /* R5F_TCMA [ size 32.00 KB ] */
+    R5F_TCMA                 (    X ) : ORIGIN = 0x00000000 , LENGTH = 0x00008000
+    /* R5F_TCMB0_VECS [ size 256 B ] */
+    R5F_TCMB0_VECS           ( RWIX ) : ORIGIN = 0x41010000 , LENGTH = 0x00000100
+    /* R5F_TCMB0 [ size 31.75 KB ] */
+    R5F_TCMB0                ( RWIX ) : ORIGIN = 0x41010100 , LENGTH = 0x00007F00
+    /* DDR for MCU1_0 for Linux IPC [ size 1024.00 KB ] */
+    DDR_MCU1_0_IPC           ( RWIX ) : ORIGIN = 0xA0000000 , LENGTH = 0x00100000
+    /* DDR for MCU1_0 for Linux resource table [ size 1024 B ] */
+    DDR_MCU1_0_RESOURCE_TABLE ( RWIX ) : ORIGIN = 0xA0100000 , LENGTH = 0x00000400
+    /* DDR for MCU1_0 for code/data [ size 15.00 MB ] */
+    DDR_MCU1_0               ( RWIX ) : ORIGIN = 0xA0100400 , LENGTH = 0x00EFFC00
+    /* Memory for IPC Vring's. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
+    IPC_VRING_MEM                     : ORIGIN = 0xB0000000 , LENGTH = 0x02000000
+    /* Memory for remote core logging [ size 256.00 KB ] */
+    APP_LOG_MEM                       : ORIGIN = 0xB2000000 , LENGTH = 0x00040000
+    /* Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent [ size 63.62 MB ] */
+    TIOVX_OBJ_DESC_MEM                : ORIGIN = 0xB2040000 , LENGTH = 0x03FA0000
+    /* Memory for shared memory buffers in DDR [ size 512.00 MB ] */
+    DDR_SHARED_MEM                    : ORIGIN = 0xB8000000 , LENGTH = 0x20000000
+    /* DDR for MCU1_0 for local heap [ size  8.00 MB ] */
+    DDR_MCU1_0_LOCAL_HEAP    ( RWIX ) : ORIGIN = 0xE0000000 , LENGTH = 0x00800000
+
+}
+
+/*----------------------------------------------------------------------------*/
+/* Section Configuration                                                      */
+
+SECTIONS
+{
+    .vecs : {
+         *(.vecs)
+    } palign(8) > R5F_TCMB0_VECS
+    .vecs       : {
+        __VECS_ENTRY_POINT = .;
+    } palign(8) > R5F_TCMB0_VECS
+    xdc.meta (COPY): { *(xdc.meta) } > R5F_TCMB0
+    .init_text  : {
+                     boot.*(.text)
+                     *(.text:ti_sysbios_family_arm_MPU_*)
+                     *(.text:ti_sysbios_family_arm_v7r_Cache_*)
+                  }  > R5F_TCMB0
+    .text:xdc_runtime_Startup_reset__I     : {} palign(8) > R5F_TCMB0
+    .bootCode    	: {} palign(8) 		> R5F_TCMB0
+    .startupCode 	: {} palign(8) 		> R5F_TCMB0
+    .startupData 	: {} palign(8) 		> R5F_TCMB0, type = NOINIT
+    .ipcCopyVecsToExc : {} palign(8) > R5F_TCMB0
+
+    .text    	: {} palign(8) 		> DDR_MCU1_0
+    .const   	: {} palign(8) 		> DDR_MCU1_0
+    .cinit   	: {} palign(8) 		> DDR_MCU1_0
+    .pinit   	: {} palign(8) 		> DDR_MCU1_0
+
+    /* For NDK packet memory, we need to map this sections before .bss*/
+    .bss:NDK_MMBUFFER  (NOLOAD) {} ALIGN (128) > DDR_MCU1_0
+    .bss:NDK_PACKETMEM (NOLOAD) {} ALIGN (128) > DDR_MCU1_0
+
+    .bss     	: {} align(4)  		> DDR_MCU1_0
+    .far     	: {} align(4)  		> DDR_MCU1_0
+    .data    	: {} palign(128) 	> DDR_MCU1_0
+    .data_buffer: {} palign(128) 	> DDR_MCU1_0
+	.sysmem  	: {} 				> DDR_MCU1_0
+	.stack  	: {} align(4)		> DDR_MCU1_0  (HIGH) fill=FILL_PATTERN
+
+    .bss.devgroup* : {} align(4)       > DDR_MCU1_0
+    .const.devgroup*: {} align(4)      > DDR_MCU1_0
+    .data_user      : {} align(4)      > DDR_MCU1_0
+    .boardcfg_data  : {} align(4)      > DDR_MCU1_0
+    /* USB or any other LLD buffer for benchmarking */
+    .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR_MCU1_0
+
+    /* Additional sections settings     */
+    McalTextSection : fill=FILL_PATTERN, align=4, load > DDR_MCU1_0
+    {
+        .=align(4);
+        __linker_cdd_ipc_text_start = .;
+        . += FILL_LENGTH;
+        *(CDD_IPC_TEXT_SECTION)
+        *(CDD_IPC_ISR_TEXT_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_cdd_ipc_text_end = .;
+
+    }
+    McalConstSection : fill=FILL_PATTERN, align=4, load > DDR_MCU1_0
+    {
+        .=align(4);
+        __linker_cdd_ipc_const_start = .;
+        . += FILL_LENGTH;
+        *(CDD_IPC_CONST_32_SECTION)
+        *(CDD_IPC_CONFIG_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_cdd_ipc_const_end = .;
+    }
+
+    McalInitSection : fill=FILL_PATTERN, align=4, load > DDR_MCU1_0
+    {
+        .=align(4);
+        __linker_cdd_ipc_init_start = .;
+        . += FILL_LENGTH;
+        *(CDD_IPC_DATA_INIT_UNSPECIFIED_SECTION)
+        *(CDD_IPC_DATA_INIT_32_SECTION)
+        *(CDD_IPC_DATA_INIT_8_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_cdd_ipc_init_end = .;
+    }
+    McalNoInitSection : fill=FILL_PATTERN, align=4, load > DDR_MCU1_0, type = NOINIT
+    {
+        __linker_cdd_ipc_no_init_start = .;
+        . += FILL_LENGTH;
+        *(CDD_IPC_DATA_NO_INIT_UNSPECIFIED_SECTION)
+        *(CDD_IPC_DATA_NO_INIT_8_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_cdd_ipc_no_init_end = .;
+
+    }
+    /* Example Utility specifics */
+    VariablesAlignedNoInitSection : align=8, load > DDR_MCU1_0, type = NOINIT
+    {
+        .=align(8);
+        __linker_cdd_ipc_no_init_align_8b_start = .;
+        . += FILL_LENGTH;
+        *(CDD_IPC_DATA_NO_INIT_8_ALIGN_8B_SECTION)
+        .=align(8);
+        . += FILL_LENGTH;
+        __linker_cdd_ipc_no_init_align_8b_end = .;
+    }
+    /* Example Utility specifics */
+    UtilityNoInitSection : align=4, load > DDR_MCU1_0, type = NOINIT
+    {
+        .=align(4);
+        __linker_utility_no_init_start = .;
+        . += FILL_LENGTH;
+        *(EG_TEST_RESULT_32_SECTION)
+        .=align(4);
+        . += FILL_LENGTH;
+        __linker_utility_no_init_end = .;
+    }
+    SciClientBoardCfgSection : align=128, load > DDR_MCU1_0, type = NOINIT
+    {
+        .=align(128);
+        __linker_boardcfg_data_start = .;
+        . += FILL_LENGTH;
+        *(.boardcfg_data)
+        .=align(128);
+        . += FILL_LENGTH;
+        __linker_boardcfg_data_end = .;
+    }
+
+}  /* end of SECTIONS */
+
+/*----------------------------------------------------------------------------*/
+/* Misc linker settings                                                       */
+
+
+/*-------------------------------- END ---------------------------------------*/
