------Layer #(Type) [Exec ID , Data ID] --[Ni x inW x inH] => [No x outW x outH] [Ni/G] [dataflowType] [preFetch, preFetchAlign, firstTransferRemainder, procSize, inPlaneSize] [dmaFreq] [dmaFreqWt] [kernelFreq] [In Data Ids] -----
------  4(TIDL_DataConvertLayer) [1, 4] --[3 x 800 x  800] => [3 x 800 x  800] *** [3] ***[ COL] ***[0, 0, 0, 214400, 2560000]**** [36], [0],[36] -[0 ]---
  IN: DDR, DMA, 271000(2560000), 271000(2560000),    3(    3), 753400(7681024),   0,        0 ||||  L2, DMA,  68b00(428800),  68b00(428800),    1(    1),  68b00( 428800),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  9cd63(642403),  9cd63(642403),    3(    3), 1d6900(1927424), 322,       5e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  5(TIDL_ConvolutionLayer) [2, 5] --[3 x 800 x  800] => [32 x 400 x  400] *** [3] ***[ROW_C] ***[802, 802, 802, 64080, 641602]**** [10], [1],[10] -[4 ]---
  IN:MSMC, DMA,  9cd63(642403),  9cd63(642403),    3(    3), 1d6900(1927424),   0,       5e ||||  L2, DMA,  20000(131072),  20000(131072),    3(    3),  60000( 393216),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  275c0(161216),  275b3(161203),   20(   32), 4eb880(5159040), 192,   1d696e 
  WT:DDR_PERSIST, DMA,     1c(    28),     1c(    28),   20(   32),    380(    896),   0,        0 ||||  L2, DMA,     1c(    28),     1c(    28),   20(   32),    380(    896),   0,    60000 
 STG:MSMC, DMA_ONCE,     1c(    28),     1c(    28),   20(   32),    380(    896),   0,   7b9880 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  6(TIDL_BatchNormLayer) [3, 6] --[32 x 400 x  400] => [32 x 400 x  400] *** [32] ***[ COL] ***[0, 0, 0, 160400, 160400]**** [32], [0],[32] -[5 ]---
  IN:MSMC, DMA,  275c0(161216),  275b3(161203),   20(   32), 4eb880(5159040), 192,   1d696e ||||  L2, DMA,  27743(161603),  27743(161603),    2(    2),  4ef00( 323328),   0,        0 
 OUT:MSMC, CPU,  272c0(160448),  27290(160400),    2(    2),  4e580( 320896),   0,        0 |||| DDR, DMA,  275b3(161203),  275b3(161203),   20(   32), 4eba80(5159552), 192,       6e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  7(TIDL_EltWiseLayer) [4, 7] --[64 x 400 x  400] => [32 x 400 x  400] *** [64] ***[ COL] ***[0, 0, 0, 80200, 160400]**** [64], [0],[64] -[5 6 ]---
  IN:MSMC, DMA,  275c0(161216),  275b3(161203),   20(   32), 4eb880(5159040), 192,   1d696e ||||  L2, DMA,  13948( 80200),  13948( 80200),    2(    2),  4e580( 320896),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  275c0(161216),  275b3(161203),   20(   32), 4eb880(5159040), 192,       6e 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  8(TIDL_ConvolutionLayer) [5, 8] --[32 x 400 x  400] => [64 x 200 x  200] *** [32] ***[ROW_L] ***[402, 402, 402, 4010, 160802]**** [40], [1],[40] -[7 ]---
  IN:MSMC, DMA,  275c0(161216),  275b3(161203),   20(   32), 4eb880(5159040),   0,       6e ||||  L2, DMA,   2140(  8512),   2140(  8512),   20(   32),  67b00( 424704),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   9ec0( 40640),   9e9b( 40603),   40(   64), 27b080(2601088),  ca,   4eb8b6 
  WT:DDR_PERSIST, DMA,    121(   289),    121(   289),   40(   64),   4880(  18560),   0,      380 ||||  L2, DMA,    140(   320),    121(   289),   40(   64),   5000(  20480),   0,    67b00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  9(TIDL_BatchNormLayer) [6, 9] --[64 x 200 x  200] => [64 x 200 x  200] *** [64] ***[ COL] ***[0, 0, 0, 40200, 40200]**** [16], [0],[16] -[8 ]---
  IN:MSMC, DMA,   9ec0( 40640),   9e9b( 40603),   40(   64), 27b080(2601088),  ca,   4eb8b6 ||||  L2, DMA,   9f63( 40803),   9f63( 40803),    8(    8),  4fb80( 326528),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   9ec0( 40640),   9e9b( 40603),   40(   64), 27b080(2601088),  ca,       36 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  10(TIDL_EltWiseLayer) [7, 10] --[128 x 200 x  200] => [64 x 200 x  200] *** [128] ***[ COL] ***[0, 0, 0, 40200, 40200]**** [32], [0],[32] -[8 9 ]---
  IN:MSMC, DMA,   9ec0( 40640),   9e9b( 40603),   40(   64), 27b080(2601088),  ca,   4eb8b6 ||||  L2, DMA,   9f63( 40803),   9f63( 40803),    4(    4),  4fb80( 326528),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   9ec0( 40640),   9e9b( 40603),   40(   64), 27b080(2601088),  ca,       36 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  11(TIDL_ConvolutionLayer) [8, 11] --[64 x 200 x  200] => [64 x 200 x  200] *** [64] ***[ROW_L] ***[0, 0, 0, 3136, 40200]**** [13], [1],[13] -[10 ]---
  IN:MSMC, DMA,   9ec0( 40640),   9e9b( 40603),   40(   64), 27b080(2601088),  ca,       36 ||||  L2, DMA,   18c0(  6336),   18c0(  6336),   40(   64),  6b680( 439936),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   9ec0( 40640),   9e9b( 40603),   40(   64), 27b080(2601088),  ca,       36 
  WT:DDR_PERSIST, DMA,     41(    65),     41(    65),   40(   64),   1080(   4224),   0,     4c00 ||||  L2, DMA,     c0(   192),     41(    65),   40(   64),   3000(  12288),   0,    6b680 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  12(TIDL_BatchNormLayer) [9, 12] --[64 x 200 x  200] => [64 x 200 x  200] *** [64] ***[ COL] ***[0, 0, 0, 40200, 40200]**** [16], [0],[16] -[11 ]---
  IN:MSMC, DMA,   9ec0( 40640),   9e9b( 40603),   40(   64), 27b080(2601088),  ca,       36 ||||  L2, DMA,   9f63( 40803),   9f63( 40803),    8(    8),  4fb80( 326528),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   9ec0( 40640),   9e9b( 40603),   40(   64), 27b080(2601088),  ca,   27b0b6 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  13(TIDL_EltWiseLayer) [10, 13] --[128 x 200 x  200] => [64 x 200 x  200] *** [128] ***[ COL] ***[0, 0, 0, 40200, 40200]**** [32], [0],[32] -[11 12 ]---
  IN:MSMC, DMA,   9ec0( 40640),   9e9b( 40603),   40(   64), 27b080(2601088),  ca,       36 ||||  L2, DMA,   9f63( 40803),   9f63( 40803),    4(    4),  4fb80( 326528),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   9e9b( 40603),   9e9b( 40603),   40(   64), 27a780(2598784),  ca,   4f6136 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  14(TIDL_SliceLayer) [11, 14] --[64 x 200 x  200] => [32 x 200 x  200] *** [64] ***[ COL] ***[0, 0, 0, 40200, 40200]**** [16], [0],[16] -[13 ]---
  IN:MSMC, DMA,   9e9b( 40603),   9e9b( 40603),   40(   64), 27a780(2598784),  ca,   4f6136 ||||  L2, DMA,   9f63( 40803),   9f63( 40803),    8(    8),  4fb80( 326528),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   9e9b( 40603),   9e9b( 40603),   20(   32), 27a780(2598784),  ca,   4f6136 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  15(TIDL_SliceLayer) [12, 15] --[64 x 200 x  200] => [32 x 200 x  200] *** [64] ***[ COL] ***[0, 0, 0, 40200, 40200]**** [16], [0],[16] -[13 ]---
  IN:MSMC, DMA,   9e9b( 40603),   9e9b( 40603),   40(   64), 27a780(2598784),  ca,   4f6136 ||||  L2, DMA,   9f63( 40803),   9f63( 40803),    8(    8),  4fb80( 326528),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   9ec0( 40640),   9e9b( 40603),   20(   32), 13d880(1300608),  ca,       36 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  16(TIDL_ConvolutionLayer) [13, 16] --[32 x 200 x  200] => [32 x 200 x  200] *** [32] ***[ROW_L] ***[404, 448, 448, 6208, 40603]**** [7], [1],[7] -[15 ]---
  IN:MSMC, DMA,   9ec0( 40640),   9e9b( 40603),   20(   32), 13d880(1300608),   0,       36 ||||  L2, DMA,   3240( 12864),   3240( 12864),   20(   32),  6c180( 442752),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   9ec0( 40640),   9e9b( 40603),   20(   32), 13d880(1300608),  ca,   13d8b6 
  WT:DDR_PERSIST, DMA,    121(   289),    121(   289),   20(   32),   2480(   9344),   0,     5c80 ||||  L2, DMA,    140(   320),    121(   289),   20(   32),   2800(  10240),   0,    6c180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  17(TIDL_BatchNormLayer) [14, 17] --[32 x 200 x  200] => [32 x 200 x  200] *** [32] ***[ COL] ***[0, 0, 0, 40200, 40200]**** [8], [0],[8] -[16 ]---
  IN:MSMC, DMA,   9ec0( 40640),   9e9b( 40603),   20(   32), 13d880(1300608),  ca,   13d8b6 ||||  L2, DMA,   9f63( 40803),   9f63( 40803),    8(    8),  4fb80( 326528),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   9ec0( 40640),   9e9b( 40603),   20(   32), 13d880(1300608),  ca,   27b136 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  18(TIDL_EltWiseLayer) [15, 18] --[64 x 200 x  200] => [32 x 200 x  200] *** [64] ***[ COL] ***[0, 0, 0, 40200, 40200]**** [16], [0],[16] -[16 17 ]---
  IN:MSMC, DMA,   9ec0( 40640),   9e9b( 40603),   20(   32), 13d880(1300608),  ca,   13d8b6 ||||  L2, DMA,   9f63( 40803),   9f63( 40803),    4(    4),  4fb80( 326528),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   9ec0( 40640),   9e9b( 40603),   20(   32), 13d880(1300608),  ca,   13d8b6 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  19(TIDL_ConvolutionLayer) [16, 19] --[32 x 200 x  200] => [32 x 200 x  200] *** [32] ***[ROW_L] ***[404, 448, 448, 6208, 40603]**** [7], [1],[7] -[18 ]---
  IN:MSMC, DMA,   9ec0( 40640),   9e9b( 40603),   20(   32), 13d880(1300608),   0,   13d8b6 ||||  L2, DMA,   3240( 12864),   3240( 12864),   20(   32),  6c180( 442752),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   9ec0( 40640),   9e9b( 40603),   20(   32), 13d880(1300608),  ca,   13d8b6 
  WT:DDR_PERSIST, DMA,    121(   289),    121(   289),   20(   32),   2480(   9344),   0,     8100 ||||  L2, DMA,    140(   320),    121(   289),   20(   32),   2800(  10240),   0,    6c180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  20(TIDL_BatchNormLayer) [17, 20] --[32 x 200 x  200] => [32 x 200 x  200] *** [32] ***[ COL] ***[0, 0, 0, 40200, 40200]**** [8], [0],[8] -[19 ]---
  IN:MSMC, DMA,   9ec0( 40640),   9e9b( 40603),   20(   32), 13d880(1300608),  ca,   13d8b6 ||||  L2, DMA,   9f63( 40803),   9f63( 40803),    8(    8),  4fb80( 326528),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   9ec0( 40640),   9e9b( 40603),   20(   32), 13d880(1300608),  ca,   27b136 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  21(TIDL_EltWiseLayer) [18, 21] --[64 x 200 x  200] => [32 x 200 x  200] *** [64] ***[ COL] ***[0, 0, 0, 40200, 40200]**** [16], [0],[16] -[19 20 ]---
  IN:MSMC, DMA,   9ec0( 40640),   9e9b( 40603),   20(   32), 13d880(1300608),  ca,   13d8b6 ||||  L2, DMA,   9f63( 40803),   9f63( 40803),    4(    4),  4fb80( 326528),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   9ec0( 40640),   9e9b( 40603),   20(   32), 13d880(1300608),  ca,   13d8b6 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  22(TIDL_EltWiseLayer) [19, 22] --[64 x 200 x  200] => [32 x 200 x  200] *** [64] ***[ COL] ***[0, 0, 0, 40200, 40200]**** [16], [0],[16] -[15 21 ]---
  IN:MSMC, DMA,   9ec0( 40640),   9e9b( 40603),   20(   32), 13d880(1300608),  ca,       36 ||||  L2, DMA,   9f63( 40803),   9f63( 40803),    4(    4),  4fb80( 326528),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   9ec0( 40640),   9e9b( 40603),   20(   32), 13d880(1300608),  ca,   27b136 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  23(TIDL_ConcatLayer) [20, 23] --[96 x 200 x  200] => [96 x 200 x  200] *** [96] ***[ COL] ***[0, 0, 0, 40200, 40200]**** [24], [0],[24] -[14 15 22 ]---
  IN:MSMC, DMA,   9e9b( 40603),   9e9b( 40603),   20(   32), 27a780(2598784),  ca,   4f6136 ||||  L2, DMA,   9f63( 40803),   9f63( 40803),    8(    8),  4fb80( 326528),   0,        0 
 OUT:MSMC, CPU,   9d40( 40256),   9d08( 40200),    8(    8),  4ea00( 322048),   0,   13d880 |||| DDR, DMA,   9e9b( 40603),   9e9b( 40603),   60(   96), 3b7e80(3899008),  ca,       36 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  24(TIDL_ConvolutionLayer) [21, 24] --[96 x 200 x  200] => [64 x 200 x  200] *** [96] ***[ROW_L] ***[0, 0, 0, 2048, 40200]**** [20], [1],[20] -[23 ]---
  IN: DDR, DMA,   9e9b( 40603),   9e9b( 40603),   60(   96), 3b7e80(3899008),  ca,       36 ||||  L2, DMA,   1040(  4160),   1040(  4160),   60(   96),  6a800( 436224),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   9ec0( 40640),   9e9b( 40603),   40(   64), 27b080(2601088),  ca,       36 
  WT:DDR_PERSIST, DMA,     61(    97),     61(    97),   40(   64),   1880(   6272),   0,     a580 ||||  L2, DMA,     c0(   192),     61(    97),   40(   64),   3000(  12288),   0,    6a800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  25(TIDL_BatchNormLayer) [22, 25] --[64 x 200 x  200] => [64 x 200 x  200] *** [64] ***[ COL] ***[0, 0, 0, 40200, 40200]**** [16], [0],[16] -[24 ]---
  IN:MSMC, DMA,   9ec0( 40640),   9e9b( 40603),   40(   64), 27b080(2601088),  ca,       36 ||||  L2, DMA,   9f63( 40803),   9f63( 40803),    8(    8),  4fb80( 326528),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   9ec0( 40640),   9e9b( 40603),   40(   64), 27b080(2601088),  ca,   27b0b6 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  26(TIDL_EltWiseLayer) [23, 26] --[128 x 200 x  200] => [64 x 200 x  200] *** [128] ***[ COL] ***[0, 0, 0, 40200, 40200]**** [32], [0],[32] -[24 25 ]---
  IN:MSMC, DMA,   9ec0( 40640),   9e9b( 40603),   40(   64), 27b080(2601088),  ca,       36 ||||  L2, DMA,   9f63( 40803),   9f63( 40803),    4(    4),  4fb80( 326528),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   9ec0( 40640),   9e9b( 40603),   40(   64), 27b080(2601088),  ca,       36 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  27(TIDL_ConvolutionLayer) [24, 27] --[64 x 200 x  200] => [128 x 100 x  100] *** [64] ***[ROW_L] ***[202, 202, 202, 2412, 40402]**** [17], [1],[17] -[26 ]---
  IN:MSMC, DMA,   9ec0( 40640),   9e9b( 40603),   40(   64), 27b080(2601088),   0,       36 ||||  L2, DMA,   13c0(  5056),   13c0(  5056),   40(   64),  57d80( 359808),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   27b09a 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   80(  128),  12080(  73856),   0,     be00 ||||  L2, DMA,    2c0(   704),    241(   577),   80(  128),  16000(  90112),   0,    57d80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  28(TIDL_BatchNormLayer) [25, 28] --[128 x 100 x  100] => [128 x 100 x  100] *** [128] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [8], [0],[8] -[27 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   27b09a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   20(   32),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,       1a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  29(TIDL_EltWiseLayer) [26, 29] --[256 x 100 x  100] => [128 x 100 x  100] *** [256] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [16], [0],[16] -[27 28 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   27b09a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   10(   16),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,       1a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  30(TIDL_ConvolutionLayer) [27, 30] --[128 x 100 x  100] => [128 x 100 x  100] *** [128] ***[ROW_L] ***[0, 0, 0, 1600, 10100]**** [7], [1],[7] -[29 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,       1a ||||  L2, DMA,    cc0(  3264),    cc0(  3264),   80(  128),  67f00( 425728),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   14201a 
  WT:DDR_PERSIST, DMA,     81(   129),     81(   129),   80(  128),   4080(  16512),   0,    1de80 ||||  L2, DMA,     c0(   192),     81(   129),   80(  128),   6000(  24576),   0,    67f00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  31(TIDL_BatchNormLayer) [28, 31] --[128 x 100 x  100] => [128 x 100 x  100] *** [128] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [8], [0],[8] -[30 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   14201a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   20(   32),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   28409a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  32(TIDL_EltWiseLayer) [29, 32] --[256 x 100 x  100] => [128 x 100 x  100] *** [256] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [16], [0],[16] -[30 31 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   14201a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   10(   16),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   283f( 10303),   283f( 10303),   80(  128), 142000(1318912),  66,       1a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  33(TIDL_SliceLayer) [30, 33] --[128 x 100 x  100] => [64 x 100 x  100] *** [128] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [8], [0],[8] -[32 ]---
  IN:MSMC, DMA,   283f( 10303),   283f( 10303),   80(  128), 142000(1318912),  66,       1a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   20(   32),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   283f( 10303),   283f( 10303),   40(   64), 142000(1318912),  66,       1a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  34(TIDL_SliceLayer) [31, 34] --[128 x 100 x  100] => [64 x 100 x  100] *** [128] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [8], [0],[8] -[32 ]---
  IN:MSMC, DMA,   283f( 10303),   283f( 10303),   80(  128), 142000(1318912),  66,       1a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   20(   32),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   14201a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  35(TIDL_ConvolutionLayer) [32, 35] --[64 x 100 x  100] => [64 x 100 x  100] *** [64] ***[ROW_L] ***[204, 256, 256, 3008, 10303]**** [4], [1],[4] -[34 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),   0,   14201a ||||  L2, DMA,   18c0(  6336),   18c0(  6336),   40(   64),  64780( 411520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   1e309a 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   40(   64),   9080(  36992),   0,    21f00 ||||  L2, DMA,    2c0(   704),    241(   577),   40(   64),   b000(  45056),   0,    64780 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  36(TIDL_BatchNormLayer) [33, 36] --[64 x 100 x  100] => [64 x 100 x  100] *** [64] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [4], [0],[4] -[35 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   1e309a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   20(   32),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   28411a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  37(TIDL_EltWiseLayer) [34, 37] --[128 x 100 x  100] => [64 x 100 x  100] *** [128] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [8], [0],[8] -[35 36 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   1e309a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   10(   16),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   1e309a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  38(TIDL_ConvolutionLayer) [35, 38] --[64 x 100 x  100] => [64 x 100 x  100] *** [64] ***[ROW_L] ***[204, 256, 256, 3008, 10303]**** [4], [1],[4] -[37 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),   0,   1e309a ||||  L2, DMA,   18c0(  6336),   18c0(  6336),   40(   64),  64780( 411520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   1e309a 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   40(   64),   9080(  36992),   0,    2af80 ||||  L2, DMA,    2c0(   704),    241(   577),   40(   64),   b000(  45056),   0,    64780 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  39(TIDL_BatchNormLayer) [36, 39] --[64 x 100 x  100] => [64 x 100 x  100] *** [64] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [4], [0],[4] -[38 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   1e309a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   20(   32),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   28411a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  40(TIDL_EltWiseLayer) [37, 40] --[128 x 100 x  100] => [64 x 100 x  100] *** [128] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [8], [0],[8] -[38 39 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   1e309a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   10(   16),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   28411a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  41(TIDL_EltWiseLayer) [38, 41] --[128 x 100 x  100] => [64 x 100 x  100] *** [128] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [8], [0],[8] -[34 40 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   14201a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   10(   16),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   1e309a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  42(TIDL_ConvolutionLayer) [39, 42] --[64 x 100 x  100] => [64 x 100 x  100] *** [64] ***[ROW_L] ***[204, 256, 256, 3008, 10303]**** [4], [1],[4] -[41 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),   0,   1e309a ||||  L2, DMA,   18c0(  6336),   18c0(  6336),   40(   64),  64780( 411520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   28411a 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   40(   64),   9080(  36992),   0,    34000 ||||  L2, DMA,    2c0(   704),    241(   577),   40(   64),   b000(  45056),   0,    64780 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  43(TIDL_BatchNormLayer) [40, 43] --[64 x 100 x  100] => [64 x 100 x  100] *** [64] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [4], [0],[4] -[42 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   28411a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   20(   32),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   32519a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  44(TIDL_EltWiseLayer) [41, 44] --[128 x 100 x  100] => [64 x 100 x  100] *** [128] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [8], [0],[8] -[42 43 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   28411a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   10(   16),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   28411a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  45(TIDL_ConvolutionLayer) [42, 45] --[64 x 100 x  100] => [64 x 100 x  100] *** [64] ***[ROW_L] ***[204, 256, 256, 3008, 10303]**** [4], [1],[4] -[44 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),   0,   28411a ||||  L2, DMA,   18c0(  6336),   18c0(  6336),   40(   64),  64780( 411520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   28411a 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   40(   64),   9080(  36992),   0,    3d080 ||||  L2, DMA,    2c0(   704),    241(   577),   40(   64),   b000(  45056),   0,    64780 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  46(TIDL_BatchNormLayer) [43, 46] --[64 x 100 x  100] => [64 x 100 x  100] *** [64] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [4], [0],[4] -[45 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   28411a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   20(   32),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   32519a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  47(TIDL_EltWiseLayer) [44, 47] --[128 x 100 x  100] => [64 x 100 x  100] *** [128] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [8], [0],[8] -[45 46 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   28411a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   10(   16),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   32519a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  48(TIDL_EltWiseLayer) [45, 48] --[128 x 100 x  100] => [64 x 100 x  100] *** [128] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [8], [0],[8] -[41 47 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   1e309a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   10(   16),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   28411a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  49(TIDL_ConcatLayer) [46, 49] --[256 x 100 x  100] => [256 x 100 x  100] *** [256] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [16], [0],[16] -[33 34 41 48 ]---
  IN:MSMC, DMA,   283f( 10303),   283f( 10303),   40(   64), 142000(1318912),  66,       1a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   20(   32),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),  100(  256), 284080(2637952),  66,   32519a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  50(TIDL_ConvolutionLayer) [47, 50] --[256 x 100 x  100] => [128 x 100 x  100] *** [256] ***[ROW_L] ***[0, 0, 0, 704, 10100]**** [15], [1],[15] -[49 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),  100(  256), 284080(2637952),  66,   32519a ||||  L2, DMA,    5c0(  1472),    5c0(  1472),  100(  256),  5e380( 385920),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,       1a 
  WT:DDR_PERSIST, DMA,    101(   257),    101(   257),   80(  128),   8080(  32896),   0,    46100 ||||  L2, DMA,    140(   320),    101(   257),   80(  128),   a000(  40960),   0,    5e380 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  51(TIDL_BatchNormLayer) [48, 51] --[128 x 100 x  100] => [128 x 100 x  100] *** [128] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [8], [0],[8] -[50 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,       1a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   20(   32),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   14209a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  52(TIDL_EltWiseLayer) [49, 52] --[256 x 100 x  100] => [128 x 100 x  100] *** [256] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [16], [0],[16] -[50 51 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,       1a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   10(   16),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,       1a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  53(TIDL_ConvolutionLayer) [50, 53] --[128 x 100 x  100] => [256 x 50 x  50] *** [128] ***[ROW_L] ***[102, 102, 102, 404, 10202]**** [25], [1],[25] -[52 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),   0,       1a ||||  L2, DMA,    3c0(   960),    3c0(   960),   80(  128),  20480( 132224),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   1420cc 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),  100(  256),  48100( 295168),   0,    4e180 ||||  L2, DMA,    4c0(  1216),    481(  1153),  100(  256),  4c000( 311296),   0,    20480 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  54(TIDL_BatchNormLayer) [51, 54] --[256 x 50 x  50] => [256 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[53 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   1420cc ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   1ee14c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  55(TIDL_EltWiseLayer) [52, 55] --[512 x 50 x  50] => [256 x 50 x  50] *** [512] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [8], [0],[8] -[53 54 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   1420cc ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   40(   64),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   29a1cc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  56(TIDL_ConvolutionLayer) [53, 56] --[256 x 50 x  50] => [256 x 50 x  50] *** [256] ***[ROW_L] ***[0, 0, 0, 640, 2550]**** [4], [1],[4] -[55 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   29a1cc ||||  L2, DMA,    540(  1344),    540(  1344),  100(  256),  54500( 345344),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   1e7e4c 
  WT:DDR_PERSIST, DMA,    101(   257),    101(   257),  100(  256),  10100(  65792),   0,    96280 ||||  L2, DMA,    140(   320),    101(   257),  100(  256),  14000(  81920),   0,    54500 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  57(TIDL_BatchNormLayer) [54, 57] --[256 x 50 x  50] => [256 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[56 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   1e7e4c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   293ecc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  58(TIDL_EltWiseLayer) [55, 58] --[512 x 50 x  50] => [256 x 50 x  50] *** [512] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [8], [0],[8] -[56 57 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   1e7e4c ||||  L2, DMA,    a8f(  2703),    a8f(  2703),   40(   64),  54780( 345984),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    a5d(  2653),    a5d(  2653),  100(  256),  a5d80( 679296),  34,   1420cc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  59(TIDL_SliceLayer) [56, 59] --[256 x 50 x  50] => [128 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[58 ]---
  IN:MSMC, DMA,    a5d(  2653),    a5d(  2653),  100(  256),  a5d80( 679296),  34,   1420cc ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    a5d(  2653),    a5d(  2653),   80(  128),  a5d80( 679296),  34,   1420cc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  60(TIDL_SliceLayer) [57, 60] --[256 x 50 x  50] => [128 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[58 ]---
  IN:MSMC, DMA,    a5d(  2653),    a5d(  2653),  100(  256),  a5d80( 679296),  34,   1420cc ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   1e7e4c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  61(TIDL_ConvolutionLayer) [58, 61] --[128 x 50 x  50] => [128 x 50 x  50] *** [128] ***[ROW_L] ***[104, 128, 128, 1024, 2653]**** [3], [1],[3] -[60 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),   0,   1e7e4c ||||  L2, DMA,    8c0(  2240),    8c0(  2240),   80(  128),  46400( 287744),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   23decc 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,    a6380 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    46400 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  62(TIDL_BatchNormLayer) [59, 62] --[128 x 50 x  50] => [128 x 50 x  50] *** [128] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [1], [0],[1] -[61 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   23decc ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   293f4c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  63(TIDL_EltWiseLayer) [60, 63] --[256 x 50 x  50] => [128 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[61 62 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   23decc ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   40(   64),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   23decc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  64(TIDL_ConvolutionLayer) [61, 64] --[128 x 50 x  50] => [128 x 50 x  50] *** [128] ***[ROW_L] ***[104, 128, 128, 1024, 2653]**** [3], [1],[3] -[63 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),   0,   23decc ||||  L2, DMA,    8c0(  2240),    8c0(  2240),   80(  128),  46400( 287744),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   23decc 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,    ca400 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    46400 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  65(TIDL_BatchNormLayer) [62, 65] --[128 x 50 x  50] => [128 x 50 x  50] *** [128] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [1], [0],[1] -[64 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   23decc ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   293f4c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  66(TIDL_EltWiseLayer) [63, 66] --[256 x 50 x  50] => [128 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[64 65 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   23decc ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   40(   64),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   293f4c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  67(TIDL_EltWiseLayer) [64, 67] --[256 x 50 x  50] => [128 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[60 66 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   1e7e4c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   40(   64),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   23decc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  68(TIDL_ConvolutionLayer) [65, 68] --[128 x 50 x  50] => [128 x 50 x  50] *** [128] ***[ROW_L] ***[104, 128, 128, 1024, 2653]**** [3], [1],[3] -[67 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),   0,   23decc ||||  L2, DMA,    8c0(  2240),    8c0(  2240),   80(  128),  46400( 287744),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   293f4c 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,    ee480 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    46400 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  69(TIDL_BatchNormLayer) [66, 69] --[128 x 50 x  50] => [128 x 50 x  50] *** [128] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [1], [0],[1] -[68 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   293f4c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   2e9fcc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  70(TIDL_EltWiseLayer) [67, 70] --[256 x 50 x  50] => [128 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[68 69 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   293f4c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   40(   64),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   293f4c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  71(TIDL_ConvolutionLayer) [68, 71] --[128 x 50 x  50] => [128 x 50 x  50] *** [128] ***[ROW_L] ***[104, 128, 128, 1024, 2653]**** [3], [1],[3] -[70 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),   0,   293f4c ||||  L2, DMA,    8c0(  2240),    8c0(  2240),   80(  128),  46400( 287744),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   293f4c 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,   112500 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    46400 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  72(TIDL_BatchNormLayer) [69, 72] --[128 x 50 x  50] => [128 x 50 x  50] *** [128] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [1], [0],[1] -[71 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   293f4c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   2e9fcc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  73(TIDL_EltWiseLayer) [70, 73] --[256 x 50 x  50] => [128 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[71 72 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   293f4c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   40(   64),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   2e9fcc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  74(TIDL_EltWiseLayer) [71, 74] --[256 x 50 x  50] => [128 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[67 73 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   23decc ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   40(   64),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   293f4c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  75(TIDL_ConcatLayer) [72, 75] --[512 x 50 x  50] => [512 x 50 x  50] *** [512] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [8], [0],[8] -[59 60 67 74 ]---
  IN:MSMC, DMA,    a5d(  2653),    a5d(  2653),   80(  128),  a5d80( 679296),  34,   1420cc ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  200(  512), 158080(1409152),  34,   2e9fcc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  76(TIDL_ConvolutionLayer) [73, 76] --[512 x 50 x  50] => [256 x 50 x  50] *** [512] ***[ROW_L] ***[0, 0, 0, 256, 2550]**** [10], [1],[10] -[75 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  200(  512), 158080(1409152),  34,   2e9fcc ||||  L2, DMA,    240(   576),    240(   576),  200(  512),  48800( 296960),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   19a14c 
  WT:DDR_PERSIST, DMA,    201(   513),    201(   513),  100(  256),  20100( 131328),   0,   136580 ||||  L2, DMA,    240(   576),    201(   513),  100(  256),  24000( 147456),   0,    48800 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  77(TIDL_BatchNormLayer) [74, 77] --[256 x 50 x  50] => [256 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[76 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   19a14c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   2461cc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  78(TIDL_EltWiseLayer) [75, 78] --[512 x 50 x  50] => [256 x 50 x  50] *** [512] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [8], [0],[8] -[76 77 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   19a14c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   40(   64),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   19a14c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  79(TIDL_ConvolutionLayer) [76, 79] --[256 x 50 x  50] => [512 x 25 x  25] *** [256] ***[ROW_L] ***[52, 52, 52, 204, 2602]**** [13], [104],[104] -[78 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),   0,   19a14c ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24880( 149632),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,   1420e5 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),  200(  512), 120200(1180160),   0,   156680 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    24880 
 STG:MSMC, DMA,    940(  2368),    901(  2305),  200(  512), 128000(1212416),   0,   246180 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  80(TIDL_BatchNormLayer) [77, 80] --[512 x 25 x  25] => [512 x 25 x  25] *** [512] ***[ COL] ***[0, 0, 0, 650, 650]**** [1], [0],[1] -[79 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,   1420e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  200(  512),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,   2461e5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  81(TIDL_EltWiseLayer) [78, 81] --[1024 x 25 x  25] => [512 x 25 x  25] *** [1024] ***[ COL] ***[0, 0, 0, 650, 650]**** [4], [0],[4] -[79 80 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,   1420e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,   1420e5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  82(TIDL_ConvolutionLayer) [79, 82] --[512 x 25 x  25] => [512 x 25 x  25] *** [512] ***[ROW_L] ***[0, 0, 0, 64, 650]**** [11], [1],[11] -[81 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,   1420e5 ||||  L2, DMA,     c0(   192),     c0(   192),  200(  512),  18200(  98816),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,   2461e5 
  WT:DDR_PERSIST, DMA,    201(   513),    201(   513),  200(  512),  40200( 262656),   0,   276880 ||||  L2, DMA,    240(   576),    201(   513),  200(  512),  48000( 294912),   0,    18200 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  83(TIDL_BatchNormLayer) [80, 83] --[512 x 25 x  25] => [512 x 25 x  25] *** [512] ***[ COL] ***[0, 0, 0, 650, 650]**** [1], [0],[1] -[82 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,   2461e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  200(  512),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,   29e265 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  84(TIDL_EltWiseLayer) [81, 84] --[1024 x 25 x  25] => [512 x 25 x  25] *** [1024] ***[ COL] ***[0, 0, 0, 650, 650]**** [4], [0],[4] -[82 83 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,   2461e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2bf(   703),    2bf(   703),  200(  512),  57e80( 360064),  1b,   1420e5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  85(TIDL_SliceLayer) [82, 85] --[512 x 25 x  25] => [256 x 25 x  25] *** [512] ***[ COL] ***[0, 0, 0, 650, 650]**** [1], [0],[1] -[84 ]---
  IN:MSMC, DMA,    2bf(   703),    2bf(   703),  200(  512),  57e80( 360064),  1b,   1420e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  200(  512),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2bf(   703),    2bf(   703),  100(  256),  57e80( 360064),  1b,   1420e5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  86(TIDL_SliceLayer) [83, 86] --[512 x 25 x  25] => [256 x 25 x  25] *** [512] ***[ COL] ***[0, 0, 0, 650, 650]**** [1], [0],[1] -[84 ]---
  IN:MSMC, DMA,    2bf(   703),    2bf(   703),  200(  512),  57e80( 360064),  1b,   1420e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  200(  512),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   2461e5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  87(TIDL_ConvolutionLayer) [84, 87] --[256 x 25 x  25] => [256 x 25 x  25] *** [256] ***[ROW_L] ***[54, 64, 64, 256, 703]**** [3], [12],[12] -[86 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),   0,   2461e5 ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24100( 147712),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   306265 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),  100(  256),  90100( 590080),   0,   2b6a80 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    24100 
 STG:MSMC, DMA,    940(  2368),    901(  2305),  100(  256),  94000( 606208),   0,   272200 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  88(TIDL_BatchNormLayer) [85, 88] --[256 x 25 x  25] => [256 x 25 x  25] *** [256] ***[ COL] ***[0, 0, 0, 650, 650]**** [1], [0],[1] -[87 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   306265 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  2d800( 186368),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   272265 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  89(TIDL_EltWiseLayer) [86, 89] --[512 x 25 x  25] => [256 x 25 x  25] *** [512] ***[ COL] ***[0, 0, 0, 650, 650]**** [2], [0],[2] -[87 88 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   306265 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   272265 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  90(TIDL_ConvolutionLayer) [87, 90] --[256 x 25 x  25] => [256 x 25 x  25] *** [256] ***[ROW_L] ***[54, 64, 64, 256, 703]**** [3], [12],[12] -[89 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),   0,   272265 ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24100( 147712),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   3322e5 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),  100(  256),  90100( 590080),   0,   346b80 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    24100 
 STG:MSMC, DMA,    940(  2368),    901(  2305),  100(  256),  94000( 606208),   0,   29e280 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  91(TIDL_BatchNormLayer) [88, 91] --[256 x 25 x  25] => [256 x 25 x  25] *** [256] ***[ COL] ***[0, 0, 0, 650, 650]**** [1], [0],[1] -[90 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   3322e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  2d800( 186368),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   272265 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  92(TIDL_EltWiseLayer) [89, 92] --[512 x 25 x  25] => [256 x 25 x  25] *** [512] ***[ COL] ***[0, 0, 0, 650, 650]**** [2], [0],[2] -[90 91 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   3322e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   29e2e5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  93(TIDL_EltWiseLayer) [90, 93] --[512 x 25 x  25] => [256 x 25 x  25] *** [512] ***[ COL] ***[0, 0, 0, 650, 650]**** [2], [0],[2] -[86 92 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   2461e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   272265 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  94(TIDL_ConcatLayer) [91, 94] --[768 x 25 x  25] => [768 x 25 x  25] *** [768] ***[ COL] ***[0, 0, 0, 650, 650]**** [3], [0],[3] -[85 86 93 ]---
  IN:MSMC, DMA,    2bf(   703),    2bf(   703),  100(  256),  57e80( 360064),  1b,   1420e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  200(  512),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  300(  768),  84080( 540800),  1b,   29e2e5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  95(TIDL_ConvolutionLayer) [92, 95] --[768 x 25 x  25] => [512 x 25 x  25] *** [768] ***[ROW_L] ***[0, 0, 0, 192, 650]**** [4], [32],[32] -[94 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  300(  768),  84080( 540800),  1b,   29e2e5 ||||  L2, DMA,    1c0(   448),    1c0(   448),  300(  768),  54180( 344448),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,   1420e5 
  WT:DDR_PERSIST, DMA,    301(   769),    301(   769),  200(  512),  60200( 393728),   0,   3d6c80 ||||  L2, DMA,    340(   832),    301(   769),   80(  128),  1a000( 106496),   0,    54180 
 STG:MSMC, DMA,    340(   832),    301(   769),  200(  512),  68000( 425984),   0,   322300 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  96(TIDL_BatchNormLayer) [93, 96] --[512 x 25 x  25] => [512 x 25 x  25] *** [512] ***[ COL] ***[0, 0, 0, 650, 650]**** [1], [0],[1] -[95 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,   1420e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  200(  512),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,   2461e5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  97(TIDL_EltWiseLayer) [94, 97] --[1024 x 25 x  25] => [512 x 25 x  25] *** [1024] ***[ COL] ***[0, 0, 0, 650, 650]**** [4], [0],[4] -[95 96 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,   1420e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,   1420e5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  98(TIDL_ConvolutionLayer) [95, 98] --[512 x 25 x  25] => [256 x 25 x  25] *** [512] ***[ROW_L] ***[0, 0, 0, 256, 650]**** [3], [1],[3] -[97 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,   1420e5 ||||  L2, DMA,    240(   576),    240(   576),  200(  512),  48100( 295168),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   1420e5 
  WT:DDR_PERSIST, DMA,    201(   513),    201(   513),  100(  256),  20100( 131328),   0,   436e80 ||||  L2, DMA,    240(   576),    201(   513),  100(  256),  24000( 147456),   0,    48100 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  99(TIDL_BatchNormLayer) [96, 99] --[256 x 25 x  25] => [256 x 25 x  25] *** [256] ***[ COL] ***[0, 0, 0, 650, 650]**** [1], [0],[1] -[98 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   1420e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  2d800( 186368),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   2461e5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  100(TIDL_EltWiseLayer) [97, 100] --[512 x 25 x  25] => [256 x 25 x  25] *** [512] ***[ COL] ***[0, 0, 0, 650, 650]**** [2], [0],[2] -[98 99 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   1420e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   29e2e5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  101(TIDL_PoolingLayer) [98, 101] --[256 x 25 x  25] => [256 x 25 x  25] *** [256] ***[ COL] ***[0, 0, 0, 703, 703]**** [1], [0],[1] -[100 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),   0,   29e2e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  2d800( 186368),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   1420e5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  102(TIDL_PoolingLayer) [99, 102] --[256 x 25 x  25] => [256 x 25 x  25] *** [256] ***[ COL] ***[0, 0, 0, 703, 703]**** [1], [0],[1] -[101 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),   0,   1420e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  2d800( 186368),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   1420e5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  103(TIDL_PoolingLayer) [100, 103] --[256 x 25 x  25] => [256 x 25 x  25] *** [256] ***[ COL] ***[0, 0, 0, 703, 703]**** [1], [0],[1] -[102 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),   0,   1420e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  2d800( 186368),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   2461e5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  104(TIDL_PoolingLayer) [101, 104] --[256 x 25 x  25] => [256 x 25 x  25] *** [256] ***[ COL] ***[0, 0, 0, 703, 703]**** [1], [0],[1] -[103 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),   0,   2461e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  2d800( 186368),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   2461e5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  105(TIDL_PoolingLayer) [102, 105] --[256 x 25 x  25] => [256 x 25 x  25] *** [256] ***[ COL] ***[0, 0, 0, 703, 703]**** [1], [0],[1] -[104 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),   0,   2461e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  2d800( 186368),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   272265 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  106(TIDL_PoolingLayer) [103, 106] --[256 x 25 x  25] => [256 x 25 x  25] *** [256] ***[ COL] ***[0, 0, 0, 703, 703]**** [1], [0],[1] -[105 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),   0,   272265 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  2d800( 186368),   0,       80 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   272265 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  0],  To fill zero OUT: [ 0,  0]
------  107(TIDL_ConcatLayer) [104, 107] --[1024 x 25 x  25] => [1024 x 25 x  25] *** [1024] ***[ COL] ***[0, 0, 0, 650, 650]**** [4], [0],[4] -[100 102 104 106 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   29e2e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  200(  512),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  400( 1024),  b0080( 721024),  1b,   29e2e5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  108(TIDL_ConvolutionLayer) [105, 108] --[1024 x 25 x  25] => [512 x 25 x  25] *** [1024] ***[ROW_L] ***[0, 0, 0, 64, 650]**** [11], [88],[88] -[107 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  400( 1024),  b0080( 721024),  1b,   29e2e5 ||||  L2, DMA,     c0(   192),     c0(   192),  400( 1024),  30200( 197120),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,   1420e5 
  WT:DDR_PERSIST, DMA,    401(  1025),    401(  1025),  200(  512),  80200( 524800),   0,   456f80 ||||  L2, DMA,    440(  1088),    401(  1025),   80(  128),  22000( 139264),   0,    30200 
 STG:MSMC, DMA,    440(  1088),    401(  1025),  200(  512),  88000( 557056),   0,   34e300 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  109(TIDL_BatchNormLayer) [106, 109] --[512 x 25 x  25] => [512 x 25 x  25] *** [512] ***[ COL] ***[0, 0, 0, 650, 650]**** [1], [0],[1] -[108 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,   1420e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  200(  512),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,   2461e5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  110(TIDL_EltWiseLayer) [107, 110] --[1024 x 25 x  25] => [512 x 25 x  25] *** [1024] ***[ COL] ***[0, 0, 0, 650, 650]**** [4], [0],[4] -[108 109 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,   1420e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,   1420e5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  111(TIDL_ResizeLayer) [108, 111] --[512 x 25 x  25] => [512 x 50 x  50] *** [512] ***[ COL] ***[0, 0, 0, 729, 729]**** [1], [0],[1] -[110 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),   0,   1420e5 ||||  L2, DMA,    340(   832),    340(   832),  200(  512),  68000( 425984),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  200(  512), 158080(1409152),  34,   2461cc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  112(TIDL_ConcatLayer) [109, 112] --[768 x 50 x  50] => [768 x 50 x  50] *** [768] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [12], [0],[12] -[111 78 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  200(  512), 158080(1409152),  34,   2461cc ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  300(  768), 204080(2113664),  34,   2461cc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  113(TIDL_ConvolutionLayer) [110, 113] --[768 x 50 x  50] => [256 x 50 x  50] *** [768] ***[ROW_L] ***[0, 0, 0, 64, 2550]**** [40], [1],[40] -[112 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  300(  768), 204080(2113664),  34,   2461cc ||||  L2, DMA,     c0(   192),     c0(   192),  300(  768),  24980( 149888),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   24010c 
  WT:DDR_PERSIST, DMA,    301(   769),    301(   769),  100(  256),  30100( 196864),   0,   4d7180 ||||  L2, DMA,    340(   832),    301(   769),  100(  256),  34000( 212992),   0,    24980 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  114(TIDL_BatchNormLayer) [111, 114] --[256 x 50 x  50] => [256 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[113 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   24010c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   2ec18c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  115(TIDL_EltWiseLayer) [112, 115] --[512 x 50 x  50] => [256 x 50 x  50] *** [512] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [8], [0],[8] -[113 114 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   24010c ||||  L2, DMA,    a8f(  2703),    a8f(  2703),   40(   64),  54780( 345984),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    a5d(  2653),    a5d(  2653),  100(  256),  a5d80( 679296),  34,   19a14c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  116(TIDL_SliceLayer) [113, 116] --[256 x 50 x  50] => [128 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[115 ]---
  IN:MSMC, DMA,    a5d(  2653),    a5d(  2653),  100(  256),  a5d80( 679296),  34,   19a14c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    a5d(  2653),    a5d(  2653),   80(  128),  a5d80( 679296),  34,   19a14c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  117(TIDL_SliceLayer) [114, 117] --[256 x 50 x  50] => [128 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[115 ]---
  IN:MSMC, DMA,    a5d(  2653),    a5d(  2653),  100(  256),  a5d80( 679296),  34,   19a14c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   23fecc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  118(TIDL_ConvolutionLayer) [115, 118] --[128 x 50 x  50] => [128 x 50 x  50] *** [128] ***[ROW_L] ***[104, 128, 128, 1024, 2653]**** [3], [1],[3] -[117 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),   0,   23fecc ||||  L2, DMA,    8c0(  2240),    8c0(  2240),   80(  128),  46400( 287744),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   295f4c 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,   507280 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    46400 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  119(TIDL_BatchNormLayer) [116, 119] --[128 x 50 x  50] => [128 x 50 x  50] *** [128] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [1], [0],[1] -[118 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   295f4c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   2ebfcc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  120(TIDL_EltWiseLayer) [117, 120] --[256 x 50 x  50] => [128 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[118 119 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   295f4c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   40(   64),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   295f4c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  121(TIDL_ConvolutionLayer) [118, 121] --[128 x 50 x  50] => [128 x 50 x  50] *** [128] ***[ROW_L] ***[104, 128, 128, 1024, 2653]**** [3], [1],[3] -[120 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),   0,   295f4c ||||  L2, DMA,    8c0(  2240),    8c0(  2240),   80(  128),  46400( 287744),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   295f4c 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,   52b300 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    46400 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  122(TIDL_BatchNormLayer) [119, 122] --[128 x 50 x  50] => [128 x 50 x  50] *** [128] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [1], [0],[1] -[121 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   295f4c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   2ebfcc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  123(TIDL_EltWiseLayer) [120, 123] --[256 x 50 x  50] => [128 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[121 122 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   295f4c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   40(   64),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   295f4c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  124(TIDL_ConcatLayer) [121, 124] --[384 x 50 x  50] => [384 x 50 x  50] *** [384] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [6], [0],[6] -[116 117 123 ]---
  IN:MSMC, DMA,    a5d(  2653),    a5d(  2653),   80(  128),  a5d80( 679296),  34,   19a14c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  180(  384), 102080(1056896),  34,   2ebfcc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  125(TIDL_ConvolutionLayer) [122, 125] --[384 x 50 x  50] => [256 x 50 x  50] *** [384] ***[ROW_L] ***[0, 0, 0, 384, 2550]**** [7], [1],[7] -[124 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  180(  384), 102080(1056896),  34,   2ebfcc ||||  L2, DMA,    340(   832),    340(   832),  180(  384),  4e780( 321408),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   19a14c 
  WT:DDR_PERSIST, DMA,    181(   385),    181(   385),  100(  256),  18100(  98560),   0,   54f380 ||||  L2, DMA,    1c0(   448),    181(   385),  100(  256),  1c000( 114688),   0,    4e780 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  126(TIDL_BatchNormLayer) [123, 126] --[256 x 50 x  50] => [256 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[125 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   19a14c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   2461cc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  127(TIDL_EltWiseLayer) [124, 127] --[512 x 50 x  50] => [256 x 50 x  50] *** [512] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [8], [0],[8] -[125 126 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   19a14c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   40(   64),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   19a14c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  128(TIDL_ResizeLayer) [125, 128] --[256 x 50 x  50] => [256 x 100 x  100] *** [256] ***[ COL] ***[0, 0, 0, 2653, 2653]**** [4], [0],[4] -[127 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),   0,   19a14c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),  100(  256), 284080(2637952),  66,   24619a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  129(TIDL_ConcatLayer) [126, 129] --[384 x 100 x  100] => [384 x 100 x  100] *** [384] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [24], [0],[24] -[128 52 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),  100(  256), 284080(2637952),  66,   24619a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   20(   32),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),  180(  384), 3c6080(3956864),  66,   24619a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  130(TIDL_ConvolutionLayer) [127, 130] --[384 x 100 x  100] => [128 x 100 x  100] *** [384] ***[ROW_L] ***[0, 0, 0, 448, 10100]**** [23], [1],[23] -[129 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),  180(  384), 3c6080(3956864),  66,   24619a ||||  L2, DMA,    3c0(   960),    3c0(   960),  180(  384),  5c480( 377984),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   24619a 
  WT:DDR_PERSIST, DMA,    181(   385),    181(   385),   80(  128),   c080(  49280),   0,   567480 ||||  L2, DMA,    1c0(   448),    181(   385),   80(  128),   e000(  57344),   0,    5c480 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  131(TIDL_BatchNormLayer) [128, 131] --[128 x 100 x  100] => [128 x 100 x  100] *** [128] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [8], [0],[8] -[130 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   24619a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   20(   32),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   38821a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  132(TIDL_EltWiseLayer) [129, 132] --[256 x 100 x  100] => [128 x 100 x  100] *** [256] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [16], [0],[16] -[130 131 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   24619a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   10(   16),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   283f( 10303),   283f( 10303),   80(  128), 142000(1318912),  66,       1a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  133(TIDL_SliceLayer) [130, 133] --[128 x 100 x  100] => [64 x 100 x  100] *** [128] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [8], [0],[8] -[132 ]---
  IN:MSMC, DMA,   283f( 10303),   283f( 10303),   80(  128), 142000(1318912),  66,       1a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   20(   32),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   283f( 10303),   283f( 10303),   40(   64), 142000(1318912),  66,       1a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  134(TIDL_SliceLayer) [131, 134] --[128 x 100 x  100] => [64 x 100 x  100] *** [128] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [8], [0],[8] -[132 ]---
  IN:MSMC, DMA,   283f( 10303),   283f( 10303),   80(  128), 142000(1318912),  66,       1a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   20(   32),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   24619a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  135(TIDL_ConvolutionLayer) [132, 135] --[64 x 100 x  100] => [64 x 100 x  100] *** [64] ***[ROW_L] ***[204, 256, 256, 3008, 10303]**** [4], [1],[4] -[134 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),   0,   24619a ||||  L2, DMA,   18c0(  6336),   18c0(  6336),   40(   64),  64780( 411520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   2e721a 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   40(   64),   9080(  36992),   0,   573500 ||||  L2, DMA,    2c0(   704),    241(   577),   40(   64),   b000(  45056),   0,    64780 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  136(TIDL_BatchNormLayer) [133, 136] --[64 x 100 x  100] => [64 x 100 x  100] *** [64] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [4], [0],[4] -[135 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   2e721a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   20(   32),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   38829a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  137(TIDL_EltWiseLayer) [134, 137] --[128 x 100 x  100] => [64 x 100 x  100] *** [128] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [8], [0],[8] -[135 136 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   2e721a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   10(   16),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   2e721a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  138(TIDL_ConvolutionLayer) [135, 138] --[64 x 100 x  100] => [64 x 100 x  100] *** [64] ***[ROW_L] ***[204, 256, 256, 3008, 10303]**** [4], [1],[4] -[137 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),   0,   2e721a ||||  L2, DMA,   18c0(  6336),   18c0(  6336),   40(   64),  64780( 411520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   2e721a 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   40(   64),   9080(  36992),   0,   57c580 ||||  L2, DMA,    2c0(   704),    241(   577),   40(   64),   b000(  45056),   0,    64780 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  139(TIDL_BatchNormLayer) [136, 139] --[64 x 100 x  100] => [64 x 100 x  100] *** [64] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [4], [0],[4] -[138 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   2e721a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   20(   32),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   38829a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  140(TIDL_EltWiseLayer) [137, 140] --[128 x 100 x  100] => [64 x 100 x  100] *** [128] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [8], [0],[8] -[138 139 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   2e721a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   10(   16),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   2e721a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  141(TIDL_ConcatLayer) [138, 141] --[192 x 100 x  100] => [192 x 100 x  100] *** [192] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [12], [0],[12] -[133 134 140 ]---
  IN:MSMC, DMA,   283f( 10303),   283f( 10303),   40(   64), 142000(1318912),  66,       1a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   20(   32),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   c0(  192), 1e3080(1978496),  66,   38829a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  142(TIDL_ConvolutionLayer) [139, 142] --[192 x 100 x  100] => [128 x 100 x  100] *** [192] ***[ROW_L] ***[0, 0, 0, 1024, 10100]**** [10], [1],[10] -[141 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   c0(  192), 1e3080(1978496),  66,   38829a ||||  L2, DMA,    840(  2112),    840(  2112),   c0(  192),  65000( 413696),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,       1a 
  WT:DDR_PERSIST, DMA,     c1(   193),     c1(   193),   80(  128),   6080(  24704),   0,   585600 ||||  L2, DMA,    140(   320),     c1(   193),   80(  128),   a000(  40960),   0,    65000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  143(TIDL_BatchNormLayer) [140, 143] --[128 x 100 x  100] => [128 x 100 x  100] *** [128] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [8], [0],[8] -[142 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,       1a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   20(   32),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   24619a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  144(TIDL_EltWiseLayer) [141, 144] --[256 x 100 x  100] => [128 x 100 x  100] *** [256] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [16], [0],[16] -[142 143 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,       1a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   10(   16),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,       1a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  145(TIDL_ConvolutionLayer) [142, 145] --[128 x 100 x  100] => [64 x 100 x  100] *** [128] ***[ROW_L] ***[204, 256, 256, 1280, 10303]**** [8], [1],[8] -[144 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),   0,       1a ||||  L2, DMA,    b40(  2880),    b40(  2880),   80(  128),  5be00( 376320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   24619a 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   40(   64),  12080(  73856),   0,   58b680 ||||  L2, DMA,    4c0(  1216),    481(  1153),   40(   64),  13000(  77824),   0,    5be00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  146(TIDL_BatchNormLayer) [143, 146] --[64 x 100 x  100] => [64 x 100 x  100] *** [64] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [4], [0],[4] -[145 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   24619a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   20(   32),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   2e721a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  147(TIDL_EltWiseLayer) [144, 147] --[128 x 100 x  100] => [64 x 100 x  100] *** [128] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [8], [0],[8] -[145 146 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   24619a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   10(   16),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   24619a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  148(TIDL_ConvolutionLayer) [145, 148] --[64 x 100 x  100] => [64 x 100 x  100] *** [64] ***[ROW_L] ***[204, 256, 256, 3008, 10303]**** [4], [1],[4] -[147 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),   0,   24619a ||||  L2, DMA,   18c0(  6336),   18c0(  6336),   40(   64),  64780( 411520),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   24619a 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   40(   64),   9080(  36992),   0,   59d700 ||||  L2, DMA,    2c0(   704),    241(   577),   40(   64),   b000(  45056),   0,    64780 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  149(TIDL_BatchNormLayer) [146, 149] --[64 x 100 x  100] => [64 x 100 x  100] *** [64] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [4], [0],[4] -[148 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   24619a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   20(   32),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   2e721a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  150(TIDL_EltWiseLayer) [147, 150] --[128 x 100 x  100] => [64 x 100 x  100] *** [128] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [8], [0],[8] -[148 149 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   24619a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   10(   16),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   24619a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  151(TIDL_ConvolutionLayer) [148, 151] --[64 x 100 x  100] => [64 x 100 x  100] *** [64] ***[ROW_L] ***[0, 0, 0, 3392, 10100]**** [3], [1],[3] -[150 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   24619a ||||  L2, DMA,   1ac0(  6848),   1ac0(  6848),   40(   64),  6bd00( 441600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   24619a 
  WT:DDR_PERSIST, DMA,     41(    65),     41(    65),   40(   64),   1080(   4224),   0,   5a6780 ||||  L2, DMA,     c0(   192),     41(    65),   40(   64),   3000(  12288),   0,    6bd00 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  152(TIDL_ConvolutionLayer) [149, 152] --[128 x 100 x  100] => [128 x 100 x  100] *** [128] ***[ROW_L] ***[204, 256, 256, 960, 10303]**** [11], [1],[11] -[144 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),   0,       1a ||||  L2, DMA,    8c0(  2240),    8c0(  2240),   80(  128),  48180( 295296),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   2e721a 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,   5a7800 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    48180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  153(TIDL_BatchNormLayer) [150, 153] --[128 x 100 x  100] => [128 x 100 x  100] *** [128] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [8], [0],[8] -[152 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   2e721a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   20(   32),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   42929a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  154(TIDL_EltWiseLayer) [151, 154] --[256 x 100 x  100] => [128 x 100 x  100] *** [256] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [16], [0],[16] -[152 153 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   2e721a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   10(   16),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   2e721a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  155(TIDL_ConvolutionLayer) [152, 155] --[128 x 100 x  100] => [128 x 100 x  100] *** [128] ***[ROW_L] ***[204, 256, 256, 960, 10303]**** [11], [1],[11] -[154 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),   0,   2e721a ||||  L2, DMA,    8c0(  2240),    8c0(  2240),   80(  128),  48180( 295296),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   2e721a 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,   5cb880 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    48180 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  156(TIDL_BatchNormLayer) [153, 156] --[128 x 100 x  100] => [128 x 100 x  100] *** [128] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [8], [0],[8] -[155 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   2e721a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   20(   32),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   42929a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  157(TIDL_EltWiseLayer) [154, 157] --[256 x 100 x  100] => [128 x 100 x  100] *** [256] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [16], [0],[16] -[155 156 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   2e721a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),   10(   16),  51480( 332928),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   2e721a 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  158(TIDL_ConvolutionLayer) [155, 158] --[128 x 100 x  100] => [3 x 100 x  100] *** [128] ***[ROW_L] ***[0, 0, 0, 1664, 10100]**** [7], [1],[7] -[157 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),  66,   2e721a ||||  L2, DMA,    d40(  3392),    d40(  3392),   80(  128),  6c080( 442496),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2840( 10304),   283f( 10303),    3(    3),   7980(  31104),  66,   2ec29a 
  WT:DDR_PERSIST, DMA,     81(   129),     81(   129),    3(    3),    200(    512),   0,   5ef900 ||||  L2, DMA,     c0(   192),     81(   129),    3(    3),    280(    640),   0,    6c080 
 STG:MSMC, DMA_ONCE,     c0(   192),     81(   129),    3(    3),    280(    640),   0,   7b9c00 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  159(TIDL_ConcatLayer) [156, 159] --[67 x 100 x  100] => [67 x 100 x  100] *** [67] ***[ COL] ***[0, 0, 0, 10100, 10100]**** [67], [0],[67] -[151 158 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   40(   64),  a1080( 659584),  66,   24619a ||||  L2, DMA,   28a3( 10403),   28a3( 10403),    2(    2),   5180(  20864),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2740( 10048),   2710( 10000),   43(   67),  a4680( 673408),   0,   246180 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  228(TIDL_DataConvertLayer) [157, 228] --[67 x 100 x  100] => [67 x 100 x  100] *** [67] ***[ COL] ***[0, 0, 0, 10000, 10000]**** [67], [0],[67] -[159 ]---
  IN:MSMC, DMA,   2740( 10048),   2710( 10000),   43(   67),  a4680( 673408),   0,   246180 ||||  L2, DMA,   2710( 10000),   2710( 10000),    2(    2),   4e80(  20096),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   2710( 10000),   2710( 10000),   43(   67),  a3a00( 670208),   0,   2ea800 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  231(TIDL_ReshapeLayer) [158, 231] --[67 x 100 x  100] => [1 x 10000 x  67] *** [67] ***[ COL] ***[0, 0, 0, 10000, 10000]**** [67], [0],[67] -[228 ]---
  IN:MSMC, DMA,   2710( 10000),   2710( 10000),   43(   67),  a3a00( 670208),   0,   2ea800 ||||  L2, DMA,   2710( 10000),   2710( 10000),    2(    2),   4e80(  20096),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  a3930(670000),  a3930(670000),    1(    1),  a3a00( 670208),   0,   2ea800 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  160(TIDL_ConvolutionLayer) [159, 160] --[128 x 100 x  100] => [128 x 50 x  50] *** [128] ***[ROW_L] ***[102, 102, 102, 1010, 10202]**** [10], [1],[10] -[144 ]---
  IN:MSMC, DMA,   2840( 10304),   283f( 10303),   80(  128), 142080(1319040),   0,       1a ||||  L2, DMA,    8c0(  2240),    8c0(  2240),   80(  128),  47f80( 294784),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    a40(  2624),    9c5(  2501),   80(  128),  52080( 336000),   0,   246180 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,   5efb00 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    47f80 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  161(TIDL_BatchNormLayer) [160, 161] --[128 x 50 x  50] => [128 x 50 x  50] *** [128] ***[ COL] ***[0, 0, 0, 2500, 2500]**** [1], [0],[1] -[160 ]---
  IN:MSMC, DMA,    a40(  2624),    9c5(  2501),   80(  128),  52080( 336000),   0,   246180 ||||  L2, DMA,    a5a(  2650),    a5a(  2650),   80(  128),  52d00( 339200),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    a40(  2624),    9c4(  2500),   80(  128),  52080( 336000),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  162(TIDL_EltWiseLayer) [161, 162] --[256 x 50 x  50] => [128 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2500, 2500]**** [4], [0],[4] -[160 161 ]---
  IN:MSMC, DMA,    a40(  2624),    9c5(  2501),   80(  128),  52080( 336000),   0,   246180 ||||  L2, DMA,    a5a(  2650),    a5a(  2650),   40(   64),  52d00( 339200),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    a40(  2624),    9c4(  2500),   80(  128),  52080( 336000),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  163(TIDL_ConcatLayer) [162, 163] --[384 x 50 x  50] => [384 x 50 x  50] *** [384] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [6], [0],[6] -[162 127 ]---
  IN:MSMC, DMA,    a40(  2624),    9c4(  2500),   80(  128),  52080( 336000),  34,        0 ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  180(  384), 102080(1056896),  34,   38e24c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  164(TIDL_ConvolutionLayer) [163, 164] --[384 x 50 x  50] => [256 x 50 x  50] *** [384] ***[ROW_L] ***[0, 0, 0, 384, 2550]**** [7], [1],[7] -[163 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  180(  384), 102080(1056896),  34,   38e24c ||||  L2, DMA,    340(   832),    340(   832),  180(  384),  4e780( 321408),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   19a14c 
  WT:DDR_PERSIST, DMA,    181(   385),    181(   385),  100(  256),  18100(  98560),   0,   613b80 ||||  L2, DMA,    1c0(   448),    181(   385),  100(  256),  1c000( 114688),   0,    4e780 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  165(TIDL_BatchNormLayer) [164, 165] --[256 x 50 x  50] => [256 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[164 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   19a14c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   38e24c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  166(TIDL_EltWiseLayer) [165, 166] --[512 x 50 x  50] => [256 x 50 x  50] *** [512] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [8], [0],[8] -[164 165 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   19a14c ||||  L2, DMA,    a8f(  2703),    a8f(  2703),   40(   64),  54780( 345984),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    a5d(  2653),    a5d(  2653),  100(  256),  a5d80( 679296),  34,       4c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  167(TIDL_SliceLayer) [166, 167] --[256 x 50 x  50] => [128 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[166 ]---
  IN:MSMC, DMA,    a5d(  2653),    a5d(  2653),  100(  256),  a5d80( 679296),  34,       4c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    a5d(  2653),    a5d(  2653),   80(  128),  a5d80( 679296),  34,       4c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  168(TIDL_SliceLayer) [167, 168] --[256 x 50 x  50] => [128 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[166 ]---
  IN:MSMC, DMA,    a5d(  2653),    a5d(  2653),  100(  256),  a5d80( 679296),  34,       4c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,    a5dcc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  169(TIDL_ConvolutionLayer) [168, 169] --[128 x 50 x  50] => [128 x 50 x  50] *** [128] ***[ROW_L] ***[104, 128, 128, 1024, 2653]**** [3], [1],[3] -[168 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),   0,    a5dcc ||||  L2, DMA,    8c0(  2240),    8c0(  2240),   80(  128),  46400( 287744),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   19a14c 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,   62bc80 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    46400 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  170(TIDL_BatchNormLayer) [169, 170] --[128 x 50 x  50] => [128 x 50 x  50] *** [128] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [1], [0],[1] -[169 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   19a14c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   1f01cc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  171(TIDL_EltWiseLayer) [170, 171] --[256 x 50 x  50] => [128 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[169 170 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   19a14c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   40(   64),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   19a14c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  172(TIDL_ConvolutionLayer) [171, 172] --[128 x 50 x  50] => [128 x 50 x  50] *** [128] ***[ROW_L] ***[104, 128, 128, 1024, 2653]**** [3], [1],[3] -[171 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),   0,   19a14c ||||  L2, DMA,    8c0(  2240),    8c0(  2240),   80(  128),  46400( 287744),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   19a14c 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,   64fd00 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    46400 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  173(TIDL_BatchNormLayer) [172, 173] --[128 x 50 x  50] => [128 x 50 x  50] *** [128] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [1], [0],[1] -[172 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   19a14c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   1f01cc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  174(TIDL_EltWiseLayer) [173, 174] --[256 x 50 x  50] => [128 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[172 173 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   19a14c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   40(   64),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   19a14c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  175(TIDL_ConcatLayer) [174, 175] --[384 x 50 x  50] => [384 x 50 x  50] *** [384] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [6], [0],[6] -[167 168 174 ]---
  IN:MSMC, DMA,    a5d(  2653),    a5d(  2653),   80(  128),  a5d80( 679296),  34,       4c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  180(  384), 102080(1056896),  34,   38e24c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  176(TIDL_ConvolutionLayer) [175, 176] --[384 x 50 x  50] => [256 x 50 x  50] *** [384] ***[ROW_L] ***[0, 0, 0, 384, 2550]**** [7], [1],[7] -[175 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  180(  384), 102080(1056896),  34,   38e24c ||||  L2, DMA,    340(   832),    340(   832),  180(  384),  4e780( 321408),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,       4c 
  WT:DDR_PERSIST, DMA,    181(   385),    181(   385),  100(  256),  18100(  98560),   0,   673d80 ||||  L2, DMA,    1c0(   448),    181(   385),  100(  256),  1c000( 114688),   0,    4e780 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  177(TIDL_BatchNormLayer) [176, 177] --[256 x 50 x  50] => [256 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[176 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,       4c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,   19a14c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  178(TIDL_EltWiseLayer) [177, 178] --[512 x 50 x  50] => [256 x 50 x  50] *** [512] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [8], [0],[8] -[176 177 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,       4c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   40(   64),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),  34,       4c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  179(TIDL_ConvolutionLayer) [178, 179] --[256 x 50 x  50] => [64 x 50 x  50] *** [256] ***[ROW_L] ***[104, 128, 128, 448, 2653]**** [6], [1],[6] -[178 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),   0,       4c ||||  L2, DMA,    440(  1088),    440(  1088),  100(  256),  44700( 280320),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   40(   64),  2b080( 176256),  34,    ac0cc 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),   40(   64),  24080( 147584),   0,   68be80 ||||  L2, DMA,    940(  2368),    901(  2305),   40(   64),  25000( 151552),   0,    44700 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  180(TIDL_BatchNormLayer) [179, 180] --[64 x 50 x  50] => [64 x 50 x  50] *** [64] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [1], [0],[1] -[179 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   40(   64),  2b080( 176256),  34,    ac0cc ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   40(   64),  2b080( 176256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   40(   64),  2b080( 176256),  34,    d714c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  181(TIDL_EltWiseLayer) [180, 181] --[128 x 50 x  50] => [64 x 50 x  50] *** [128] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [2], [0],[2] -[179 180 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   40(   64),  2b080( 176256),  34,    ac0cc ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   40(   64),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   40(   64),  2b080( 176256),  34,    ac0cc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  182(TIDL_ConvolutionLayer) [181, 182] --[64 x 50 x  50] => [64 x 50 x  50] *** [64] ***[ROW_L] ***[104, 128, 128, 2525, 2653]**** [1], [1],[1] -[181 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   40(   64),  2b080( 176256),   0,    ac0cc ||||  L2, DMA,    ac0(  2752),    ac0(  2752),   40(   64),  2b000( 176128),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   40(   64),  2b080( 176256),  34,    ac0cc 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   40(   64),   9080(  36992),   0,   6aff00 ||||  L2, DMA,    2c0(   704),    241(   577),   40(   64),   b000(  45056),   0,    2b000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  183(TIDL_BatchNormLayer) [182, 183] --[64 x 50 x  50] => [64 x 50 x  50] *** [64] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [1], [0],[1] -[182 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   40(   64),  2b080( 176256),  34,    ac0cc ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   40(   64),  2b080( 176256),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   40(   64),  2b080( 176256),  34,    d714c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  184(TIDL_EltWiseLayer) [183, 184] --[128 x 50 x  50] => [64 x 50 x  50] *** [128] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [2], [0],[2] -[182 183 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   40(   64),  2b080( 176256),  34,    ac0cc ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   40(   64),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   40(   64),  2b080( 176256),  34,   1021cc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  185(TIDL_ConvolutionLayer) [184, 185] --[64 x 50 x  50] => [64 x 50 x  50] *** [64] ***[ROW_L] ***[0, 0, 0, 2550, 2550]**** [1], [1],[1] -[184 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   40(   64),  2b080( 176256),  34,   1021cc ||||  L2, DMA,    a40(  2624),    a40(  2624),   40(   64),  29000( 167936),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   40(   64),  2b080( 176256),  34,    d4fcc 
  WT:DDR_PERSIST, DMA,     41(    65),     41(    65),   40(   64),   1080(   4224),   0,   6b8f80 ||||  L2, DMA,     c0(   192),     41(    65),   40(   64),   3000(  12288),   0,    29000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  186(TIDL_ConvolutionLayer) [185, 186] --[256 x 50 x  50] => [128 x 50 x  50] *** [256] ***[ROW_L] ***[104, 128, 128, 192, 2653]**** [14], [1],[14] -[178 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),   0,       4c ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24900( 149760),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   19a14c 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),   80(  128),  48080( 295040),   0,   6ba000 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    24900 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  187(TIDL_BatchNormLayer) [186, 187] --[128 x 50 x  50] => [128 x 50 x  50] *** [128] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [1], [0],[1] -[186 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   19a14c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   1f01cc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  188(TIDL_EltWiseLayer) [187, 188] --[256 x 50 x  50] => [128 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[186 187 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   19a14c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   40(   64),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   19a14c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  189(TIDL_ConvolutionLayer) [188, 189] --[128 x 50 x  50] => [128 x 50 x  50] *** [128] ***[ROW_L] ***[104, 128, 128, 1024, 2653]**** [3], [1],[3] -[188 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),   0,   19a14c ||||  L2, DMA,    8c0(  2240),    8c0(  2240),   80(  128),  46400( 287744),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   19a14c 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,   702080 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    46400 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  190(TIDL_BatchNormLayer) [189, 190] --[128 x 50 x  50] => [128 x 50 x  50] *** [128] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [1], [0],[1] -[189 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   19a14c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   80(  128),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   1f01cc 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  191(TIDL_EltWiseLayer) [190, 191] --[256 x 50 x  50] => [128 x 50 x  50] *** [256] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [4], [0],[4] -[189 190 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   19a14c ||||  L2, DMA,    ac2(  2754),    ac2(  2754),   40(   64),  56100( 352512),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   19a14c 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  192(TIDL_ConvolutionLayer) [191, 192] --[128 x 50 x  50] => [3 x 50 x  50] *** [128] ***[ROW_L] ***[0, 0, 0, 1728, 2550]**** [2], [1],[2] -[191 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   80(  128),  56080( 352384),  34,   19a14c ||||  L2, DMA,    dc0(  3520),    dc0(  3520),   80(  128),  6e000( 450560),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    ac0(  2752),    a5d(  2653),    3(    3),   2100(   8448),  34,    ac0cc 
  WT:DDR_PERSIST, DMA,     81(   129),     81(   129),    3(    3),    200(    512),   0,   726100 ||||  L2, DMA,     c0(   192),     81(   129),    3(    3),    280(    640),   0,    6e000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  193(TIDL_ConcatLayer) [192, 193] --[67 x 50 x  50] => [67 x 50 x  50] *** [67] ***[ COL] ***[0, 0, 0, 2550, 2550]**** [67], [0],[67] -[185 192 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),   40(   64),  2b080( 176256),  34,    d4fcc ||||  L2, DMA,    ac2(  2754),    ac2(  2754),    2(    2),   1600(   5632),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    a40(  2624),    9c4(  2500),   43(   67),  2af80( 176000),   0,    d4f80 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  229(TIDL_DataConvertLayer) [193, 229] --[67 x 50 x  50] => [67 x 50 x  50] *** [67] ***[ COL] ***[0, 0, 0, 2500, 2500]**** [67], [0],[67] -[193 ]---
  IN:MSMC, DMA,    a40(  2624),    9c4(  2500),   43(   67),  2af80( 176000),   0,    d4f80 ||||  L2, DMA,    9c4(  2500),    9c4(  2500),    2(    2),   1400(   5120),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    9c4(  2500),    9c4(  2500),   43(   67),  28f00( 167680),   0,    ac080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  232(TIDL_ReshapeLayer) [194, 232] --[67 x 50 x  50] => [1 x 2500 x  67] *** [67] ***[ COL] ***[0, 0, 0, 2500, 2500]**** [67], [0],[67] -[229 ]---
  IN:MSMC, DMA,    9c4(  2500),    9c4(  2500),   43(   67),  28f00( 167680),   0,    ac080 ||||  L2, DMA,    9c4(  2500),    9c4(  2500),    2(    2),   1400(   5120),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  28e4c(167500),  28e4c(167500),    1(    1),  28f00( 167680),   0,    ac080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  194(TIDL_ConvolutionLayer) [195, 194] --[256 x 50 x  50] => [256 x 25 x  25] *** [256] ***[ROW_L] ***[52, 52, 52, 204, 2602]**** [13], [52],[52] -[178 ]---
  IN:MSMC, DMA,    ac0(  2752),    a5d(  2653),  100(  256),  ac080( 704640),   0,       4c ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24880( 149632),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    272(   626),  100(  256),  2c080( 180352),   0,    d4f80 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),  100(  256),  90100( 590080),   0,   726300 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    24880 
 STG:MSMC, DMA,    940(  2368),    901(  2305),  100(  256),  94000( 606208),   0,   19a100 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  195(TIDL_BatchNormLayer) [196, 195] --[256 x 25 x  25] => [256 x 25 x  25] *** [256] ***[ COL] ***[0, 0, 0, 625, 625]**** [1], [0],[1] -[194 ]---
  IN:MSMC, DMA,    2c0(   704),    272(   626),  100(  256),  2c080( 180352),   0,    d4f80 ||||  L2, DMA,    2d5(   725),    2d5(   725),  100(  256),  2d500( 185600),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    271(   625),  100(  256),  2c080( 180352),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  196(TIDL_EltWiseLayer) [197, 196] --[512 x 25 x  25] => [256 x 25 x  25] *** [512] ***[ COL] ***[0, 0, 0, 625, 625]**** [2], [0],[2] -[194 195 ]---
  IN:MSMC, DMA,    2c0(   704),    272(   626),  100(  256),  2c080( 180352),   0,    d4f80 ||||  L2, DMA,    2d5(   725),    2d5(   725),  100(  256),  5aa00( 371200),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    271(   625),  100(  256),  2c080( 180352),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  197(TIDL_ConcatLayer) [198, 197] --[768 x 25 x  25] => [768 x 25 x  25] *** [768] ***[ COL] ***[0, 0, 0, 650, 650]**** [3], [0],[3] -[196 110 ]---
  IN:MSMC, DMA,    2c0(   704),    271(   625),  100(  256),  2c080( 180352),  1b,        0 ||||  L2, DMA,    2d8(   728),    2d8(   728),  200(  512),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  300(  768),  84080( 540800),  1b,   19a165 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  198(TIDL_ConvolutionLayer) [199, 198] --[768 x 25 x  25] => [512 x 25 x  25] *** [768] ***[ROW_L] ***[0, 0, 0, 192, 650]**** [4], [32],[32] -[197 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  300(  768),  84080( 540800),  1b,   19a165 ||||  L2, DMA,    1c0(   448),    1c0(   448),  300(  768),  54180( 344448),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,    d4fe5 
  WT:DDR_PERSIST, DMA,    301(   769),    301(   769),  200(  512),  60200( 393728),   0,   7b6400 ||||  L2, DMA,    340(   832),    301(   769),   80(  128),  1a000( 106496),   0,    54180 
 STG:MSMC, DMA,    340(   832),    301(   769),  200(  512),  68000( 425984),   0,    2c080 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  199(TIDL_BatchNormLayer) [200, 199] --[512 x 25 x  25] => [512 x 25 x  25] *** [512] ***[ COL] ***[0, 0, 0, 650, 650]**** [1], [0],[1] -[198 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,    d4fe5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  200(  512),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,   12d065 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  200(TIDL_EltWiseLayer) [201, 200] --[1024 x 25 x  25] => [512 x 25 x  25] *** [1024] ***[ COL] ***[0, 0, 0, 650, 650]**** [4], [0],[4] -[198 199 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,    d4fe5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2bf(   703),    2bf(   703),  200(  512),  57e80( 360064),  1b,       65 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  201(TIDL_SliceLayer) [202, 201] --[512 x 25 x  25] => [256 x 25 x  25] *** [512] ***[ COL] ***[0, 0, 0, 650, 650]**** [1], [0],[1] -[200 ]---
  IN:MSMC, DMA,    2bf(   703),    2bf(   703),  200(  512),  57e80( 360064),  1b,       65 ||||  L2, DMA,    2d8(   728),    2d8(   728),  200(  512),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2bf(   703),    2bf(   703),  100(  256),  57e80( 360064),  1b,       65 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  202(TIDL_SliceLayer) [203, 202] --[512 x 25 x  25] => [256 x 25 x  25] *** [512] ***[ COL] ***[0, 0, 0, 650, 650]**** [1], [0],[1] -[200 ]---
  IN:MSMC, DMA,    2bf(   703),    2bf(   703),  200(  512),  57e80( 360064),  1b,       65 ||||  L2, DMA,    2d8(   728),    2d8(   728),  200(  512),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,    57ee5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 1,  1],  To fill zero OUT: [ 1,  1]
------  203(TIDL_ConvolutionLayer) [204, 203] --[256 x 25 x  25] => [256 x 25 x  25] *** [256] ***[ROW_L] ***[54, 64, 64, 256, 703]**** [3], [12],[12] -[202 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),   0,    57ee5 ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24100( 147712),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   168fe5 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),  100(  256),  90100( 590080),   0,   816600 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    24100 
 STG:MSMC, DMA,    940(  2368),    901(  2305),  100(  256),  94000( 606208),   0,    d4f80 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  204(TIDL_BatchNormLayer) [205, 204] --[256 x 25 x  25] => [256 x 25 x  25] *** [256] ***[ COL] ***[0, 0, 0, 650, 650]**** [1], [0],[1] -[203 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   168fe5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  2d800( 186368),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,    d4fe5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  205(TIDL_EltWiseLayer) [206, 205] --[512 x 25 x  25] => [256 x 25 x  25] *** [512] ***[ COL] ***[0, 0, 0, 650, 650]**** [2], [0],[2] -[203 204 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   168fe5 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,    d4fe5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  206(TIDL_ConvolutionLayer) [207, 206] --[256 x 25 x  25] => [256 x 25 x  25] *** [256] ***[ROW_L] ***[54, 64, 64, 256, 703]**** [3], [12],[12] -[205 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),   0,    d4fe5 ||||  L2, DMA,    240(   576),    240(   576),  100(  256),  24100( 147712),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   195065 
  WT:DDR_PERSIST, DMA,    901(  2305),    901(  2305),  100(  256),  90100( 590080),   0,   8a6700 ||||  L2, DMA,    940(  2368),    901(  2305),   80(  128),  4a000( 303104),   0,    24100 
 STG:MSMC, DMA,    940(  2368),    901(  2305),  100(  256),  94000( 606208),   0,   101000 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  207(TIDL_BatchNormLayer) [208, 207] --[256 x 25 x  25] => [256 x 25 x  25] *** [256] ***[ COL] ***[0, 0, 0, 650, 650]**** [1], [0],[1] -[206 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   195065 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  2d800( 186368),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,    d4fe5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  208(TIDL_EltWiseLayer) [209, 208] --[512 x 25 x  25] => [256 x 25 x  25] *** [512] ***[ COL] ***[0, 0, 0, 650, 650]**** [2], [0],[2] -[206 207 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,   195065 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  100(  256),  2c080( 180352),  1b,    d4fe5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  209(TIDL_ConcatLayer) [210, 209] --[768 x 25 x  25] => [768 x 25 x  25] *** [768] ***[ COL] ***[0, 0, 0, 650, 650]**** [3], [0],[3] -[201 202 208 ]---
  IN:MSMC, DMA,    2bf(   703),    2bf(   703),  100(  256),  57e80( 360064),  1b,       65 ||||  L2, DMA,    2d8(   728),    2d8(   728),  200(  512),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  300(  768),  84080( 540800),  1b,   101065 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  210(TIDL_ConvolutionLayer) [211, 210] --[768 x 25 x  25] => [512 x 25 x  25] *** [768] ***[ROW_L] ***[0, 0, 0, 192, 650]**** [4], [32],[32] -[209 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  300(  768),  84080( 540800),  1b,   101065 ||||  L2, DMA,    1c0(   448),    1c0(   448),  300(  768),  54180( 344448),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,       65 
  WT:DDR_PERSIST, DMA,    301(   769),    301(   769),  200(  512),  60200( 393728),   0,   936800 ||||  L2, DMA,    340(   832),    301(   769),   80(  128),  1a000( 106496),   0,    54180 
 STG:MSMC, DMA,    340(   832),    301(   769),  200(  512),  68000( 425984),   0,   185080 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  211(TIDL_BatchNormLayer) [212, 211] --[512 x 25 x  25] => [512 x 25 x  25] *** [512] ***[ COL] ***[0, 0, 0, 650, 650]**** [1], [0],[1] -[210 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,       65 ||||  L2, DMA,    2d8(   728),    2d8(   728),  200(  512),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,    d4fe5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  212(TIDL_EltWiseLayer) [213, 212] --[1024 x 25 x  25] => [512 x 25 x  25] *** [1024] ***[ COL] ***[0, 0, 0, 650, 650]**** [4], [0],[4] -[210 211 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,       65 ||||  L2, DMA,    2d8(   728),    2d8(   728),  100(  256),  5b000( 372736),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),  1b,       65 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  213(TIDL_ConvolutionLayer) [214, 213] --[512 x 25 x  25] => [64 x 25 x  25] *** [512] ***[ROW_L] ***[54, 64, 64, 64, 703]**** [10], [1],[10] -[212 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),   0,       65 ||||  L2, DMA,     c0(   192),     c0(   192),  200(  512),  18200(  98816),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),   40(   64),   b080(  45184),  1b,    580e5 
  WT:DDR_PERSIST, DMA,   1201(  4609),   1201(  4609),   40(   64),  48080( 295040),   0,   996a00 ||||  L2, DMA,   1240(  4672),   1201(  4609),   40(   64),  49000( 299008),   0,    18200 
 STG:MSMC, DMA_ONCE,   1240(  4672),   1201(  4609),   40(   64),  49000( 299008),   0,   770880 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  214(TIDL_BatchNormLayer) [215, 214] --[64 x 25 x  25] => [64 x 25 x  25] *** [64] ***[ COL] ***[0, 0, 0, 650, 650]**** [1], [0],[1] -[213 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),   40(   64),   b080(  45184),  1b,    580e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),   40(   64),   b600(  46592),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),   40(   64),   b080(  45184),  1b,    63165 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  215(TIDL_EltWiseLayer) [216, 215] --[128 x 25 x  25] => [64 x 25 x  25] *** [128] ***[ COL] ***[0, 0, 0, 650, 650]**** [2], [0],[2] -[213 214 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),   40(   64),   b080(  45184),  1b,    580e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),   40(   64),  16c00(  93184),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),   40(   64),   b080(  45184),  1b,    580e5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  216(TIDL_ConvolutionLayer) [217, 216] --[64 x 25 x  25] => [64 x 25 x  25] *** [64] ***[ROW_L] ***[54, 64, 64, 639, 703]**** [1], [1],[1] -[215 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),   40(   64),   b080(  45184),   0,    580e5 ||||  L2, DMA,    2c0(   704),    2c0(   704),   40(   64),   b000(  45056),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),   40(   64),   b080(  45184),  1b,    580e5 
  WT:DDR_PERSIST, DMA,    241(   577),    241(   577),   40(   64),   9080(  36992),   0,   9dea80 ||||  L2, DMA,    2c0(   704),    241(   577),   40(   64),   b000(  45056),   0,     b000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  217(TIDL_BatchNormLayer) [218, 217] --[64 x 25 x  25] => [64 x 25 x  25] *** [64] ***[ COL] ***[0, 0, 0, 650, 650]**** [1], [0],[1] -[216 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),   40(   64),   b080(  45184),  1b,    580e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),   40(   64),   b600(  46592),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),   40(   64),   b080(  45184),  1b,    63165 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  218(TIDL_EltWiseLayer) [219, 218] --[128 x 25 x  25] => [64 x 25 x  25] *** [128] ***[ COL] ***[0, 0, 0, 650, 650]**** [2], [0],[2] -[216 217 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),   40(   64),   b080(  45184),  1b,    580e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),   40(   64),  16c00(  93184),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),   40(   64),   b080(  45184),  1b,    580e5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  219(TIDL_ConvolutionLayer) [220, 219] --[64 x 25 x  25] => [64 x 25 x  25] *** [64] ***[ROW_L] ***[0, 0, 0, 650, 650]**** [1], [1],[1] -[218 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),   40(   64),   b080(  45184),  1b,    580e5 ||||  L2, DMA,    2c0(   704),    2c0(   704),   40(   64),   b000(  45056),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),   40(   64),   b080(  45184),  1b,    580e5 
  WT:DDR_PERSIST, DMA,     41(    65),     41(    65),   40(   64),   1080(   4224),   0,   9e7b00 ||||  L2, DMA,     c0(   192),     41(    65),   40(   64),   3000(  12288),   0,     b000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  220(TIDL_ConvolutionLayer) [221, 220] --[512 x 25 x  25] => [128 x 25 x  25] *** [512] ***[ROW_L] ***[54, 64, 64, 64, 703]**** [10], [40],[40] -[212 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),  200(  512),  58080( 360576),   0,       65 ||||  L2, DMA,     c0(   192),     c0(   192),  200(  512),  18200(  98816),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),   80(  128),  16080(  90240),  1b,    63165 
  WT:DDR_PERSIST, DMA,   1201(  4609),   1201(  4609),   80(  128),  90080( 589952),   0,   9e8b80 ||||  L2, DMA,   1240(  4672),   1201(  4609),   40(   64),  49000( 299008),   0,    18200 
 STG:MSMC, DMA,   1240(  4672),   1201(  4609),   80(  128),  92000( 598016),   0,    d4f80 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  221(TIDL_BatchNormLayer) [222, 221] --[128 x 25 x  25] => [128 x 25 x  25] *** [128] ***[ COL] ***[0, 0, 0, 650, 650]**** [1], [0],[1] -[220 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),   80(  128),  16080(  90240),  1b,    63165 ||||  L2, DMA,    2d8(   728),    2d8(   728),   80(  128),  16c00(  93184),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),   80(  128),  16080(  90240),  1b,       65 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  222(TIDL_EltWiseLayer) [223, 222] --[256 x 25 x  25] => [128 x 25 x  25] *** [256] ***[ COL] ***[0, 0, 0, 650, 650]**** [2], [0],[2] -[220 221 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),   80(  128),  16080(  90240),  1b,    63165 ||||  L2, DMA,    2d8(   728),    2d8(   728),   80(  128),  2d800( 186368),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),   80(  128),  16080(  90240),  1b,       65 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 1,  1]
------  223(TIDL_ConvolutionLayer) [224, 223] --[128 x 25 x  25] => [128 x 25 x  25] *** [128] ***[ROW_L] ***[54, 64, 64, 639, 703]**** [1], [1],[1] -[222 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),   80(  128),  16080(  90240),   0,       65 ||||  L2, DMA,    2c0(   704),    2c0(   704),   80(  128),  16000(  90112),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),   80(  128),  16080(  90240),  1b,       65 
  WT:DDR_PERSIST, DMA,    481(  1153),    481(  1153),   80(  128),  24080( 147584),   0,   a78c00 ||||  L2, DMA,    4c0(  1216),    481(  1153),   80(  128),  26000( 155648),   0,    16000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  224(TIDL_BatchNormLayer) [225, 224] --[128 x 25 x  25] => [128 x 25 x  25] *** [128] ***[ COL] ***[0, 0, 0, 650, 650]**** [1], [0],[1] -[223 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),   80(  128),  16080(  90240),  1b,       65 ||||  L2, DMA,    2d8(   728),    2d8(   728),   80(  128),  16c00(  93184),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),   80(  128),  16080(  90240),  1b,    160e5 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  225(TIDL_EltWiseLayer) [226, 225] --[256 x 25 x  25] => [128 x 25 x  25] *** [256] ***[ COL] ***[0, 0, 0, 650, 650]**** [2], [0],[2] -[223 224 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),   80(  128),  16080(  90240),  1b,       65 ||||  L2, DMA,    2d8(   728),    2d8(   728),   80(  128),  2d800( 186368),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),   80(  128),  16080(  90240),  1b,       65 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  226(TIDL_ConvolutionLayer) [227, 226] --[128 x 25 x  25] => [3 x 25 x  25] *** [128] ***[ROW_L] ***[0, 0, 0, 650, 650]**** [1], [1],[1] -[225 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),   80(  128),  16080(  90240),  1b,       65 ||||  L2, DMA,    2c0(   704),    2c0(   704),   80(  128),  16000(  90112),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    2bf(   703),    3(    3),    900(   2304),  1b,       65 
  WT:DDR_PERSIST, DMA,     81(   129),     81(   129),    3(    3),    200(    512),   0,   a9cc80 ||||  L2, DMA,     c0(   192),     81(   129),    3(    3),    280(    640),   0,    16000 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 1,  1], Required OUT : [ 0,  1],  To fill zero OUT: [ 0,  0]
------  227(TIDL_ConcatLayer) [228, 227] --[67 x 25 x  25] => [67 x 25 x  25] *** [67] ***[ COL] ***[0, 0, 0, 650, 650]**** [67], [0],[67] -[219 226 ]---
  IN:MSMC, DMA,    2c0(   704),    2bf(   703),   40(   64),   b080(  45184),  1b,    580e5 ||||  L2, DMA,    2d8(   728),    2d8(   728),    2(    2),    600(   1536),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    2c0(   704),    271(   625),   43(   67),   b900(  47360),   0,     a480 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 1,  1] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  230(TIDL_DataConvertLayer) [229, 230] --[67 x 25 x  25] => [67 x 25 x  25] *** [67] ***[ COL] ***[0, 0, 0, 625, 625]**** [67], [0],[67] -[227 ]---
  IN:MSMC, DMA,    2c0(   704),    271(   625),   43(   67),   b900(  47360),   0,     a480 ||||  L2, DMA,    271(   625),    271(   625),    2(    2),    500(   1280),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,    271(   625),    271(   625),   43(   67),   a480(  42112),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  233(TIDL_ReshapeLayer) [230, 233] --[67 x 25 x  25] => [1 x 625 x  67] *** [67] ***[ COL] ***[0, 0, 0, 625, 625]**** [67], [0],[67] -[230 ]---
  IN:MSMC, DMA,    271(   625),    271(   625),   43(   67),   a480(  42112),   0,        0 ||||  L2, DMA,    271(   625),    271(   625),    2(    2),    500(   1280),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   a393( 41875),   a393( 41875),    1(    1),   a480(  42112),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  234(TIDL_ConcatLayer) [231, 234] --[1 x 10000 x  67] => [1 x 13125 x  67] *** [1] ***[ COL] ***[0, 0, 0, 120000, 670000]**** [6], [0],[6] -[231 232 233 ]---
  IN:MSMC, DMA,  a3930(670000),  a3930(670000),    1(    1),  a3a00( 670208),   0,   2ea800 ||||  L2, DMA,  3a980(240000),  3a980(240000),    1(    1),  3a980( 240000),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  d6b40(879424),  d6b0f(879375),    1(    1),  d6c00( 879616),   0,    d6d00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  236(TIDL_SliceLayer) [232, 236] --[1 x 13125 x  67] => [1 x 13125 x  3] *** [1] ***[ COL] ***[0, 0, 0, 26250, 879375]**** [2], [0],[2] -[234 ]---
  IN:MSMC, DMA,  d6b40(879424),  d6b0f(879375),    1(    1),  d6c00( 879616),   0,    d6d00 ||||  L2, DMA,   cd14( 52500),   cd14( 52500),    1(    1),   cd80(  52608),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   9a40( 39488),   99cf( 39375),    1(    1),   9b00(  39680),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  237(TIDL_BatchNormLayer) [233, 237] --[1 x 13125 x  3] => [1 x 13125 x  3] *** [1] ***[ COL] ***[0, 0, 0, 39375, 39375]**** [1], [0],[1] -[236 ]---
  IN:MSMC, DMA,   9a40( 39488),   99cf( 39375),    1(    1),   9b00(  39680),   0,        0 ||||  L2, DMA,   cd14( 52500),   cd14( 52500),    1(    1),   cd80(  52608),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   9a40( 39488),   99cf( 39375),    1(    1),   9b00(  39680),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  235(TIDL_SliceLayer) [234, 235] --[1 x 13125 x  67] => [1 x 13125 x  64] *** [1] ***[ COL] ***[0, 0, 0, 210000, 879375]**** [4], [0],[4] -[234 ]---
  IN:MSMC, DMA,  d6b40(879424),  d6b0f(879375),    1(    1),  d6c00( 879616),   0,    d6d00 ||||  L2, DMA,  668a0(420000),  668a0(420000),    1(    1),  66900( 420096),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  cd140(840000),  cd140(840000),    1(    1),  cd200( 840192),   0,     9b00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  238(TIDL_ReshapeLayer) [235, 238] --[1 x 13125 x  64] => [4 x 500 x  420] *** [1] ***[ COL] ***[0, 0, 0, 223125, 840000]**** [1], [0],[1] -[235 ]---
  IN:MSMC, DMA,  cd140(840000),  cd140(840000),    1(    1),  cd200( 840192),   0,     9b00 ||||  L2, DMA,  6cf2a(446250),  6cf2a(446250),    1(    1),  6cf80( 446336),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  33450(210000),  33450(210000),    4(    4),  cd200( 840192),   0,     9b00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  239(TIDL_DataConvertLayer) [236, 239] --[4 x 500 x  420] => [420 x 4 x  500] *** [4] ***[ COL] ***[0, 0, 0, 30000, 210000]**** [7], [0],[7] -[238 ]---
  IN:MSMC, DMA,  33450(210000),  33450(210000),    4(    4),  cd200( 840192),   0,     9b00 ||||  L2, DMA,  3a980(240000),  3a980(240000),    1(    1),  3a980( 240000),   0,        0 
 OUT:MSMC, CPU,    7d0(  2000),    7d0(  2000),   d2(  210),  66900( 420096),   0,    d6d00 ||||MSMC, DMA,    7d0(  2000),    7d0(  2000),  1a4(  420),  cd200( 840192),   0,   13d600 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  240(TIDL_ReshapeLayer) [237, 240] --[4 x 500 x  420] => [1 x 4 x  1] *** [4] ***[ COL] ***[0, 0, 0, 210000, 210000]**** [4], [0],[4] -[239 ]---
  IN:MSMC, DMA,    7d0(  2000),    7d0(  2000),  1a4(  420),  cd200( 840192),   0,   13d600 ||||  L2, DMA,  33450(210000),  33450(210000),    2(    2),  66900( 420096),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,      4(     4),      4(     4),    1(    1),  cd200( 840192),   0,   13d600 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  241(TIDL_TransposeLayer) [238, 241] --[1 x 4 x  1] => [13125 x 4 x  16] *** [1] ***[ COL] ***[0, 0, 0, 4, 4]**** [1], [0],[1] -[240 ]---
  IN:MSMC, DMA,      4(     4),      4(     4),    1(    1),  cd200( 840192),   0,   13d600 ||||  L2, DMA,      4(     4),      4(     4),    1(    1),     80(    128),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     40(    64),     40(    64), 3345(13125),  cd200( 840192),   0,     9b00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  242(TIDL_SoftMaxLayer) [239, 242] --[13125 x 16 x  4] => [13125 x 16 x  4] *** [13125] ***[ COL] ***[0, 0, 0, 64, 64]**** [5], [0],[5] -[241 ]---
  IN:MSMC, DMA,     40(    64),     40(    64), 3345(13125),  cd200( 840192),   0,     9b00 ||||  L2, DMA,     40(    64),     40(    64), 1482( 5250),  52080( 336000),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,     40(    64),     40(    64), 3345(13125),  cd200( 840192),   0,     9b00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  243(TIDL_DataConvertLayer) [240, 243] --[13125 x 4 x  16] => [16 x 13125 x  4] *** [13125] ***[ COL] ***[0, 0, 0, 16, 64]**** [4], [0],[4] -[242 ]---
  IN:MSMC, DMA,     40(    64),     40(    64), 3345(13125),  cd200( 840192),   0,     9b00 ||||  L2, DMA,  668a0(420000),  668a0(420000),    1(    1),  66900( 420096),   0,        0 
 OUT:MSMC, CPU,   cd14( 52500),   cd14( 52500),    8(    8),  66900( 420096),   0,    d6d00 ||||MSMC, DMA,   cd14( 52500),   cd14( 52500),   10(   16),  cd200( 840192),   0,   13d600 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  244(TIDL_ReshapeLayer) [241, 244] --[13125 x 4 x  16] => [16 x 13125 x  4] *** [13125] ***[ COL] ***[0, 0, 0, 64, 64]**** [5], [0],[5] -[243 ]---
  IN:MSMC, DMA,   cd14( 52500),   cd14( 52500),   10(   16),  cd200( 840192),   0,   13d600 ||||  L2, DMA,     40(    64),     40(    64), 1482( 5250),  52080( 336000),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   cd14( 52500),   cd14( 52500),   10(   16),  cd200( 840192),   0,   13d600 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  245(TIDL_ConvolutionLayer) [242, 245] --[16 x 13125 x  4] => [1 x 13125 x  4] *** [16] ***[ROW_L] ***[0, 0, 0, 12992, 52500]**** [5], [1],[5] -[244 ]---
  IN:MSMC, DMA,   cd14( 52500),   cd14( 52500),   10(   16),  cd200( 840192),   0,   13d600 ||||  L2, DMA,   65c0( 26048),   65c0( 26048),   10(   16),  6f400( 455680),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   cd40( 52544),   cd14( 52500),    1(    1),   ce00(  52736),   0,     9b00 
  WT:DDR_PERSIST, DMA,     10(    16),     10(    16),    1(    1),     80(    128),   0,   a9ce80 ||||  L2, DMA,     10(    16),     10(    16),    1(    1),     80(    128),   0,    6f400 
 STG:MSMC, DMA_ONCE,     10(    16),     10(    16),    1(    1),     80(    128),   0,   7b9e80 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  246(TIDL_SliceLayer) [243, 246] --[1 x 13125 x  4] => [1 x 13125 x  2] *** [1] ***[ COL] ***[0, 0, 0, 52500, 52500]**** [1], [0],[1] -[245 ]---
  IN:MSMC, DMA,   cd40( 52544),   cd14( 52500),    1(    1),   ce00(  52736),   0,     9b00 ||||  L2, DMA,  10059( 65625),  10059( 65625),    1(    1),  10080(  65664),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   66c0( 26304),   668a( 26250),    1(    1),   6780(  26496),   0,    16900 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  1(TIDL_ConstDataLayer) [244, 1] --[3 x 800 x  800] => [1 x 13125 x  2] *** [3] ***[FRAME] ***[0, 0, 0, 640000, 640000]**** [1], [0],[1] -[]---
  IN: DDR, DMA, 271000(2560000),  9c400(640000),    1(    1), 753400(7681024),   0,        0 ||||MSMC, DMA,  9c400(640000),  9c400(640000),    2(    2), 138800(1280000),   0,    1d080 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||DDR_PERSIST, CPU,   668a( 26250),   668a( 26250),    1(    1),   6700(  26368),   0,   a9cf00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  249(TIDL_EltWiseLayer) [245, 249] --[2 x 13125 x  2] => [1 x 13125 x  2] *** [2] ***[ COL] ***[0, 0, 0, 26250, 26250]**** [1], [0],[1] -[1 246 ]---
  IN:DDR_PERSIST, DMA,   668a( 26250),   668a( 26250),    1(    1),   6700(  26368),   0,   a9cf00 ||||  L2, DMA,   99cf( 39375),   99cf( 39375),    2(    2),  26780( 157568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   66c0( 26304),   668a( 26250),    1(    1),   6780(  26496),   0,    16900 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  247(TIDL_SliceLayer) [246, 247] --[1 x 13125 x  4] => [1 x 13125 x  2] *** [1] ***[ COL] ***[0, 0, 0, 52500, 52500]**** [1], [0],[1] -[245 ]---
  IN:MSMC, DMA,   cd40( 52544),   cd14( 52500),    1(    1),   ce00(  52736),   0,     9b00 ||||  L2, DMA,  10059( 65625),  10059( 65625),    1(    1),  10080(  65664),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   66c0( 26304),   668a( 26250),    1(    1),   6780(  26496),   0,    1d080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  248(TIDL_BatchNormLayer) [247, 248] --[1 x 13125 x  2] => [1 x 13125 x  2] *** [1] ***[ COL] ***[0, 0, 0, 26250, 26250]**** [1], [0],[1] -[247 ]---
  IN:MSMC, DMA,   66c0( 26304),   668a( 26250),    1(    1),   6780(  26496),   0,    1d080 ||||  L2, DMA,   99cf( 39375),   99cf( 39375),    1(    1),   9a00(  39424),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   66c0( 26304),   668a( 26250),    1(    1),   6780(  26496),   0,     9b00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  2(TIDL_ConstDataLayer) [248, 2] --[3 x 800 x  800] => [1 x 13125 x  2] *** [3] ***[FRAME] ***[0, 0, 0, 640000, 640000]**** [1], [0],[1] -[]---
  IN: DDR, DMA, 271000(2560000),  9c400(640000),    1(    1), 753400(7681024),   0,        0 ||||MSMC, DMA,  9c400(640000),  9c400(640000),    2(    2), 138800(1280000),   0,    1d080 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||DDR_PERSIST, CPU,   668a( 26250),   668a( 26250),    1(    1),   6700(  26368),   0,   aa3600 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  250(TIDL_EltWiseLayer) [249, 250] --[2 x 13125 x  2] => [1 x 13125 x  2] *** [2] ***[ COL] ***[0, 0, 0, 26250, 26250]**** [1], [0],[1] -[2 248 ]---
  IN:DDR_PERSIST, DMA,   668a( 26250),   668a( 26250),    1(    1),   6700(  26368),   0,   aa3600 ||||  L2, DMA,   99cf( 39375),   99cf( 39375),    2(    2),  26780( 157568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   66c0( 26304),   668a( 26250),    1(    1),   6780(  26496),   0,    1d080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  251(TIDL_EltWiseLayer) [250, 251] --[2 x 13125 x  2] => [1 x 13125 x  2] *** [2] ***[ COL] ***[0, 0, 0, 26250, 26250]**** [1], [0],[1] -[250 249 ]---
  IN:MSMC, DMA,   66c0( 26304),   668a( 26250),    1(    1),   6780(  26496),   0,    1d080 ||||  L2, DMA,   99cf( 39375),   99cf( 39375),    2(    2),  26780( 157568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   66c0( 26304),   668a( 26250),    1(    1),   6780(  26496),   0,     9b00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  252(TIDL_BatchNormLayer) [251, 252] --[1 x 13125 x  2] => [1 x 13125 x  2] *** [1] ***[ COL] ***[0, 0, 0, 26250, 26250]**** [1], [0],[1] -[251 ]---
  IN:MSMC, DMA,   66c0( 26304),   668a( 26250),    1(    1),   6780(  26496),   0,     9b00 ||||  L2, DMA,   99cf( 39375),   99cf( 39375),    1(    1),   9a00(  39424),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   66c0( 26304),   668a( 26250),    1(    1),   6780(  26496),   0,     9b00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  253(TIDL_BatchNormLayer) [252, 253] --[1 x 13125 x  2] => [1 x 13125 x  2] *** [1] ***[ COL] ***[0, 0, 0, 26250, 26250]**** [1], [0],[1] -[250 ]---
  IN:MSMC, DMA,   66c0( 26304),   668a( 26250),    1(    1),   6780(  26496),   0,    1d080 ||||  L2, DMA,   99cf( 39375),   99cf( 39375),    1(    1),   9a00(  39424),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   66c0( 26304),   668a( 26250),    1(    1),   6780(  26496),   0,    1d080 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  254(TIDL_EltWiseLayer) [253, 254] --[2 x 13125 x  2] => [1 x 13125 x  2] *** [2] ***[ COL] ***[0, 0, 0, 26250, 26250]**** [1], [0],[1] -[249 253 ]---
  IN:MSMC, DMA,   66c0( 26304),   668a( 26250),    1(    1),   6780(  26496),   0,    16900 ||||  L2, DMA,   99cf( 39375),   99cf( 39375),    2(    2),  26780( 157568),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   66c0( 26304),   668a( 26250),    1(    1),   6780(  26496),   0,    10280 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  255(TIDL_ConcatLayer) [254, 255] --[1 x 13125 x  2] => [1 x 13125 x  4] *** [1] ***[ COL] ***[0, 0, 0, 26250, 26250]**** [1], [0],[1] -[252 254 ]---
  IN:MSMC, DMA,   66c0( 26304),   668a( 26250),    1(    1),   6780(  26496),   0,     9b00 ||||  L2, DMA,   99cf( 39375),   99cf( 39375),    2(    2),  13400(  78848),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   cd40( 52544),   cd14( 52500),    1(    1),   ce00(  52736),   0,    16a00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  3(TIDL_ConstDataLayer) [255, 3] --[3 x 800 x  800] => [1 x 13125 x  1] *** [3] ***[FRAME] ***[0, 0, 0, 640000, 640000]**** [1], [0],[1] -[]---
  IN: DDR, DMA, 271000(2560000),  9c400(640000),    1(    1), 753400(7681024),   0,        0 ||||MSMC, DMA,  9c400(640000),  9c400(640000),    2(    2), 138800(1280000),   0,    23800 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||DDR_PERSIST, CPU,   3345( 13125),   3345( 13125),    1(    1),   3380(  13184),   0,   aa9d00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  256(TIDL_EltWiseLayer) [256, 256] --[2 x 13125 x  4] => [1 x 13125 x  4] *** [2] ***[ COL] ***[0, 0, 0, 52500, 52500]**** [1], [0],[1] -[255 3 ]---
  IN:MSMC, DMA,   cd40( 52544),   cd14( 52500),    1(    1),   ce00(  52736),   0,    16a00 ||||  L2, DMA,  10059( 65625),  10059( 65625),    2(    2),  40180( 262528),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,   cd40( 52544),   cd14( 52500),    1(    1),   ce00(  52736),   0,    23800 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  257(TIDL_ConcatLayer) [257, 257] --[1 x 13125 x  4] => [1 x 13125 x  7] *** [1] ***[ COL] ***[0, 0, 0, 52500, 52500]**** [1], [0],[1] -[256 237 ]---
  IN:MSMC, DMA,   cd40( 52544),   cd14( 52500),    1(    1),   ce00(  52736),   0,    23800 ||||  L2, DMA,  10059( 65625),  10059( 65625),    2(    2),  20100( 131328),   0,        0 
 OUT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||MSMC, CPU,  16740( 91968),  166e3( 91875),    1(    1),  16800(  92160),   0,     9b00 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
------  258(TIDL_DataConvertLayer) [258, 258] --[1 x 13125 x  7] => [1 x 13125 x  7] *** [1] ***[ COL] ***[0, 0, 0, 52500, 91875]**** [2], [0],[2] -[257 ]---
  IN:MSMC, DMA,  16740( 91968),  166e3( 91875),    1(    1),  16800(  92160),   0,     9b00 ||||  L2, DMA,  19a28(105000),  19a28(105000),    1(    1),  19a80( 105088),   0,        0 
 OUT:MSMC, CPU,  33450(210000),  33450(210000),    2(    2),  66900( 420096),   0,    20300 |||| DDR, DMA,  59b8c(367500),  59b8c(367500),    1(    1),  5a000( 368640),   0,        0 
  WT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff ||||NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
 STG:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
CONT:NONE,  NA,      0(     0),      0(     0),    0(    0),      0(      0),   0, ffffffff 
Padding Info [Row, Col]: Actual  IN -> OUT : [ 0,  0] -> [ 0,  0], Required OUT : [ 0,  0],  To fill zero OUT: [ 0,  0]
