;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; 09 Aug 19 - Richard Woodruff - Create.
; 17 Feb 20 - Richard Woodruff - update for J7ES.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

Step 1: Enter DDR information into DDR Config XLS
Step 2: Generate GEL file "J7-DDR-EVM-LP4-3733.gel" from XLS
Step 3: Create a new file J7_DDR_EVM_LP4_3733.gel merging J7-DDR-addr-map-offs.gel + J7-DDR-EVM-LP4-3733.gel + J7_DDR_config.gel
Step 4: Merge in GEL differences from the EVM template.  Do not overwrite J7_DDR_config.gel updates /* Need to file bugs on converter */
Step 5: Generate a CMM using the gel converter. gelconverter <filea>.gel <filea>.cmm
Step 6: Merge template CMM fixes into newly created CMM file. /* Need to file bugs on converter */
Step 7: Connect with a TRACE32 PowerView instance and run the script "run_all_ddr_test.cmm"
Step 8: If the A72 memtester starts, enter a buffer base address of 0x81000000 with a size suitable for testing.
        Note: The prints are a bit slow as the TI-CC semi-host patch for AARCH32 doesn't buffer and each char goes to the host and back
        Note: An AARCH64 memtester can also be run which has a cleaner semi-host interface as its GCC based.
