From 4d276c7ced40199849cae95415fa7fac44fe350f Mon Sep 17 00:00:00 2001 From: Bas Vermeulen Date: Tue, 3 Mar 2026 13:52:41 +0100 Subject: [PATCH] updated memory map --- repo/vision_apps/platform/am62a/rtos/app_mem_map.h | 22 ++++++------ repo/vision_apps/platform/am62a/rtos/c7x_1/example.syscfg | 34 +++++++++---------- repo/vision_apps/platform/am62a/rtos/c7x_1/linker_mem_map.cmd | 14 ++++---- repo/vision_apps/platform/am62a/rtos/mcu1_0/example.syscfg | 6 ++-- repo/vision_apps/platform/am62a/rtos/mcu1_0/linker_mem_map.cmd | 12 +++---- repo/vision_apps/platform/am62a/rtos/system_memory_map.html | 32 ++++++++--------- 6 files changed, 60 insertions(+), 60 deletions(-) diff --git a/repo/vision_apps/platform/am62a/rtos/app_mem_map.h b/repo/vision_apps/platform/am62a/rtos/app_mem_map.h index c93a3ae..ea8a255 100755 --- a/repo/vision_apps/platform/am62a/rtos/app_mem_map.h +++ b/repo/vision_apps/platform/am62a/rtos/app_mem_map.h @@ -123,37 +123,37 @@ #define TIOVX_LOG_RT_MEM_ADDR (0xA2400000u) #define TIOVX_LOG_RT_MEM_SIZE (0x00C00000u) -/* Memory for shared memory buffers in DDR [ size 172.00 MB ] */ +/* Memory for shared memory buffers in DDR [ size 252.00 MB ] */ #define DDR_SHARED_MEM_ADDR (0xA3000000u) -#define DDR_SHARED_MEM_SIZE (0x0AC00000u) +#define DDR_SHARED_MEM_SIZE (0x0FC00000u) /* DDR for storing DMA buffers for VISS configuration [ size 4.00 MB ] */ -#define DDR_DM_R5F_VISS_CONFIG_HEAP_ADDR (0xADC00000u) +#define DDR_DM_R5F_VISS_CONFIG_HEAP_ADDR (0xB2C00000u) #define DDR_DM_R5F_VISS_CONFIG_HEAP_SIZE (0x00400000u) /* DDR for MCU R5F for local heap [ size 16.00 MB ] */ -#define DDR_MCU_R5F_LOCAL_HEAP_ADDR (0xAE000000u) +#define DDR_MCU_R5F_LOCAL_HEAP_ADDR (0xB3000000u) #define DDR_MCU_R5F_LOCAL_HEAP_SIZE (0x01000000u) /* DDR for DM R5F for local heap [ size 16.00 MB ] */ -#define DDR_DM_R5F_LOCAL_HEAP_ADDR (0xAF000000u) +#define DDR_DM_R5F_LOCAL_HEAP_ADDR (0xB4000000u) #define DDR_DM_R5F_LOCAL_HEAP_SIZE (0x01000000u) /* DDR for c7x_1 for non cacheable local heap [ size 16.00 MB ] */ -#define DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_ADDR (0xB0000000u) +#define DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_ADDR (0xB5000000u) #define DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_SIZE (0x01000000u) /* DDR for c7x_1 for non cacheable scratch Memory [ size 16.00 MB ] */ -#define DDR_C7X_1_SCRATCH_NON_CACHEABLE_ADDR (0xB1000000u) +#define DDR_C7X_1_SCRATCH_NON_CACHEABLE_ADDR (0xB6000000u) #define DDR_C7X_1_SCRATCH_NON_CACHEABLE_SIZE (0x01000000u) /* DDR for c7x_1 for local heap [ size 112.00 MB ] */ -#define DDR_C7X_1_LOCAL_HEAP_ADDR (0xB2000000u) +#define DDR_C7X_1_LOCAL_HEAP_ADDR (0xB7000000u) #define DDR_C7X_1_LOCAL_HEAP_SIZE (0x07000000u) -/* DDR for c7x_1 for Scratch Memory [ size 112.00 MB ] */ -#define DDR_C7X_1_SCRATCH_ADDR (0xB9000000u) -#define DDR_C7X_1_SCRATCH_SIZE (0x07000000u) +/* DDR for c7x_1 for Scratch Memory [ size 32.00 MB ] */ +#define DDR_C7X_1_SCRATCH_ADDR (0xBE000000u) +#define DDR_C7X_1_SCRATCH_SIZE (0x02000000u) #define DDR_64BIT_BASE_VADDR (0x00000000u) #define DDR_64BIT_BASE_PADDR (0x00000000u) diff --git a/repo/vision_apps/platform/am62a/rtos/c7x_1/example.syscfg b/repo/vision_apps/platform/am62a/rtos/c7x_1/example.syscfg index 0a00d3e..d7c49d5 100644 --- a/repo/vision_apps/platform/am62a/rtos/c7x_1/example.syscfg +++ b/repo/vision_apps/platform/am62a/rtos/c7x_1/example.syscfg @@ -68,14 +68,14 @@ mmu_armv87.pAddr = 0x7C400000; mmu_armv87.size = 0x100000; mmu_armv87.$name = "DRU"; -mmu_armv88.vAddr = 0x7E000000; -mmu_armv88.pAddr = 0x7E000000; +mmu_armv88.vAddr = 0x7E000000; +mmu_armv88.pAddr = 0x7E000000; mmu_armv88.$name = "L2RAM_C7x_1_MAIN"; -mmu_armv88.size = 0x1000000; +mmu_armv88.size = 0x100000; -mmu_armv89.vAddr = 0x7F000000; -mmu_armv89.pAddr = 0x7F000000; -mmu_armv89.size = 0x1000000; +mmu_armv89.vAddr = 0x7F000000; +mmu_armv89.pAddr = 0x7F000000; +mmu_armv89.size = 0x03C000; mmu_armv89.$name = "L2RAM_C7x_1_AUX"; mmu_armv810.attribute = "MAIR7"; @@ -87,25 +87,25 @@ mmu_armv810.size = 0xF00000; mmu_armv811.$name = "DDR_SHARED_MEM"; mmu_armv811.vAddr = 0xA3000000; mmu_armv811.pAddr = 0xA3000000; -mmu_armv811.size = 0xAC00000; +mmu_armv811.size = 0xFC00000; mmu_armv811.attribute = "MAIR7"; -mmu_armv812.vAddr = 0xB2000000; -mmu_armv812.pAddr = 0xB2000000; +mmu_armv812.vAddr = 0xB7000000; +mmu_armv812.pAddr = 0xB7000000; mmu_armv812.size = 0x7000000; mmu_armv812.$name = "DDR_C7X_1_LOCAL_HEAP"; mmu_armv812.attribute = "MAIR7"; mmu_armv813.$name = "DDR_C7X_1_SCRATCH"; mmu_armv813.attribute = "MAIR7"; -mmu_armv813.vAddr = 0xB9000000; -mmu_armv813.pAddr = 0xB9000000; -mmu_armv813.size = 0x7000000; +mmu_armv813.vAddr = 0xBE000000; +mmu_armv813.pAddr = 0xBE000000; +mmu_armv813.size = 0x2000000; mmu_armv814.attribute = "MAIR4"; mmu_armv814.vAddr = 0xA1000000; mmu_armv814.pAddr = 0xA1000000; -mmu_armv814.size = 0x40000; +mmu_armv814.size = 0x040000; mmu_armv814.$name = "APP_LOG_MEM"; mmu_armv815.$name = "APP_FILEIO_MEM"; @@ -139,13 +139,13 @@ mmu_armv819.attribute = "MAIR4"; mmu_armv819.$name = "TIOVX_LOG_RT_MEM"; mmu_armv820.$name = "DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE"; -mmu_armv820.vAddr = 0xB0000000; +mmu_armv820.vAddr = 0xB5000000; mmu_armv820.size = 0x1000000; -mmu_armv820.pAddr = 0xB0000000; +mmu_armv820.pAddr = 0xB5000000; mmu_armv820.attribute = "MAIR4"; mmu_armv821.$name = "DDR_C7X_1_SCRATCH_NON_CACHEABLE"; -mmu_armv821.vAddr = 0xB1000000; -mmu_armv821.pAddr = 0xB1000000; +mmu_armv821.vAddr = 0xB6000000; +mmu_armv821.pAddr = 0xB6000000; mmu_armv821.size = 0x1000000; mmu_armv821.attribute = "MAIR4"; diff --git a/repo/vision_apps/platform/am62a/rtos/c7x_1/linker_mem_map.cmd b/repo/vision_apps/platform/am62a/rtos/c7x_1/linker_mem_map.cmd index 14e8d36..4bae76c 100644 --- a/repo/vision_apps/platform/am62a/rtos/c7x_1/linker_mem_map.cmd +++ b/repo/vision_apps/platform/am62a/rtos/c7x_1/linker_mem_map.cmd @@ -92,14 +92,14 @@ MEMORY TIOVX_OBJ_DESC_MEM : ORIGIN = 0xA1040000 , LENGTH = 0x00FC0000 /* Memory for remote core file operations [ size 4.00 MB ] */ APP_FILEIO_MEM : ORIGIN = 0xA2000000 , LENGTH = 0x00400000 - /* Memory for shared memory buffers in DDR [ size 172.00 MB ] */ - DDR_SHARED_MEM : ORIGIN = 0xA3000000 , LENGTH = 0x0AC00000 + /* Memory for shared memory buffers in DDR [ size 252.00 MB ] */ + DDR_SHARED_MEM : ORIGIN = 0xA3000000 , LENGTH = 0x0FC00000 /* DDR for c7x_1 for non cacheable local heap [ size 16.00 MB ] */ - DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE ( RWIX ) : ORIGIN = 0xB0000000 , LENGTH = 0x01000000 + DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE ( RWIX ) : ORIGIN = 0xB5000000 , LENGTH = 0x01000000 /* DDR for c7x_1 for non cacheable scratch Memory [ size 16.00 MB ] */ - DDR_C7X_1_SCRATCH_NON_CACHEABLE ( RWIX ) : ORIGIN = 0xB1000000 , LENGTH = 0x01000000 + DDR_C7X_1_SCRATCH_NON_CACHEABLE ( RWIX ) : ORIGIN = 0xB6000000 , LENGTH = 0x01000000 /* DDR for c7x_1 for local heap [ size 112.00 MB ] */ - DDR_C7X_1_LOCAL_HEAP ( RWIX ) : ORIGIN = 0xB2000000 , LENGTH = 0x07000000 - /* DDR for c7x_1 for Scratch Memory [ size 112.00 MB ] */ - DDR_C7X_1_SCRATCH ( RWIX ) : ORIGIN = 0xB9000000 , LENGTH = 0x07000000 + DDR_C7X_1_LOCAL_HEAP ( RWIX ) : ORIGIN = 0xB7000000 , LENGTH = 0x07000000 + /* DDR for c7x_1 for Scratch Memory [ size 32.00 MB ] */ + DDR_C7X_1_SCRATCH ( RWIX ) : ORIGIN = 0xBE000000 , LENGTH = 0x02000000 } diff --git a/repo/vision_apps/platform/am62a/rtos/mcu1_0/example.syscfg b/repo/vision_apps/platform/am62a/rtos/mcu1_0/example.syscfg index 093f7e4..1953db2 100644 --- a/repo/vision_apps/platform/am62a/rtos/mcu1_0/example.syscfg +++ b/repo/vision_apps/platform/am62a/rtos/mcu1_0/example.syscfg @@ -64,7 +64,7 @@ mpu_armv75.tex = 5; mpu_armv75.isCacheable = false; mpu_armv76.baseAddr = 0x9C800000; -mpu_armv76.size = 21; +mpu_armv76.size = 20; mpu_armv76.$name = "IPC_VRING_RESOURCE_TABLE_LINUX"; mpu_armv76.attributes = "CUSTOM"; mpu_armv76.tex = 0; @@ -88,7 +88,7 @@ mpu_armv78.isCacheable = false; mpu_armv78.isBufferable = false; mpu_armv78.tex = 0; mpu_armv78.baseAddr = 0xA1000000; -mpu_armv78.size = 24; +mpu_armv78.size = 18; mpu_armv79.$name = "TIOVX_RUN_TIME_LOGGING2"; mpu_armv79.allowExecute = false; @@ -97,7 +97,7 @@ mpu_armv79.isCacheable = false; mpu_armv79.isBufferable = false; mpu_armv79.tex = 0; mpu_armv79.baseAddr = 0xA2000000; -mpu_armv79.size = 24; +mpu_armv79.size = 22; mpu_armv710.$name = "DDR_DM_R5F_VISS_CONFIG_HEAP"; mpu_armv710.size = 22; diff --git a/repo/vision_apps/platform/am62a/rtos/mcu1_0/linker_mem_map.cmd b/repo/vision_apps/platform/am62a/rtos/mcu1_0/linker_mem_map.cmd index f3b328a..721a80b 100644 --- a/repo/vision_apps/platform/am62a/rtos/mcu1_0/linker_mem_map.cmd +++ b/repo/vision_apps/platform/am62a/rtos/mcu1_0/linker_mem_map.cmd @@ -4,7 +4,7 @@ */ /* * - * Copyright (c) 2018 Texas Instruments Incorporated + * Copyright (c) 2024 Texas Instruments Incorporated * * All rights reserved not granted herein. * @@ -94,10 +94,10 @@ MEMORY TIOVX_OBJ_DESC_MEM : ORIGIN = 0xA1040000 , LENGTH = 0x00FC0000 /* Memory for remote core file operations [ size 4.00 MB ] */ APP_FILEIO_MEM : ORIGIN = 0xA2000000 , LENGTH = 0x00400000 - /* Memory for shared memory buffers in DDR [ size 172.00 MB ] */ - DDR_SHARED_MEM : ORIGIN = 0xA3000000 , LENGTH = 0x0AC00000 - /* Memory for storing DMA buffers for VISS configuration [ size 4.00 MB ] */ - DDR_DM_R5F_VISS_CONFIG_HEAP ( RW ) : ORIGIN = 0xADC00000 , LENGTH = 0x00400000 + /* Memory for shared memory buffers in DDR [ size 252.00 MB ] */ + DDR_SHARED_MEM : ORIGIN = 0xA3000000 , LENGTH = 0x0FC00000 + /* DDR for storing DMA buffers for VISS configuration [ size 4.00 MB ] */ + DDR_DM_R5F_VISS_CONFIG_HEAP ( RW ) : ORIGIN = 0xB2C00000 , LENGTH = 0x00400000 /* DDR for DM R5F for local heap [ size 16.00 MB ] */ - DDR_DM_R5F_LOCAL_HEAP ( RWIX ) : ORIGIN = 0xAF000000 , LENGTH = 0x01000000 + DDR_DM_R5F_LOCAL_HEAP ( RWIX ) : ORIGIN = 0xB4000000 , LENGTH = 0x01000000 } diff --git a/repo/vision_apps/platform/am62a/rtos/system_memory_map.html b/repo/vision_apps/platform/am62a/rtos/system_memory_map.html index 53526ca..94b4d96 100644 --- a/repo/vision_apps/platform/am62a/rtos/system_memory_map.html +++ b/repo/vision_apps/platform/am62a/rtos/system_memory_map.html @@ -227,64 +227,64 @@ DDR_SHARED_MEM 0xA3000000 - 0xADBFFFFF - 172.00 MB + 0xB2BFFFFF + 252.00 MB Memory for shared memory buffers in DDR DDR_DM_R5F_VISS_CONFIG_HEAP - 0xADC00000 - 0xADFFFFFF + 0xB2C00000 + 0xB2FFFFFF 4.00 MB RW DDR for storing DMA buffers for VISS configuration DDR_MCU_R5F_LOCAL_HEAP - 0xAE000000 - 0xAEFFFFFF + 0xB3000000 + 0xB3FFFFFF 16.00 MB RWIX DDR for MCU R5F for local heap DDR_DM_R5F_LOCAL_HEAP - 0xAF000000 - 0xAFFFFFFF + 0xB4000000 + 0xB4FFFFFF 16.00 MB RWIX DDR for DM R5F for local heap DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE - 0xB0000000 - 0xB0FFFFFF + 0xB5000000 + 0xB5FFFFFF 16.00 MB RWIX DDR for c7x_1 for non cacheable local heap DDR_C7X_1_SCRATCH_NON_CACHEABLE - 0xB1000000 - 0xB1FFFFFF + 0xB6000000 + 0xB6FFFFFF 16.00 MB RWIX DDR for c7x_1 for non cacheable scratch Memory DDR_C7X_1_LOCAL_HEAP - 0xB2000000 - 0xB8FFFFFF + 0xB7000000 + 0xBDFFFFFF 112.00 MB RWIX DDR for c7x_1 for local heap DDR_C7X_1_SCRATCH - 0xB9000000 + 0xBE000000 0xBFFFFFFF - 112.00 MB + 32.00 MB RWIX DDR for c7x_1 for Scratch Memory -- 2.43.0