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C<2x%~%mpu_dpll_hs_clk_divfixed-factor-clock%x&~&dpll_mpu_ckti,omap5-mpu-dpll-clock&C`dlhx~dpll_mpu_m2_ckti,divider-clock Cp2x'~'mpu_dclk_divfixed-factor-clock'x~dsp_dpll_hs_clk_divfixed-factor-clock%x(~(dpll_dsp_byp_mux ti,mux-clock(C@x)~)dpll_dsp_ckti,omap4-dpll-clock)C48@<_*o#Fx*~*dpll_dsp_m2_ckti,divider-clock* CD2_+o#Fx+~+iva_dpll_hs_clk_divfixed-factor-clock%x,~,dpll_iva_byp_mux ti,mux-clock,Cx-~-dpll_iva_ckti,omap4-dpll-clock-C_.oEp}@x.~.dpll_iva_m2_ckti,divider-clock. C2_/o%x/~/iva_dclkfixed-factor-clock/x~dpll_gpu_byp_mux ti,mux-clock!Cx0~0dpll_gpu_ckti,omap4-dpll-clock0C_1oLy@x1~1dpll_gpu_m2_ckti,divider-clock1 C2_2o_(kx2~2dpll_core_m2_ckti,divider-clock# C02x3~3core_dpll_out_dclk_divfixed-factor-clock3x~dpll_ddr_byp_mux ti,mux-clock!Cx4~4dpll_ddr_ckti,omap4-dpll-clock4Cx5~5dpll_ddr_m2_ckti,divider-clock5 C 2x~dpll_gmac_byp_mux ti,mux-clock!Cx6~6dpll_gmac_ckti,omap4-dpll-clock6Cx7~7dpll_gmac_m2_ckti,divider-clock7 C2x~video2_dclk_divfixed-factor-clock8x~video1_dclk_divfixed-factor-clock9x~hdmi_dclk_divfixed-factor-clock:x~per_dpll_hs_clk_divfixed-factor-clock!xi~iusb_dpll_hs_clk_divfixed-factor-clock!xm~meve_dpll_hs_clk_divfixed-factor-clock%x;~;dpll_eve_byp_mux ti,mux-clock;Cx<~<dpll_eve_ckti,omap4-dpll-clock<Cx=~=dpll_eve_m2_ckti,divider-clock= C2x>~>eve_dclk_divfixed-factor-clock>x~dpll_core_h13x2_ckti,divider-clock$? C@2dpll_core_h14x2_ckti,divider-clock$? CD2x}~}dpll_core_h22x2_ckti,divider-clock$? CT2xF~Fdpll_core_h23x2_ckti,divider-clock$? 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C2x~dpll_gmac_m3x2_ckti,divider-clockB C2gmii_m_clk_divfixed-factor-clockChdmi_clk2_divfixed-factor-clock:xY~Yhdmi_div_clkfixed-factor-clock:x_~_l3_iclk_divti,divider-clockC%Ix ~ l4_root_clk_divfixed-factor-clock x ~ video1_clk2_divfixed-factor-clockDxW~Wvideo1_div_clkfixed-factor-clockDx]~]video2_clk2_divfixed-factor-clockExX~Xvideo2_div_clkfixed-factor-clockEx^~^ipu1_gfclk_mux ti,mux-clock FC _GFxG~Gmcasp1_ahclkr_mux ti,mux-clock8HIJKLMNOPQRSTUCPx#~#mcasp1_ahclkx_mux ti,mux-clock8HIJKLMNOPQRSTUCPx"~"mcasp1_aux_gfclk_mux ti,mux-clockVWXYCPx!~!timer5_gfclk_mux ti,mux-clock0Z[OPQRS\]^_`CXtimer6_gfclk_mux ti,mux-clock0Z[OPQRS\]^_`C`timer7_gfclk_mux ti,mux-clock0Z[OPQRS\]^_`Chtimer8_gfclk_mux ti,mux-clock0Z[OPQRS\]^_`Cpuart6_gfclk_mux ti,mux-clockabCdummy_ck fixed-clockclockdomainscm_core@8000ti,dra7-cm-coreC0clocksdpll_pcie_ref_ckti,omap4-dpll-clockC xc~cdpll_pcie_ref_m2ldo_ckti,divider-clockc C2xd~dapll_pcie_in_clk_mux@4ae06118 ti,mux-clockdeCxf~fapll_pcie_ckti,dra7-apll-clockfcC xg~goptfclk_pciephy1_32khz@4a0093b0ti,gate-clock[Cx ~ optfclk_pciephy2_32khz@4a0093b8ti,gate-clock[Cx~optfclk_pciephy_div@4a00821cti,divider-clockgCxh~hoptfclk_pciephy1_clk@4a0093b0ti,gate-clockgC x ~ optfclk_pciephy2_clk@4a0093b8ti,gate-clockgC x~optfclk_pciephy1_div_clk@4a0093b0ti,gate-clockhC x~optfclk_pciephy2_div_clk@4a0093b8ti,gate-clockhC x~apll_pcie_clkvcoldofixed-factor-clockgapll_pcie_clkvcoldo_divfixed-factor-clockgapll_pcie_m2_ckfixed-factor-clockgx~dpll_per_byp_mux ti,mux-clockiCLxj~jdpll_per_ckti,omap4-dpll-clockjC@DLHxk~kdpll_per_m2_ckti,divider-clockk CP2xl~lfunc_96m_aon_dclk_divfixed-factor-clocklx~dpll_usb_byp_mux ti,mux-clockmCxn~ndpll_usb_ckti,omap4-dpll-j-type-clocknCxo~odpll_usb_m2_ckti,divider-clocko C2xr~rdpll_pcie_ref_m2_ckti,divider-clockc C2x~dpll_per_x2_ckti,omap4-dpll-x2-clockkxp~pdpll_per_h11x2_ckti,divider-clockp? CX2xq~qdpll_per_h12x2_ckti,divider-clockp? C\2xu~udpll_per_h13x2_ckti,divider-clockp? C`2x~dpll_per_h14x2_ckti,divider-clockp? Cd2x~~~dpll_per_m2x2_ckti,divider-clockp CP2xb~bdpll_usb_clkdcoldofixed-factor-clockoxt~tfunc_128m_clkfixed-factor-clockqx~func_12m_fclkfixed-factor-clockbfunc_24m_clkfixed-factor-clocklxJ~Jfunc_48m_fclkfixed-factor-clockbxa~afunc_96m_fclkfixed-factor-clockbl3init_60m_fclkti,divider-clockrCclkout2_clkti,gate-clocksCl3init_960m_gfclkti,gate-clocktCxy~ydss_32khz_clkti,gate-clock[ C dss_48mhz_clkti,gate-clocka C x@~@dss_dss_clkti,gate-clockuC x<~<dss_hdmi_clkti,gate-clockv C xA~Adss_video1_clkti,gate-clockw C x=~=dss_video2_clkti,gate-clockx C x>~>gpio2_dbclkti,gate-clock[C`gpio3_dbclkti,gate-clock[Chgpio4_dbclkti,gate-clock[Cpgpio5_dbclkti,gate-clock[Cxgpio6_dbclkti,gate-clock[Cgpio7_dbclkti,gate-clock[Cgpio8_dbclkti,gate-clock[Cmmc1_clk32kti,gate-clock[C(mmc2_clk32kti,gate-clock[C0mmc3_clk32kti,gate-clock[C mmc4_clk32kti,gate-clock[C(sata_ref_clkti,gate-clockCx ~ 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ti,mux-clockVWXYCx.~.mcasp7_ahclkx_mux ti,mux-clock8HIJKLMNOPQRSTUCx2~2mcasp7_aux_gfclk_mux ti,mux-clockVWXYCx1~1mcasp8_ahclkx_mux ti,mux-clock8HIJKLMNOPQRSTUCx5~5mcasp8_aux_gfclk_mux ti,mux-clockVWXYCx4~4mmc1_fclk_mux ti,mux-clockbC(x~mmc1_fclk_divti,divider-clockC(Immc2_fclk_mux ti,mux-clockbC0x~mmc2_fclk_divti,divider-clockC0Immc3_gfclk_mux ti,mux-clockabC x~mmc3_gfclk_divti,divider-clockC Immc4_gfclk_mux ti,mux-clockabC(x~mmc4_gfclk_divti,divider-clockC(Iqspi_gfclk_mux ti,mux-clockC8x~qspi_gfclk_divti,divider-clockC8Ix ~ timer10_gfclk_mux ti,mux-clock,Z[OPQRS\]^_C(timer11_gfclk_mux ti,mux-clock,Z[OPQRS\]^_C0timer13_gfclk_mux ti,mux-clock,Z[OPQRS\]^_Ctimer14_gfclk_mux ti,mux-clock,Z[OPQRS\]^_Ctimer15_gfclk_mux ti,mux-clock,Z[OPQRS\]^_Ctimer16_gfclk_mux ti,mux-clock,Z[OPQRS\]^_C0timer2_gfclk_mux ti,mux-clock,Z[OPQRS\]^_C8timer3_gfclk_mux ti,mux-clock,Z[OPQRS\]^_C@timer4_gfclk_mux ti,mux-clock,Z[OPQRS\]^_CHtimer9_gfclk_mux ti,mux-clock,Z[OPQRS\]^_CPuart1_gfclk_mux ti,mux-clockabC@uart2_gfclk_mux ti,mux-clockabCHuart3_gfclk_mux ti,mux-clockabCPuart4_gfclk_mux ti,mux-clockabCXuart5_gfclk_mux ti,mux-clockabCpuart7_gfclk_mux ti,mux-clockabCuart8_gfclk_mux ti,mux-clockabCuart9_gfclk_mux ti,mux-clockabCvip1_gclk_mux ti,mux-clock C vip2_gclk_mux ti,mux-clock C(vip3_gclk_mux ti,mux-clock C0clockdomainscoreaon_clkdmti,clockdomainol4@4ae00000ti,dra7-l4-wkupsimple-bus rJcounter@4000ti,omap-counter32kC@@ hcounter_32kprm@6000 ti,dra7-prmC`0 Gclockssys_clkin1 ti,mux-clockCx~abe_dpll_sys_clk_mux ti,mux-clockOCx~abe_dpll_bypass_clk_mux ti,mux-clock[Cx~abe_dpll_clk_mux ti,mux-clock[C x~abe_24m_fclkti,divider-clock CxH~Haess_fclkti,divider-clockCxx~abe_giclk_divti,divider-clockCtx\~\abe_lp_clk_divti,divider-clock C x~abe_sys_clk_divti,divider-clockC xI~Iadc_gfclk_mux ti,mux-clock O[Csys_clk1_dclk_divti,divider-clock@CIx~sys_clk2_dclk_divti,divider-clockO@CIx~per_abe_x1_dclk_divti,divider-clockz@CIx~dsp_gclk_divti,divider-clock+@CIx~gpu_dclkti,divider-clock2@CIx~emif_phy_dclk_divti,divider-clock@CIx~gmac_250m_dclk_divti,divider-clock@CIx~gmac_main_clkfixed-factor-clockx6~6l3init_480m_dclk_divti,divider-clockr@CIx~usb_otg_dclk_divti,divider-clock@CIx~sata_dclk_divti,divider-clock@CIx~pcie2_dclk_divti,divider-clock@CIx~pcie_dclk_divti,divider-clock@CIx~emu_dclk_divti,divider-clock@CIx~secure_32k_dclk_divti,divider-clock@CIx~clkoutmux0_clk_mux ti,mux-clockXCXx`~`clkoutmux1_clk_mux ti,mux-clockXC\clkoutmux2_clk_mux ti,mux-clockXC`xs~scustefuse_sys_gfclk_divfixed-factor-clockeve_clk ti,mux-clock>AChdmi_dpll_clk_mux ti,mux-clockOCdxv~vmlb_clkti,divider-clock@C4IxT~Tmlbp_clkti,divider-clock@C0IxU~Uper_abe_x1_gfclk2_divti,divider-clockz@C8IxV~Vtimer_sys_clk_divti,divider-clockCDxZ~Zvideo1_dpll_clk_mux ti,mux-clockOChxw~wvideo2_dpll_clk_mux ti,mux-clockOClxx~xwkupaon_iclk_mux ti,mux-clockCx~gpio1_dbclkti,gate-clock[C8dcan1_sys_clk_mux ti,mux-clockOCx9~9timer1_gfclk_mux ti,mux-clock,Z[OPQRS\]^_C@uart10_gfclk_mux ti,mux-clockabCclockdomainsscm_conf@c000sysconCx~axi@0 simple-busrQQ0 pcie@51000000 ti,dra7-pcieCQ Q L rc_dbicsti_confconfigG7pci0r0 00ghpcie1 pcie-phy0`interrupt-controllerRgx~axi@1 simple-busrQQ00 disabledpcie@51800000 ti,dra7-pcieCQ Q L rc_dbicsti_confconfigGcd7pci0r0000ghpcie2 pcie-phy0`interrupt-controllerRgx~ocmcram@40300000 disabled mmio-sramC@0 r@0x`~`sram-hs@0ti,secure-ramCocmcram@40400000 disabled mmio-sramC@@ r@@ocmcram@40500000 disabled mmio-sramC@P r@Pbandgap@4a0021e00CJ! J#, J#,J#txrxokay?LZgt qC|defaulthssdr12sdr25sdr50ddr50-rev11sdr104-rev11ddr50sdr104  mmc@480b4000ti,dra7-hsmmcti,omap4-hsmmcCH @ GQhmmc2(/0txrxokay  q?|defaulthsddr_1_8v-rev11ddr_1_8vhs200_1_8v-rev11hs200_1_8vmmc@480ad000ti,dra7-hsmmcti,omap4-hsmmcCH  GYhmmc3(MNtxrx disabledtZmmc@480d1000ti,dra7-hsmmcti,omap4-hsmmcCH  G[hmmc4(9:txrxokay & 9F|default-rev11defaulths-rev11hssdr12-rev11sdr12sdr25-rev11sdr25 mmu@40d01000ti,dra7-dsp-iommuC@ G hmmu0_dsp1 O \okayx~mmu@40d02000ti,dra7-dsp-iommuC@  G hmmu1_dsp1 O \okayx~mmu@58882000ti,dra7-iommuCX  G hmmu_ipu1 O pokay9nx~mmu@55082000ti,dra7-iommuCU  G hmmu_ipu2 O pokay9nx~pruss@4b200000ti,am5728-prusshpruss10CK K K!K"` K"K# X$dram0dram1shrdram2cfgiepmii_rtr disabledintc@4b220000ti,am5728-pruss-intcCK" intc`G09host2host3host4host5host6host7host8host9Rgpru0@4b234000ti,am5728-pruCK#@0K" K"$iramcontroldebug disabledpru1@4b238000ti,am5728-pruCK#0K"@K"Diramcontroldebug disabledmdio@4b232400ti,davinci_mdiofck B@CK#$ disabledpruss@4b280000ti,am5728-prusshpruss20CK( K( K)K*` K*K+ X$dram0dram1shrdram2cfgiepmii_rtr disabledintc@4b2a0000ti,am5728-pruss-intcCK* intc`G09host2host3host4host5host6host7host8host9Rgpru0@4b2b4000ti,am5728-pruCK+@0K* K*$iramcontroldebug disabledpru1@4b2b8000ti,am5728-pruCK+0K*@K*Diramcontroldebug disabledmdio@4b2b2400ti,davinci_mdiofck B@CK+$ disabledregulator-abb-mpu ti,abb-v3abb_mpu 2 (CJ}J}J`J; JXDsetup-addresscontrol-addressint-addressefuse-addressldo-address   H ,@vx~regulator-abb-ivahd ti,abb-v3 abb_ivahd 2 (CJ~4J~$J`J% J$pDsetup-addresscontrol-addressint-addressefuse-addressldo-address @  H 0x~regulator-abb-dspeve ti,abb-v3 abb_dspeve 2 (CJ~0J~ J`J% J$lDsetup-addresscontrol-addressint-addressefuse-addressldo-address   H 0x~regulator-abb-gpu ti,abb-v3abb_gpu 2 (CJ}J}J`J; JTDsetup-addresscontrol-addressint-addressefuse-addressldo-address   H vx~oppdm@4a003b20ti,omap5-oppdm  CJ;  ,@v +` Fx~oppdm@4a0025ccti,omap5-oppdm  CJ%  0 +` Foppdm@4a0025e0ti,omap5-oppdm  CJ%  0 +` Foppdm@4a003b08ti,omap5-oppdm  CJ;  v +` Foppdm@4a0025f4ti,omap5-core-oppdm CJ%  +` Fspi@48098000ti,omap4-mcspiCH  G<hmcspi1 Q@#$%&'()* tx0rx0tx1rx1tx2rx2tx3rx3okayspidev1@0Crohm,dh2228fv _spi@4809a000ti,omap4-mcspiCH  G=hmcspi2 Q +,-.tx0rx0tx1rx1okayspi@480b8000ti,omap4-mcspiCH  GVhmcspi3 Qtx0rx0 disabledspi@480ba000ti,omap4-mcspiCH  G+hmcspi4 QFGtx0rx0 disabledqspi@4b300000ti,dra7xxx-qspiCK0\qspi_baseqspi_mmap qXhqspi fck X GWokay _m25p80@0 s25fl256s1 _C  partition@0 fckvideo1_clkvideo2_clk?n dispc@58001000ti,dra7-dispcCX G hdss_dispc<fck4nencoder@58060000 ti,dra7-hdmi CXXXXwppllphycore G`okay hdss_hdmi@A fcksys_clkL audio_tx"BportendpointlCx~ports disabledport@lcd3Cendpoint.port@lcd1CendpointlD.x~vdrm@0 ti,dra7-vdrmcrtc@0ti,dra7-vdrm-crtc9 ?XE<M42RX42RAvpeti,vpehvpefck@CH H H H HpassivexV~Vcpu_critH >criticalcooling-mapsmap0V Wgpu_thermaljUtripsgpu_critH >criticalcore_thermaljUtripscore_critH >criticaldspeve_thermaljUtripsdspeve_critH >criticaliva_thermaljUtripsiva_critH >criticalpmuarm,cortex-a15-pmu&Gsound@0simple-audio-cardDRA7xx-EVM-sound0 LineLine In8IN2_RLine InIN3_RLine InIN2_LLine InIN3_LLine Ini2ssimple-audio-card,cpu-X7$simple-audio-card,codec-YN^k7$sound@1simple-audio-cardDRA7xx-EVM-sound1HHeadphoneHeadphone JackLineLine OutMicrophoneMic JackLineLine InHeadphone JackHPLOUTHeadphone JackHPROUTLine OutLLOUTLine OutRLOUTMIC3LMic JackMIC3RMic JackMic JackMic BiasLINE1LLine InLINE1RLine Indsp_b~ZZsimple-audio-card,cpu-[7DoutxZ~Zsimple-audio-card,codec-\7Dsound2simple-audio-cardDRA7xx-EVM-sound2ZMicrophoneMic JackLineLine InLineLine OutHeadphoneHP JackSpeakerSpeaker External}Line OutMONO_LOUTSpeaker ExternalLLOUTSpeaker ExternalRLOUTLINE1LLine InLINE1RLine InMIC3LMic JackMIC3RMic Jackdsp_b~]]simple-audio-card,cpu-^7Doutx]~]simple-audio-card,codec-_7Dreserved-memoryripu2_cma@95800000shared-dma-poolCokayx~dsp1_cma@99000000shared-dma-poolCokayx~ipu1_cma@9d000000shared-dma-poolCokayx~dsp2_cma@9f000000shared-dma-poolCokayxN~Nlate_pgtbl@bfc00000Cokaycmem@40300000shared-dma-poolC@00 `okaycmem@A8000000shared-dma-poolCokayvsdk_sr1_mem@84000000shared-dma-poolCokayvsdk_sr0_mem@A0000000shared-dma-poolCokayvsdk_eve_mem@A2000000shared-dma-poolCokayfixedregulator-evm_1v8regulator-fixedevm_1v8aw@w@fixedregulator-sdregulator-fixed evm_3v3_sd2Z2Z bfixedregulator-evm_3v3_swregulator-fixed evm_3v3_swc2Z2Zx~fixedregulator-aic_dvddregulator-fixed aic_dvddw@w@fixedregulator-mmcwlregulator-fixed vmmcwl_fixedw@w@ .pfixedregulator-vttregulator-fixed vtt_fixedppAUd   #address-cells#size-cellscompatibleinterrupt-parentmodelstdout-pathi2c0i2c1i2c2i2c3i2c4serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9ethernet0ethernet1d_can0d_can1rproc0rproc1rproc2rproc3display0sound0sound1sound2i2c7i2c11i2c12i2c13i2c14i2c15i2c16device_typereginterruptsinterrupt-controller#interrupt-cellslinux,phandleoperating-points-v2cpu-opp-domainti,syscon-efuseti,syscon-revclocksclock-namesclock-latencyclock-frequencycooling-min-levelcooling-max-level#cooling-cellsopp-sharedopp-hzopp-microvoltopp-supported-hwopp-suspendti,hwmodsrangesinterrupts-extendedsysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinslabelgpiosdefault-stateautorepeatlinux,coderemote-endpointpinctrl-namespinctrl-0pinctrl-1ddc-i2c-busmcasp-gpio#dma-cellsdma-requeststi,dma-safe-mapdma-mastersclock-multclock-divti,max-divti,autoidle-shiftti,index-starts-at-oneti,invert-autoidle-bitti,index-power-of-twoassigned-clocksassigned-clock-ratesassigned-clock-parentsti,dividersti,set-rate-parentreg-namesnum-laneslinux,pci-domainphysphy-namesinterrupt-map-maskinterrupt-mapstatus#thermal-sensor-cellsdma-channelsinterrupt-namesti,tptcsgpio-controller#gpio-cellsti,no-reset-on-initti,no-idle-on-initdmasdma-namesrts-gpiors485-rts-active-highlinux,rs485-enabled-at-boot-time#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,timer-alwonti,late-attachti,timer-secure#hwlock-cellsiommusti,rproc-standby-infomemory-regionmboxestimerswatchdog-timerssyscon-bootreg#sound-dai-cellsadc-settle-msadc3101-micbias-vggpio-resetskip-vga-initti,palmas-override-powerholdti,system-power-controllerregulator-always-onregulator-boot-onregulator-allow-bypasslines-initial-statesmux-gpiosexport-devnodehsync-activevsync-activepclk-sampleinit-dirinit-valslave-modeai3x-micbias-vggpio_pwdngpio_intgpio_rstti,dual-voltti,needs-special-resetpbias-supplysd-uhs-sdr104sd-uhs-sdr50sd-uhs-ddr50sd-uhs-sdr25sd-uhs-sdr12vmmc-supplyvmmc_aux-supplybus-widthti,non-removablemax-frequencypinctrl-2pinctrl-3pinctrl-4pinctrl-5pinctrl-6pinctrl-7pinctrl-8mmc-ddr-1_8vcap-power-off-cardkeep-power-in-suspend#iommu-cellsti,syscon-mmuconfigti,iommu-bus-err-backbus_freqti,settling-timeti,clock-cyclesti,tranxdone-status-maskti,ldovbb-override-maskti,ldovbb-vset-maskti,abb_info#oppdm-cellsvbb-supplyti,efuse-settingsti,absolute-max-voltage-uvvdd-supplyti,spi-num-csspi-max-frequencysyscon-chipselectsspi-tx-bus-widthspi-rx-bus-widthsyscon-phy-powersyscon-pllreset#phy-cellssyscon-pcsphy-supplyutmi-modetx-fifo-resizemaximum-speeddr_modesnps,dis_u3_susphy_quirksnps,dis_u2_susphy_quirksnps,hsphy_interfacegpmc,num-csgpmc,num-waitpinsrb-gpiosti,nand-ecc-optti,elm-idnand-bus-widthgpmc,device-widthgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,access-nsgpmc,wr-access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsti,provided-clocksbwsawsop-modetdm-slotsserial-dirtx-num-evtrx-num-evtti,max-irqsti,max-crossbar-sourcesti,reg-sizeti,irqs-reservedti,irqs-skipti,irqs-safe-mapcpdma_channelsale_entriesbd_ram_sizemac_controlslavesactive_slavecpts_clock_multcpts_clock_shiftti,no-idledual_emacti,rx-internal-delayti,tx-internal-delayti,fifo-depthti,min-output-impedanceti,dp83867-rxctrl-strap-quirkmac-addressphy_idphy-modedual_emac_res_vlansyscon-raminitsyscon-pll-ctrlvdda_video-supplyis_sharedsyscon-polvdda-supplydata-linesx-resy-resrefreshsupported-formats#pwm-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicesimple-audio-card,namesimple-audio-card,widgetssimple-audio-card,routingsimple-audio-card,formatsound-daisystem-clock-frequencybitclock-masterframe-masterbitclock-inversionsimple-audio-card,bitclock-mastersimple-audio-card,frame-mastersimple-audio-card,bitclock-inversionsystem-clock-directionreusableno-mapsramvin-supplyenable-active-highstartup-delay-us