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Internal or External or Both */ #define SPI_CHANNELBUFFERS (SPI_IB_EB) /** \brief Internal Buffer length in bytes - applicable only for SPI_IB */ #define SPI_IB_MAX_LENGTH (64U) /** \brief Enable/disable SPI dev detect error */ #define SPI_DEV_ERROR_DETECT (STD_ON) /** \brief Enable/disable SPI job log */ #define SPI_JOB_LOG (STD_OFF) /** \brief Maximum job log entries when logging is ON */ #define SPI_MAX_JOB_LOG (100U) /** \brief Enable/disable SPI DMA Support */ #define SPI_MAX_HW_DMA_UNIT (0U) /** \brief Enable/disable SPI DMA Support */ #define SPI_DMA_ENABLE (STD_ON) /* * Scalability levels */ /** \brief Basic Synchronous functions */ #define SPI_LEVEL_0 (0U) /** \brief Basic Asynchronous functions */ #define SPI_LEVEL_1 (1U) /** \brief Synchronous and Asynchronous functions */ #define SPI_LEVEL_2 (2U) /** \brief Concurrent sync transmit support - by defualt this is off */ #define SPI_SUPPORT_CONCURRENT_SYNC_TRANSMIT (STD_OFF) /** \brief Scalability level */ #define SPI_SCALEABILITY (SPI_LEVEL_2) /** \brief Enable/disable SPI get version info API */ #define SPI_VERSION_INFO_API (STD_ON) /** \brief Enable/disable SPI HW Status API */ #define SPI_HW_STATUS_API (STD_ON) /** \brief Enable/disable SPI cancel API */ #define SPI_CANCEL_API (STD_ON) /* * All below macros are used for static memory allocation and can be changed to * match the usecase requirements. */ /** \brief Maximum channels allowed per job */ #define SPI_MAX_CHANNELS_PER_JOB (1U) /** \brief Maximum jobs allowed per sequence */ #define SPI_MAX_JOBS_PER_SEQ (1U) /** \brief Maximum channels across all jobs/sequence/hwunit */ #define SPI_MAX_CHANNELS (1U) /** \brief Maximum jobs across all sequence/hwunit */ #define SPI_MAX_JOBS (1U) /** \brief Maximum sequence across all hwunit */ #define SPI_MAX_SEQ (1U) /** * \brief Maximum HW unit - This should match the sum for the below units ISR * which are ON. */ #define SPI_MAX_HW_UNIT (8U) /** * \brief Maximum external device cfg */ #define SPI_MAX_EXT_DEV (11U) /* All below macros are used for enabling the ISR for a particular hardware. */ /** \brief Enable/disable SPI MCU MCSPI0 unit ISR */ #define SPI_UNIT_MCU_MCSPI0_ACTIVE (STD_ON) /** \brief Enable/disable SPI MCU MCSPI1 unit ISR */ #define SPI_UNIT_MCU_MCSPI1_ACTIVE (STD_OFF) /** \brief Enable/disable SPI MCU MCSPI2 unit ISR */ #define SPI_UNIT_MCU_MCSPI2_ACTIVE (STD_OFF) /** \brief Enable/disable SPI MCSPI0 unit ISR */ #define SPI_UNIT_MCSPI0_ACTIVE (STD_OFF) /** \brief Enable/disable SPI MCSPI1 unit ISR */ #define SPI_UNIT_MCSPI1_ACTIVE (STD_OFF) /** \brief Enable/disable SPI MCSPI2 unit ISR */ #define SPI_UNIT_MCSPI2_ACTIVE (STD_OFF) /** \brief Enable/disable SPI MCSPI3 unit ISR */ #define SPI_UNIT_MCSPI3_ACTIVE (STD_OFF) /** \brief Enable/disable SPI MCSPI4 unit ISR */ #define SPI_UNIT_MCSPI4_ACTIVE (STD_OFF) /** \brief Enable/disable SPI MCSPI5 unit ISR */ #define SPI_UNIT_MCSPI5_ACTIVE (STD_OFF) /** \brief Enable/disable SPI MCSPI6 unit ISR */ #define SPI_UNIT_MCSPI6_ACTIVE (STD_OFF) /** \brief Enable/disable SPI MCSPI7 unit ISR */ #define SPI_UNIT_MCSPI7_ACTIVE (STD_OFF) /** \brief ISR type */ #define SPI_ISR_TYPE (SPI_ISR_CAT1) /** \brief OS counter ID - used for timeout in case of error */ #define SPI_OS_COUNTER_ID ((CounterType)OsCounter_0) /** * \brief SPI timeout - used in McSPI IP reset * Each tick is 31.25us (for 32K Counter). Wait for 100ms which comes to * below value */ #define SPI_TIMEOUT_DURATION (32000U) /** \brief Enable/disable SPI register read back API */ #define SPI_REGISTER_READBACK_API (STD_ON) /** \brief Symbolic Name Channel Id - 0 SpiChannel_0 */ #define SpiConf_SpiChannel_SpiChannel_0 (0U) /** \brief Symbolic Name Chip Select - 0 */ #define SpiConf_SpiExternalDevice_CS0 (SPI_CS0) /** \brief Symbolic Name Job Id - 0 SpiJob_0 */ #define SpiConf_SpiJob_SpiJob_0 (0U) /** \brief Symbolic Name Sequence Id - 0 SpiSequence_0 */ #define SpiConf_SpiSequence_SpiSequence_0 (0U) /** \brief Symbolic Name HW Unit - 0 */ #define SpiConf_SpiExternalDevice_HwUnitId0 (CSIB0) /** \brief Symbolic Name HW Unit - 1 */ #define SpiConf_SpiExternalDevice_HwUnitId1 (CSIB1) /** \brief Symbolic Name HW Unit - 2 */ #define SpiConf_SpiExternalDevice_HwUnitId2 (CSIB2) /** \brief Symbolic Name HW Unit - 3 */ #define SpiConf_SpiExternalDevice_HwUnitId3 (CSIB3) /** \brief Symbolic Name HW Unit - 4 */ #define SpiConf_SpiExternalDevice_HwUnitId4 (CSIB4) /** \brief Symbolic Name HW Unit - 5 */ #define SpiConf_SpiExternalDevice_HwUnitId5 (CSIB5) /** \brief Symbolic Name HW Unit - 6 */ #define SpiConf_SpiExternalDevice_HwUnitId6 (CSIB6) /** \brief Symbolic Name HW Unit - 7 */ #define SpiConf_SpiExternalDevice_HwUnitId7 (CSIB7) /** * \name SPI DEM Error codes to report * * Pre-compile switches for enabling/disabling DEM events * @{ */ #ifndef SPI_E_HARDWARE_ERROR /** \brief Hardware failed */ #define SPI_E_HARDWARE_ERROR (DemConf_DemEventParameter_SPI_E_HARDWARE_ERROR) #endif /** * \name SPI HW unit Info * @{ */ /** \brief MCU MCSPI0 instance */ #define SPI_UNIT_MCU_MCSPI0 ((Spi_HWUnitType) CSIB0) /** \brief MCU MCSPI1 instance */ #define SPI_UNIT_MCU_MCSPI1 ((Spi_HWUnitType) CSIB1) /** \brief MCU MCSPI2 instance */ #define SPI_UNIT_MCU_MCSPI2 ((Spi_HWUnitType) CSIB2) /** \brief MCSPI0 instance */ #define SPI_UNIT_MCSPI0 ((Spi_HWUnitType) CSIB3) /** \brief MCSPI1 instance */ #define SPI_UNIT_MCSPI1 ((Spi_HWUnitType) CSIB4) /** \brief MCSPI2 instance */ #define SPI_UNIT_MCSPI2 ((Spi_HWUnitType) CSIB5) /** \brief MCSPI3 instance */ #define SPI_UNIT_MCSPI3 ((Spi_HWUnitType) CSIB6) /** \brief MCSPI4 instance */ #define SPI_UNIT_MCSPI4 ((Spi_HWUnitType) CSIB7) /** \brief MCSPI5 instance */ #define SPI_UNIT_MCSPI5 ((Spi_HWUnitType) CSIB8) /** \brief MCSPI6 instance */ #define SPI_UNIT_MCSPI6 ((Spi_HWUnitType) CSIB9) /** \brief MCSPI7 instance */ #define SPI_UNIT_MCSPI7 ((Spi_HWUnitType) CSIB10) /* @} */ /** * \brief Total HW units - used for array allocation. This should be +1 of the * max unit number */ #define SPI_HW_UNIT_CNT (11U) extern const uint32 Spi_HwUnitBaseAddr[SPI_HW_UNIT_CNT]; /* @} */ /* ========================================================================== */ /* Structures and Enums */ /* ========================================================================== */ /** * \brief This type defines a range of HW SPI Hardware microcontroller * peripheral allocated to this Job */ typedef enum { CSIB0 = 0U, /**< MCU MCSPI0 instance */ CSIB1, /**< MCU MCSPI1 instance */ CSIB2, /**< MCU MCSPI2 instance */ CSIB3, /**< MCSPI0 instance */ CSIB4, /**< MCSPI1 instance */ CSIB5, /**< MCSPI2 instance */ CSIB6, /**< MCSPI3 instance */ CSIB7, /**< MCSPI4 instance */ CSIB8, /**< MCSPI5 instance */ CSIB9, /**< MCSPI6 instance */ CSIB10, /**< MCSPI7 instance */ } Spi_HwUnitType; /** \brief Cache write-back invalidate function */ extern void SpiApp_wbInvCache(uint8 *buf, uint16 len); /** \brief Cache write-back function */ extern void SpiApp_wbCache(uint8 *buf, uint16 len); /** \brief Cache invalidate function */ extern void SpiApp_invCache(uint8 *buf, uint16 len); /** \brief SPI Configuration struct declaration */ extern const struct Spi_ConfigType_s SpiDriver; /* ========================================================================== */ /* Function Declarations */ /* ========================================================================== */ /** * \brief SPI Hwunit ISR */ /** \brief SPI MCU_MCSPI0 ISR */ FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi0TxRx(void); /** \brief SPI MCU_MCSPI1 ISR */ FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi1TxRx(void); /** \brief SPI MCU_MCSPI2 ISR */ FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi2TxRx(void); /** \brief SPI MCSPI0 ISR */ FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi0TxRx(void); /** \brief SPI MCSPI1 ISR */ FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi1TxRx(void); /** \brief SPI MCSPI2 ISR */ FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi2TxRx(void); /** \brief SPI MCSPI3 ISR */ FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi3TxRx(void); /** \brief SPI MCSPI4 ISR */ FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi4TxRx(void); FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi0DmaTx(void); FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi0DmaRx(void); FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi1DmaTx(void); FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi1DmaRx(void); #ifdef __cplusplus } #endif #endif /* #ifndef SPI_CFG_H_ */ /* @} */