Introduction
Directory structure
Setting up build environment to use CSL
Using CSL examples
Unarchive the sources
Bugs fixed
This is the release note for C6000 CSL version 2.31.00.8. This release provides chip support libraries for C6201, C6202, C6203, C6204, C6205, C6211, C6410, C6411, C6412, C6413, C6414, C6415, C6416, C6418, C6701, C6711, C6711C, C6712, C6712C, C6713, DA610, DM642, DM641 and DM640 devices. All the libraries are built using Codegen tools v4.32 with options -mo -al -k -qq -o3 -ml3 . User documentation for C6000 CSL can be found in "TMS320C6000 Chip Support Library API Reference Guide" (spru401).
include - This directory contains CSL headers. (e.g. csl_dma.h, csl_mcbsp.h etc.)
lib - This directory contains CSL libraries (e.g. csl6201.lib, csl6201e.lib etc.) and
archives CSL sources in (csl6000.src)
examples - This directory contains CSL examples for evm6201, dsk6211 , dsk6711 , dsk6713 and evmDM642.
- In CCS based build environment:
Assuming CSL is installed at <User_Install_Dir> , all the existing CCS project files need to add :
-i"<User_Install_Dir>\include" in compiler options and
-l"<User_Install_Dir>\lib" in linker options
- In Non-CCS based build environment:
Assuming <User_Install_Dir> is the directory of CSL installation, all makefiles used to build the application need to add:
-i"<User_Install_Dir>\include" in compiler options and
-l"<User_Install_Dir>\lib" in linker options
The CSL examples provided with this release use CSL headers and libraries from CCS installation by default. In order to build the examples using latest CSL in this release, please refer point 3 above.
All CSL sources (header files, c files and asm files) can be unarchived using following command:
ar6x x csl6000.src
SDSsq38280 - Typo in csl_vphal.h (definition error in VP – VDIMGOFF address
register macros)
SDSsq37840 - Problem with tccAllocTable definition in 6x csl_edma.h file
Enhancements
--------------
* Included chip support library for C6418.
Enhancements
--------------
* Included chip support libraries for DM641 and DM640 devices
* Fixed BIOS-CSL dependency bug. This version of CSL has a fix for incorrect TIMER0 initialization during BIOS initialization.
This CSL version fixes this bug for all BIOS versions.
* CSL has been updated for VP module as per the latest documentation,SPRU629a.pdf
a) VP module changes (Field names):-
VCTxP field in VPCTL register.
old name new name
VCT3P VCT2P
VCT2P VCT1P
VCT1P VCT0P
VCTLxS field in VDCTL register,
old name new name
VCTL3S VCTL2S
VCTL2S VCTL1S
VCTL1S VCTL0S
b) VP module changes ( symbolic constants) :-
old name
new name
PFUNC:
VP_PFUNC_PFUNC20_VCTL1
VP_PFUNC_PFUNC20_VCTL0
VP_PFUNC_PFUNC21_VCTL2
VP_PFUNC_PFUNC21_VCTL1
VP_PFUNC_PFUNC22_VCTL3
VP_PFUNC_PFUNC22_VCTL2
PDIR:
VP_PDIR_PDIR22_VCTL3IN VP_PDIR_PDIR22_VCTL2IN
VP_PDIR_PDIR22_VCTL3OUT VP_PDIR_PDIR22_VCTL2OUT
VP_PDIR_PDIR21_VCTL2IN VP_PDIR_PDIR21_VCTL1IN
VP_PDIR_PDIR21_VCTL2OUT VP_PDIR_PDIR21_VCTL1OUT
VP_PDIR_PDIR20_VCTL1IN VP_PDIR_PDIR20_VCTL0IN
VP_PDIR_PDIR20_VCTL1OUT VP_PDIR_PDIR20_VCTL0OUT
PDIN:
VP_PDIN_PDIN22_VCTL3LO VP_PDIN_PDIN22_VCTL2LO
VP_PDIN_PDIN22_VCTL3HI VP_PDIN_PDIN22_VCTL2HI
VP_PDIN_PDIN21_VCTL2LO VP_PDIN_PDIN21_VCTL1LO
VP_PDIN_PDIN21_VCTL2HI VP_PDIN_PDIN21_VCTL1HI
VP_PDIN_PDIN20_VCTL1LO VP_PDIN_PDIN20_VCTL0LO
VP_PDIN_PDIN20_VCTL1HI VP_PDIN_PDIN20_VCTL0HI
PDOUT:
VP_PDOUT_PDOUT22_VCTL3LO VP_PDOUT_PDOUT22_VCTL2LO
VP_PDOUT_PDOUT22_VCTL3HI VP_PDOUT_PDOUT22_VCTL2HI
VP_PDOUT_PDOUT21_VCTL2LO VP_PDOUT_PDOUT21_VCTL1LO
VP_PDOUT_PDOUT21_VCTL2HI VP_PDOUT_PDOUT21_VCTL1HI
VP_PDOUT_PDOUT20_VCTL1LO VP_PDOUT_PDOUT20_VCTL0LO
VP_PDOUT_PDOUT20_VCTL1HI VP_PDOUT_PDOUT20_VCTL0HI
PDSET:
VP_PDSET_PDSET22_VCTL3HI VP_PDSET_PDSET22_VCTL2HI
VP_PDSET_PDSET21_VCTL2HI VP_PDSET_PDSET21_VCTL1HI
VP_PDSET_PDSET20_VCTL1HI VP_PDSET_PDSET20_VCTL0HI
PDCLR:
VP_PDCLR_PDCLR22_VCTL3CLR VP_PDCLR_PDCLR22_VCTL2CLR
VP_PDCLR_PDCLR21_VCTL2CLR VP_PDCLR_PDCLR21_VCTL1CLR
VP_PDCLR_PDCLR20_VCTL1CLR VP_PDCLR_PDCLR20_VCTL0CLR
PIEN:
VP_PIEN_PIEN22_VCTL3LO VP_PIEN_PIEN22_VCTL2LO
VP_PIEN_PIEN22_VCTL3HI VP_PIEN_PIEN22_VCTL2HI
VP_PIEN_PIEN21_VCTL2LO
VP_PIEN_PIEN21_VCTL1LO
VP_PIEN_PIEN21_VCTL2HI VP_PIEN_PIEN21_VCTL1HI
VP_PIEN_PIEN20_VCTL1LO
VP_PIEN_PIEN20_VCTL0LO
VP_PIEN_PIEN20_VCTL1HI VP_PIEN_PIEN20_VCTL0HI
PIPOL:
VP_PIPOL_PIPOL22_VCTL3ACTHI VP_PIPOL_PIPOL22_VCTL2ACTHI
VP_PIPOL_PIPOL22_VCTL3ACTLO VP_PIPOL_PIPOL22_VCTL2ACTLO
VP_PIPOL_PIPOL21_VCTL2ACTHI VP_PIPOL_PIPOL21_VCTL1ACTHI
VP_PIPOL_PIPOL21_VCTL2ACTLO VP_PIPOL_PIPOL21_VCTL1ACTLO
VP_PIPOL_PIPOL20_VCTL1ACTHI VP_PIPOL_PIPOL20_VCTL0ACTHI
VP_PIPOL_PIPOL20_VCTL1ACTLO VP_PIPOL_PIPOL20_VCTL0ACTLO
PISTAT:
VP_PISTAT_PISTAT22_VCTL3INT VP_PISTAT_PISTAT22_VCTL2INT
VP_PISTAT_PISTAT21_VCTL2INT VP_PISTAT_PISTAT21_VCTL1INT
VP_PISTAT_PISTAT20_VCTL1INT VP_PISTAT_PISTAT20_VCTL0INT
PICLR:
VP_PICLR_PICLR22_VCTL3CLR
VP_PICLR_PICLR22_VCTL2CLR
VP_PICLR_PICLR21_VCTL2CLR
VP_PICLR_PICLR21_VCTL1CLR
VP_PICLR_PICLR20_VCTL1CLR
VP_PICLR_PICLR20_VCTL0CLR
VDCTL:
VP_VDCTL_VCTL3S_CBLNK
VP_VDCTL_VCTL2S_CBLNK
VP_VDCTL_VCTL3S_FLD VP_VDCTL_VCTL2S_FLD
VP_VDCTL_VCTL2S_VYSYNC
VP_VDCTL_VCTL1S_VYSYNC
VP_VDCTL_VCTL2S_VBLNK
VP_VDCTL_VCTL1S_VBLNK
VP_VDCTL_VCTL2S_CSYNC VP_VDCTL_VCTL1S_CSYNC
VP_VDCTL_VCTL2S_FLD VP_VDCTL_VCTL1S_FLD
VP_VDCTL_VCTL1S_HYSYNC
VP_VDCTL_VCTL0S_HYSYNC
VP_VDCTL_VCTL1S_HBLNK
VP_VDCTL_VCTL0S_HBLNK
VP_VDCTL_VCTL1S_AVID VP_VDCTL_VCTL0S_AVID
VP_VDCTL_VCTL1S_FLD VP_VDCTL_VCTL0S_FLD