


1. Boot EVM in No Boot mode.
SW3 {pin 0 - pin8) = 10000000 (0-ON, 1-OFF)

SW5(pin0 -  pin8) = 00000000

2. Launch CCS and connect to GEM core 0. Let the GEL file run to initialize PLL and DDR memory. 

3. Go to the bin/flashwriter and ensure that norwriter_input_txt points to "app.dat"

For full instructions for flashing the boot image to SPI NOR refer to README (C6657) in the NORwriter package in MCSDK/Processor SDK. 

3. Rename spirom_le_swap.dat create by spiboot.bat in the build folder to app.dat. In CCS load memory location 0x80000000 using memory browser.
Copy the .dat file into the bin directory where the norwriter out file is present. Load norwriter .out file and run.

Refer to user guide if you have any questions.

4. Reboot EVM into direct SPI mode. To do this, configure dip switches:

SW3 {pin 0 - pin8) = 10110000 (0-ON, 1-OFF)

SW5(pin0 -  pin8) = 00100000

5. On power up connect to Core0 using CCS, the DDR should be configured by the boot image. 
To test, connect to GEM core 0 and navigate to address 0x80000000 in the memory browser in CCS.