diff --git a/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi
index 31429e31d1..db0dcc33e9 100644
--- a/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi
+++ b/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
- * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.0
- * This file was generated on 05/23/2022
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.10.0
+ * This file was generated on 11/28/2023
 */
 
 #define DDRSS_PLL_FHS_CNT 10
@@ -11,10 +11,10 @@
 #define DDRSS_PLL_FREQUENCY_2 1066500000
 
 #define MULTI_DDR_CFG_INTRLV_GRAN 0
-#define MULTI_DDR_CFG_INTRLV_SIZE 12
+#define MULTI_DDR_CFG_INTRLV_SIZE 11
 #define MULTI_DDR_CFG_ECC_ENABLE 0
-#define MULTI_DDR_CFG_HYBRID_SELECT 24
-#define MULTI_DDR_CFG_EMIFS_ACTIVE 15
+#define MULTI_DDR_CFG_HYBRID_SELECT 2
+#define MULTI_DDR_CFG_EMIFS_ACTIVE 3
 
 #define DDRSS0_CTL_00_DATA 0x00000B00
 #define DDRSS0_CTL_01_DATA 0x00000000
@@ -60,11 +60,11 @@
 #define DDRSS0_CTL_41_DATA 0x1760008B
 #define DDRSS0_CTL_42_DATA 0x2000422B
 #define DDRSS0_CTL_43_DATA 0x000A0A09
-#define DDRSS0_CTL_44_DATA 0x0400078A
+#define DDRSS0_CTL_44_DATA 0x040003C5
 #define DDRSS0_CTL_45_DATA 0x1E161104
-#define DDRSS0_CTL_46_DATA 0x10012458
+#define DDRSS0_CTL_46_DATA 0x1000922C
 #define DDRSS0_CTL_47_DATA 0x1E161110
-#define DDRSS0_CTL_48_DATA 0x10012458
+#define DDRSS0_CTL_48_DATA 0x1000922C
 #define DDRSS0_CTL_49_DATA 0x02030410
 #define DDRSS0_CTL_50_DATA 0x2C040500
 #define DDRSS0_CTL_51_DATA 0x08292C29
@@ -77,11 +77,11 @@
 #define DDRSS0_CTL_58_DATA 0x00010100
 #define DDRSS0_CTL_59_DATA 0x03010000
 #define DDRSS0_CTL_60_DATA 0x00001508
-#define DDRSS0_CTL_61_DATA 0x000000CE
+#define DDRSS0_CTL_61_DATA 0x00000063
 #define DDRSS0_CTL_62_DATA 0x0000032B
-#define DDRSS0_CTL_63_DATA 0x00002073
+#define DDRSS0_CTL_63_DATA 0x00001035
 #define DDRSS0_CTL_64_DATA 0x0000032B
-#define DDRSS0_CTL_65_DATA 0x00002073
+#define DDRSS0_CTL_65_DATA 0x00001035
 #define DDRSS0_CTL_66_DATA 0x00000005
 #define DDRSS0_CTL_67_DATA 0x00050000
 #define DDRSS0_CTL_68_DATA 0x00CB0012
@@ -118,27 +118,27 @@
 #define DDRSS0_CTL_99_DATA 0x00000000
 #define DDRSS0_CTL_100_DATA 0x00040005
 #define DDRSS0_CTL_101_DATA 0x00000000
-#define DDRSS0_CTL_102_DATA 0x00003380
-#define DDRSS0_CTL_103_DATA 0x00003380
-#define DDRSS0_CTL_104_DATA 0x00003380
-#define DDRSS0_CTL_105_DATA 0x00003380
-#define DDRSS0_CTL_106_DATA 0x00003380
+#define DDRSS0_CTL_102_DATA 0x000018C0
+#define DDRSS0_CTL_103_DATA 0x000018C0
+#define DDRSS0_CTL_104_DATA 0x000018C0
+#define DDRSS0_CTL_105_DATA 0x000018C0
+#define DDRSS0_CTL_106_DATA 0x000018C0
 #define DDRSS0_CTL_107_DATA 0x00000000
-#define DDRSS0_CTL_108_DATA 0x000005A2
-#define DDRSS0_CTL_109_DATA 0x00081CC0
-#define DDRSS0_CTL_110_DATA 0x00081CC0
-#define DDRSS0_CTL_111_DATA 0x00081CC0
-#define DDRSS0_CTL_112_DATA 0x00081CC0
-#define DDRSS0_CTL_113_DATA 0x00081CC0
+#define DDRSS0_CTL_108_DATA 0x000002B5
+#define DDRSS0_CTL_109_DATA 0x00040D40
+#define DDRSS0_CTL_110_DATA 0x00040D40
+#define DDRSS0_CTL_111_DATA 0x00040D40
+#define DDRSS0_CTL_112_DATA 0x00040D40
+#define DDRSS0_CTL_113_DATA 0x00040D40
 #define DDRSS0_CTL_114_DATA 0x00000000
-#define DDRSS0_CTL_115_DATA 0x0000E325
-#define DDRSS0_CTL_116_DATA 0x00081CC0
-#define DDRSS0_CTL_117_DATA 0x00081CC0
-#define DDRSS0_CTL_118_DATA 0x00081CC0
-#define DDRSS0_CTL_119_DATA 0x00081CC0
-#define DDRSS0_CTL_120_DATA 0x00081CC0
+#define DDRSS0_CTL_115_DATA 0x00007173
+#define DDRSS0_CTL_116_DATA 0x00040D40
+#define DDRSS0_CTL_117_DATA 0x00040D40
+#define DDRSS0_CTL_118_DATA 0x00040D40
+#define DDRSS0_CTL_119_DATA 0x00040D40
+#define DDRSS0_CTL_120_DATA 0x00040D40
 #define DDRSS0_CTL_121_DATA 0x00000000
-#define DDRSS0_CTL_122_DATA 0x0000E325
+#define DDRSS0_CTL_122_DATA 0x00007173
 #define DDRSS0_CTL_123_DATA 0x00000000
 #define DDRSS0_CTL_124_DATA 0x00000000
 #define DDRSS0_CTL_125_DATA 0x00000000
@@ -405,29 +405,29 @@
 #define DDRSS0_CTL_386_DATA 0x00000000
 #define DDRSS0_CTL_387_DATA 0x3A3A1B00
 #define DDRSS0_CTL_388_DATA 0x000A0000
-#define DDRSS0_CTL_389_DATA 0x0000019C
+#define DDRSS0_CTL_389_DATA 0x000000C6
 #define DDRSS0_CTL_390_DATA 0x00000200
 #define DDRSS0_CTL_391_DATA 0x00000200
 #define DDRSS0_CTL_392_DATA 0x00000200
 #define DDRSS0_CTL_393_DATA 0x00000200
-#define DDRSS0_CTL_394_DATA 0x000004D4
-#define DDRSS0_CTL_395_DATA 0x00001018
+#define DDRSS0_CTL_394_DATA 0x00000252
+#define DDRSS0_CTL_395_DATA 0x000007BC
 #define DDRSS0_CTL_396_DATA 0x00000204
-#define DDRSS0_CTL_397_DATA 0x000040E6
+#define DDRSS0_CTL_397_DATA 0x0000206A
 #define DDRSS0_CTL_398_DATA 0x00000200
 #define DDRSS0_CTL_399_DATA 0x00000200
 #define DDRSS0_CTL_400_DATA 0x00000200
 #define DDRSS0_CTL_401_DATA 0x00000200
-#define DDRSS0_CTL_402_DATA 0x0000C2B2
-#define DDRSS0_CTL_403_DATA 0x000288FC
+#define DDRSS0_CTL_402_DATA 0x0000613E
+#define DDRSS0_CTL_403_DATA 0x00014424
 #define DDRSS0_CTL_404_DATA 0x00000E15
-#define DDRSS0_CTL_405_DATA 0x000040E6
+#define DDRSS0_CTL_405_DATA 0x0000206A
 #define DDRSS0_CTL_406_DATA 0x00000200
 #define DDRSS0_CTL_407_DATA 0x00000200
 #define DDRSS0_CTL_408_DATA 0x00000200
 #define DDRSS0_CTL_409_DATA 0x00000200
-#define DDRSS0_CTL_410_DATA 0x0000C2B2
-#define DDRSS0_CTL_411_DATA 0x000288FC
+#define DDRSS0_CTL_410_DATA 0x0000613E
+#define DDRSS0_CTL_411_DATA 0x00014424
 #define DDRSS0_CTL_412_DATA 0x02020E15
 #define DDRSS0_CTL_413_DATA 0x03030202
 #define DDRSS0_CTL_414_DATA 0x00000022
@@ -646,11 +646,11 @@
 #define DDRSS0_PI_167_DATA 0x02000200
 #define DDRSS0_PI_168_DATA 0x48120C04
 #define DDRSS0_PI_169_DATA 0x00154812
-#define DDRSS0_PI_170_DATA 0x000000CE
+#define DDRSS0_PI_170_DATA 0x00000063
 #define DDRSS0_PI_171_DATA 0x0000032B
-#define DDRSS0_PI_172_DATA 0x00002073
+#define DDRSS0_PI_172_DATA 0x00001035
 #define DDRSS0_PI_173_DATA 0x0000032B
-#define DDRSS0_PI_174_DATA 0x04002073
+#define DDRSS0_PI_174_DATA 0x04001035
 #define DDRSS0_PI_175_DATA 0x01010404
 #define DDRSS0_PI_176_DATA 0x00001501
 #define DDRSS0_PI_177_DATA 0x00150015
@@ -695,22 +695,22 @@
 #define DDRSS0_PI_216_DATA 0x3212005B
 #define DDRSS0_PI_217_DATA 0x09000301
 #define DDRSS0_PI_218_DATA 0x04010504
-#define DDRSS0_PI_219_DATA 0x040006C9
+#define DDRSS0_PI_219_DATA 0x04000364
 #define DDRSS0_PI_220_DATA 0x0A032001
 #define DDRSS0_PI_221_DATA 0x2C31110A
 #define DDRSS0_PI_222_DATA 0x00002918
-#define DDRSS0_PI_223_DATA 0x6001071C
+#define DDRSS0_PI_223_DATA 0x6000838E
 #define DDRSS0_PI_224_DATA 0x1E202008
 #define DDRSS0_PI_225_DATA 0x2C311116
 #define DDRSS0_PI_226_DATA 0x00002918
-#define DDRSS0_PI_227_DATA 0x6001071C
+#define DDRSS0_PI_227_DATA 0x6000838E
 #define DDRSS0_PI_228_DATA 0x1E202008
-#define DDRSS0_PI_229_DATA 0x00019C16
-#define DDRSS0_PI_230_DATA 0x00001018
-#define DDRSS0_PI_231_DATA 0x000040E6
-#define DDRSS0_PI_232_DATA 0x000288FC
-#define DDRSS0_PI_233_DATA 0x000040E6
-#define DDRSS0_PI_234_DATA 0x000288FC
+#define DDRSS0_PI_229_DATA 0x0000C616
+#define DDRSS0_PI_230_DATA 0x000007BC
+#define DDRSS0_PI_231_DATA 0x0000206A
+#define DDRSS0_PI_232_DATA 0x00014424
+#define DDRSS0_PI_233_DATA 0x0000206A
+#define DDRSS0_PI_234_DATA 0x00014424
 #define DDRSS0_PI_235_DATA 0x033B0016
 #define DDRSS0_PI_236_DATA 0x0303033B
 #define DDRSS0_PI_237_DATA 0x002AF803
@@ -2245,11 +2245,11 @@
 #define DDRSS1_CTL_41_DATA 0x1760008B
 #define DDRSS1_CTL_42_DATA 0x2000422B
 #define DDRSS1_CTL_43_DATA 0x000A0A09
-#define DDRSS1_CTL_44_DATA 0x0400078A
+#define DDRSS1_CTL_44_DATA 0x040003C5
 #define DDRSS1_CTL_45_DATA 0x1E161104
-#define DDRSS1_CTL_46_DATA 0x10012458
+#define DDRSS1_CTL_46_DATA 0x1000922C
 #define DDRSS1_CTL_47_DATA 0x1E161110
-#define DDRSS1_CTL_48_DATA 0x10012458
+#define DDRSS1_CTL_48_DATA 0x1000922C
 #define DDRSS1_CTL_49_DATA 0x02030410
 #define DDRSS1_CTL_50_DATA 0x2C040500
 #define DDRSS1_CTL_51_DATA 0x08292C29
@@ -2262,11 +2262,11 @@
 #define DDRSS1_CTL_58_DATA 0x00010100
 #define DDRSS1_CTL_59_DATA 0x03010000
 #define DDRSS1_CTL_60_DATA 0x00001508
-#define DDRSS1_CTL_61_DATA 0x000000CE
+#define DDRSS1_CTL_61_DATA 0x00000063
 #define DDRSS1_CTL_62_DATA 0x0000032B
-#define DDRSS1_CTL_63_DATA 0x00002073
+#define DDRSS1_CTL_63_DATA 0x00001035
 #define DDRSS1_CTL_64_DATA 0x0000032B
-#define DDRSS1_CTL_65_DATA 0x00002073
+#define DDRSS1_CTL_65_DATA 0x00001035
 #define DDRSS1_CTL_66_DATA 0x00000005
 #define DDRSS1_CTL_67_DATA 0x00050000
 #define DDRSS1_CTL_68_DATA 0x00CB0012
@@ -2303,27 +2303,27 @@
 #define DDRSS1_CTL_99_DATA 0x00000000
 #define DDRSS1_CTL_100_DATA 0x00040005
 #define DDRSS1_CTL_101_DATA 0x00000000
-#define DDRSS1_CTL_102_DATA 0x00003380
-#define DDRSS1_CTL_103_DATA 0x00003380
-#define DDRSS1_CTL_104_DATA 0x00003380
-#define DDRSS1_CTL_105_DATA 0x00003380
-#define DDRSS1_CTL_106_DATA 0x00003380
+#define DDRSS1_CTL_102_DATA 0x000018C0
+#define DDRSS1_CTL_103_DATA 0x000018C0
+#define DDRSS1_CTL_104_DATA 0x000018C0
+#define DDRSS1_CTL_105_DATA 0x000018C0
+#define DDRSS1_CTL_106_DATA 0x000018C0
 #define DDRSS1_CTL_107_DATA 0x00000000
-#define DDRSS1_CTL_108_DATA 0x000005A2
-#define DDRSS1_CTL_109_DATA 0x00081CC0
-#define DDRSS1_CTL_110_DATA 0x00081CC0
-#define DDRSS1_CTL_111_DATA 0x00081CC0
-#define DDRSS1_CTL_112_DATA 0x00081CC0
-#define DDRSS1_CTL_113_DATA 0x00081CC0
+#define DDRSS1_CTL_108_DATA 0x000002B5
+#define DDRSS1_CTL_109_DATA 0x00040D40
+#define DDRSS1_CTL_110_DATA 0x00040D40
+#define DDRSS1_CTL_111_DATA 0x00040D40
+#define DDRSS1_CTL_112_DATA 0x00040D40
+#define DDRSS1_CTL_113_DATA 0x00040D40
 #define DDRSS1_CTL_114_DATA 0x00000000
-#define DDRSS1_CTL_115_DATA 0x0000E325
-#define DDRSS1_CTL_116_DATA 0x00081CC0
-#define DDRSS1_CTL_117_DATA 0x00081CC0
-#define DDRSS1_CTL_118_DATA 0x00081CC0
-#define DDRSS1_CTL_119_DATA 0x00081CC0
-#define DDRSS1_CTL_120_DATA 0x00081CC0
+#define DDRSS1_CTL_115_DATA 0x00007173
+#define DDRSS1_CTL_116_DATA 0x00040D40
+#define DDRSS1_CTL_117_DATA 0x00040D40
+#define DDRSS1_CTL_118_DATA 0x00040D40
+#define DDRSS1_CTL_119_DATA 0x00040D40
+#define DDRSS1_CTL_120_DATA 0x00040D40
 #define DDRSS1_CTL_121_DATA 0x00000000
-#define DDRSS1_CTL_122_DATA 0x0000E325
+#define DDRSS1_CTL_122_DATA 0x00007173
 #define DDRSS1_CTL_123_DATA 0x00000000
 #define DDRSS1_CTL_124_DATA 0x00000000
 #define DDRSS1_CTL_125_DATA 0x00000000
@@ -2590,29 +2590,29 @@
 #define DDRSS1_CTL_386_DATA 0x00000000
 #define DDRSS1_CTL_387_DATA 0x3A3A1B00
 #define DDRSS1_CTL_388_DATA 0x000A0000
-#define DDRSS1_CTL_389_DATA 0x0000019C
+#define DDRSS1_CTL_389_DATA 0x000000C6
 #define DDRSS1_CTL_390_DATA 0x00000200
 #define DDRSS1_CTL_391_DATA 0x00000200
 #define DDRSS1_CTL_392_DATA 0x00000200
 #define DDRSS1_CTL_393_DATA 0x00000200
-#define DDRSS1_CTL_394_DATA 0x000004D4
-#define DDRSS1_CTL_395_DATA 0x00001018
+#define DDRSS1_CTL_394_DATA 0x00000252
+#define DDRSS1_CTL_395_DATA 0x000007BC
 #define DDRSS1_CTL_396_DATA 0x00000204
-#define DDRSS1_CTL_397_DATA 0x000040E6
+#define DDRSS1_CTL_397_DATA 0x0000206A
 #define DDRSS1_CTL_398_DATA 0x00000200
 #define DDRSS1_CTL_399_DATA 0x00000200
 #define DDRSS1_CTL_400_DATA 0x00000200
 #define DDRSS1_CTL_401_DATA 0x00000200
-#define DDRSS1_CTL_402_DATA 0x0000C2B2
-#define DDRSS1_CTL_403_DATA 0x000288FC
+#define DDRSS1_CTL_402_DATA 0x0000613E
+#define DDRSS1_CTL_403_DATA 0x00014424
 #define DDRSS1_CTL_404_DATA 0x00000E15
-#define DDRSS1_CTL_405_DATA 0x000040E6
+#define DDRSS1_CTL_405_DATA 0x0000206A
 #define DDRSS1_CTL_406_DATA 0x00000200
 #define DDRSS1_CTL_407_DATA 0x00000200
 #define DDRSS1_CTL_408_DATA 0x00000200
 #define DDRSS1_CTL_409_DATA 0x00000200
-#define DDRSS1_CTL_410_DATA 0x0000C2B2
-#define DDRSS1_CTL_411_DATA 0x000288FC
+#define DDRSS1_CTL_410_DATA 0x0000613E
+#define DDRSS1_CTL_411_DATA 0x00014424
 #define DDRSS1_CTL_412_DATA 0x02020E15
 #define DDRSS1_CTL_413_DATA 0x03030202
 #define DDRSS1_CTL_414_DATA 0x00000022
@@ -2831,11 +2831,11 @@
 #define DDRSS1_PI_167_DATA 0x02000200
 #define DDRSS1_PI_168_DATA 0x48120C04
 #define DDRSS1_PI_169_DATA 0x00154812
-#define DDRSS1_PI_170_DATA 0x000000CE
+#define DDRSS1_PI_170_DATA 0x00000063
 #define DDRSS1_PI_171_DATA 0x0000032B
-#define DDRSS1_PI_172_DATA 0x00002073
+#define DDRSS1_PI_172_DATA 0x00001035
 #define DDRSS1_PI_173_DATA 0x0000032B
-#define DDRSS1_PI_174_DATA 0x04002073
+#define DDRSS1_PI_174_DATA 0x04001035
 #define DDRSS1_PI_175_DATA 0x01010404
 #define DDRSS1_PI_176_DATA 0x00001501
 #define DDRSS1_PI_177_DATA 0x00150015
@@ -2880,22 +2880,22 @@
 #define DDRSS1_PI_216_DATA 0x3212005B
 #define DDRSS1_PI_217_DATA 0x09000301
 #define DDRSS1_PI_218_DATA 0x04010504
-#define DDRSS1_PI_219_DATA 0x040006C9
+#define DDRSS1_PI_219_DATA 0x04000364
 #define DDRSS1_PI_220_DATA 0x0A032001
 #define DDRSS1_PI_221_DATA 0x2C31110A
 #define DDRSS1_PI_222_DATA 0x00002918
-#define DDRSS1_PI_223_DATA 0x6001071C
+#define DDRSS1_PI_223_DATA 0x6000838E
 #define DDRSS1_PI_224_DATA 0x1E202008
 #define DDRSS1_PI_225_DATA 0x2C311116
 #define DDRSS1_PI_226_DATA 0x00002918
-#define DDRSS1_PI_227_DATA 0x6001071C
+#define DDRSS1_PI_227_DATA 0x6000838E
 #define DDRSS1_PI_228_DATA 0x1E202008
-#define DDRSS1_PI_229_DATA 0x00019C16
-#define DDRSS1_PI_230_DATA 0x00001018
-#define DDRSS1_PI_231_DATA 0x000040E6
-#define DDRSS1_PI_232_DATA 0x000288FC
-#define DDRSS1_PI_233_DATA 0x000040E6
-#define DDRSS1_PI_234_DATA 0x000288FC
+#define DDRSS1_PI_229_DATA 0x0000C616
+#define DDRSS1_PI_230_DATA 0x000007BC
+#define DDRSS1_PI_231_DATA 0x0000206A
+#define DDRSS1_PI_232_DATA 0x00014424
+#define DDRSS1_PI_233_DATA 0x0000206A
+#define DDRSS1_PI_234_DATA 0x00014424
 #define DDRSS1_PI_235_DATA 0x033B0016
 #define DDRSS1_PI_236_DATA 0x0303033B
 #define DDRSS1_PI_237_DATA 0x002AF803
@@ -4430,11 +4430,11 @@
 #define DDRSS2_CTL_41_DATA 0x1760008B
 #define DDRSS2_CTL_42_DATA 0x2000422B
 #define DDRSS2_CTL_43_DATA 0x000A0A09
-#define DDRSS2_CTL_44_DATA 0x0400078A
+#define DDRSS2_CTL_44_DATA 0x040003C5
 #define DDRSS2_CTL_45_DATA 0x1E161104
-#define DDRSS2_CTL_46_DATA 0x10012458
+#define DDRSS2_CTL_46_DATA 0x1000922C
 #define DDRSS2_CTL_47_DATA 0x1E161110
-#define DDRSS2_CTL_48_DATA 0x10012458
+#define DDRSS2_CTL_48_DATA 0x1000922C
 #define DDRSS2_CTL_49_DATA 0x02030410
 #define DDRSS2_CTL_50_DATA 0x2C040500
 #define DDRSS2_CTL_51_DATA 0x08292C29
@@ -4447,11 +4447,11 @@
 #define DDRSS2_CTL_58_DATA 0x00010100
 #define DDRSS2_CTL_59_DATA 0x03010000
 #define DDRSS2_CTL_60_DATA 0x00001508
-#define DDRSS2_CTL_61_DATA 0x000000CE
+#define DDRSS2_CTL_61_DATA 0x00000063
 #define DDRSS2_CTL_62_DATA 0x0000032B
-#define DDRSS2_CTL_63_DATA 0x00002073
+#define DDRSS2_CTL_63_DATA 0x00001035
 #define DDRSS2_CTL_64_DATA 0x0000032B
-#define DDRSS2_CTL_65_DATA 0x00002073
+#define DDRSS2_CTL_65_DATA 0x00001035
 #define DDRSS2_CTL_66_DATA 0x00000005
 #define DDRSS2_CTL_67_DATA 0x00050000
 #define DDRSS2_CTL_68_DATA 0x00CB0012
@@ -4488,27 +4488,27 @@
 #define DDRSS2_CTL_99_DATA 0x00000000
 #define DDRSS2_CTL_100_DATA 0x00040005
 #define DDRSS2_CTL_101_DATA 0x00000000
-#define DDRSS2_CTL_102_DATA 0x00003380
-#define DDRSS2_CTL_103_DATA 0x00003380
-#define DDRSS2_CTL_104_DATA 0x00003380
-#define DDRSS2_CTL_105_DATA 0x00003380
-#define DDRSS2_CTL_106_DATA 0x00003380
+#define DDRSS2_CTL_102_DATA 0x000018C0
+#define DDRSS2_CTL_103_DATA 0x000018C0
+#define DDRSS2_CTL_104_DATA 0x000018C0
+#define DDRSS2_CTL_105_DATA 0x000018C0
+#define DDRSS2_CTL_106_DATA 0x000018C0
 #define DDRSS2_CTL_107_DATA 0x00000000
-#define DDRSS2_CTL_108_DATA 0x000005A2
-#define DDRSS2_CTL_109_DATA 0x00081CC0
-#define DDRSS2_CTL_110_DATA 0x00081CC0
-#define DDRSS2_CTL_111_DATA 0x00081CC0
-#define DDRSS2_CTL_112_DATA 0x00081CC0
-#define DDRSS2_CTL_113_DATA 0x00081CC0
+#define DDRSS2_CTL_108_DATA 0x000002B5
+#define DDRSS2_CTL_109_DATA 0x00040D40
+#define DDRSS2_CTL_110_DATA 0x00040D40
+#define DDRSS2_CTL_111_DATA 0x00040D40
+#define DDRSS2_CTL_112_DATA 0x00040D40
+#define DDRSS2_CTL_113_DATA 0x00040D40
 #define DDRSS2_CTL_114_DATA 0x00000000
-#define DDRSS2_CTL_115_DATA 0x0000E325
-#define DDRSS2_CTL_116_DATA 0x00081CC0
-#define DDRSS2_CTL_117_DATA 0x00081CC0
-#define DDRSS2_CTL_118_DATA 0x00081CC0
-#define DDRSS2_CTL_119_DATA 0x00081CC0
-#define DDRSS2_CTL_120_DATA 0x00081CC0
+#define DDRSS2_CTL_115_DATA 0x00007173
+#define DDRSS2_CTL_116_DATA 0x00040D40
+#define DDRSS2_CTL_117_DATA 0x00040D40
+#define DDRSS2_CTL_118_DATA 0x00040D40
+#define DDRSS2_CTL_119_DATA 0x00040D40
+#define DDRSS2_CTL_120_DATA 0x00040D40
 #define DDRSS2_CTL_121_DATA 0x00000000
-#define DDRSS2_CTL_122_DATA 0x0000E325
+#define DDRSS2_CTL_122_DATA 0x00007173
 #define DDRSS2_CTL_123_DATA 0x00000000
 #define DDRSS2_CTL_124_DATA 0x00000000
 #define DDRSS2_CTL_125_DATA 0x00000000
@@ -4775,29 +4775,29 @@
 #define DDRSS2_CTL_386_DATA 0x00000000
 #define DDRSS2_CTL_387_DATA 0x3A3A1B00
 #define DDRSS2_CTL_388_DATA 0x000A0000
-#define DDRSS2_CTL_389_DATA 0x0000019C
+#define DDRSS2_CTL_389_DATA 0x000000C6
 #define DDRSS2_CTL_390_DATA 0x00000200
 #define DDRSS2_CTL_391_DATA 0x00000200
 #define DDRSS2_CTL_392_DATA 0x00000200
 #define DDRSS2_CTL_393_DATA 0x00000200
-#define DDRSS2_CTL_394_DATA 0x000004D4
-#define DDRSS2_CTL_395_DATA 0x00001018
+#define DDRSS2_CTL_394_DATA 0x00000252
+#define DDRSS2_CTL_395_DATA 0x000007BC
 #define DDRSS2_CTL_396_DATA 0x00000204
-#define DDRSS2_CTL_397_DATA 0x000040E6
+#define DDRSS2_CTL_397_DATA 0x0000206A
 #define DDRSS2_CTL_398_DATA 0x00000200
 #define DDRSS2_CTL_399_DATA 0x00000200
 #define DDRSS2_CTL_400_DATA 0x00000200
 #define DDRSS2_CTL_401_DATA 0x00000200
-#define DDRSS2_CTL_402_DATA 0x0000C2B2
-#define DDRSS2_CTL_403_DATA 0x000288FC
+#define DDRSS2_CTL_402_DATA 0x0000613E
+#define DDRSS2_CTL_403_DATA 0x00014424
 #define DDRSS2_CTL_404_DATA 0x00000E15
-#define DDRSS2_CTL_405_DATA 0x000040E6
+#define DDRSS2_CTL_405_DATA 0x0000206A
 #define DDRSS2_CTL_406_DATA 0x00000200
 #define DDRSS2_CTL_407_DATA 0x00000200
 #define DDRSS2_CTL_408_DATA 0x00000200
 #define DDRSS2_CTL_409_DATA 0x00000200
-#define DDRSS2_CTL_410_DATA 0x0000C2B2
-#define DDRSS2_CTL_411_DATA 0x000288FC
+#define DDRSS2_CTL_410_DATA 0x0000613E
+#define DDRSS2_CTL_411_DATA 0x00014424
 #define DDRSS2_CTL_412_DATA 0x02020E15
 #define DDRSS2_CTL_413_DATA 0x03030202
 #define DDRSS2_CTL_414_DATA 0x00000022
@@ -5016,11 +5016,11 @@
 #define DDRSS2_PI_167_DATA 0x02000200
 #define DDRSS2_PI_168_DATA 0x48120C04
 #define DDRSS2_PI_169_DATA 0x00154812
-#define DDRSS2_PI_170_DATA 0x000000CE
+#define DDRSS2_PI_170_DATA 0x00000063
 #define DDRSS2_PI_171_DATA 0x0000032B
-#define DDRSS2_PI_172_DATA 0x00002073
+#define DDRSS2_PI_172_DATA 0x00001035
 #define DDRSS2_PI_173_DATA 0x0000032B
-#define DDRSS2_PI_174_DATA 0x04002073
+#define DDRSS2_PI_174_DATA 0x04001035
 #define DDRSS2_PI_175_DATA 0x01010404
 #define DDRSS2_PI_176_DATA 0x00001501
 #define DDRSS2_PI_177_DATA 0x00150015
@@ -5065,22 +5065,22 @@
 #define DDRSS2_PI_216_DATA 0x3212005B
 #define DDRSS2_PI_217_DATA 0x09000301
 #define DDRSS2_PI_218_DATA 0x04010504
-#define DDRSS2_PI_219_DATA 0x040006C9
+#define DDRSS2_PI_219_DATA 0x04000364
 #define DDRSS2_PI_220_DATA 0x0A032001
 #define DDRSS2_PI_221_DATA 0x2C31110A
 #define DDRSS2_PI_222_DATA 0x00002918
-#define DDRSS2_PI_223_DATA 0x6001071C
+#define DDRSS2_PI_223_DATA 0x6000838E
 #define DDRSS2_PI_224_DATA 0x1E202008
 #define DDRSS2_PI_225_DATA 0x2C311116
 #define DDRSS2_PI_226_DATA 0x00002918
-#define DDRSS2_PI_227_DATA 0x6001071C
+#define DDRSS2_PI_227_DATA 0x6000838E
 #define DDRSS2_PI_228_DATA 0x1E202008
-#define DDRSS2_PI_229_DATA 0x00019C16
-#define DDRSS2_PI_230_DATA 0x00001018
-#define DDRSS2_PI_231_DATA 0x000040E6
-#define DDRSS2_PI_232_DATA 0x000288FC
-#define DDRSS2_PI_233_DATA 0x000040E6
-#define DDRSS2_PI_234_DATA 0x000288FC
+#define DDRSS2_PI_229_DATA 0x0000C616
+#define DDRSS2_PI_230_DATA 0x000007BC
+#define DDRSS2_PI_231_DATA 0x0000206A
+#define DDRSS2_PI_232_DATA 0x00014424
+#define DDRSS2_PI_233_DATA 0x0000206A
+#define DDRSS2_PI_234_DATA 0x00014424
 #define DDRSS2_PI_235_DATA 0x033B0016
 #define DDRSS2_PI_236_DATA 0x0303033B
 #define DDRSS2_PI_237_DATA 0x002AF803
@@ -6615,11 +6615,11 @@
 #define DDRSS3_CTL_41_DATA 0x1760008B
 #define DDRSS3_CTL_42_DATA 0x2000422B
 #define DDRSS3_CTL_43_DATA 0x000A0A09
-#define DDRSS3_CTL_44_DATA 0x0400078A
+#define DDRSS3_CTL_44_DATA 0x040003C5
 #define DDRSS3_CTL_45_DATA 0x1E161104
-#define DDRSS3_CTL_46_DATA 0x10012458
+#define DDRSS3_CTL_46_DATA 0x1000922C
 #define DDRSS3_CTL_47_DATA 0x1E161110
-#define DDRSS3_CTL_48_DATA 0x10012458
+#define DDRSS3_CTL_48_DATA 0x1000922C
 #define DDRSS3_CTL_49_DATA 0x02030410
 #define DDRSS3_CTL_50_DATA 0x2C040500
 #define DDRSS3_CTL_51_DATA 0x08292C29
@@ -6632,11 +6632,11 @@
 #define DDRSS3_CTL_58_DATA 0x00010100
 #define DDRSS3_CTL_59_DATA 0x03010000
 #define DDRSS3_CTL_60_DATA 0x00001508
-#define DDRSS3_CTL_61_DATA 0x000000CE
+#define DDRSS3_CTL_61_DATA 0x00000063
 #define DDRSS3_CTL_62_DATA 0x0000032B
-#define DDRSS3_CTL_63_DATA 0x00002073
+#define DDRSS3_CTL_63_DATA 0x00001035
 #define DDRSS3_CTL_64_DATA 0x0000032B
-#define DDRSS3_CTL_65_DATA 0x00002073
+#define DDRSS3_CTL_65_DATA 0x00001035
 #define DDRSS3_CTL_66_DATA 0x00000005
 #define DDRSS3_CTL_67_DATA 0x00050000
 #define DDRSS3_CTL_68_DATA 0x00CB0012
@@ -6673,27 +6673,27 @@
 #define DDRSS3_CTL_99_DATA 0x00000000
 #define DDRSS3_CTL_100_DATA 0x00040005
 #define DDRSS3_CTL_101_DATA 0x00000000
-#define DDRSS3_CTL_102_DATA 0x00003380
-#define DDRSS3_CTL_103_DATA 0x00003380
-#define DDRSS3_CTL_104_DATA 0x00003380
-#define DDRSS3_CTL_105_DATA 0x00003380
-#define DDRSS3_CTL_106_DATA 0x00003380
+#define DDRSS3_CTL_102_DATA 0x000018C0
+#define DDRSS3_CTL_103_DATA 0x000018C0
+#define DDRSS3_CTL_104_DATA 0x000018C0
+#define DDRSS3_CTL_105_DATA 0x000018C0
+#define DDRSS3_CTL_106_DATA 0x000018C0
 #define DDRSS3_CTL_107_DATA 0x00000000
-#define DDRSS3_CTL_108_DATA 0x000005A2
-#define DDRSS3_CTL_109_DATA 0x00081CC0
-#define DDRSS3_CTL_110_DATA 0x00081CC0
-#define DDRSS3_CTL_111_DATA 0x00081CC0
-#define DDRSS3_CTL_112_DATA 0x00081CC0
-#define DDRSS3_CTL_113_DATA 0x00081CC0
+#define DDRSS3_CTL_108_DATA 0x000002B5
+#define DDRSS3_CTL_109_DATA 0x00040D40
+#define DDRSS3_CTL_110_DATA 0x00040D40
+#define DDRSS3_CTL_111_DATA 0x00040D40
+#define DDRSS3_CTL_112_DATA 0x00040D40
+#define DDRSS3_CTL_113_DATA 0x00040D40
 #define DDRSS3_CTL_114_DATA 0x00000000
-#define DDRSS3_CTL_115_DATA 0x0000E325
-#define DDRSS3_CTL_116_DATA 0x00081CC0
-#define DDRSS3_CTL_117_DATA 0x00081CC0
-#define DDRSS3_CTL_118_DATA 0x00081CC0
-#define DDRSS3_CTL_119_DATA 0x00081CC0
-#define DDRSS3_CTL_120_DATA 0x00081CC0
+#define DDRSS3_CTL_115_DATA 0x00007173
+#define DDRSS3_CTL_116_DATA 0x00040D40
+#define DDRSS3_CTL_117_DATA 0x00040D40
+#define DDRSS3_CTL_118_DATA 0x00040D40
+#define DDRSS3_CTL_119_DATA 0x00040D40
+#define DDRSS3_CTL_120_DATA 0x00040D40
 #define DDRSS3_CTL_121_DATA 0x00000000
-#define DDRSS3_CTL_122_DATA 0x0000E325
+#define DDRSS3_CTL_122_DATA 0x00007173
 #define DDRSS3_CTL_123_DATA 0x00000000
 #define DDRSS3_CTL_124_DATA 0x00000000
 #define DDRSS3_CTL_125_DATA 0x00000000
@@ -6960,29 +6960,29 @@
 #define DDRSS3_CTL_386_DATA 0x00000000
 #define DDRSS3_CTL_387_DATA 0x3A3A1B00
 #define DDRSS3_CTL_388_DATA 0x000A0000
-#define DDRSS3_CTL_389_DATA 0x0000019C
+#define DDRSS3_CTL_389_DATA 0x000000C6
 #define DDRSS3_CTL_390_DATA 0x00000200
 #define DDRSS3_CTL_391_DATA 0x00000200
 #define DDRSS3_CTL_392_DATA 0x00000200
 #define DDRSS3_CTL_393_DATA 0x00000200
-#define DDRSS3_CTL_394_DATA 0x000004D4
-#define DDRSS3_CTL_395_DATA 0x00001018
+#define DDRSS3_CTL_394_DATA 0x00000252
+#define DDRSS3_CTL_395_DATA 0x000007BC
 #define DDRSS3_CTL_396_DATA 0x00000204
-#define DDRSS3_CTL_397_DATA 0x000040E6
+#define DDRSS3_CTL_397_DATA 0x0000206A
 #define DDRSS3_CTL_398_DATA 0x00000200
 #define DDRSS3_CTL_399_DATA 0x00000200
 #define DDRSS3_CTL_400_DATA 0x00000200
 #define DDRSS3_CTL_401_DATA 0x00000200
-#define DDRSS3_CTL_402_DATA 0x0000C2B2
-#define DDRSS3_CTL_403_DATA 0x000288FC
+#define DDRSS3_CTL_402_DATA 0x0000613E
+#define DDRSS3_CTL_403_DATA 0x00014424
 #define DDRSS3_CTL_404_DATA 0x00000E15
-#define DDRSS3_CTL_405_DATA 0x000040E6
+#define DDRSS3_CTL_405_DATA 0x0000206A
 #define DDRSS3_CTL_406_DATA 0x00000200
 #define DDRSS3_CTL_407_DATA 0x00000200
 #define DDRSS3_CTL_408_DATA 0x00000200
 #define DDRSS3_CTL_409_DATA 0x00000200
-#define DDRSS3_CTL_410_DATA 0x0000C2B2
-#define DDRSS3_CTL_411_DATA 0x000288FC
+#define DDRSS3_CTL_410_DATA 0x0000613E
+#define DDRSS3_CTL_411_DATA 0x00014424
 #define DDRSS3_CTL_412_DATA 0x02020E15
 #define DDRSS3_CTL_413_DATA 0x03030202
 #define DDRSS3_CTL_414_DATA 0x00000022
@@ -7201,11 +7201,11 @@
 #define DDRSS3_PI_167_DATA 0x02000200
 #define DDRSS3_PI_168_DATA 0x48120C04
 #define DDRSS3_PI_169_DATA 0x00154812
-#define DDRSS3_PI_170_DATA 0x000000CE
+#define DDRSS3_PI_170_DATA 0x00000063
 #define DDRSS3_PI_171_DATA 0x0000032B
-#define DDRSS3_PI_172_DATA 0x00002073
+#define DDRSS3_PI_172_DATA 0x00001035
 #define DDRSS3_PI_173_DATA 0x0000032B
-#define DDRSS3_PI_174_DATA 0x04002073
+#define DDRSS3_PI_174_DATA 0x04001035
 #define DDRSS3_PI_175_DATA 0x01010404
 #define DDRSS3_PI_176_DATA 0x00001501
 #define DDRSS3_PI_177_DATA 0x00150015
@@ -7250,22 +7250,22 @@
 #define DDRSS3_PI_216_DATA 0x3212005B
 #define DDRSS3_PI_217_DATA 0x09000301
 #define DDRSS3_PI_218_DATA 0x04010504
-#define DDRSS3_PI_219_DATA 0x040006C9
+#define DDRSS3_PI_219_DATA 0x04000364
 #define DDRSS3_PI_220_DATA 0x0A032001
 #define DDRSS3_PI_221_DATA 0x2C31110A
 #define DDRSS3_PI_222_DATA 0x00002918
-#define DDRSS3_PI_223_DATA 0x6001071C
+#define DDRSS3_PI_223_DATA 0x6000838E
 #define DDRSS3_PI_224_DATA 0x1E202008
 #define DDRSS3_PI_225_DATA 0x2C311116
 #define DDRSS3_PI_226_DATA 0x00002918
-#define DDRSS3_PI_227_DATA 0x6001071C
+#define DDRSS3_PI_227_DATA 0x6000838E
 #define DDRSS3_PI_228_DATA 0x1E202008
-#define DDRSS3_PI_229_DATA 0x00019C16
-#define DDRSS3_PI_230_DATA 0x00001018
-#define DDRSS3_PI_231_DATA 0x000040E6
-#define DDRSS3_PI_232_DATA 0x000288FC
-#define DDRSS3_PI_233_DATA 0x000040E6
-#define DDRSS3_PI_234_DATA 0x000288FC
+#define DDRSS3_PI_229_DATA 0x0000C616
+#define DDRSS3_PI_230_DATA 0x000007BC
+#define DDRSS3_PI_231_DATA 0x0000206A
+#define DDRSS3_PI_232_DATA 0x00014424
+#define DDRSS3_PI_233_DATA 0x0000206A
+#define DDRSS3_PI_234_DATA 0x00014424
 #define DDRSS3_PI_235_DATA 0x033B0016
 #define DDRSS3_PI_236_DATA 0x0303033B
 #define DDRSS3_PI_237_DATA 0x002AF803
diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c
index a59adaf051..050614a64b 100644
--- a/board/ti/j784s4/evm.c
+++ b/board/ti/j784s4/evm.c
@@ -65,8 +65,8 @@ int dram_init_banksize(void)
 #ifdef CONFIG_PHYS_64BIT
 	/* Bank 1 declares the memory available in the DDR high region */
 	gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
-	gd->bd->bi_dram[1].size = 0x77fffffff;
-	gd->ram_size = 0x800000000;
+	gd->bd->bi_dram[1].size = 0x37fffffff;
+	gd->ram_size = 0x400000000;
 #endif
 
 	return 0;
