From 663046ba77d70e709c07f49a825469c22a0748c5 Mon Sep 17 00:00:00 2001
From: Buddy Liong <a0270631@ti.com>
Date: Fri, 11 Aug 2017 16:04:50 -0500
Subject: [PATCH] RVC: Enabling OSD panel for J6/J6Eco

Before the patch, LG display panel is used for J6 EVM.
When enabling J6Eco EVM, OSD display panel needs to be enabled which can be used for J6 EVM as well.
For J6Entry, only AUO display panel is supported.

Signed-off-by: Buddy Liong <a0270631@ti.com>
---
 .../rvcDiags/rvcDiagnostic_algLink_priv.h          | 37 +++++----
 .../tda2xx/src/common/chains_main_robust_rvc.c     |  3 +-
 .../tda2xx/src/usecases/common/chains_common.c     | 13 +++
 .../chains_vipSingleRvcCamCrc_Display.c            | 94 +++++++++++++---------
 4 files changed, 92 insertions(+), 55 deletions(-)

diff --git a/examples/tda2xx/src/alg_plugins/rvcDiags/rvcDiagnostic_algLink_priv.h b/examples/tda2xx/src/alg_plugins/rvcDiags/rvcDiagnostic_algLink_priv.h
index d1a4e75..f37f402 100755
--- a/examples/tda2xx/src/alg_plugins/rvcDiags/rvcDiagnostic_algLink_priv.h
+++ b/examples/tda2xx/src/alg_plugins/rvcDiags/rvcDiagnostic_algLink_priv.h
@@ -158,10 +158,11 @@ static RegField_t perFrameDiagnosticsRegField[MAX_PF_DIAG_REGFIELDS] =
     // DISPC Module
 #ifdef TDA2EX_BUILD
     // 4: SOC_DISPC_BASE, DSS_DISPC_TIMING_H3 - HBP, HFP, HSW
-    {SOC_DISPC_BASE, DSS_DISPC_TIMING_H3, 0xFFFFFFFF, 0, 0x02F02F1F},
+    //{SOC_DISPC_BASE, DSS_DISPC_TIMING_H3, 0xFFFFFFFF, 0, 0x02F02F1F},
 #else
     // 4: SOC_DISPC_BASE, DSS_DISPC_TIMING_H1 - HBP, HFP, HSW
-    {SOC_DISPC_BASE, DSS_DISPC_TIMING_H1, 0xFFFFFFFF, 0, 0x02B02F1F},
+    //{SOC_DISPC_BASE, DSS_DISPC_TIMING_H1, 0xFFFFFFFF, 0, 0x02B02F1F},
+    {SOC_DISPC_BASE, DSS_DISPC_TIMING_H1, 0xFFFFFFFF, 0, 0x01F06F0F},
 #endif
     // 5: SOC_DISPC_BASE, DSS_DISPC_POL_FREQ1 - IEO
     {SOC_DISPC_BASE, DSS_DISPC_POL_FREQ1, DSS_DISPC_POL_FREQ1_IEO_MASK, DSS_DISPC_POL_FREQ1_IEO_SHIFT, 0x0},
@@ -169,18 +170,21 @@ static RegField_t perFrameDiagnosticsRegField[MAX_PF_DIAG_REGFIELDS] =
     {SOC_DISPC_BASE, DSS_DISPC_GLOBAL_ALPHA, 0xFFFFFFFF, 0, 0xFFFFFFFF},
 #ifdef TDA2EX_BUILD
     // 7: SOC_DISPC_BASE, DSS_DISPC_SIZE_LCD3 - LPP (lines per panel), PPL (pixels per line)
-    {SOC_DISPC_BASE, DSS_DISPC_SIZE_LCD3, 0xFFFFFFFF, 0, 0x031F04FF},
+    //{SOC_DISPC_BASE, DSS_DISPC_SIZE_LCD3, 0xFFFFFFFF, 0, 0x031F04FF},
 #else
     // 7: SOC_DISPC_BASE, DSS_DISPC_SIZE_LCD1 - LPP (lines per panel), PPL (pixels per line)
-    {SOC_DISPC_BASE, DSS_DISPC_SIZE_LCD1, 0xFFFFFFFF, 0, 0x031F04FF},
+    //{SOC_DISPC_BASE, DSS_DISPC_SIZE_LCD1, 0xFFFFFFFF, 0, 0x031F04FF},
+    {SOC_DISPC_BASE, DSS_DISPC_SIZE_LCD1, 0xFFFFFFFF, 0, 0x04AF077F},
 #endif
     // 8: DSS_DISPC_VID2_POSITION (POSX = 280; POSY = 45)
-    {SOC_DISPC_BASE, DSS_DISPC_VID2_POSITION, 0xFFFFFFFF, 0, 0x002D0118},
+    //{SOC_DISPC_BASE, DSS_DISPC_VID2_POSITION, 0xFFFFFFFF, 0, 0x002D0118},
+    {SOC_DISPC_BASE, DSS_DISPC_VID2_POSITION, 0xFFFFFFFF, 0, 0x0},
     // 9: DSS_DISPC_VID2_SIZE (SIZEY = 479; SIZEX = 719; 720x480 VID2 size)
-    {SOC_DISPC_BASE, DSS_DISPC_VID2_SIZE, 0xFFFFFFFF, 0, 0x01DF02CF},
+    // Depending on the usecase for VID2 size
+    //{SOC_DISPC_BASE, DSS_DISPC_VID2_SIZE, 0xFFFFFFFF, 0, 0x01DF02CF},
 #ifdef TDA2EX_BUILD
     // 10: DSS_DISPC_VID2_ATTRIBUTES
-    {SOC_DISPC_BASE, DSS_DISPC_VID2_ATTRIBUTES, 0xFFFFFFFF, 0, 0x8628886B},
+    //{SOC_DISPC_BASE, DSS_DISPC_VID2_ATTRIBUTES, 0xFFFFFFFF, 0, 0x8628886B},
 #else
     // 10: DSS_DISPC_VID2_ATTRIBUTES
     {SOC_DISPC_BASE, DSS_DISPC_VID2_ATTRIBUTES, 0xFFFFFFFF, 0, 0x0628886B},
@@ -190,21 +194,24 @@ static RegField_t perFrameDiagnosticsRegField[MAX_PF_DIAG_REGFIELDS] =
     // 12: DSS_DISPC_VID2_ROW_INC
     {SOC_DISPC_BASE, DSS_DISPC_VID2_ROW_INC, 0xFFFFFFFF, 0, 0x1},
     // 13: Resize factors for horizontal and vertical up/down sampling
-    {SOC_DISPC_BASE, DSS_DISPC_VID2_FIR, 0xFFFFFFFF, 0, 0x06AA071C},
+    //{SOC_DISPC_BASE, DSS_DISPC_VID2_FIR, 0xFFFFFFFF, 0, 0x06AA071C},
+    //{SOC_DISPC_BASE, DSS_DISPC_VID2_FIR, 0xFFFFFFFF, 0, 0x0A000AAA},
     // 14: picture size before up/down scaling MEMSIZEY, MEMSIZEX
-    {SOC_DISPC_BASE, DSS_DISPC_VID2_PICTURE_SIZE, 0xFFFFFFFF, 0, 0x031F04FF},
+    //{SOC_DISPC_BASE, DSS_DISPC_VID2_PICTURE_SIZE, 0xFFFFFFFF, 0, 0x031F04FF},
+    {SOC_DISPC_BASE, DSS_DISPC_VID2_PICTURE_SIZE, 0xFFFFFFFF, 0, 0x04AF077F},
     // 15: DSS_DISPC_VID3_POSITION
-    {SOC_DISPC_BASE, DSS_DISPC_VID3_POSITION, 0xFFFFFFFF, 0, 0x000A0118},
+    //{SOC_DISPC_BASE, DSS_DISPC_VID3_POSITION, 0xFFFFFFFF, 0, 0x000A0118},
+    {SOC_DISPC_BASE, DSS_DISPC_VID3_POSITION, 0xFFFFFFFF, 0, 0x0},
     // 16: DSS_DISPC_VID3_SIZE
-    {SOC_DISPC_BASE, DSS_DISPC_VID3_SIZE, 0x0FFF0FFF, 0, 0x01DF02CF},
+    //{SOC_DISPC_BASE, DSS_DISPC_VID3_SIZE, 0x0FFF0FFF, 0, 0x01DF02CF},
 #ifdef TDA2EX_BUILD
     // 17: DSS_DISPC_VID3_ATTRIBUTES
-    {SOC_DISPC_BASE, DSS_DISPC_VID3_ATTRIBUTES, 0xFFFFFFFF, 0, 0x8A288A35},
+    //{SOC_DISPC_BASE, DSS_DISPC_VID3_ATTRIBUTES, 0xFFFFFFFF, 0, 0x8A288A35},
 #else
     // 17: DSS_DISPC_VID3_ATTRIBUTES
     {SOC_DISPC_BASE, DSS_DISPC_VID3_ATTRIBUTES, 0xFFFFFFFF, 0, 0x0A288A35},
 #endif
-    // 18: DSS_DISPC_VID3_ATTRIBUTES2
+    // 18: DSS_DISPC_VID3_ATTRIBUTES
     {SOC_DISPC_BASE, DSS_DISPC_VID3_ATTRIBUTES2, 0xFFFFFFFF, 0, 0x0},
     // 19: DSS_DISPC_VID3_ROW_INC
     {SOC_DISPC_BASE, DSS_DISPC_VID3_ROW_INC, 0xFFFFFFFF, 0, 0x1},
@@ -215,9 +222,9 @@ static RegField_t perFrameDiagnosticsRegField[MAX_PF_DIAG_REGFIELDS] =
 #ifdef GPIO_IN_INTERRUPT
 #ifdef TDA2EX_BUILD
     // 22: GPIO 6 Pin 28 - reverse gear detection; SOC_CORE_PAD_IO_REGISTERS_BASE - set MUXMODE to gpio6_28 CTRL_CORE_PAD_MMC1_SDWP
-    {SOC_CORE_PAD_IO_REGISTERS_BASE, CTRL_CORE_PAD_MMC1_SDWP, CTRL_CORE_PAD_MMC1_SDWP_MMC1_SDWP_MUXMODE_MASK, CTRL_CORE_PAD_MMC1_SDWP_MMC1_SDWP_MUXMODE_SHIFT, CTRL_CORE_PAD_MMC1_SDWP_MMC1_SDWP_MUXMODE_GPIO6_28_14},
+    //{SOC_CORE_PAD_IO_REGISTERS_BASE, CTRL_CORE_PAD_MMC1_SDWP, CTRL_CORE_PAD_MMC1_SDWP_MMC1_SDWP_MUXMODE_MASK, CTRL_CORE_PAD_MMC1_SDWP_MMC1_SDWP_MUXMODE_SHIFT, CTRL_CORE_PAD_MMC1_SDWP_MMC1_SDWP_MUXMODE_GPIO6_28_14},
     // 23: GPIO 6 Pin 28 - reverse gear detection; CTRL_CORE_IPU2_IRQ_49_50 - set IPU2_IRQ_49 to point to IRQ_CROSSBAR_347 (0x15B)
-    {SOC_IRQ_DMARQ_CROSSBAR_REGISTERS_BASE, CTRL_CORE_IPU2_IRQ_49_50, CTRL_CORE_IPU2_IRQ_49_50_IPU2_IRQ_49_MASK, CTRL_CORE_IPU2_IRQ_49_50_IPU2_IRQ_49_SHIFT, 0x8F}
+    //{SOC_IRQ_DMARQ_CROSSBAR_REGISTERS_BASE, CTRL_CORE_IPU2_IRQ_49_50, CTRL_CORE_IPU2_IRQ_49_50_IPU2_IRQ_49_MASK, CTRL_CORE_IPU2_IRQ_49_50_IPU2_IRQ_49_SHIFT, 0x8F}
 #else
     // 22: GPIO 7 Pin 18 - reverse gear detection; SOC_CORE_PAD_IO_REGISTERS_BASE - set MUXMODE to gpio7_18
     {SOC_CORE_PAD_IO_REGISTERS_BASE, CTRL_CORE_PAD_GPMC_AD8, CTRL_CORE_PAD_GPMC_AD8_GPMC_AD8_MUXMODE_MASK, CTRL_CORE_PAD_GPMC_AD8_GPMC_AD8_MUXMODE_SHIFT, CTRL_CORE_PAD_GPMC_AD8_GPMC_AD8_MUXMODE_GPIO7_18_14},
diff --git a/examples/tda2xx/src/common/chains_main_robust_rvc.c b/examples/tda2xx/src/common/chains_main_robust_rvc.c
index 9751539..4db6aa2 100644
--- a/examples/tda2xx/src/common/chains_main_robust_rvc.c
+++ b/examples/tda2xx/src/common/chains_main_robust_rvc.c
@@ -163,7 +163,8 @@ Void Chains_main(UArg arg0, UArg arg1)
     Rvc_ChainsCommon_Init();
 
     Chains_Ctrl_Init(&gChains_usecaseCfg);
-    gChains_usecaseCfg.displayType = CHAINS_DISPLAY_TYPE_LCD_10_INCH;
+    gChains_usecaseCfg.displayType = CHAINS_DISPLAY_TYPE_LDC_10_INCH_LCDCTRL_TC358778_MIPI_DSI_1920_1200;
+    //gChains_usecaseCfg.displayType = CHAINS_DISPLAY_TYPE_LCD_10_INCH;
     gChains_usecaseCfg.captureSrc = CHAINS_CAPTURE_SRC_VIDDEC_TVP5158;
 
     Chains_menuSingleCameraRun();
diff --git a/examples/tda2xx/src/usecases/common/chains_common.c b/examples/tda2xx/src/usecases/common/chains_common.c
index 421c7aa..5255e70 100644
--- a/examples/tda2xx/src/usecases/common/chains_common.c
+++ b/examples/tda2xx/src/usecases/common/chains_common.c
@@ -272,6 +272,18 @@ static Void ChainsCommon_SetDctrlConfig(
         pVInfo->mInfo.vSyncLen                  =   2U;
         pVInfo->mInfo.vFrontPorch               =   7U;
     #else
+#ifdef ROBUST_RVC_INCLUDE
+        Vps_printf("ChainsCommon_setDctrlConfig setting correctly for OSD panel\n");
+
+        pVInfo->mInfo.pixelClock				=	154000U;
+        pVInfo->mInfo.fps					=	60U;
+        pVInfo->mInfo.hBackPorch				=	32U;
+        pVInfo->mInfo.hSyncLen					=	16U;
+        pVInfo->mInfo.hFrontPorch				=	112U;
+        pVInfo->mInfo.vBackPorch				=	16U;
+        pVInfo->mInfo.vSyncLen					=	2U;
+        pVInfo->mInfo.vFrontPorch				=	16U;
+#else
         pVInfo->mInfo.pixelClock                =   78000U;
         pVInfo->mInfo.fps                       =   32U;
         pVInfo->mInfo.hBackPorch                =   32U;
@@ -280,6 +292,7 @@ static Void ChainsCommon_SetDctrlConfig(
         pVInfo->mInfo.vBackPorch                =   16U;
         pVInfo->mInfo.vSyncLen                  =   2U;
         pVInfo->mInfo.vFrontPorch               =   17U;
+#endif
     #endif
         pVInfo->vencDivisorInfo.divisorLCD      =   1;
         pVInfo->vencDivisorInfo.divisorPCD      =   1;
diff --git a/examples/tda2xx/src/usecases/vip_single_rvc_cam_view_crc/chains_vipSingleRvcCamCrc_Display.c b/examples/tda2xx/src/usecases/vip_single_rvc_cam_view_crc/chains_vipSingleRvcCamCrc_Display.c
index 0050887..e5be940 100644
--- a/examples/tda2xx/src/usecases/vip_single_rvc_cam_view_crc/chains_vipSingleRvcCamCrc_Display.c
+++ b/examples/tda2xx/src/usecases/vip_single_rvc_cam_view_crc/chains_vipSingleRvcCamCrc_Display.c
@@ -25,10 +25,10 @@
 #include <soc_defines.h>
 #endif
 
-#define VID2_POSX        (280)
-#define VID2_POSY        (45)
-#define VID3_POSX        (280)
-#define VID3_POSY        (10)
+#define VID2_POSX        (0)
+#define VID2_POSY        (0)
+#define VID3_POSX        (0)
+#define VID3_POSY        (0)
 
 #define CAPTURE_SENSOR_INPUT_WIDTH      (720)
 #define CAPTURE_SENSOR_INPUT_HEIGHT     (480)
@@ -36,7 +36,7 @@
 #define CAPTURE_SENSOR_OUTPUT_WIDTH      (720)
 #define CAPTURE_SENSOR_OUTPUT_HEIGHT     (480)
 
-#define CAPTURE_DISPLAY_WIDTH      (720)
+#define CAPTURE_DISPLAY_WIDTH      (1920)
 #define CAPTURE_DISPLAY_HEIGHT     (480)
 
 #define AUTOMATIC_UPDATE_COUNTER (5)
@@ -51,35 +51,40 @@
 #define DISPLAY_WB_EXTRA_PIXELS             (2U)
 
 #ifdef GPIO_IN_INTERRUPT
-#ifdef TDA2EX_BUILD
-/* GPIO INPUT INTERRUPT by default is configured using GPIO 6 pin 28
- * which is connected to CTRL_CORE_PAD_MMC1_SDWP
- * MUXMODE 14 (0xE) - gpio6_28
- * The Interrupt is GPIO6_IRQ_2 with IRQ_CROSSBAR_143.
- * The Control Module used CTRL_CORE_IPU2_IRQ_49_50.
- * IPU2_IRQ_49 is set to IRQ_CROSSBAR_143 (0x8F)
- */
+
 #define GPIO_PIN_MASK_ALL (0xFFFFFFFFU)
 #define PINMUX_MODE_14 ((UInt32) 14U)
 #define SOC_CTRL_CORE_IPU2_IRQ_49_50 (0x4A002888)
 #define IRQ_CROSSBAR_143 (0x8F)
+#define IRQ_CROSSBAR_347 (0x15B)
 #define SOC_CTRL_CORE_IPU2_IRQ_49_50_MASK_LSB (0xFFFF0000)
 #define SOC_CTRL_CORE_IPU2_IRQ_49_50_MASK_MSB (0x0000FFFF)
 
-uint32_t gpio_in_base_address = SOC_GPIO6_BASE;
-uint32_t gpio_in_pin          = 28;
-uint32_t rvc_int_num          = 49;
-
 /* In TDA2EX schematic GPMC_D08 is connected to GPMC_AD8
  * which is on SW4 pin#1.
  * At boot, SW4 pin#1 DIP SWITCH is set to 1 means RVC run
  *
  * In TDA2EX schematic TP29 is connected to MMC1_SDWP (gpio6_28)
  * At boot, TP29 needs to be set to 1 for RVC run
+ *
+ * In TDA2XX schematic GPMC_D08 is connected to GPMC_AD8
+ * which is on SW3 pin#1
+ * At boot, SW3 pin#1 DIP SWITCH is set to 1 means RVC run
  */
 static uint32_t gpio_value = 1;
 
-#else
+/* GPIO INPUT INTERRUPT by default is configured using GPIO 6 pin 28
+ * which is connected to CTRL_CORE_PAD_MMC1_SDWP
+ * MUXMODE 14 (0xE) - gpio6_28
+ * The Interrupt is GPIO6_IRQ_2 with IRQ_CROSSBAR_143.
+ * The Control Module used CTRL_CORE_IPU2_IRQ_49_50.
+ * IPU2_IRQ_49 is set to IRQ_CROSSBAR_143 (0x8F)
+ */
+
+uint32_t gpio_in_base_address_j6entry = SOC_GPIO6_BASE;
+uint32_t gpio_in_pin_j6entry          = 28;
+uint32_t rvc_int_num_j6entry          = 49;
+
 /* GPIO INPUT INTERRUPT by default is configured using GPIO 7 pin 18
   * which is connected to CTRL_CORE_PAD_GPMC_AD8
   * MUXMODE 14 (0xE) - gpio7_18
@@ -87,23 +92,11 @@ static uint32_t gpio_value = 1;
   * The Control Module used CTRL_CORE_IPU2_IRQ_49_50.
   * IPU2_IRQ_49 is set to IRQ_CROSSBAR_347 (0x15B)
   */
-#define GPIO_PIN_MASK_ALL (0xFFFFFFFFU)
-#define PINMUX_MODE_14 ((UInt32) 14U)
-#define SOC_CTRL_CORE_IPU2_IRQ_49_50 (0x4A002888)
-#define IRQ_CROSSBAR_347 (0x15B)
-#define SOC_CTRL_CORE_IPU2_IRQ_49_50_MASK_LSB (0xFFFF0000)
-#define SOC_CTRL_CORE_IPU2_IRQ_49_50_MASK_MSB (0x0000FFFF)
 
 uint32_t gpio_in_base_address = SOC_GPIO7_BASE;
 uint32_t gpio_in_pin          = 18;
 uint32_t rvc_int_num          = 49;
 
-/* In TDA2XX schematic GPMC_D08 is connected to GPMC_AD8
- * which is on SW3 pin#1
- * At boot, SW3 pin#1 DIP SWITCH is set to 1 means RVC run
- */
-static uint32_t gpio_value = 1;
-#endif
 #endif
 
 /**
@@ -410,7 +403,7 @@ Void chains_vipSingleRvcCamCrc_Display_SetAppPrms(chains_vipSingleRvcCamCrc_Disp
 
     // Create parameter for RVC Diagnostics Alg Plugin
     pUcObj->Alg_RvcDiagnosticPrm.appData = pObj;
-    pUcObj->Alg_RvcDiagnosticPrm.autoCorrectFlag = TRUE;
+    pUcObj->Alg_RvcDiagnosticPrm.autoCorrectFlag = FALSE;
     pUcObj->Alg_RvcDiagnosticPrm.autoCorrectCount = AUTOMATIC_UPDATE_COUNTER;
 }
 
@@ -496,6 +489,7 @@ Void chains_vipSingleRvcCamCrc_Display_StopAndDeleteApp(Chains_vipSingleRvcCamCr
      * never call ChainsCommon_StartDisplayDevice(). No need to call
      * ChainsCommon_StopDisplayDevice(pObj->chainsCfg->displayType);
      */
+    //ChainsCommon_StopDisplayDevice(pObj->chainsCfg->displayType);
 
     /* Print the HWI, SWI and all tasks load */
     /* Reset the accumulated timer ticks */
@@ -591,15 +585,25 @@ void gpioInIsr(void *arg)
     key = Hwi_disable();
 
     /* GPIO_IRQSTATUS_x  */
-    gpio_pin_status = GPIOPinIntStatus(gpio_in_base_address, GPIO_INT_LINE_2, gpio_in_pin);
+    if (BSP_PLATFORM_PACKAGE_TYPE_17x17 == Bsp_platformGetPackageType()) {
+        gpio_pin_status = GPIOPinIntStatus(gpio_in_base_address_j6entry, GPIO_INT_LINE_2, gpio_in_pin_j6entry);
+
+        /* Set global gpio_value with the information from GPIO_DATAIN on the configured GPIO and pin */
+        gpio_value = (GPIOPinRead(gpio_in_base_address_j6entry, gpio_in_pin_j6entry)) >> gpio_in_pin_j6entry;
+    } else {
+        gpio_pin_status = GPIOPinIntStatus(gpio_in_base_address, GPIO_INT_LINE_2, gpio_in_pin);
 
-    /* Set global gpio_value with the information from GPIO_DATAIN on the configured GPIO and pin */
-    gpio_value = (GPIOPinRead(gpio_in_base_address, gpio_in_pin)) >> gpio_in_pin;
+        /* Set global gpio_value with the information from GPIO_DATAIN on the configured GPIO and pin */
+        gpio_value = (GPIOPinRead(gpio_in_base_address, gpio_in_pin)) >> gpio_in_pin;
+    }
 
     Hwi_restore(key);
 
     /* Clear the bit on the configured GPIO and pin ONLY. */
-    GPIOPinIntClear(gpio_in_base_address, GPIO_INT_LINE_2, gpio_in_pin);
+    if (BSP_PLATFORM_PACKAGE_TYPE_17x17 == Bsp_platformGetPackageType())
+        GPIOPinIntClear(gpio_in_base_address_j6entry, GPIO_INT_LINE_2, gpio_in_pin_j6entry);
+    else
+        GPIOPinIntClear(gpio_in_base_address, GPIO_INT_LINE_2, gpio_in_pin);
 }
 
 void ConfigureGPIOInterrupt(Chains_vipSingleRvcCamCrcCameraViewAppObj *pObj)
@@ -613,8 +617,14 @@ void ConfigureGPIOInterrupt(Chains_vipSingleRvcCamCrcCameraViewAppObj *pObj)
     hwiAttrs.maskSetting = Hwi_MaskingOption_LOWER;
     hwiAttrs.arg = (UArg) pObj;
 
-    Hwi_create(rvc_int_num, (Hwi_FuncPtr) gpioInIsr, &hwiAttrs, NULL);
-    Hwi_enableInterrupt(rvc_int_num);
+    if (BSP_PLATFORM_PACKAGE_TYPE_17x17 == Bsp_platformGetPackageType()) {
+        Hwi_create(rvc_int_num, (Hwi_FuncPtr) gpioInIsr, &hwiAttrs, NULL);
+        Hwi_enableInterrupt(rvc_int_num);
+    }
+    else {
+        Hwi_create(rvc_int_num_j6entry, (Hwi_FuncPtr) gpioInIsr, &hwiAttrs, NULL);
+        Hwi_enableInterrupt(rvc_int_num_j6entry);
+    }
 
     Hwi_restore(key);
 }
@@ -660,7 +670,10 @@ void Utils_gpioInEnable(uint32_t baseAdd, uint32_t pinNumber)
      * bit 8:0 to IRQ_CROSSBAR_347 (0x15B) for GPIO7_IRQ_2
      */
 #ifdef TDA2EX_BUILD
-    RvcCtrlModule_Config(SOC_CTRL_CORE_IPU2_IRQ_49_50, IRQ_CROSSBAR_143, SOC_CTRL_CORE_IPU2_IRQ_49_50_MASK_LSB);
+    if (BSP_PLATFORM_PACKAGE_TYPE_17x17 == Bsp_platformGetPackageType())
+        RvcCtrlModule_Config(SOC_CTRL_CORE_IPU2_IRQ_49_50, IRQ_CROSSBAR_143, SOC_CTRL_CORE_IPU2_IRQ_49_50_MASK_LSB);
+    else
+        RvcCtrlModule_Config(SOC_CTRL_CORE_IPU2_IRQ_49_50, IRQ_CROSSBAR_347, SOC_CTRL_CORE_IPU2_IRQ_49_50_MASK_LSB);
 #else
     RvcCtrlModule_Config(SOC_CTRL_CORE_IPU2_IRQ_49_50, IRQ_CROSSBAR_347, SOC_CTRL_CORE_IPU2_IRQ_49_50_MASK_LSB);
 #endif
@@ -729,7 +742,10 @@ void chains_vipSingleRvcCamCrc_Display(Chains_Ctrl *chainsCfg)
     ConfigureGPIOInterrupt(&chainsObj);
 
     /* Enabling GPIO */
-    Utils_gpioInEnable(gpio_in_base_address, gpio_in_pin);
+    if (BSP_PLATFORM_PACKAGE_TYPE_17x17 == Bsp_platformGetPackageType())
+        Utils_gpioInEnable(gpio_in_base_address_j6entry, gpio_in_pin_j6entry);
+    else
+        Utils_gpioInEnable(gpio_in_base_address, gpio_in_pin);
 #endif
 
     while (loop) {
-- 
1.9.1

