/*
 * Do not modify this file; it is automatically generated from the template
 * linkcmd.xdt in the ti.targets.elf package and will be overwritten.
 */

/*
 * put '"'s around paths because, without this, the linker
 * considers '-' as minus operator, not a file name character.
 */


-l"C:\git\PHX-10188-sip-upgrade-to-the-latest-ti-sdk-c667x-06.03.00.106\PhoenixPlatformCfg\Default\configPkg\package\cfg\Phx_C6678_configuration_pe66.oe66"
-l"C:\git\PHX-10188-sip-upgrade-to-the-latest-ti-sdk-c667x-06.03.00.106\PhoenixPlatformCfg\src\ipc\ipc.ae66"
-l"C:\ti\uia_2_30_01_02\packages\ti\uia\sysbios\lib\release\ti.uia.sysbios.ae66"
-l"C:\ti\uia_2_30_01_02\packages\ti\uia\loggers\lib\release\ti.uia.loggers.ae66"
-l"C:\git\PHX-10188-sip-upgrade-to-the-latest-ti-sdk-c667x-06.03.00.106\PhoenixPlatformCfg\src\utils\utils.ae66"
-l"C:\git\PHX-10188-sip-upgrade-to-the-latest-ti-sdk-c667x-06.03.00.106\PhoenixPlatformCfg\src\sysbios\sysbios.ae66"
-l"C:\ti\uia_2_30_01_02\packages\ti\uia\family\c66\lib\release\ti.uia.family.c66.ae66"
-l"C:\ti\uia_2_30_01_02\packages\ti\uia\services\lib\release\ti.uia.services.ae66"
-l"C:\ti\uia_2_30_01_02\packages\ti\uia\runtime\lib\release\ti.uia.runtime.ae66"
-l"C:\ti\uia_2_30_01_02\packages\ti\uia\events\lib\release\ti.uia.events.ae66"
-l"C:\ti\bios_6_76_03_01\packages\ti\targets\rts6000\lib\ti.targets.rts6000.ae66"
-l"C:\ti\bios_6_76_03_01\packages\ti\targets\rts6000\lib\boot.ae66"

--retain="*(xdc.meta)"


--args 0x0
-heap  0x0
-stack 0x1000

MEMORY
{
    MSMCSRAM (RWX) : org = 0xc000000, len = 0x400000
    L1DSRAM (RW) : org = 0xf00000, len = 0x8000
    L1PSRAM (RWX) : org = 0xe00000, len = 0x8000
    L2SRAM (RWX) : org = 0x800000, len = 0x19f00
    L2HEAP (RWX) : org = 0x819f00, len = 0x46100
    DDRUNCACHED (RWX) : org = 0x80000000, len = 0xfffe00
    DDRCINE (RWX) : org = 0xc9400000, len = 0x36c00000
    IBL_VERSIONS (RW) : org = 0x80fffe00, len = 0x100
    DDR_HEAP (RW) : org = 0x81000000, len = 0x45200000
    DDR_CODE (RX) : org = 0xc6200000, len = 0x400000
    DDR_DATA (RW) : org = 0xc6600000, len = 0x2e00000
}

/*
 * Linker command file contributions from all loaded packages:
 */

/* Content from xdc.services.global (null): */

/* Content from xdc (null): */

/* Content from xdc.corevers (null): */

/* Content from xdc.rov (null): */

/* Content from xdc.runtime (null): */

/* Content from xdc.rov.runtime (null): */

/* Content from xdc.shelf (null): */

/* Content from xdc.services.spec (null): */

/* Content from xdc.services.intern.xsr (null): */

/* Content from xdc.services.intern.gen (null): */

/* Content from xdc.services.intern.cmd (null): */

/* Content from xdc.bld (null): */

/* Content from ti.targets (null): */

/* Content from ti.targets.elf (null): */

/* Content from ti.targets.rts6000 (null): */

/* Content from xdc.rta (null): */

/* Content from ti.uia.events (null): */

/* Content from ti.uia.runtime (null): */

/* Content from ti.sysbios.interfaces (null): */

/* Content from ti.sysbios.family (null): */

/* Content from xdc.runtime.knl (null): */

/* Content from xdc.services.getset (null): */

/* Content from ti.sdo.ipc.interfaces (null): */

/* Content from ti.sdo.ipc.family (null): */

/* Content from ti.sysbios.family.c62 (null): */

/* Content from ti.sysbios.family.c64p.tci6488 (null): */

/* Content from ti.uia.services (null): */

/* Content from ti.catalog.c6000 (null): */

/* Content from ti.catalog (null): */

/* Content from ti.catalog.peripherals.hdvicp2 (null): */

/* Content from xdc.platform (null): */

/* Content from xdc.cfg (null): */

/* Content from ti.platforms.generic (null): */

/* Content from PhoenixPlat_C6678 (null): */

/* Content from ti.uia.family.c66 (null): */

/* Content from ti.sysbios.hal (null): */

/* Content from ti.sysbios (null): */

/* Content from ti.sysbios.rts (null): */

/* Content from ti.sysbios.rts.ti (ti/sysbios/rts/ti/linkcmd.xdt): */

/* Content from ti.sysbios.knl (null): */

/* Content from ti.sysbios.timers.timer64 (null): */

/* Content from ti.sysbios.family.c64p (ti/sysbios/family/c64p/linkcmd.xdt): */

/* Content from ti.sysbios.family.c66 (ti/sysbios/family/c66/linkcmd.xdt): */
ti_sysbios_family_c66_Cache_l1dSize = 32768;
ti_sysbios_family_c66_Cache_l1pSize = 32768;
ti_sysbios_family_c66_Cache_l2Size = 131072;

/* Content from ti.sysbios.syncs (null): */

/* Content from ti.sysbios.gates (null): */

/* Content from ti.sdo.utils (null): */

/* Content from ti.sysbios.heaps (null): */

/* Content from ti.sysbios.family.c66.tci66xx (null): */

/* Content from ti.sysbios.xdcruntime (null): */

/* Content from ti.uia.loggers (null): */

/* Content from ti.sysbios.utils (null): */

/* Content from ti.uia.sysbios (null): */

/* Content from ti.sdo.ipc.heaps (null): */

/* Content from ti.sdo.ipc.gates (null): */

/* Content from ti.sdo.ipc.notifyDrivers (null): */

/* Content from ti.sdo.ipc (ti/sdo/ipc/linkcmd.xdt): */

SECTIONS
{
    ti.sdo.ipc.SharedRegion_0:  { . += 0x10000;} run > 0xc000000, type = NOLOAD
    ti.sdo.ipc.SharedRegion_1:  { . += 0x45200000;} run > 0x81000000, type = NOLOAD
    ti.sdo.ipc.SharedRegion_2:  { . += 0x370000;} run > 0xc010000, type = NOLOAD
    ti.sdo.ipc.SharedRegion_3:  { . += 0x800000;} run > 0x80100000, type = NOLOAD
}

/* Content from ti.sdo.ipc.family.c647x (null): */

/* Content from ti.sdo.ipc.transports (null): */

/* Content from ti.sdo.ipc.nsremote (null): */

/* Content from configPkg (null): */

/* Content from xdc.services.io (null): */

/* Content from ti.sdo.ipc.family.ti81xx (null): */

/* Content from ti.ipc.remoteproc (ti/ipc/remoteproc/linkcmd.xdt): */




/*
 * symbolic aliases for static instance objects
 */
xdc_runtime_Startup__EXECFXN__C = 1;
xdc_runtime_Startup__RESETFXN__C = 1;
xdc_rov_runtime_Mon__checksum = 1;
xdc_rov_runtime_Mon__write = 1;

SECTIONS
{



    .heapll2:                       load >> L2HEAP       align = 0x8
    .text:                          load >> MSMCSRAM     align = 0x8
    .vecs:                          load >> MSMCSRAM     align = 0x8
    .sect_SL2:                      load >  MSMCSRAM     align = 0x8
    .sect_SL2_infr_data:            load >  MSMCSRAM     align = 0x40
    .sect_SL2_EDMA:                 load >> MSMCSRAM     align = 0x8
    .sect_cine_data:                load >  DDRCINE      align = 0x8
    .sect_DDR2_code:                load >  DDR_CODE     align = 0x8      
	.cinit:                         load >  DDR_DATA     align = 0x80
	xdc.meta:                       load >  DDR_DATA     type=COPY
		  
	GROUP: load = DDR_DATA
	{
	    .const:                         {} align = 0x80
	    .sect_infr_data:                {} align = 0x80
	    .sect_external_read_only_data:  {} align = 0x80
	    .sect_ecg_data:                 {} align = 0x80
	    .sect_outmgr_dbg_data:          {} align = 0x80
	    .sect_twod_enq_test_data:       {} align = 0x80
	    .sect_doppler_test_data:        {} align = 0x80
	    .sect_ecg_test_data:            {} align = 0x80
	    .sect_hw_spctrl_dbg_data:       {} align = 0x80
	    .sect_hw_srio_test_data:        {} align = 0x80
	    .sect_mmode_test_data:          {} align = 0x80
	    .sect_colorflow_ddr:            {} align = 0x80
	    .sect_doppler_output:           {} align = 0x80
	    .sect_doppler_data:             {} align = 0x80
	    .sect_mem_ext:                  {} align = 0x80      		  
    }

    GROUP: load = L2SRAM
    {
        .far                            {} align = 0x8
        .cio:                           {} align = 0x8
        .sysmem:                        {} align = 0x8
        .bss:                           {} align = 0x8
        .pinit:                         {} align = 0x8
		.init_array                     {} align = 0x8
		.fardata                        {} align = 0x8
		.neardata                       {} align = 0x8
		.rodata                         {} align = 0x8
        .switch:                        {} align = 0x8
        .data:                          {} align = 0x8
        .stack:                         {} align = 0x8
        .sect_LL2:                      {} align = 0x8, RUN_START(pokableLL2Start)
        .sect_doppler_data_LL2:         {} align = 0x8, RUN_END(pokableLL2End)
    }
    GROUP: load = DDRUNCACHED
    {
        .sect_host_interface_struct:    {} align = 0x8
        .sect_params:                   {} align = 0x8
        .sect_params_misc:              {} align = 0x8
        .sect_error:                    {} align = 0x8
        .sect_noncached_DDR2            {} align = 0x8
        .sect_diagnostics               {} align = 0x8
        .sect_dup_vers_struct           {} align = 0x8
    }
    GROUP: load = IBL_VERSIONS
    {
        .sect_ibl_version               {} align = 0x8
        // .sect_top_of_DDR_vars MUST be the last section in IBL_VERSIONS
        //    That section is used to calculate the bottom of the DDR_HEAP
        .sect_top_of_DDR_vars:          {} align = 0x8
    }
    
    /*Placing _c_int00 on 10-bit aligned address to support DSP warm reset through PSC registers.*/
    boot palign(0x400)
    {
        -l boot.ae66<boot.oe66>(.text:_c_int00)
    } > DDR_CODE

    /* overlap Bootloader with the uninitialized section */
    UNION: run = L2SRAM 
    {
        .boot_entry {}
        .far {}
    }
    UNION: run = L2SRAM 
    {
        .sect_Core0_LL2 {}   ,RUN_START(pokableCore0LL2Start), RUN_END(pokableCore0LL2End)
        .sect_Doppler_LL2 {}
    }


/* -----------------------------------------------
 *        Revision History
 * -----------------------------------------------
 * 21-Feb-2016  ll: Make _c_int00 on 10-bit aligned address.
 * 10-Jun-2014 wrz: Modified further for M2HF/6678, taking into account the standard memory segment names for that 
 *                  platform (as created), and modifying the custom ones accordingly.
 *                  NOTE: I've mapped the existing M2 memory sections onto the 
 *                        memory segments I defined as the M2HF platform in CCS. Note that several
 *                        of the memory sections are now misnomers. That is, .sect_DDR2 doesn't really
 *                        point to DDR2, because this system has DDR3. We could change that if the 
 *                        misnomers bother anyone. I recommend that, if we do go through the entire 
 *                        code base to remove references to _DDR2 (there's a couple hundred of them), 
 *                        we simplify them to _DDR rather than renaming them to _DDR3, or we'll have 
 *                        to do the entire exercise over again when DDR4 becomes the standard.
 *       NOTE: Note new .sect_extended code/data section. In the new 
 *           M2HF platform, that memory is defined as the top 1GB of DDR3, and should be
 *           considered to be reserve memory. That means it should be unused until the DSP
 *           group as a whole decides on the best way to use it. Don't just use it.
 * 06-Jun-2014 wrz: Modified for M2HF/6678
 * 23-Oct-2012 wrz: removed .sect_color_LL2. Now Color Wall Filter and MP_FIR can co-exist in one core with 
 *                  any other cluster without fear of overlapping memory sections causing trouble.
 * 19-Sep-2012  ll: Added new memory section: .sect_DDR2_code
 * 24-Aug-2012 dwu: Added 256 MB to the DDR2 Cine memory 
 * 20-Jul-2012 dwu: Updated IPC, XDC and SYS/BIOS to ipc_1_24_03_32, xdctools_3_23_02_47 and bios_6_33_05_46
 * 30-Jan-2012 wrz: Added .sect_top_of_DDR_vars. This is to make sure that the STATIC value in
 *                  M2_EVM6472.cfg that controls the base of DDR2 heap memory, namely Program.global.CFG_DDR2_BASE,
 *                  is AFTER the statically-allocate memory of the program. I define a variable in the
 *                  new section, and compare its address to the base of the newly created DDR2 heap
 *                  in HeapMemMgr_create(). A better solution would be one which adjusts this value at
 *                  compile time (i.e., linker-generated), but that does not appear to be easy to do. The
 *                  next best thing, which I've done in that function, is to fatal assert if there's an
 *                  overlap. 
 * 27-Oct-2011 wrz: In the light of core-overlapping DDR access issue, set .sect_colorflow_ddr to
 *                  128-byte alignment, which is one full cache line. This will make all accesses
 *                  within that section cache-independent of all other cores. This should be done 
 *                  for all DDR sections that are accessed by subordinate cores.
 * 26-Oct-2011 dwu: Increase SL2 heap size by 64KB. 
 * 19-Sep-2011 dwu: Updated CGT, IPC and SYS/BIOS to cgt_7_2_6, ipc_1_22_03_23 and bios_6_31_04_27 
 * 25-Aug-2011 ejp: Increased DDR2HOST section to accomodate new CW resampling filter coeffs.
 * 17-Aug-2011 dwu: Removed unused/duplicated memory sections 
 * 18-Mar-2011 dwu: Added DDR2CINE sections (128MB) and reduce the size of DDR2 heap to 100MB 
 * 25-mar-2011 ejp: - added boot section to memory, but could not get .text:boot_entry to work
 *                  (the syntax somehow destroys the following sections).
 *                  - added host section for spDspInterface.
 * 03-Mar-2011 dwu: created
 */







}
