This directory contains scripts used with Lauterbach's TRACE32 on the Texas Instruments J784S4 & J742S2 SOC. Supported hosts will be Windows,
  Linux, and Mac. The AHP SOC comes in a 33x33 package with 4-EMIFs and a 27x27 package 2 with 2-EMIFs.  the AHP27 is a strict subset of AHP33.
  A run time check is in the scripts which adjusts EMIF setup

The TRACE32 image used on J784S4/TDA4VH (AHP33) is composed of:
	1: The earliest support point is composed of:
	  - A base image using the R.2021.02.000136263 release from https://www.lauterbach.com/frames.html?download_trace32.html
	    -- targets installed were ARM, ARM64, and C7000
	  - Next, the daily build patch trace32_n_2022_04_000146885_ti_internal_conf_20220413143035.zip was installed (available from Lauterbach support)
	    -- It is expected that daily builds past this point will fully work with the J784S4 SOC
	2: Subsequent TRACE32 stable releases (R.xxxx.02 or R.xxxx.08) are alternate valid base image.
	3: TI example scripts, cmm-tda4vh_j784s4.7z, unzipped into the install directory
	  !! --> edit the file is_soc_J742S2_or_j784S4.cmm to point to the SOC type you using <-- !!

The supported TRACE32 system.cpu names used in scripts are:
	For AHP(33)  : J784S4/TDA4VH/AM69
	; CM4 (2x1)  : TDA4VH-CM4-0 TDA4VH-CM4-1
	; A72 (2x4)  : TDA4VH (core.assign 1 2 3 4 5 6 7 8)
	; CR5 (4x2)  : TDA4VH-CR5-MCU TDA4VH-CR5-MAIN0 TDA4VH-CR5-MAIN1 TDA4VH-CR5-MAIN2 (core.assign 1 2)
	; C7x (4x1)  : TDA4VH-C71X (core.assign 1 2 3 4)

	For AHP(27)  : J742S2/TDA4VPE/TDA4VAP/AM69-27
	; CM4 (2x1)  : TDA4VPE-CM4-0 TDA4VH-CM4-1
	; A72 (2x4)  : TDA4VPE-CA72 (core.assign 1 2 3 4)
	; CR5 (4x2)  : TDA4VPE-CR5-MCU TDA4VPE-CR5-MAIN0 TDA4VPE-CR5-MAIN1 TDA4VPE-CR5-MAIN2 (core.assign 1 2)
	; C7x (4x1)  : TDA4VPE-C71X (core.assign 1 2 3)

TI example scripts will largely use J784S4 naming with a run time check to remove J742S2 components. Users may find direct usage of J742S2
will provide a simpler usage model as tool menus will only show valid options.  Builds newer than 28-Jun-24 contain the J742S2 definitions.

The system supports J784S4/J742S2 HW features:
	- basic debug on all cores (load/run, step/break, view, dap-sample-based-trace)
	- advanced processor trace on all cores to on-chip buffers and to off-chip receivers
	  -- ETM on the Cortex-A72 (code) and Cortex-R5 (code and data)
	  -- ETM and ITM on Cortex-M4
	  -- DSP processor trace on the C7000 (code & data)
	- System trace
	  -- System messages via cptracers (throughput, latency, transaction, C7x-events)
	  -- Coresight STM messages
	- Peripheral suspend when a core is halted
	- Cross triggering via CTI/CTM networks
	- All standard TRACE32 features
	  -- Trace and sample-based analysis
	  -- Code coverage
	  -- Performance profiling
	  -- Awareness for J784S4/J742S2 HLOS (Linux, QNX) and Hypervisors
	  -- Awareness for J784S4/J742S2 RTOS (FreeRTOS, SafeRTOS, AutoSar, TIRTOS)
	  -- All standard features ..., ..., ...

Directory/Files:
	bsdl : BSDL support for test and flashing
	dsp-c7x: scripts used to attach to running targets
	mcu-r5:
		burn_flash: controller-based flasher
		<other> scripts used to attach and debug running targets
	mpu-a72: scripts used to attach to running targets
	notes: Information on cptracer and suspend-router features
	x_gel_to_cmm:
		pdk_rtos_test: scripts to launch PDK examples via JTAG which use TI system firmware
		memtester: simple memtesters to validate DDR
		<other>: TI validation scripts used to initialize power, clocks and DDR typically used with bare metal development
	logic analyzer: Scripts used with TRACE32 addon logic and analyzer extensions: ciprobe, iprobe, probe, integrator
	j784s4_win_launcher.ts2 : standard Windows t32start compatible launcher

Getting started:
	A first-time user on the EVM should see example videos then mimic them:
		Running the x_gel_to_cmm/_J784S4_allcoretypes_connect.cmm script
			This initializes the platform and brings up basic debug for all cores.
			If you don't have licenses for all the cores comment out the ones not desired
		Run the example memtester
	Early board checkout and RTOS development likely use files in x_gel_to_cmm
		A custom board can be added at this level. Minimally the DDR scripts will need to be regenerated using the TI DDR config tool
	Higher-level usage tends to happen with HLOS scripts.  The script files content increases over the life of the chip so check for CDDS updates











