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; 19 Jun 22 - Richard Woodruff - Adapt from J721S2 for J784S4
; 13 Jul 22 - Richard Woodruff - gelconverter 2.5.3 needs no fixes, others do
; 14 May 24 - Richard Woodruff - Add in AHP27 (27x27 run time check)
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Step 1: Enter DDR information into DDR Config XLS
Step 2: Generate GEL file "J784S4-DDR-EVM-LP4-4266.gel" from XLS
Step 3: Create a new file J784S4_addr-map-offs-LP4-4266_DDR_config.gel merging J7-DDR-addr-map-offs.gel + J784S4-DDR-EVM-LP4-4266.gel + J7_DDR_config.gel
Step 4: Merge in any GEL differences from the EVM template.  Do not overwrite J7_DDR_config.gel updates /* Some gel_converter bugs depending on version none for 2.4.3 */
Step 5: Generate a CMM using the gel converter. gelconverter <filea>.gel <filea>.cmm
Step 6: Merge template CMM fixes into newly created CMM file. /* none needed for gel_converter  2.5.3, early SW-pdk usage may require some work around */
Step 7: Connect with a TRACE32 PowerView instance and run the script "run_all_ddr_test.cmm"
Step 8: If the A72 memtester starts, enter a buffer base address of 0x81000000 with a size suitable for testing.
Step 9: If using the 27x27 package then it only has 2 EMIFs not 4.  The timings are the same except for the first few defines.  A run time check of the
       JTAG_USER_ID will give the package information.   If you want 27x27 you must manually add them as the default is for the 31x31 package.

LOCAL &pkg &stmp
&stmp=OS.PPF()
&stmp=OS.FILE.PATH("&stmp")
DO "&stmp/../../is_soc_J784S4_or_J742S2.cmm"
RETURNVALUES &pkg

IF "&pkg"=="AHP27" // AHP27x27 has 2 EMIFS
(
  GLOBAL &__MULTI_DDR_CFG_INTRLV_GRAN
  &__MULTI_DDR_CFG_INTRLV_GRAN=0.
  GLOBAL &__MULTI_DDR_CFG_INTRLV_SIZE
  &__MULTI_DDR_CFG_INTRLV_SIZE=11.
  GLOBAL &__MULTI_DDR_CFG_ECC_ENABLE
  &__MULTI_DDR_CFG_ECC_ENABLE=0.
  GLOBAL &__MULTI_DDR_CFG_HYBRID_SELECT
  &__MULTI_DDR_CFG_HYBRID_SELECT=0.
  GLOBAL &__MULTI_DDR_CFG_EMIFS_ACTIVE
  &__MULTI_DDR_CFG_EMIFS_ACTIVE=3.
)
ELSE    // AHP31x31 has 4 EMIFs
(
  GLOBAL &__MULTI_DDR_CFG_INTRLV_GRAN
  &__MULTI_DDR_CFG_INTRLV_GRAN=0.
  GLOBAL &__MULTI_DDR_CFG_INTRLV_SIZE
  &__MULTI_DDR_CFG_INTRLV_SIZE=12.
  GLOBAL &__MULTI_DDR_CFG_ECC_ENABLE
  &__MULTI_DDR_CFG_ECC_ENABLE=0.
  GLOBAL &__MULTI_DDR_CFG_HYBRID_SELECT
  &__MULTI_DDR_CFG_HYBRID_SELECT=24.
  GLOBAL &__MULTI_DDR_CFG_EMIFS_ACTIVE
  &__MULTI_DDR_CFG_EMIFS_ACTIVE=15.
)

