All CPUs which have L1/L2 caches can use the TRACE32 cache analysis features.
This command set allows raw dumping on data and tag rams along with their
association with any loaded symbols. This allows for performance profiling and
debug of cache maintenance code, see:
 - https://www2.lauterbach.com/pdf/general_ref_c.pdf#page=13

KS3 Cores with caches which support analysis are:
	ARM Cortex-A72/A53
	ARM Cortex-R5
	DSP C7x
	DSP C6x
Notes:

-1-
To avoid having the debugger disturb the cache contents before viewing the 
following command should be executed:
  -->  system.Option.CFLUSH.off
If this is not done actions like break points and single stepping can clear
the icache.

-2-
The viewing of the Cortex-R5 cache requires the use of a test AXI bus. To 
To select this bus a sequence is needed.  After the cache is viewed the 
sequence needs to be undone or no new allocations in the cache will happen.
  --> system.Option.CFLUSH.off
  --> break
  --> ACTLR =| AXISCEN|AXISCUEN or PER.Set.simple C15:0x101 %Long 0D800027
  --> step
  --> cache.dump.ic
  --> ACTLR =& ~(AXISCEN|AXISCUEN) or PER.Set.simple C15:0x101 %Long 0C000027

-3-
In addition to the cache.<xyz> command set, cache analysis is possible using 
other command sets. The information comes from 
  - BMC.<xyz> which uses PMU counters (ARM and DSP)
  - cts.cache which uses CPU HW trace (ARM and DSP)
  - cpt which uses hardware probes (C7x)
  - mmu.<xyz> (ARM and C7x)
	