Peripherals can be frozen when a core is put into debug halt if a suspend
signal is associated between a core and a peripheral.  This can be useful
for debug of peripherals that have running timers, watchdogs, or DMAs.

1: The first step is to associate a CPU's debug entry with a peripheral:

Suspend CPU mapping:
============================
Suspend Router: @APB:0x9D300000 | @AXI:0x4C:0x3D300000

CPU Suspend Input mappings:
-----------------------------
0     => unused
1-7   => A72-0, A72-1, ..., A72-7
8-11  => C7x-0, C7x-1, C7x-2, C7x-3
15,16 => MCU-R50, MCU-R51
18,19 => MAIN0-R50, MAIN0-R51
20,21 => MAIN1-R50, MAIN1-R51
22,23 => MAIN2-R50, MAIN2-R51
30    => SMS-CM4_0 (TIFS)
31    => SMS-CM4_1 (HSM)

Peripheral Outputs (0-127 slots):
----------------------------------
main timers main_0 to main_19 are mapped to slots 16 to 35
mcu timers mcu_0 to mcu_9 are mapped to slots 105 through 114
gtc is mapped to slot 0 (gtc feeds multiple clocks, eg: A72-arch-timer)

MCU-TIMER0 is in slot 105 (105+1) x 4 = 424 = 0x1A8
  @APB:0x9D3001A8         - debug address plane
  @AXI:0x4C:0x3D3001A8    - 64bit-system address

stop timer if "MCU-R50" is halted by writing:
  Data.Set EAPB:0x9D3001A8 %LE %Long (0x10000|17.)
  or Data.Set AXI:0x4C:0x3D3001A8 %LE %Long (0x10000|17.)

stop timer if "A72-0" is halted by writing:
  Data.Set EAPB:0x9D3001A8 %LE %Long (0x10000|1.)
  or Data.Set AXI:0x4C:0x3D3001A8 %LE %Long (0x10000|1.)

2: The second step is to enable the peripheral to react to the suspend signal.
Many peripherals have a 'freeze' or halt bit control in their register space.
For example, for the GTC, GTC_CNTCR.HDBG[1] needs to be set.
 Data.Set EZAXI:0x00A90000 %LE %Long 0x3
For a TIMER a TICOP_CFG.EMUFREE flag needs to be cleared