diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index bbc6bed..0369227 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -134,6 +134,7 @@ int board_mmc_init(bd_t *bis)
 {
 	switch (spl_boot_device()) {
 	case BOOT_DEVICE_MMC1:
+	debug("\n Entered board_mmc_init ");
 		omap_mmc_init(0, 0, 0, -1, -1);
 		break;
 	case BOOT_DEVICE_MMC2:
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 697d6e0..023b527 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -1132,7 +1132,8 @@ static void do_sdram_init(u32 base)
 
 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 	emif_get_reg_dump(emif_nr, &regs);
-	if (!regs) {
+	debug("CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS");
+        if (!regs) {
 		debug("EMIF: reg dump not provided\n");
 		return;
 	}
@@ -1160,7 +1161,8 @@ static void do_sdram_init(u32 base)
 	/* Return if no devices on this EMIF */
 	if (!dev_details.cs0_device_details &&
 	    !dev_details.cs1_device_details) {
-		return;
+		debug("Return if no devices on this EMIF");
+                return;
 	}
 
 	/*
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index c5e2286..da3cc7f 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -147,6 +147,8 @@ void board_init_f(ulong dummy)
 	board_early_init_f();
 #endif
 	/* For regular u-boot sdram_init() is called from dram_init() */
+	preloader_console_init();
+debug("\n console init ");
 	sdram_init();
 }
 #endif
diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c
index fc4290c..82317d8 100644
--- a/arch/arm/cpu/armv7/omap-common/mem-common.c
+++ b/arch/arm/cpu/armv7/omap-common/mem-common.c
@@ -77,8 +77,9 @@ void gpmc_init(void)
 {
 	/* putting a blanket check on GPMC based on ZeBu for now */
 	gpmc_cfg = (struct gpmc *)GPMC_BASE;
-#if defined(CONFIG_NOR)
+//#if defined(CONFIG_NOR)
 /* configure GPMC for NOR */
+#if 0
 	const u32 gpmc_regs[GPMC_MAX_REG] = {	STNOR_GPMC_CONFIG1,
 						STNOR_GPMC_CONFIG2,
 						STNOR_GPMC_CONFIG3,
@@ -93,7 +94,8 @@ void gpmc_init(void)
 	/* > 32MB */	((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M  :
 	/* > 16MB */	((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M  :
 	/* min 16MB */	GPMC_SIZE_16M)));
-#elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
+#endif
+#if defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
 /* configure GPMC for NAND */
 	const u32  gpmc_regs[GPMC_MAX_REG] = {	M_NAND_GPMC_CONFIG1,
 						M_NAND_GPMC_CONFIG2,
@@ -133,6 +135,8 @@ void gpmc_init(void)
 #else
 	writel(0x00000012, &gpmc_cfg->config);
 #endif
+writel(0x00000012, &gpmc_cfg->config);
+        //puts("\n Enabling NAND Memory");
 	/*
 	 * Disable the GPMC0 config set by ROM code
 	 */
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 0525207..78c2074 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -138,6 +138,7 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
 };
 
 const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
+#if 0
 	.sdram_config_init              = 0x61851ab2,
 	.sdram_config                   = 0x61851ab2,
 	.sdram_config2			= 0x08000000,
@@ -160,6 +161,29 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
 	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 	.emif_rd_wr_lvl_ctl             = 0x00000000,
 	.emif_rd_wr_exec_thresh         = 0x00000305
+#endif
+	.sdram_config_init      = 0x61851AB2,
+         .sdram_config           = 0x61851AB2, 
+         .sdram_config2          = 0x00000000,
+         .ref_ctrl               = 0x000040F1,
+         .ref_ctrl_final         = 0x00001035,
+         .sdram_tim1             = 0xCCCF365B,
+         .sdram_tim2             = 0x305A7FDA,
+         .sdram_tim3             = 0x407F8558,
+         .read_idle_ctrl         = 0x00050000,
+         .zq_config              = 0x5007190b,
+         .temp_alert_config      = 0x00000000,
+         .emif_ddr_phy_ctlr_1_init = 0x0024400b,
+         .emif_ddr_phy_ctlr_1    = 0x0e24400b,
+         .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+         .emif_ddr_ext_phy_ctrl_2 = 0x00820082,
+         .emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
+         .emif_ddr_ext_phy_ctrl_4 = 0x00800080,
+         .emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
+         .emif_rd_wr_lvl_rmp_win = 0x00000000,
+         .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+         .emif_rd_wr_lvl_ctl     = 0x00000000,
+         .emif_rd_wr_exec_thresh = 0x00000305
 };
 
 const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
@@ -228,9 +252,10 @@ const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
  */
 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = {
 	.dmm_lisa_map_0 = 0x0,
-	.dmm_lisa_map_1 = 0x80640300,
-	.dmm_lisa_map_2 = 0xC0500220,
-	.dmm_lisa_map_3 = 0xFF020100,
+	.dmm_lisa_map_1 = 0x80500100,
+        .dmm_lisa_map_2 = 0xC0500100,
+        .dmm_lisa_map_3 = 0x0,
+
 	.is_ma_present	= 0x1
 };
 
@@ -426,6 +451,7 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
 /* Ext phy ctrl 1-35 regs */
 const u32
 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
+#if 0
 	0x10040100,
 	0x00910091,
 	0x00950095,
@@ -461,6 +487,54 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
 	0x0,
 	0x0,
 	0x0
+#endif
+     0x04040100,// EMIF1_EXT_PHY_CTRL_1
+     0x006B00A7,// EMIF1_EXT_PHY_CTRL_2
+     0x006B00AA,// EMIF1_EXT_PHY_CTRL_3
+     0x006B00AA,// EMIF1_EXT_PHY_CTRL_4
+     0x006B00A9,// EMIF1_EXT_PHY_CTRL_5
+     0x006B00AC,// EMIF1_EXT_PHY_CTRL_6
+     0x00320032,// EMIF1_EXT_PHY_CTRL_7
+     0x00320032,// EMIF1_EXT_PHY_CTRL_8
+     0x00320032,// EMIF1_EXT_PHY_CTRL_9
+     0x00320032,// EMIF1_EXT_PHY_CTRL_10
+     0x00320032,// EMIF1_EXT_PHY_CTRL_11
+     0x00600069,// EMIF1_EXT_PHY_CTRL_12
+     0x00600066,// EMIF1_EXT_PHY_CTRL_13
+     0x00600073,// EMIF1_EXT_PHY_CTRL_14
+     0x00600074,// EMIF1_EXT_PHY_CTRL_15
+     0x0060007E,// EMIF1_EXT_PHY_CTRL_16
+     0x00400049,// EMIF1_EXT_PHY_CTRL_17
+     0x00400046,// EMIF1_EXT_PHY_CTRL_18
+     0x00400053,// EMIF1_EXT_PHY_CTRL_19
+     0x00400054,// EMIF1_EXT_PHY_CTRL_20
+     0x0040005E,// EMIF1_EXT_PHY_CTRL_21
+     0x00800080,// EMIF1_EXT_PHY_CTRL_22
+     0x00800080,// EMIF1_EXT_PHY_CTRL_23
+     0x40010080,// EMIF1_EXT_PHY_CTRL_24
+     0x08102040,// EMIF1_EXT_PHY_CTRL_25
+     0x005B0097,// EMIF1_EXT_PHY_CTRL_26
+     0x005B009A,// EMIF1_EXT_PHY_CTRL_27
+     0x005B009A,// EMIF1_EXT_PHY_CTRL_28
+     0x005B0099,// EMIF1_EXT_PHY_CTRL_29
+     0x005B009C,// EMIF1_EXT_PHY_CTRL_30
+     0x00300039,// EMIF1_EXT_PHY_CTRL_31
+     0x00300036,// EMIF1_EXT_PHY_CTRL_32
+     0x00300043,// EMIF1_EXT_PHY_CTRL_33
+     0x00300044,// EMIF1_EXT_PHY_CTRL_34
+     0x0030004E,// EMIF1_EXT_PHY_CTRL_35
+     0x00000077,// EMIF1_EXT_PHY_CTRL_36
+     0x0,
+     0x0,
+     0x0,
+     0x0,
+     0x0,
+     0x0,
+     0x0,
+     0x0,
+     0x0,
+     0x0
+
 };
 
 /* Ext phy ctrl 1-35 regs */
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 03335a2..3bf5a34 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -559,6 +559,7 @@ extern struct prcm_regs const omap4_prcm;
 extern struct prcm_regs const dra7xx_prcm;
 extern struct dplls const **dplls_data;
 extern struct dplls dra7xx_dplls;
+extern struct dplls dra72x_dplls;
 extern struct vcores_data const **omap_vcores;
 extern const u32 sys_clk_array[8];
 extern struct omap_sys_ctrl_regs const **ctrl;
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index ee56d74..5b1a412 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -71,7 +71,7 @@ void arch_lmb_reserve(struct lmb *lmb)
  */
 static void announce_and_cleanup(int fake)
 {
-	printf("\nStarting kernel ...%s\n\n", fake ?
+	printf("\nStarting Medha kernel ...%s\n\n", fake ?
 		"(fake run for tracing)" : "");
 	bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
 #ifdef CONFIG_BOOTSTAGE_FDT
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 4d90020..6ab6050 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -25,6 +25,8 @@
 #include <asm/arch/omap.h>
 #include <environment.h>
 #include <usb.h>
+#include <miiphy.h>
+#include <cpsw.h>
 #include <linux/usb/gadget.h>
 #include <dwc3-uboot.h>
 #include <dwc3-omap-uboot.h>
@@ -44,16 +46,42 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* GPIO 7_11 */
-#define GPIO_DDR_VTT_EN 203
+/* GPIO 7_7 */
+#define GPIO_DDR_VTT_EN 199
 
 const struct omap_sysinfo sysinfo = {
 	"Board: UNKNOWN(BeagleBoard X15?)\n"
 };
 
 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
-	.dmm_lisa_map_3 = 0x80740300,
+ /*1GB on EMIF1 ONLY*/
+ /*   .dmm_lisa_map_0 = 0x0,
+     .dmm_lisa_map_1 = 0x0,
+     .dmm_lisa_map_2 = 0x80700100,
+     .dmm_lisa_map_3 = 0xFF020100,
+     .is_ma_present = 0x1   */
+/*EMIF2 ONLY CONFIG*/
+    /*    .dmm_lisa_map_0 = 0x0,
+	.dmm_lisa_map_1 = 0x0,
+	.dmm_lisa_map_2 = 0x80600200,
+	.dmm_lisa_map_3 = 0xFF020100,
+	.is_ma_present	= 0x1  */
+
+	.dmm_lisa_map_3 = 0x80640100,
 	.is_ma_present  = 0x1
+/*For 512MB on DDR1 Channel 
+    .dmm_lisa_map_0 = 0x0,
+     .dmm_lisa_map_1 = 0x0,
+     .dmm_lisa_map_2 = 0x80500100,
+     .dmm_lisa_map_3 = 0xFF020100,
+     .is_ma_present = 0x1  */
+/*
+	.dmm_lisa_map_0 = 0x0,
+        .dmm_lisa_map_1 = 0x80640300,
+        .dmm_lisa_map_2 = 0xC0500220,
+        .dmm_lisa_map_3 = 0xFF020100,	
+	.is_ma_present = 0x1
+*/
 };
 
 static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
@@ -64,7 +92,10 @@ static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 {
 	if (board_is_am571x_idk())
-		*dmm_lisa_regs = &am571x_idk_lisa_regs;
+	{
+		*dmm_lisa_regs = &beagle_x15_lisa_regs;//am571x_idk_lisa_regs;
+		printf("\n Board is AM571x");
+	}
 	else
 		*dmm_lisa_regs = &beagle_x15_lisa_regs;
 }
@@ -72,13 +103,13 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
 	.sdram_config_init	= 0x61851b32,
 	.sdram_config		= 0x61851b32,
-	.sdram_config2		= 0x8000000,
+	.sdram_config2		= 0x08000000,
 	.ref_ctrl		= 0x000040F1,
 	.ref_ctrl_final		= 0x00001035,
 	.sdram_tim1		= 0xcccf36ab,
 	.sdram_tim2		= 0x308f7fda,
 	.sdram_tim3		= 0x409f88a8,
-	.read_idle_ctrl		= 0x00090000,
+	.read_idle_ctrl		= 0x00050000,
 	.zq_config		= 0x5007190b,
 	.temp_alert_config	= 0x00000000,
 	.emif_ddr_phy_ctlr_1_init = 0x0024400b,
@@ -92,6 +123,31 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
 	.emif_rd_wr_lvl_rmp_ctl	= 0x80000000,
 	.emif_rd_wr_lvl_ctl	= 0x00000000,
 	.emif_rd_wr_exec_thresh	= 0x00000305
+#if 0
+         .sdram_config_init      = 0x61851B32,
+         .sdram_config           = 0x61851B32,
+         .sdram_config2          = 0x00000000,
+         .ref_ctrl               = 0x000040F1,
+         .ref_ctrl_final         = 0x00001035,
+         .sdram_tim1             = 0xCCCF365B,
+         .sdram_tim2             = 0x305A7FDA,
+         .sdram_tim3             = 0x407F8558,
+         .read_idle_ctrl         = 0x00050000,
+         .zq_config              = 0x5007190b,
+         .temp_alert_config      = 0x00000000,
+         .emif_ddr_phy_ctlr_1_init = 0x0024400b,
+         .emif_ddr_phy_ctlr_1    = 0x0e24400b,
+         .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+         .emif_ddr_ext_phy_ctrl_2 = 0x00820082,
+         .emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
+         .emif_ddr_ext_phy_ctrl_4 = 0x00800080,
+         .emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
+         .emif_rd_wr_lvl_rmp_win = 0x00000000,
+         .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+         .emif_rd_wr_lvl_ctl     = 0x00000000,
+         .emif_rd_wr_exec_thresh = 0x00000305
+#endif
+
 };
 
 /* Ext phy ctrl regs 1-35 */
@@ -131,17 +187,88 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 	0x0,
 	0x0,
 	0x0
+#if 0
+     0x04040100,// EMIF1_EXT_PHY_CTRL_1
+     0x006B00A7,// EMIF1_EXT_PHY_CTRL_2
+     0x006B00AA,// EMIF1_EXT_PHY_CTRL_3
+     0x006B00AA,// EMIF1_EXT_PHY_CTRL_4
+     0x006B00A9,// EMIF1_EXT_PHY_CTRL_5
+     0x006B00AC,// EMIF1_EXT_PHY_CTRL_6
+     0x00320032,// EMIF1_EXT_PHY_CTRL_7
+     0x00320032,// EMIF1_EXT_PHY_CTRL_8
+     0x00320032,// EMIF1_EXT_PHY_CTRL_9
+     0x00320032,// EMIF1_EXT_PHY_CTRL_10
+     0x00320032,// EMIF1_EXT_PHY_CTRL_11
+     0x00600069,// EMIF1_EXT_PHY_CTRL_12
+     0x00600066,// EMIF1_EXT_PHY_CTRL_13
+     0x00600073,// EMIF1_EXT_PHY_CTRL_14 
+     0x00600074,// EMIF1_EXT_PHY_CTRL_15
+     0x0060007E,// EMIF1_EXT_PHY_CTRL_16
+     0x00400049,// EMIF1_EXT_PHY_CTRL_17
+     0x00400046,// EMIF1_EXT_PHY_CTRL_18
+     0x00400053,// EMIF1_EXT_PHY_CTRL_19
+     0x00400054,// EMIF1_EXT_PHY_CTRL_20
+     0x0040005E,// EMIF1_EXT_PHY_CTRL_21
+     0x00800080,// EMIF1_EXT_PHY_CTRL_22
+     0x00800080,// EMIF1_EXT_PHY_CTRL_23
+     0x40010080,// EMIF1_EXT_PHY_CTRL_24
+     0x08102040,// EMIF1_EXT_PHY_CTRL_25
+     0x005B0097,// EMIF1_EXT_PHY_CTRL_26
+     0x005B009A,// EMIF1_EXT_PHY_CTRL_27
+     0x005B009A,// EMIF1_EXT_PHY_CTRL_28
+     0x005B0099,// EMIF1_EXT_PHY_CTRL_29
+     0x005B009C,// EMIF1_EXT_PHY_CTRL_30
+     0x00300039,// EMIF1_EXT_PHY_CTRL_31
+     0x00300036,// EMIF1_EXT_PHY_CTRL_32
+     0x00300043,// EMIF1_EXT_PHY_CTRL_33
+     0x00300044,// EMIF1_EXT_PHY_CTRL_34
+     0x0030004E,// EMIF1_EXT_PHY_CTRL_35
+     0x00000077,// EMIF1_EXT_PHY_CTRL_36
+     0x0,
+     0x0,
+     0x0,
+     0x0,
+     0x0,
+     0x0,
+     0x0,
+     0x0,
+     0x0,
+     0x0
+#endif
 };
 
 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 	.sdram_config_init	= 0x61851b32,
 	.sdram_config		= 0x61851b32,
-	.sdram_config2		= 0x8000000,
+	.sdram_config2		= 0x08000000,
 	.ref_ctrl		= 0x000040F1,
 	.ref_ctrl_final		= 0x00001035,
-	.sdram_tim1		= 0xcccf36ab,
+	.sdram_tim1		= 0xcccf36b3,
 	.sdram_tim2		= 0x308f7fda,
-	.sdram_tim3		= 0x409f88a8,
+	.sdram_tim3		= 0x407f88a8,
+	.read_idle_ctrl		= 0x00050000,
+	.zq_config		= 0x5007190b,
+	.temp_alert_config	= 0x00000000,
+	.emif_ddr_phy_ctlr_1_init = 0x0024400b,
+	.emif_ddr_phy_ctlr_1	= 0x0e24400b,
+	.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
+	.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
+	.emif_rd_wr_lvl_rmp_win	= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl	= 0x80000000,
+	.emif_rd_wr_lvl_ctl	= 0x00000000,
+	.emif_rd_wr_exec_thresh	= 0x00000305
+#if 0
+	.sdram_config_init	= 0x61851b32,
+	.sdram_config		= 0x61851b32,
+	.sdram_config2		= 0x8000000,
+	.ref_ctrl		= 0x000040F1,
+	.ref_ctrl_final		= 0x00001035,
+        .sdram_tim1             = 0xCCCF365B,
+        .sdram_tim2             = 0x305A7FDA,
+        .sdram_tim3             = 0x407F8558,
 	.read_idle_ctrl		= 0x00090000,
 	.zq_config		= 0x5007190b,
 	.temp_alert_config	= 0x00000000,
@@ -156,6 +283,7 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
 	.emif_rd_wr_lvl_rmp_ctl	= 0x80000000,
 	.emif_rd_wr_lvl_ctl	= 0x00000000,
 	.emif_rd_wr_exec_thresh	= 0x00000305
+#endif
 };
 
 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
@@ -232,25 +360,25 @@ struct vcores_data beagle_x15_volts = {
 	.eve.value		= VDD_EVE_DRA752_HIGH,
 	.eve.efuse.reg		= STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
 	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
-	.eve.addr		= TPS659038_REG_ADDR_SMPS45,
+	.eve.addr		= TPS65917_REG_ADDR_SMPS3,//TPS659038_REG_ADDR_SMPS45,
 	.eve.pmic		= &tps659038,
 
 	.gpu.value		= VDD_GPU_DRA752_HIGH,
 	.gpu.efuse.reg		= STD_FUSE_OPP_VMIN_GPU_HIGH,
 	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
-	.gpu.addr		= TPS659038_REG_ADDR_SMPS45,
+	.gpu.addr		= TPS65917_REG_ADDR_SMPS3,//TPS659038_REG_ADDR_SMPS6,
 	.gpu.pmic		= &tps659038,
 
 	.core.value		= VDD_CORE_DRA752,
 	.core.efuse.reg		= STD_FUSE_OPP_VMIN_CORE_NOM,
 	.core.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
-	.core.addr		= TPS659038_REG_ADDR_SMPS6,
+	.core.addr		= TPS65917_REG_ADDR_SMPS2,//TPS659038_REG_ADDR_SMPS7,
 	.core.pmic		= &tps659038,
 
 	.iva.value		= VDD_IVA_DRA752_HIGH,
 	.iva.efuse.reg		= STD_FUSE_OPP_VMIN_IVA_HIGH,
 	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
-	.iva.addr		= TPS659038_REG_ADDR_SMPS45,
+	.iva.addr		= TPS65917_REG_ADDR_SMPS3,//TPS659038_REG_ADDR_SMPS8,
 	.iva.pmic		= &tps659038,
 };
 
@@ -277,12 +405,12 @@ void do_board_detect(void)
 	struct ti_am_eeprom *ep;
 	char *bname = NULL;
 	int rc;
-
+	
 	rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
 				  CONFIG_EEPROM_CHIP_ADDRESS, &ep);
 	if (rc)
 		printf("ti_i2c_eeprom_init failed %d\n", rc);
-
+	
 	if (board_is_x15())
 		bname = "BeagleBoard X15";
 	else if (board_is_am572x_evm())
@@ -291,10 +419,15 @@ void do_board_detect(void)
 		bname = "AM572x IDK";
 	else if (board_is_am571x_idk())
 		bname = "AM571x IDK";
-
+	bname = "AM571x IDK";
 	if (bname)
-		snprintf(sysinfo.board_string, sizeof(sysinfo.board_string),
-			 "Board: %s\n", bname);
+	{
+		snprintf(sysinfo.board_string, 16,"Board: %s\n", bname);
+	}
+	else
+	{
+		printf("\n Board name is NULL");
+	}
 }
 
 static void setup_board_eeprom_env(void)
@@ -322,7 +455,7 @@ static void setup_board_eeprom_env(void)
 	else
 		printf("Unidentified board claims %s in eeprom header\n",
 		       p.name);
-
+	name = "am571x_idk";
 invalid_eeprom:
 	set_board_info_env(name, p.version, p.serial);
 }
@@ -334,14 +467,14 @@ invalid_eeprom:
 void hw_data_init(void)
 {
 	*prcm = &dra7xx_prcm;
-	*dplls_data = &dra7xx_dplls;
+	*dplls_data = &dra72x_dplls;
 	*omap_vcores = &beagle_x15_volts;
 	*ctrl = &dra7xx_ctrl;
 }
 
 int board_init(void)
 {
-	gpmc_init();
+	//gpmc_init();/*We are not using in SOM*/
 	gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
 
 	return 0;
@@ -349,8 +482,8 @@ int board_init(void)
 
 int board_late_init(void)
 {
-	init_sata(0);
-	setup_board_eeprom_env();
+	//init_sata(0);
+	//setup_board_eeprom_env();
 
 	/*
 	 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
@@ -373,7 +506,7 @@ void recalibrate_iodelay(void)
 	const struct iodelay_cfg_entry *iod;
 	int pconf_sz, iod_sz;
 
-	if (board_is_am572x_idk()) {
+	/*if (board_is_am572x_idk()) {
 		pconf = core_padconf_array_essential_am572x_idk;
 		pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
 		iod = iodelay_cfg_array_am572x_idk;
@@ -383,13 +516,13 @@ void recalibrate_iodelay(void)
 		pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
 		iod = iodelay_cfg_array_am571x_idk;
 		iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
-	} else {
+	} else {*/
 		/* Common for X15/GPEVM */
 		pconf = core_padconf_array_essential_x15;
 		pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
 		iod = iodelay_cfg_array_x15;
 		iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15);
-	}
+	//}
 
 	__recalibrate_iodelay(pconf, pconf_sz, iod, iod_sz);
 }
@@ -605,7 +738,7 @@ int board_eth_init(bd_t *bis)
 		if (is_valid_ethaddr(mac_addr))
 			eth_setenv_enetaddr("ethaddr", mac_addr);
 	}
-
+#if 0
 	mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
 	mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
 	mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
@@ -619,17 +752,19 @@ int board_eth_init(bd_t *bis)
 		if (is_valid_ethaddr(mac_addr))
 			eth_setenv_enetaddr("eth1addr", mac_addr);
 	}
-
+#endif
 	ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
-	ctrl_val |= 0x22;
+	ctrl_val |= 0x11;/*To enable RMII Interface*/
 	writel(ctrl_val, (*ctrl)->control_core_control_io1);
-
+	//writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
 	/* The phy address for the AM57xx IDK are different than x15 */
 	if (board_is_am572x_idk() || board_is_am571x_idk()) {
-		cpsw_data.slave_data[0].phy_addr = 0;
-		cpsw_data.slave_data[1].phy_addr = 1;
+		cpsw_data.slave_data[0].phy_addr = 9;
+		//cpsw_data.slave_data[1].phy_addr = 1;
 	}
 
+	cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
+	cpsw_data.slave_data[0].phy_addr = 9;	
 	ret = cpsw_register(&cpsw_data);
 	if (ret < 0)
 		printf("Error %d registering CPSW switch\n", ret);
diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h
index d43fd73..f4fa2f1 100644
--- a/board/ti/am57xx/mux_data.h
+++ b/board/ti/am57xx/mux_data.h
@@ -12,42 +12,44 @@
 
 #include <asm/arch/mux_dra7xx.h>
 
+
 const struct pad_conf_entry core_padconf_array_essential_x15[] = {
-	{GPMC_AD0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad0.vin3a_d0 */
-	{GPMC_AD1, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_ad1.vin3a_d1 */
-	{GPMC_AD2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad2.vin3a_d2 */
-	{GPMC_AD3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad3.vin3a_d3 */
-	{GPMC_AD4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad4.vin3a_d4 */
-	{GPMC_AD5, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_ad5.vin3a_d5 */
-	{GPMC_AD6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad6.vin3a_d6 */
-	{GPMC_AD7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad7.vin3a_d7 */
-	{GPMC_AD8, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_ad8.vin3a_d8 */
-	{GPMC_AD9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad9.vin3a_d9 */
-	{GPMC_AD10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad10.vin3a_d10 */
-	{GPMC_AD11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad11.vin3a_d11 */
-	{GPMC_AD12, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad12.vin3a_d12 */
-	{GPMC_AD13, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad13.vin3a_d13 */
-	{GPMC_AD14, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad14.vin3a_d14 */
-	{GPMC_AD15, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_ad15.vin3a_d15 */
-	{GPMC_A0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a0.vin3a_d16 */
-	{GPMC_A1, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a1.vin3a_d17 */
-	{GPMC_A2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a2.vin3a_d18 */
-	{GPMC_A3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a3.vin3a_d19 */
-	{GPMC_A4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a4.vin3a_d20 */
-	{GPMC_A5, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a5.vin3a_d21 */
-	{GPMC_A6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a6.vin3a_d22 */
-	{GPMC_A7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a7.vin3a_d23 */
-	{GPMC_A8, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a8.vin3a_hsync0 */
-	{GPMC_A9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a9.vin3a_vsync0 */
-	{GPMC_A10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a10.vin3a_de0 */
-	{GPMC_A11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a11.vin3a_fld0 */
-	{GPMC_A12, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_a12.gpio2_2 */
-	{GPMC_A13, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_a13.gpio2_3 */
-	{GPMC_A14, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_a14.gpio2_4 */
-	{GPMC_A15, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_a15.gpio2_5 */
-	{GPMC_A16, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_a16.gpio2_6 */
-	{GPMC_A17, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_a17.gpio2_7 */
-	{GPMC_A18, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_a18.gpio2_8 */
+//#if 1
+	{GPMC_AD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad0.vin3a_d0 */
+	{GPMC_AD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_ad1.vin3a_d1 */
+	{GPMC_AD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad2.vin3a_d2 */
+	{GPMC_AD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad3.vin3a_d3 */
+	{GPMC_AD4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad4.vin3a_d4 */
+	{GPMC_AD5, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_ad5.vin3a_d5 */
+	{GPMC_AD6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad6.vin3a_d6 */
+	{GPMC_AD7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad7.vin3a_d7 */
+	{GPMC_AD8, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_ad8.vin3a_d8 */
+	{GPMC_AD9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad9.vin3a_d9 */
+	{GPMC_AD10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad10.vin3a_d10 */
+	{GPMC_AD11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad11.vin3a_d11 */
+	{GPMC_AD12, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad12.vin3a_d12 */
+	{GPMC_AD13, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad13.vin3a_d13 */
+	{GPMC_AD14, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_ad14.vin3a_d14 */
+	{GPMC_AD15, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* gpmc_ad15.vin3a_d15 */
+//	{GPMC_A0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a0.vin3a_d16 */
+//	{GPMC_A1, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a1.vin3a_d17 */
+	{GPMC_A2, (M7 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a2.vin3a_d18 */
+	{GPMC_A3, (M7 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a3.vin3a_d19 */
+	{GPMC_A4, (M8 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a4.vin3a_d20 */
+	{GPMC_A5, (M8 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a5.vin3a_d21 */
+	{GPMC_A6, (M7 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a6.vin3a_d22 */
+	{GPMC_A7, (M7 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a7.vin3a_d23 */
+//	{GPMC_A8, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a8.vin3a_hsync0 */
+//	{GPMC_A9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a9.vin3a_vsync0 */
+//	{GPMC_A10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a10.vin3a_de0 */
+//	{GPMC_A11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* gpmc_a11.vin3a_fld0 */
+//	{GPMC_A12, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_a12.gpio2_2 */
+//	{GPMC_A13, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_a13.gpio2_3 */
+//	{GPMC_A14, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_a14.gpio2_4 */
+//	{GPMC_A15, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_a15.gpio2_5 */
+//	{GPMC_A16, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_a16.gpio2_6 */
+//	{GPMC_A17, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_a17.gpio2_7 */
+//	{GPMC_A18, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_a18.gpio2_8 */
 	{GPMC_A19, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a19.mmc2_dat4 */
 	{GPMC_A20, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a20.mmc2_dat5 */
 	{GPMC_A21, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a21.mmc2_dat6 */
@@ -58,11 +60,12 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = {
 	{GPMC_A26, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a26.mmc2_dat2 */
 	{GPMC_A27, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_a27.mmc2_dat3 */
 	{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},	/* gpmc_cs1.mmc2_cmd */
-	{GPMC_CS0, (M14 | PIN_INPUT_PULLDOWN)},	/* gpmc_cs0.gpio2_19 */
-	{GPMC_CS2, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_cs2.gpio2_20 */
-	{GPMC_CS3, (M2 | PIN_INPUT_PULLDOWN)},	/* gpmc_cs3.vin3a_clk0 */
-	{GPMC_CLK, (M9 | PIN_INPUT_PULLDOWN)},	/* gpmc_clk.dma_evt1 */
-	{GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_advn_ale.gpio2_23 */
+	{GPMC_CS0, (M14 | PIN_OUTPUT)},	/* gpmc_cs0.gpio2_19 */
+	{GPMC_CS2, (M14 | PIN_OUTPUT)},	/* gpmc_cs2.gpio2_20 */
+	{GPMC_CS3, (M14 | PIN_OUTPUT)},	/* gpmc_cs3.vin3a_clk0 */
+	//{GPMC_CLK, (M9 | PIN_INPUT_PULLDOWN)},	/* gpmc_clk.dma_evt1 */
+     #if 0	
+       {GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_advn_ale.gpio2_23 */
 	{GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_oen_ren.gpio2_24 */
 	{GPMC_WEN, (M14 | PIN_INPUT_PULLUP)},	/* gpmc_wen.gpio2_25 */
 	{GPMC_BEN0, (M9 | PIN_INPUT_PULLDOWN)},	/* gpmc_ben0.dma_evt3 */
@@ -114,6 +117,36 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = {
 	{VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d21.rgmii1_rxd2 */
 	{VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d22.rgmii1_rxd1 */
 	{VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
+    #endif
+
+	{VIN2A_HSYNC0, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_hsync0.pr1_uart0_cts_n */
+	{VIN2A_VSYNC0, (M14 | PIN_INPUT_PULLUP)},	/* vin2a_vsync0.pr1_uart0_rts_n */
+	{VIN2A_D0, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d0.pr1_uart0_rxd */
+	{VIN2A_D1, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d1.pr1_uart0_txd */
+	{VIN2A_D2, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d2.uart10_rxd */
+	{VIN2A_D3, (M14 | PIN_OUTPUT)},	/* vin2a_d3.uart10_txd */
+	{VIN2A_D4, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d4.uart10_ctsn */
+	{VIN2A_D5, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d5.uart10_rtsn */
+	{VIN2A_D6, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d6.gpio4_7 */
+	{VIN2A_D7, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d7.gpio4_8 */
+	{VIN2A_D8, (M14 | PIN_OUTPUT)},	/* vin2a_d8.gpio4_9 */
+	{VIN2A_D9, (M14 | PIN_OUTPUT)},	/* vin2a_d9.gpio4_10 */
+	{VIN2A_D10, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d10.ehrpwm2B */
+	{VIN2A_D11, (M14 | PIN_INPUT_PULLDOWN)},	/* vin2a_d11.ehrpwm2_tripzone_input */
+	{VIN2A_D12, (M14 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d12.rgmii1_txc */
+	{VIN2A_D13, (M14 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d13.rgmii1_txctl */
+	{VIN2A_D14, (M14 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d14.rgmii1_txd3 */
+	{VIN2A_D15, (M14 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* vin2a_d15.rgmii1_txd2 */
+	{VIN2A_D16, (M14 | PIN_OUTPUT)},	/* vin2a_d16.rgmii1_txd1 */
+	{VIN2A_D17, (M14 | PIN_OUTPUT)},	/* vin2a_d17.rgmii1_txd0 */
+	{VIN2A_D18, (M14 | PIN_OUTPUT)},	/* vin2a_d18.rgmii1_rxc */
+	{VIN2A_D19, (M14 | PIN_OUTPUT)},	/* vin2a_d19.rgmii1_rxctl */
+	{VIN2A_D20, (M14 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d20.rgmii1_rxd3 */
+	{VIN2A_D21, (M14 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d21.rgmii1_rxd2 */
+	{VIN2A_D22, (M14 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d22.rgmii1_rxd1 */
+	{VIN2A_D23, (M14 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
+
+
 	{VOUT1_CLK, (M0 | PIN_OUTPUT)},		/* vout1_clk.vout1_clk */
 	{VOUT1_DE, (M0 | PIN_OUTPUT)},		/* vout1_de.vout1_de */
 	{VOUT1_FLD, (M14 | PIN_INPUT)},		/* vout1_fld.gpio4_21 */
@@ -145,23 +178,27 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = {
 	{VOUT1_D23, (M0 | PIN_OUTPUT)},		/* vout1_d23.vout1_d23 */
 	{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP)},	/* mdio_mclk.mdio_mclk */
 	{MDIO_D, (M0 | PIN_INPUT_PULLUP)},	/* mdio_d.mdio_d */
-	{RMII_MHZ_50_CLK, (M14 | PIN_INPUT_PULLUP)},	/* RMII_MHZ_50_CLK.gpio5_17 */
-	{UART3_RXD, (M14 | PIN_INPUT_PULLDOWN)},	/* uart3_rxd.gpio5_18 */
-	{UART3_TXD, (M14 | PIN_INPUT_PULLDOWN)},	/* uart3_txd.gpio5_19 */
-	{RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
+	
+        {RMII_MHZ_50_CLK, (M0 | PIN_INPUT_PULLUP)},	/* RMII_MHZ_50_CLK.gpio5_17 */
+	{UART3_RXD, (M7 | PIN_INPUT_PULLDOWN)},	/* uart3_rxd.spi_clk */
+	{UART3_TXD, (M7 | PIN_INPUT_PULLDOWN)},	/* uart3_txd.spi_miso */
+//	{RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txc.rgmii0_txc */
 	{RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txctl.rgmii0_txctl */
-	{RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd3.rgmii0_txd3 */
-	{RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd2.rgmii0_txd2 */
-	{RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd1.rgmii0_txd1 */
-	{RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_txd0.rgmii0_txd0 */
-	{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
-	{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
-	{RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
-	{RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd2.rgmii0_rxd2 */
-	{RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd1.rgmii0_rxd1 */
-	{RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd0.rgmii0_rxd0 */
+	{RGMII0_TXD3, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rmii0_crrsdv */
+	{RGMII0_TXD2, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rmii0_rx_er */
+	{RGMII0_TXD1, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rmii0_rx_d1 */
+	{RGMII0_TXD0, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rmii0_rx_d0 */
+	//{RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxc.rgmii0_rxc */
+	//{RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},	/* rgmii0_rxctl.rgmii0_rxctl */
+	//{RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rgmii0_rxd3.rgmii0_rxd3 */
+	{RGMII0_RXD2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rmii0_tx_en */
+	{RGMII0_RXD1, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rmii0_tx_d1 */
+	{RGMII0_RXD0, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* rmii0_tx_d0 */
+
 	{USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)},	/* usb1_drvvbus.usb1_drvvbus */
-	{USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)},	/* usb2_drvvbus.usb2_drvvbus */
+	{USB2_DRVVBUS, (M14 | PIN_OUTPUT)},	/* usb2_drvvbus.usb2_drvvbus */
+	{XREF_CLK2, (M3 | PIN_OUTPUT)},	/* xref_clk2.atl_clk2 */
+     #if 0
 	{GPIO6_14, (M10 | PIN_INPUT_PULLUP)},	/* gpio6_14.timer1 */
 	{GPIO6_15, (M10 | PIN_INPUT_PULLUP)},	/* gpio6_15.timer2 */
 	{GPIO6_16, (M10 | PIN_INPUT_PULLUP)},	/* gpio6_16.timer3 */
@@ -169,12 +206,12 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = {
 	{XREF_CLK1, (M14 | PIN_INPUT_PULLDOWN)},	/* xref_clk1.gpio6_18 */
 	{XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)},	/* xref_clk2.gpio6_19 */
 	{XREF_CLK3, (M9 | PIN_INPUT_PULLDOWN)},	/* xref_clk3.clkout3 */
-	{MCASP1_ACLKX, (M10 | PIN_INPUT_PULLUP)},	/* mcasp1_aclkx.i2c3_sda */
+	
 	{MCASP1_FSX, (M10 | PIN_INPUT_PULLUP)},	/* mcasp1_fsx.i2c3_scl */
-	{MCASP1_ACLKR, (M10 | PIN_INPUT_PULLUP)},	/* mcasp1_aclkr.i2c4_sda */
+	
 	{MCASP1_FSR, (M10 | PIN_INPUT_PULLUP)},	/* mcasp1_fsr.i2c4_scl */
-	{MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr0.i2c5_sda */
-	{MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr1.i2c5_scl */
+
+	
 	{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr2.gpio5_4 */
 	{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr3.gpio5_5 */
 	{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr4.gpio5_6 */
@@ -184,36 +221,55 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = {
 	{MCASP1_AXR8, (M14 | PIN_INPUT_SLEW)},	/* mcasp1_axr8.gpio5_10 */
 	{MCASP1_AXR9, (M14 | PIN_INPUT_SLEW)},	/* mcasp1_axr9.gpio5_11 */
 	{MCASP1_AXR10, (M14 | PIN_INPUT_SLEW)},	/* mcasp1_axr10.gpio5_12 */
-	{MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr11.gpio4_17 */
-	{MCASP1_AXR12, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr12.mcasp7_axr0 */
+	
+	
 	{MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr13.mcasp7_axr1 */
 	{MCASP1_AXR14, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr14.mcasp7_aclkx */
 	{MCASP1_AXR15, (M1 | PIN_INPUT_SLEW)},	/* mcasp1_axr15.mcasp7_fsx */
 	{MCASP2_ACLKX, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_aclkx.mcasp2_aclkx */
 	{MCASP2_FSX, (M0 | PIN_INPUT_SLEW)},	/* mcasp2_fsx.mcasp2_fsx */
 	{MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_aclkr.mcasp2_aclkr */
-	{MCASP2_FSR, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_fsr.mcasp2_fsr */
+	
 	{MCASP2_AXR0, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr0.mcasp2_axr0 */
-	{MCASP2_AXR1, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr1.mcasp2_axr1 */
+	
 	{MCASP2_AXR2, (M0 | PIN_INPUT_SLEW)},	/* mcasp2_axr2.mcasp2_axr2 */
 	{MCASP2_AXR3, (M0 | PIN_INPUT_SLEW)},	/* mcasp2_axr3.mcasp2_axr3 */
 	{MCASP2_AXR4, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr4.mcasp2_axr4 */
 	{MCASP2_AXR5, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr5.mcasp2_axr5 */
 	{MCASP2_AXR6, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr6.mcasp2_axr6 */
 	{MCASP2_AXR7, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr7.mcasp2_axr7 */
+
+
+	
+	
+	
+	
+	{MCASP5_AXR1, (M3 | PIN_INPUT_PULLUP)},	/* mcasp5_axr1.uart9_rtsn */
+     #endif
+	{MCASP1_ACLKR, (M14 | PIN_INPUT_PULLUP)},	/* mcasp1_aclkr.i2c4_sda */
+	{MCASP1_AXR0, (M14 | PIN_INPUT_PULLUP )},	/* mcasp1_axr0.i2c5_sda */
+	{MCASP1_AXR1, (M14 | PIN_OUTPUT)},	/* mcasp1_axr1.i2c5_scl */
+	{MCASP1_ACLKX, (M14 | PIN_INPUT_PULLUP)},	/* mcasp1_aclkx.i2c3_sda */
+	{MCASP2_FSR, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp2_fsr.mcasp2_fsr */
+	{MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* mcasp1_axr11.gpio4_17 */
+	{MCASP1_AXR12, (M14 | PIN_INPUT_PULLDOWN)},	/* mcasp1_axr12.mcasp7_axr0 */
+
 	{MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp3_aclkx.mcasp3_aclkx */
 	{MCASP3_FSX, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp3_fsx.mcasp3_fsx */
 	{MCASP3_AXR0, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp3_axr0.mcasp3_axr0 */
 	{MCASP3_AXR1, (M0 | PIN_INPUT_PULLDOWN)},	/* mcasp3_axr1.mcasp3_axr1 */
+
+	{MCASP4_AXR1, (M3 | PIN_INPUT_PULLUP)},	/* mcasp4_axr1.uart8_rtsn */
 	{MCASP4_ACLKX, (M3 | PIN_INPUT_PULLDOWN)},	/* mcasp4_aclkx.uart8_rxd */
 	{MCASP4_FSX, (M3 | PIN_INPUT_PULLDOWN)},	/* mcasp4_fsx.uart8_txd */
 	{MCASP4_AXR0, (M3 | PIN_INPUT_PULLDOWN)},	/* mcasp4_axr0.uart8_ctsn */
-	{MCASP4_AXR1, (M3 | PIN_INPUT_PULLUP)},	/* mcasp4_axr1.uart8_rtsn */
-	{MCASP5_ACLKX, (M3 | PIN_INPUT_PULLDOWN)},	/* mcasp5_aclkx.uart9_rxd */
-	{MCASP5_FSX, (M3 | PIN_INPUT_PULLDOWN)},	/* mcasp5_fsx.uart9_txd */
-	{MCASP5_AXR0, (M3 | PIN_INPUT_PULLDOWN)},	/* mcasp5_axr0.uart9_ctsn */
-	{MCASP5_AXR1, (M3 | PIN_INPUT_PULLUP)},	/* mcasp5_axr1.uart9_rtsn */
-	{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_clk.mmc1_clk */
+
+	{MCASP2_AXR1, (M2 | PIN_INPUT_PULLDOWN)},	/* mcasp2_axr1.spi_cs */
+	{MCASP5_FSX, (M2 | PIN_INPUT_PULLDOWN)},	/* mcasp5_fsx.spi_data */
+	{MCASP5_AXR0, (M2 | PIN_INPUT_PULLDOWN)},	/* mcasp5_axr0.spi1_mosi*/
+	{MCASP5_ACLKX, (M3 | PIN_INPUT_PULLDOWN)},	/* mcasp5_aclkx.spi_clk */
+
+       {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_clk.mmc1_clk */
 	{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_cmd.mmc1_cmd */
 	{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat0.mmc1_dat0 */
 	{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat1.mmc1_dat1 */
@@ -221,6 +277,14 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = {
 	{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_dat3.mmc1_dat3 */
 	{MMC1_SDCD, (M0 | PIN_INPUT_PULLUP)},	/* mmc1_sdcd.mmc1_sdcd */
 	{MMC1_SDWP, (M14 | PIN_OUTPUT)},	/* mmc1_sdwp.gpio6_28 */
+
+	{SPI1_CS1, (M2 | PIN_OUTPUT_PULLUP)},	/* spi1_cs1.gpio7_11 */
+	{SPI1_CS3, (M15 | PULL_UP )},	/* spi1_cs3.hdmi1_cec */
+{SPI1_CS2, (M15 | PULL_UP )},	/* spi1_cs2.gpio7_12 */
+	{GPIO6_14, (M15 | PULL_UP)},  /* gpio6_14.gpio6_14 */
+{GPIO6_15, (M15 | PULL_UP)},	/* gpio6_15.timer2 */
+	{SPI1_SCLK, (M14 |PIN_OUTPUT_PULLUP)},	/* spi1_sclk.gpio7_7 */
+     #if 0
 	{GPIO6_10, (M10 | PIN_INPUT_PULLDOWN)},	/* gpio6_10.ehrpwm2A */
 	{GPIO6_11, (M14 | PIN_INPUT_PULLUP)},	/* gpio6_11.gpio6_11 */
 	{MMC3_CLK, (M0 | PIN_INPUT_PULLUP)},	/* mmc3_clk.mmc3_clk */
@@ -233,17 +297,18 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = {
 	{MMC3_DAT5, (M1 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat5.spi4_d1 */
 	{MMC3_DAT6, (M1 | PIN_INPUT_PULLDOWN)},	/* mmc3_dat6.spi4_d0 */
 	{MMC3_DAT7, (M1 | PIN_INPUT_PULLUP)},	/* mmc3_dat7.spi4_cs0 */
-	{SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_sclk.gpio7_7 */
+	
 	{SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_d1.gpio7_8 */
 	{SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_d0.gpio7_9 */
 	{SPI1_CS0, (M14 | PIN_OUTPUT)},		/* spi1_cs0.gpio7_10 */
-	{SPI1_CS1, (M14 | PIN_OUTPUT_PULLUP)},	/* spi1_cs1.gpio7_11 */
+	
 	{SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)},	/* spi1_cs2.gpio7_12 */
-	{SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi1_cs3.hdmi1_cec */
+	
 	{SPI2_SCLK, (M14 | PIN_INPUT_PULLDOWN)},	/* spi2_sclk.gpio7_14 */
 	{SPI2_D1, (M14 | PIN_INPUT_PULLDOWN)},	/* spi2_d1.gpio7_15 */
 	{SPI2_D0, (M14 | PIN_INPUT_PULLUP)},	/* spi2_d0.gpio7_16 */
 	{SPI2_CS0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)},	/* spi2_cs0.gpio7_17 */
+     #endif
 	{DCAN1_TX, (M15 | PULL_UP)},	/* dcan1_tx.safe for dcan1_tx */
 	{DCAN1_RX, (M15 | PULL_UP)},	/* dcan1_rx.safe for dcan1_rx */
 	{UART1_RXD, (M0 | PIN_INPUT_SLEW)},	/* uart1_rxd.uart1_rxd */
@@ -255,13 +320,187 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = {
 	{UART2_RTSN, (M1 | PIN_INPUT_SLEW)},	/* uart2_rtsn.uart3_txd */
 	{I2C2_SDA, (M1 | PIN_INPUT)},		/* i2c2_sda.hdmi1_ddc_scl */
 	{I2C2_SCL, (M1 | PIN_INPUT)},		/* i2c2_scl.hdmi1_ddc_sda */
-	{WAKEUP0, (M0 | PULL_UP)},	/* Wakeup0.Wakeup0 */
+	{WAKEUP0, (M15 | PULL_UP)},	/* Wakeup0.Wakeup0 */
 	{WAKEUP1, (M0)},	/* Wakeup1.Wakeup1 */
 	{WAKEUP2, (M0)},	/* Wakeup2.Wakeup2 */
-	{WAKEUP3, (M0 | PULL_UP)},	/* Wakeup3.Wakeup3 */
+	{WAKEUP3, (M15 | PULL_UP)},	/* Wakeup3.Wakeup3 */
 	{ON_OFF, (M1 | PIN_OUTPUT_PULLUP)},	/* on_off.on_off */
 	{RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)},	/* rtc_porz.rtc_porz */
 	{RTCK, (M0 | PIN_INPUT_PULLDOWN)},	/* rtck.rtck */
+//#endif
+#if 0
+         {GPMC_AD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},    /* gpmc_ad0.vin3a_d0 */
+         {GPMC_AD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},      /* gpmc_ad1.vin3a_d1 */
+         {GPMC_AD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},    /* gpmc_ad2.vin3a_d2 */
+         {GPMC_AD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},    /* gpmc_ad3.vin3a_d3 */
+         {GPMC_AD4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},    /* gpmc_ad4.vin3a_d4 */
+         {GPMC_AD5, ( M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},      /* gpmc_ad5.vin3a_d5 */
+         {GPMC_AD6, ( M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},    /* gpmc_ad6.vin3a_d6 */
+         {GPMC_AD7, ( M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},    /* gpmc_ad7.vin3a_d7 */
+         {GPMC_AD8, ( M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},      /* gpmc_ad8.vin3a_d8 */
+         {GPMC_AD9, ( M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},    /* gpmc_ad9.vin3a_d9 */
+         {GPMC_AD10, ( M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},   /* gpmc_ad10.vin3a_d10 */
+         {GPMC_AD11, ( M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},   /* gpmc_ad11.vin3a_d11 */
+         {GPMC_AD12, ( M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},   /* gpmc_ad12.vin3a_d12 */
+         {GPMC_AD13, ( M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},   /* gpmc_ad13.vin3a_d13 */
+         {GPMC_AD14, ( M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},   /* gpmc_ad14.vin3a_d14 */
+         {GPMC_AD15, ( M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},     /* gpmc_ad15.vin3a_d15 */
+         
+ 
+         {GPMC_A0, ( M0 | INPUT_EN | MANUAL_MODE)},     /* gpmc_a0.vin3a_d16 */
+         {GPMC_A1, ( M0 | INPUT_EN | MANUAL_MODE)},     /* gpmc_a1.vin3a_d17 */
+         {GPMC_A2, ( M0 | INPUT_EN | MANUAL_MODE)},     /* gpmc_a2.vin3a_d18 */
+         {GPMC_A3, ( M0 | INPUT_EN | MANUAL_MODE)},     /* gpmc_a3.vin3a_d19 */
+         {GPMC_A4, ( M0 | INPUT_EN | MANUAL_MODE)},     /* gpmc_a4.vin3a_d20 */
+         {GPMC_A5, ( M0 | INPUT_EN | MANUAL_MODE)},     /* gpmc_a5.vin3a_d21 */
+         {GPMC_A6, ( M0 | INPUT_EN | MANUAL_MODE)},     /* gpmc_a6.vin3a_d22 */
+         {GPMC_A7, ( M0 | INPUT_EN | MANUAL_MODE)},     /* gpmc_a7.vin3a_d23 */
+         {GPMC_A8, ( M0 | INPUT_EN | MANUAL_MODE)},     /* gpmc_a8.vin3a_hsync0 */
+         {GPMC_A9, ( M0 | INPUT_EN | MANUAL_MODE)},     /* gpmc_a9.vin3a_vsync0 */
+         {GPMC_A10, ( M0 | INPUT_EN | MANUAL_MODE)},    /* gpmc_a10.vin3a_de0 */
+         {GPMC_A11, ( M0 | INPUT_EN | MANUAL_MODE)},    /* gpmc_a11.vin3a_fld0 */
+         {GPMC_A12, ( M0 | INPUT_EN | MANUAL_MODE)},   /* gpmc_a12.gpio2_2 */
+         {GPMC_A13, ( M0 | INPUT_EN | MANUAL_MODE)}, /* gpmc_a13.gpio2_3 */
+         {GPMC_A14, ( M0 | INPUT_EN | MANUAL_MODE)},   /* gpmc_a14.gpio2_4 */
+         {GPMC_A15, ( M0 | INPUT_EN | MANUAL_MODE)}, /* gpmc_a15.gpio2_5 */
+         {GPMC_A16, ( M0 | INPUT_EN | MANUAL_MODE)}, /* gpmc_a16.gpio2_6 */
+         {GPMC_A17, ( M0 | INPUT_EN | MANUAL_MODE)}, /* gpmc_a17.gpio2_7 */
+         {GPMC_A18, ( M0 | INPUT_EN | MANUAL_MODE)},   /* gpmc_a18.gpio2_8 */
+         {GPMC_A19, ( M0 | INPUT_EN | MANUAL_MODE)},    /* gpmc_a19.mmc2_dat4 */
+         {GPMC_A20, ( M0 | INPUT_EN | MANUAL_MODE)},    /* gpmc_a20.mmc2_dat5 */
+         {GPMC_A21, ( M0 | INPUT_EN | MANUAL_MODE)},    /* gpmc_a21.mmc2_dat6 */
+         {GPMC_A22, ( M0 | INPUT_EN | MANUAL_MODE)},    /* gpmc_a22.mmc2_dat7 */ 
+         {GPMC_A23, ( M0 | INPUT_EN | MANUAL_MODE)},    /* gpmc_a23.mmc2_clk */
+         {GPMC_A24, ( M0 | INPUT_EN | MANUAL_MODE)},    /* gpmc_a24.mmc2_dat0 */
+         {GPMC_A25, ( M0 | INPUT_EN | MANUAL_MODE)},    /* gpmc_a25.mmc2_dat1 */
+         {GPMC_A26, ( M0 | INPUT_EN | MANUAL_MODE)},    /* gpmc_a26.mmc2_dat2 */
+         {GPMC_A27, ( M0 | INPUT_EN | MANUAL_MODE)},    /* gpmc_a27.mmc2_dat3 */
+  
+         {GPMC_CS1, ( M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},    /* gpmc_cs1.mmc2_cmd */
+ 
+         {GPMC_CS0, ( M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_cs0.gpio2_19 */
+         {GPMC_CS2, ( M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},   /* gpmc_cs2.gpio2_20 */
+         {GPMC_CS3, ( M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},  /* gpmc_cs3.vin3a_clk0 */
+ 
+         {GPMC_CLK, (M0 | PIN_INPUT_PULLDOWN)},  /* gpmc_clk.dma_evt1 */
+         {GPMC_ADVN_ALE, (M0 | PIN_INPUT_PULLUP)},      /* gpmc_advn_ale.gpio2_23 */
+         {GPMC_OEN_REN, (M0 | PIN_INPUT_PULLUP)},       /* gpmc_oen_ren.gpio2_24 */
+         {GPMC_WEN, (M0 | PIN_INPUT_PULLUP)},   /* gpmc_wen.gpio2_25 */
+         {GPMC_BEN0, (M0 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.dma_evt3 */
+         {GPMC_BEN1, (M0 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben1.dma_evt4 */
+         {GPMC_WAIT0, (M0 | PIN_INPUT_PULLUP)}, /* gpmc_wait0.gpio2_28 */
+ 
+  
+         {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP)},   /* mdio_mclk.mdio_mclk */
+         {MDIO_D, (M0 | PIN_INPUT_PULLUP)},      /* mdio_d.mdio_d */
+         {RMII_MHZ_50_CLK, (M14 | PIN_INPUT_PULLUP)},    /* RMII_MHZ_50_CLK.gpio5_17 */ 
+ 
+         {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},  /* rgmii0_txc.rgmii0_txc */
+        {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},        /* rgmii0_txctl.rgmii0_txctl */
+      {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */
+       {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ 
+        {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */
+        {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */
+         {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},  /* rgmii0_rxc.rgmii0_rxc */
+        {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},        /* rgmii0_rxctl.rgmii0_rxctl */
+        {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},   /* rgmii0_rxd3.rgmii0_rxd3 */
+        {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},   /* rgmii0_rxd2.rgmii0_rxd2 */
+       {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},   /* rgmii0_rxd1.rgmii0_rxd1 */
+       {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)},   /* rgmii0_rxd0.rgmii0_rxd0 */
+ 
+         {XREF_CLK0, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.clkout2 */
+         {XREF_CLK1, (M14 | PIN_INPUT_PULLDOWN)},        /* xref_clk1.gpio6_18 */
+         {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)},        /* xref_clk2.gpio6_19 */
+         {XREF_CLK3, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.clkout3 */
+
+         {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},    /* mmc1_clk.mmc1_clk */
+         {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},    /* mmc1_cmd.mmc1_cmd */
+         {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},   /* mmc1_dat0.mmc1_dat0 */ 
+         {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},   /* mmc1_dat1.mmc1_dat1 */
+         {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},   /* mmc1_dat2.mmc1_dat2 */
+         {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},   /* mmc1_dat3.mmc1_dat3 */
+         {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP)},   /* mmc1_sdcd.mmc1_sdcd */
+        // {MMC1_SDWP, (M14 | PIN_OUTPUT)},        /* mmc1_sdwp.gpio6_28 */
+ 
+ 
+         {UART1_RXD, (M0 | PIN_INPUT_SLEW)},     /* uart1_rxd.uart1_rxd */
+         {UART1_TXD, (M0 | PIN_INPUT_SLEW)},     /* uart1_txd.uart1_txd */
+ 
+    //    {UART2_RXD, (PIN_INPUT_SLEW | M0)},
+      //  {UART2_TXD, (PIN_INPUT_SLEW | M0)},
+ 
+ //       {UART2_CTSN, (PIN_INPUT_SLEW | M2)},  /*UART3_RXD*/
+  //      {UART2_RTSN, (PIN_INPUT_SLEW | M1)},  /*UART3_TXD*/
+ 
+        /*MMC3*/
+     //   {MMC3_CLK, (PIN_INPUT_PULLUP | M0)},
+      //  {MMC3_CMD, (PIN_INPUT_PULLUP | M0)},
+       // {MMC3_DAT0, (PIN_INPUT_PULLUP | M0)},
+      //  {MMC3_DAT1, (PIN_INPUT_PULLUP | M0)},
+      //  {MMC3_DAT2, (PIN_INPUT_PULLUP | M0)},
+      //  {MMC3_DAT3, (PIN_INPUT_PULLUP | M0)},
+      //  {MMC3_DAT4, (PIN_INPUT_PULLUP | M0)},
+      //  {MMC3_DAT5, (PIN_INPUT_PULLUP | M0)},
+      //  {MMC3_DAT6, (PIN_INPUT_PULLUP | M0)},
+       // {MMC3_DAT7, (PIN_INPUT_PULLUP | M0)}, 
+ 
+ 
+ /*Ehernet Channel 2*/ 
+        {VIN2A_D12, (PIN_INPUT_PULLDOWN | MANUAL_MODE | M3) },
+       {VIN2A_D13, (PIN_INPUT_PULLDOWN | MANUAL_MODE | M3) },
+        {VIN2A_D14, (PIN_INPUT_PULLDOWN | MANUAL_MODE | M3) },
+       {VIN2A_D15, (PIN_INPUT_PULLDOWN | MANUAL_MODE | M3) },
+        {VIN2A_D16, (PIN_INPUT_PULLDOWN | MANUAL_MODE | M3) },
+        {VIN2A_D17, (PIN_INPUT_PULLDOWN | MANUAL_MODE | M3) },
+       {VIN2A_D18, (PIN_INPUT_PULLDOWN | MANUAL_MODE | M3) },
+       {VIN2A_D19, (PIN_INPUT_PULLDOWN | MANUAL_MODE | M3) },
+      {VIN2A_D20, (PIN_INPUT_PULLUP | MANUAL_MODE | M3) },
+        {VIN2A_D21, (PIN_INPUT_PULLUP | MANUAL_MODE | M3) },
+        {VIN2A_D22, (PIN_INPUT_PULLUP | MANUAL_MODE | M3) }, 
+	{VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},	/* vin2a_d23.rgmii1_rxd0 */
+ //        {ON_OFF, (M1 | PIN_OUTPUT_PULLUP)},     /* on_off.on_off */
+         {RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rtc_porz.rtc_porz */
+         {RTCK, (M0 | PIN_INPUT_PULLDOWN)},      /* rtck.rtck */
+       {SPI1_CS1, (PIN_OUTPUT_PULLUP | M14) }, /* GPIO7_11 -> VTT enable*/ 
+      // LCD pins
+         {VOUT1_CLK, (M0 | PIN_OUTPUT)},         /* vout1_clk.vout1_clk */
+         {VOUT1_DE, (M0 | PIN_OUTPUT)},          /* vout1_de.vout1_de */
+         {VOUT1_FLD, (M14 | PIN_INPUT)},         /* vout1_fld.gpio4_21 */
+         {VOUT1_HSYNC, (M0 | PIN_OUTPUT)},       /* vout1_hsync.vout1_hsync */
+         {VOUT1_VSYNC, (M0 | PIN_OUTPUT)},       /* vout1_vsync.vout1_vsync */
+         {VOUT1_D0, (M0 | PIN_OUTPUT)},          /* vout1_d0.vout1_d0 */
+         {VOUT1_D1, (M0 | PIN_OUTPUT)},          /* vout1_d1.vout1_d1 */
+         {VOUT1_D2, (M0 | PIN_OUTPUT)},          /* vout1_d2.vout1_d2 */
+         {VOUT1_D3, (M0 | PIN_OUTPUT)},          /* vout1_d3.vout1_d3 */
+         {VOUT1_D4, (M0 | PIN_OUTPUT)},          /* vout1_d4.vout1_d4 */
+         {VOUT1_D5, (M0 | PIN_OUTPUT)},          /* vout1_d5.vout1_d5 */
+         {VOUT1_D6, (M0 | PIN_OUTPUT)},          /* vout1_d6.vout1_d6 */
+         {VOUT1_D7, (M0 | PIN_OUTPUT)},          /* vout1_d7.vout1_d7 */
+         {VOUT1_D8, (M0 | PIN_OUTPUT)},          /* vout1_d8.vout1_d8 */
+         {VOUT1_D9, (M0 | PIN_OUTPUT)},          /* vout1_d9.vout1_d9 */
+         {VOUT1_D10, (M0 | PIN_OUTPUT)},         /* vout1_d10.vout1_d10 */
+         {VOUT1_D11, (M0 | PIN_OUTPUT)},         /* vout1_d11.vout1_d11 */
+         {VOUT1_D12, (M0 | PIN_OUTPUT)},         /* vout1_d12.vout1_d12 */
+         {VOUT1_D13, (M0 | PIN_OUTPUT)},         /* vout1_d13.vout1_d13 */
+         {VOUT1_D14, (M0 | PIN_OUTPUT)},         /* vout1_d14.vout1_d14 */
+         {VOUT1_D15, (M0 | PIN_OUTPUT)},         /* vout1_d15.vout1_d15 */
+         {VOUT1_D16, (M0 | PIN_OUTPUT)},         /* vout1_d16.vout1_d16 */
+         {VOUT1_D17, (M0 | PIN_OUTPUT)},         /* vout1_d17.vout1_d17 */
+         {VOUT1_D18, (M0 | PIN_OUTPUT)},         /* vout1_d18.vout1_d18 */
+         {VOUT1_D19, (M0 | PIN_OUTPUT)},         /* vout1_d19.vout1_d19 */
+         {VOUT1_D20, (M0 | PIN_OUTPUT)},         /* vout1_d20.vout1_d20 */
+         {VOUT1_D21, (M0 | PIN_OUTPUT)},         /* vout1_d21.vout1_d21 */
+         {VOUT1_D22, (M0 | PIN_OUTPUT)},         /* vout1_d22.vout1_d22 */
+         {VOUT1_D23, (M0 | PIN_OUTPUT)},         /* vout1_d23.vout1_d23 */
+
+        {WAKEUP0, (M0 | PULL_UP)},      /* Wakeup0.Wakeup0 */
+        {WAKEUP1, (M0)},        /* Wakeup1.Wakeup1 */
+        {WAKEUP2, (M0)},        /* Wakeup2.Wakeup2 */
+        {WAKEUP3, (M0 | PULL_UP)},      /* Wakeup3.Wakeup3 */
+
+        {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)},  /* usb1_drvvbus.usb1_drvvbus */
+        {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)},  /* usb2_drvvbus.usb2_drvvbus */
+#endif
 };
 
 const struct pad_conf_entry core_padconf_array_essential_am572x_idk[] = {
diff --git a/common/board_f.c b/common/board_f.c
index 73a0a60..3d543f3 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -242,7 +242,7 @@ static int init_func_i2c(void)
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 	puts("ready\n");
-	return 0;
+ 	return 0;
 }
 #endif
 
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index 43c3fb6..c6f1e6c 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -31,6 +31,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define CONFIG_SYS_MEMTEST_SCRATCH 0
 #endif
 
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END   0xB0000000
+
 static int mod_mem(cmd_tbl_t *, int, int, int, char * const []);
 
 /* Display values from last command.
@@ -707,7 +710,7 @@ static int do_mem_loopw(cmd_tbl_t *cmdtp, int flag, int argc,
 }
 #endif /* CONFIG_LOOPW */
 
-#ifdef CONFIG_CMD_MEMTEST
+//#ifdef CONFIG_CMD_MEMTEST
 static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr,
 			  vu_long *dummy)
 {
@@ -1087,7 +1090,7 @@ static int do_mem_mtest(cmd_tbl_t *cmdtp, int flag, int argc,
 
 	return ret;
 }
-#endif	/* CONFIG_CMD_MEMTEST */
+//#endif	/* CONFIG_CMD_MEMTEST */
 
 /* Modify memory.
  *
@@ -1369,13 +1372,13 @@ U_BOOT_CMD(
 );
 #endif /* CONFIG_LOOPW */
 
-#ifdef CONFIG_CMD_MEMTEST
+//#ifdef CONFIG_CMD_MEMTEST
 U_BOOT_CMD(
 	mtest,	5,	1,	do_mem_mtest,
 	"simple RAM read/write test",
 	"[start [end [pattern [iterations]]]]"
 );
-#endif	/* CONFIG_CMD_MEMTEST */
+//#endif	/* CONFIG_CMD_MEMTEST */
 
 #ifdef CONFIG_MX_CYCLIC
 U_BOOT_CMD(
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
index 1335e3d..013467c 100644
--- a/common/cmd_mmc.c
+++ b/common/cmd_mmc.c
@@ -161,7 +161,7 @@ static int do_mmcinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	if (curr_device < 0) {
 		if (get_mmc_num() > 0)
-			curr_device = 0;
+		curr_device = 0;
 		else {
 			puts("No MMC device available\n");
 			return 1;
@@ -169,6 +169,7 @@ static int do_mmcinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	}
 
 	mmc = init_mmc_device(curr_device, false);
+
 	if (!mmc)
 		return CMD_RET_FAILURE;
 
diff --git a/common/memsize.c b/common/memsize.c
index 0fb9ba5..4236dcf 100644
--- a/common/memsize.c
+++ b/common/memsize.c
@@ -32,7 +32,7 @@ long get_ram_size(long *base, long maxsize)
 	long           val;
 	long           size;
 	int            i = 0;
-
+debug("\n max size is %x",maxsize);
 	for (cnt = (maxsize / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
 		addr = base + cnt;	/* pointer arith! */
 		sync();
@@ -51,15 +51,18 @@ long get_ram_size(long *base, long maxsize)
 	if ((val = *addr) != 0) {
 		/* Restore the original data before leaving the function. */
 		sync();
+debug("\n Expected value = %x and Read Value = %x",val,*addr);
 		*addr = save[i];
 		for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) {
 			addr  = base + cnt;
 			sync();
 			*addr = save[--i];
 		}
+debug("\n return 0");
 		return (0);
 	}
 
+
 	for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) {
 		addr = base + cnt;	/* pointer arith! */
 		val = *addr;
@@ -70,6 +73,7 @@ long get_ram_size(long *base, long maxsize)
 			 * Restore the original data
 			 * before leaving the function.
 			 */
+debug("\n Expected value = %ld and Read Value = %ld",~cnt,val);
 			for (cnt <<= 1;
 			     cnt < maxsize / sizeof(long);
 			     cnt <<= 1) {
diff --git a/common/spl/spl.c b/common/spl/spl.c
index aeb0645..3b48f9d 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -188,7 +188,9 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 #endif
 
 #ifdef CONFIG_SPL_BOARD_INIT
+debug("\n spl board init start ");
 	spl_board_init();
+debug("\n spl board init ");
 #endif
 
 	boot_device = spl_boot_device();
@@ -203,6 +205,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 	case BOOT_DEVICE_MMC1:
 	case BOOT_DEVICE_MMC2:
 	case BOOT_DEVICE_MMC2_2:
+debug("\n CONFIG_SPL_MMC_SUPPORT = %d",BOOT_DEVICE_MMC1);
 		spl_mmc_load_image();
 		break;
 #endif
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 552f80d..694ebb4 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -99,26 +99,32 @@ void spl_mmc_load_image(void)
 	int err;
 	__maybe_unused int part;
 
+	debug("\n Entered spl_mmc_load_image %d" ,gd->bd);
 	mmc_initialize(gd->bd);
-
+    	debug("\n Searching mmc device ");
 	/* We register only one device. So, the dev id is always 0 */
 	mmc = find_mmc_device(0);
+        debug("mmc - %d\n", mmc);
 	if (!mmc) {
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
 		puts("spl: mmc device not found\n");
 #endif
+puts("spl: mmc hang\n");
 		hang();
 	}
 
 	err = mmc_init(mmc);
+        debug("err - %d\n", err);
 	if (err) {
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
 		printf("spl: mmc init failed with error: %d\n", err);
 #endif
+puts("spl: err hang\n");
 		hang();
 	}
 
 	boot_mode = spl_boot_mode();
+        debug("boot_mode - %d %d \n", boot_mode,MMCSD_MODE_RAW);
 	switch (boot_mode) {
 	case MMCSD_MODE_RAW:
 		debug("spl: mmc boot mode: raw\n");
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 3b3c027..43b49ac 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -2,7 +2,10 @@ CONFIG_ARM=y
 CONFIG_OMAP54XX=y
 CONFIG_TARGET_BEAGLE_X15=y
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3"
+#CONFIG_NAND=y
+#CONFIG_CMD_NAND=y
+CONFIG_MTD_DEVICE=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 79a5c94..1da7fb2 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -347,7 +347,7 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 	struct i2c *i2c_base = omap24_get_base(adap);
 	int i2c_error = 0;
 	u16 status;
-
+printf("alen == %d \n",alen);
 	if (alen < 0) {
 		puts("I2C read: addr len < 0\n");
 		return 1;
@@ -446,6 +446,7 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 			goto rd_exit;
 		}
 		if (status == 0 || (status & I2C_STAT_NACK)) {
+		printf("i2c_read (data phase): I2C_STAT_NACK");
 			i2c_error = 1;
 			goto rd_exit;
 		}
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 79e6fee..e734f75 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1743,16 +1743,29 @@ static void do_preinit(void)
 {
 	struct mmc *m;
 	struct list_head *entry;
-
+ debug("\n Entered do_preinit");
 	list_for_each(entry, &mmc_devices) {
+ debug("\n List Entry");
 		m = list_entry(entry, struct mmc, link);
 
 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
+ debug("\n CONFIG_FSL_ESDHC_ADAPTER_IDENT");
 		mmc_set_preinit(m, 1);
 #endif
+ debug("\n m->preinit = %d",m->preinit);
+debug("\n List Exit");
 		if (m->preinit)
-			mmc_start_init(m);
+		{
+		    debug("\n mmc_start_init");	
+		   mmc_start_init(m);
+		}
+		else
+		{
+		  debug("\n No mmc_start_init");	
+		}
+		
 	}
+ debug("\n Exit do_preinit");
 }
 
 
@@ -1761,8 +1774,10 @@ int mmc_initialize(bd_t *bis)
 	INIT_LIST_HEAD (&mmc_devices);
 	cur_dev_num = 0;
 
-	if (board_mmc_init(bis) < 0)
-		cpu_mmc_init(bis);
+	if (board_mmc_init(bis) < 0) 
+          cpu_mmc_init(bis);
+
+
 
 #ifndef CONFIG_SPL_BUILD
 	print_mmc_devices(',');
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index 8c8cc6c..380400a 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -115,7 +115,7 @@ static void omap5_pbias_config(struct mmc *mmc)
 	value &= ~SDCARD_BIAS_PWRDNZ;
 	writel(value, (*ctrl)->control_pbias);
 
-	palmas_mmc1_poweron_ldo();
+	//palmas_mmc1_poweron_ldo();
 
 	value = readl((*ctrl)->control_pbias);
 	value |= SDCARD_BIAS_PWRDNZ;
@@ -648,15 +648,21 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 	struct omap_hsmmc_data *priv_data;
 	struct mmc_config *cfg;
 	uint host_caps_val;
-
+	debug("\n Entered omap_mmc_init ");
+	debug("\nSize required %d ",sizeof(*priv_data));
 	priv_data = malloc(sizeof(*priv_data));
 	if (priv_data == NULL)
-		return -1;
-
+	{
+	   debug("\n No Sufficient Memory for priv_data ");
+	   return -1;
+	}
+		
+debug("\n Sufficient Memory for priv_data ");
 	host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
 
 	switch (dev_index) {
 	case 0:
+debug("\n OMAP_HSMMC1_BASE ");
 		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
 		break;
 #ifdef OMAP_HSMMC2_BASE
@@ -722,8 +728,11 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 		cfg->b_max = 1;
 #endif
 	mmc = mmc_create(cfg, priv_data);
+	
 	if (mmc == NULL)
 		return -1;
+debug("\n mmc1 device created ");
+
 
 	return 0;
 }
diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
index 4cf4c1c..adb8e9c 100644
--- a/drivers/mtd/nand/nand.c
+++ b/drivers/mtd/nand/nand.c
@@ -63,9 +63,10 @@ int nand_register(int devnum)
 	 * Add MTD device so that we can reference it later
 	 * via the mtdcore infrastructure (e.g. ubi).
 	 */
+puts("MTD device added");
 	add_mtd_device(mtd);
 #endif
-
+add_mtd_device(mtd);
 	total_nand_size += mtd->size / 1024;
 
 	if (nand_curr_device == -1)
@@ -87,13 +88,13 @@ static void nand_init_chip(int i)
 
 	mtd->priv = nand;
 	nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
-
+	puts("\n Initalising NAND Memory");
 	if (board_nand_init(nand))
 		return;
-
+	puts("\n Scanning NAND Memory");
 	if (nand_scan(mtd, maxchips))
 		return;
-
+	puts("\n Registering NAND Memory");
 	nand_register(i);
 }
 #endif
diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index 427ad3e..2b260a1 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -308,8 +308,9 @@ static int gen_get_link_speed(int phy_addr)
 
 	if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) &&
 			(tmp & 0x04)) {
-#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
-		defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+/*#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
+		defined(CONFIG_MACH_DAVINCI_DA850_EVM)*/
+#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII)
 		davinci_eth_phy_read(phy_addr, MII_LPA, &tmp);
 
 		/* Speed doesn't matter, there is no setting for it in EMAC. */
@@ -444,8 +445,9 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
 	}
 #endif
 
-#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
-	defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+/*#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
+	defined(CONFIG_MACH_DAVINCI_DA850_EVM)*/
+#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII)
 	adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
 	adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
 	adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
@@ -507,8 +509,9 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
 	writel(1, &adap_emac->RXUNICASTSET);
 
 	/* Enable MII interface and Full duplex mode */
-#if defined(CONFIG_SOC_DA8XX) || \
-	(defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII))
+/*#if defined(CONFIG_SOC_DA8XX) || \
+	(defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII))*/
+#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII)
 	writel((EMAC_MACCONTROL_MIIEN_ENABLE |
 		EMAC_MACCONTROL_FULLDUPLEX_ENABLE |
 		EMAC_MACCONTROL_RMIISPEED_100),
@@ -608,8 +611,9 @@ static void davinci_eth_close(struct eth_device *dev)
 	writel(0, &adap_ewrap->EWCTL);
 #endif
 
-#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
-	defined(CONFIG_MACH_DAVINCI_DA850_EVM)
+/*#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
+	defined(CONFIG_MACH_DAVINCI_DA850_EVM)*/
+#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII)
 	adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
 	adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
 	adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
@@ -884,9 +888,10 @@ int davinci_emac_initialize(void)
 						davinci_mii_phy_write);
 	}
 
-#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
+/*#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
 		defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \
-			!defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE)
+			!defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE)*/
+#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII)
 	for (i = 0; i < num_phy; i++) {
 		if (phy[i].is_phy_connected(i))
 			phy[i].auto_negotiate(i);
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index c6c7806..598bf90 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -171,8 +171,12 @@ int genphy_config_aneg(struct phy_device *phydev)
 	int result;
 
 	if (AUTONEG_ENABLE != phydev->autoneg)
-		return genphy_setup_forced(phydev);
+	{
+                printf("\n **********Auto Negotiation Not Available******");
+		return genphy_setup_forced(phydev);	
+	}
 
+        printf("\n **********Auto Negotiation Available******");
 	result = genphy_config_advert(phydev);
 
 	if (result < 0) /* error */
@@ -663,6 +667,7 @@ static struct phy_device *get_phy_device_by_mask(struct mii_dev *bus,
 		return phydev;
 	/* Try Standard (ie Clause 22) access */
 	/* Otherwise we have to try Clause 45 */
+
 	for (i = 0; i < 5; i++) {
 		phydev = create_phy_by_mask(bus, phy_mask,
 				i ? i : MDIO_DEVAD_NONE, interface);
diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c
deleted file mode 100644
index 6430fe0..0000000
--- a/drivers/power/palmas.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * (C) Copyright 2012-2013
- * Texas Instruments, <www.ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <config.h>
-#include <palmas.h>
-
-void palmas_init_settings(void)
-{
-#ifdef CONFIG_PALMAS_SMPS7_FPWM
-	int err;
-	/*
-	 * Set SMPS7 (1.8 V I/O supply on platforms with TWL6035/37) to
-	 * forced PWM mode. This reduces noise (but affects efficiency).
-	 */
-	u8 val = SMPS_MODE_SLP_FPWM | SMPS_MODE_ACT_FPWM;
-	err = palmas_i2c_write_u8(TWL603X_CHIP_P1, SMPS7_CTRL, val);
-	if (err)
-		printf("palmas: could not force PWM for SMPS7: err = %d\n",
-		       err);
-#endif
-}
-
-int palmas_mmc1_poweron_ldo(void)
-{
-	u8 val = 0;
-
-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
-	/*
-	 * Currently valid for the dra7xx_evm board:
-	 * Set TPS659038 LDO1 to 3.0 V
-	 */
-	val = LDO_VOLT_3V0;
-	if (palmas_i2c_write_u8(TPS65903X_CHIP_P1, LDO1_VOLTAGE, val)) {
-		printf("tps65903x: could not set LDO1 voltage.\n");
-		return 1;
-	}
-	/* TURN ON LDO1 */
-	val = RSC_MODE_SLEEP | RSC_MODE_ACTIVE;
-	if (palmas_i2c_write_u8(TPS65903X_CHIP_P1, LDO1_CTRL, val)) {
-		printf("tps65903x: could not turn on LDO1.\n");
-		return 1;
-	}
-	return 0;
-#else
-	/*
-	 * We assume that this is a OMAP543X + TWL603X board:
-	 * Set TWL6035/37 LDO9 to 3.0 V
-	 */
-	val = LDO_VOLT_3V0;
-	return twl603x_mmc1_set_ldo9(val);
-#endif
-}
-
-/*
- * On some OMAP5 + TWL603X hardware the SD card socket and LDO9_IN are
- * powered by an external 3.3 V regulator, while the output of LDO9
- * supplies VDDS_SDCARD for the OMAP5 interface only. This implies that
- * LDO9 could be set to 'bypass' mode when required (e.g. for 3.3 V cards).
- */
-int twl603x_mmc1_set_ldo9(u8 vsel)
-{
-	u8 cval = 0, vval = 0;	/* Off by default */
-	int err;
-
-	if (vsel) {
-		/* Turn on */
-		if (vsel > LDO_VOLT_3V3) {
-			/* Put LDO9 in bypass */
-			cval = LDO9_BYP_EN | RSC_MODE_SLEEP | RSC_MODE_ACTIVE;
-			vval = LDO_VOLT_3V3;
-		} else {
-			cval = RSC_MODE_SLEEP | RSC_MODE_ACTIVE;
-			vval = vsel & 0x3f;
-		}
-	}
-	err = palmas_i2c_write_u8(TWL603X_CHIP_P1, LDO9_VOLTAGE, vval);
-	if (err) {
-		printf("twl603x: could not set LDO9 %s: err = %d\n",
-		       vsel > LDO_VOLT_3V3 ? "bypass" : "voltage", err);
-		return err;
-	}
-	err = palmas_i2c_write_u8(TWL603X_CHIP_P1, LDO9_CTRL, cval);
-	if (err)
-		printf("twl603x: could not turn %s LDO9: err = %d\n",
-		       cval ? "on" : "off", err);
-	return err;
-}
-
-#ifdef CONFIG_PALMAS_AUDPWR
-/*
- * Turn audio codec power and 32 kHz clock on/off. Use for
- * testing OMAP543X + TWL603X + TWL604X boards only.
- */
-int twl603x_audio_power(u8 on)
-{
-	u8 cval = 0, vval = 0, c32k = 0;
-	int err;
-
-	if (on) {
-		vval = SMPS_VOLT_2V1;
-		cval = SMPS_MODE_SLP_AUTO | SMPS_MODE_ACT_AUTO;
-		c32k = RSC_MODE_SLEEP | RSC_MODE_ACTIVE;
-	}
-	/* Set SMPS9 to 2.1 V (for TWL604x), or to 0 (off) */
-	err = palmas_i2c_write_u8(TWL603X_CHIP_P1, SMPS9_VOLTAGE, vval);
-	if (err) {
-		printf("twl603x: could not set SMPS9 voltage: err = %d\n",
-		       err);
-		return err;
-	}
-	/* Turn on or off SMPS9 */
-	err = palmas_i2c_write_u8(TWL603X_CHIP_P1, SMPS9_CTRL, cval);
-	if (err) {
-		printf("twl603x: could not turn SMPS9 %s: err = %d\n",
-		       cval ? "on" : "off", err);
-		return err;
-	}
-	/* Output 32 kHz clock on or off */
-	err = palmas_i2c_write_u8(TWL603X_CHIP_P1, CLK32KGAUDIO_CTRL, c32k);
-	if (err)
-		printf("twl603x: could not turn CLK32KGAUDIO %s: err = %d\n",
-		       c32k ? "on" : "off", err);
-	return err;
-}
-#endif
-
-#ifdef CONFIG_PALMAS_USB_SS_PWR
-/**
- * @brief palmas_enable_ss_ldo - Configure EVM board specific configurations
- * for the USB Super speed SMPS10 regulator.
- *
- * @return 0
- */
-int palmas_enable_ss_ldo(void)
-{
-	/* Enable smps10 regulator  */
-	return palmas_i2c_write_u8(TWL603X_CHIP_P1, SMPS10_CTRL,
-				SMPS10_MODE_ACTIVE_D);
-}
-#endif
-
-/*
- * Enable/disable back-up battery (or super cap) charging on TWL6035/37.
- * Please use defined BB_xxx values.
- */
-int twl603x_enable_bb_charge(u8 bb_fields)
-{
-	u8 val = bb_fields & 0x0f;
-	int err;
-
-	val |= (VRTC_EN_SLP | VRTC_EN_OFF | VRTC_PWEN);
-	err = palmas_i2c_write_u8(TWL603X_CHIP_P1, BB_VRTC_CTRL, val);
-	if (err)
-		printf("twl603x: could not set BB_VRTC_CTRL to 0x%02x: err = %d\n",
-		       val, err);
-	return err;
-}
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index cab5465..22d4190 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -1835,7 +1835,7 @@ long int read_allocated_block(struct ext2_inode *inode, int fileblock)
 		blknr = __le32_to_cpu(ext4fs_indir3_block
 				      [rblock % perblock_child]);
 	}
-	debug("read_allocated_block %ld\n", blknr);
+	//debug("read_allocated_block %ld\n", blknr);
 
 	return blknr;
 }
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index bccc3e3..08b7d7c 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -184,8 +184,8 @@ static __u32 get_fatent(fsdata *mydata, __u32 entry)
 		return ret;
 	}
 
-	debug("FAT%d: entry: 0x%04x = %d, offset: 0x%04x = %d\n",
-	       mydata->fatsize, entry, entry, offset, offset);
+	/*debug("FAT%d: entry: 0x%04x = %d, offset: 0x%04x = %d\n",
+	       mydata->fatsize, entry, entry, offset, offset);*/
 
 	/* Read a new block of FAT entries into the cache. */
 	if (bufnum != mydata->fatbufnum) {
@@ -245,8 +245,8 @@ static __u32 get_fatent(fsdata *mydata, __u32 entry)
 		}
 		break;
 	}
-	debug("FAT%d: ret: %08x, offset: %04x\n",
-	       mydata->fatsize, ret, offset);
+	/*debug("FAT%d: ret: %08x, offset: %04x\n",
+	       mydata->fatsize, ret, offset);*/
 
 	return ret;
 }
@@ -877,7 +877,7 @@ int do_fat_read_at(const char *filename, loff_t pos, void *buffer,
 	if (vfat_enabled)
 		debug("VFAT Support enabled\n");
 
-	debug("FAT%d, fat_sect: %d, fatlength: %d\n",
+	/*debug("FAT%d, fat_sect: %d, fatlength: %d\n",
 	       mydata->fatsize, mydata->fat_sect, mydata->fatlength);
 	debug("Rootdir begins at cluster: %d, sector: %d, offset: %x\n"
 	       "Data begins at: %d\n",
@@ -885,7 +885,7 @@ int do_fat_read_at(const char *filename, loff_t pos, void *buffer,
 	       mydata->rootdir_sect,
 	       mydata->rootdir_sect * mydata->sect_size, mydata->data_begin);
 	debug("Sector size: %d, cluster size: %d\n", mydata->sect_size,
-	      mydata->clust_size);
+	      mydata->clust_size);*/
 
 	/* "cwd" is always the root... */
 	while (ISDIRDELIM(*filename))
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index e330680..c1c1e98 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -13,22 +13,104 @@
 #define __CONFIG_AM57XX_EVM_H
 
 #define CONFIG_AM57XX
-
+#ifndef CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE		0x8000000
+#endif
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_MAX_CHIPS       1
+#define CONFIG_MTD_DEVICE		/* Required for mtdparts */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_BCH
+#define CONFIG_CMD_SPL_NAND_OFS		0x00080000 /* os-boot params*/
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000 /* kernel offset */
+#define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
+
+
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_MTD_SUPPORT
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_IODELAY_RECALIBRATION
 #endif
 
+/* NAND support */
+/* NAND: device related configs */
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+/* NAND: driver related configs */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define MTDIDS_DEFAULT			"nand0=nand.0"
+#define MTDPARTS_DEFAULT		"mtdparts=nand.0:" \
+					"128k(NAND.SPL)," \
+					"128k(NAND.SPL.backup1)," \
+					"128k(NAND.SPL.backup2)," \
+					"128k(NAND.SPL.backup3)," \
+					"256k(NAND.u-boot-spl-os)," \
+					"1m(NAND.u-boot)," \
+					"128k(NAND.u-boot-env)," \
+					"128k(NAND.u-boot-env.backup1)," \
+					"8m(NAND.kernel)," \
+					"-(NAND.file-system)"
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x000c0000
+/* NAND: SPL related configs */
+#ifdef CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_AM33XX_BCH
+#endif
+/* NAND: SPL falcon mode configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_CMD_SPL_NAND_OFS		0x00080000 /* os-boot params*/
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000 /* kernel offset */
+#define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
+#endif
+ /* !CONFIG_NAND */
+
+
+
+
+
+
+
+
+
+
 #define CONFIG_BOARD_EARLY_INIT_F
 
 #define CONFIG_NR_DRAM_BANKS		2
+#if 0
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		1	/* SLOT2: eMMC(1) */
+#define CONFIG_ENV_SIZE			(128 << 10)
+#define CONFIG_ENV_OFFSET		0xE0000
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#endif
 
 #define CONFIG_ENV_SIZE			(64 << 10)
 #define CONFIG_ENV_IS_IN_FAT
 #define FAT_ENV_INTERFACE		"mmc"
-#define FAT_ENV_DEVICE_AND_PART		"0:1"
+#define FAT_ENV_DEVICE_AND_PART		"1:1"
 #define FAT_ENV_FILE			"uboot.env"
 
-#define CONSOLEDEV			"ttyO2"
+#define CONSOLEDEV			"ttyO0"
 #define CONFIG_SYS_NS16550_COM1		UART1_BASE	/* Base EVM has UART0 */
 #define CONFIG_SYS_NS16550_COM2		UART2_BASE	/* UART2 */
 #define CONFIG_SYS_NS16550_COM3		UART3_BASE	/* UART3 */
@@ -57,6 +139,7 @@
 #define CONFIG_NET_RETRY_COUNT		10
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_MII
+#define CONFIG_DRIVER_TI_EMAC_USE_RMII
 #define CONFIG_DRIVER_TI_CPSW		/* Driver for IP block */
 #define CONFIG_MII			/* Required in net/eth.c */
 #define CONFIG_PHY_GIGE			/* per-board part of CPSW */
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 6011cf8..59ef0df 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -281,6 +281,18 @@
 #define CONFIG_SPL_BOARD_INIT
 
 #ifdef CONFIG_NAND
+#define CONFIG_NAND_OMAP_GPMC
+#ifndef CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE		0x8000000
+#endif
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_CMD_NAND
+#define CONFIG_MTD_DEVICE		/* Required for mtdparts */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_BCH
+#define CONFIG_NAND_OMAP_ELM
+#define CONFIG_NAND_OMAP_ECCSCHEME
 #define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_NAND_BASE
 #define CONFIG_SPL_NAND_DRIVERS
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index d78b30f..84cd27d 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -147,7 +147,7 @@
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	DEFAULT_LINUX_BOOT_ENV \
 	DEFAULT_MMC_TI_ARGS \
-	"console=" CONSOLEDEV ",115200n8\0" \
+	"console=ttyO0,115200n8 root=PARTUUID=00000000-02 rw mem=512M rootfstype=ext4 rootwait\0" \
 	"fdtfile=undefined\0" \
 	"bootpart=0:2\0" \
 	"bootdir=/boot\0" \