diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index e3d6165..6d524eb 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -318,6 +318,7 @@
 				num-lanes = <1>;
 				linux,pci-domain = <0>;
 				ti,hwmods = "pcie1";
+				
 				phys = <&pcie1_phy>;
 				phy-names = "pcie-phy0";
 				interrupt-map-mask = <0 0 0 7>;
@@ -325,6 +326,7 @@
 						<0 0 0 2 &pcie1_intc 2>,
 						<0 0 0 3 &pcie1_intc 3>,
 						<0 0 0 4 &pcie1_intc 4>;
+        			ti,syscon-unaligned-access = <&scm_conf1 0x14 3>;
 				status = "disabled";
 				pcie1_intc: interrupt-controller {
 					interrupt-controller;
@@ -342,9 +344,10 @@
 				num-ib-windows = <4>;
 				num-ob-windows = <16>;
 				ti,hwmods = "pcie1";
+                                
 				phys = <&pcie1_phy>;
 				phy-names = "pcie-phy0";
-				syscon-legacy-mode = <&scm_conf1 0x14 2>;
+				ti,syscon-unaligned-access = <&scm_conf1 0x14 3>;
 				status = "disabled";
 			};
 		};
@@ -355,8 +358,9 @@
 			#address-cells = <1>;
 			ranges = <0x51800000 0x51800000 0x3000
 				  0x0	     0x30000000 0x10000000>;
-			status = "disabled";
-			pcie@51800000 {
+/*			status = "disabled"; */
+/*			pcie@51800000 { */
+			pcie2_rc: pcie@51800000 { 
 				compatible = "ti,dra7-pcie";
 				reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
 				reg-names = "rc_dbics", "ti_conf", "config";
@@ -377,6 +381,7 @@
 						<0 0 0 2 &pcie2_intc 2>,
 						<0 0 0 3 &pcie2_intc 3>,
 						<0 0 0 4 &pcie2_intc 4>;
+        			ti,syscon-unaligned-access = <&scm_conf1 0x14 3>;
 				pcie2_intc: interrupt-controller {
 					interrupt-controller;
 					#address-cells = <0>;
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index defa272..cb37129 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -238,8 +238,8 @@ static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
 		dev_err(dev, "No PCIe Intc node found\n");
 		return -ENODEV;
 	}
-
-	dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
+        // PCI interrupt lines start at 1 not zero so need to add 1
+	dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, 4 + 1,
 						   &intx_domain_ops, pp);
 	if (!dra7xx->irq_domain) {
 		dev_err(dev, "Failed to get a INTx IRQ domain\n");
@@ -255,12 +255,29 @@ static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
 	struct dw_pcie *pci = dra7xx->pci;
 	struct pcie_port *pp = &pci->pp;
 	u32 reg;
+	int count = 0;
 
 	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
+	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
 
 	switch (reg) {
 	case MSI:
-		dw_handle_msi_irq(pp);
+		/*
+		 * Need to make sure no MSI IRQs are pending before
+		 * exiting handler, else the wrapper will not catch new
+		 * IRQs. So loop around till dw_handle_msi_irq() returns
+		 * IRQ_NONE
+		 */
+		while (dw_handle_msi_irq(pp) != IRQ_NONE && count < 1000)
+			count++;
+
+		if (count == 1000) {
+			dev_err(pci->dev, "too much work in msi irq\n");
+			dra7xx_pcie_writel(dra7xx,
+					   PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
+					   reg);
+			return IRQ_HANDLED;
+		}
 		break;
 	case INTA:
 	case INTB:
@@ -271,8 +288,6 @@ static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
 		break;
 	}
 
-	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
-
 	return IRQ_HANDLED;
 }
 
@@ -548,7 +563,7 @@ static const struct of_device_id of_dra7xx_pcie_match[] = {
 };
 
 /*
- * dra7xx_pcie_ep_legacy_mode: workaround for AM572x/AM571x Errata i870
+ * dra7xx_pcie_unaligned_memaccess: workaround for AM572x/AM571x Errata i870
  * @dra7xx: the dra7xx device where the workaround should be applied
  *
  * Access to the PCIe slave port that are not 32-bit aligned will result
@@ -558,7 +573,7 @@ static const struct of_device_id of_dra7xx_pcie_match[] = {
  *
  * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
  */
-static int dra7xx_pcie_ep_legacy_mode(struct device *dev)
+static int dra7xx_pcie_unaligned_memaccess(struct device *dev)
 {
 	int ret;
 	struct device_node *np = dev->of_node;
@@ -566,25 +581,25 @@ static int dra7xx_pcie_ep_legacy_mode(struct device *dev)
 	unsigned int reg;
 	unsigned int field;
 
-	regmap = syscon_regmap_lookup_by_phandle(np, "syscon-legacy-mode");
+	regmap = syscon_regmap_lookup_by_phandle(np, "ti,syscon-unaligned-access");
 	if (IS_ERR(regmap)) {
-		dev_dbg(dev, "can't get syscon-legacy-mode\n");
+		dev_dbg(dev, "can't get syscon-unaligned-access\n");
 		return -EINVAL;
 	}
 
-	if (of_property_read_u32_index(np, "syscon-legacy-mode", 1, &reg)) {
-		dev_err(dev, "couldn't get legacy mode register offset\n");
+	if (of_property_read_u32_index(np, "ti,syscon-unaligned-access", 1, &reg)) {
+		dev_err(dev, "couldn't get unaligned access register offset\n");
 		return -EINVAL;
 	}
 
-	if (of_property_read_u32_index(np, "syscon-legacy-mode", 2, &field)) {
-		dev_err(dev, "can't get bit field for setting legacy mode\n");
+	if (of_property_read_u32_index(np, "ti,syscon-unaligned-access", 2, &field)) {
+		dev_err(dev, "can't get bit field for setting unaligned access mode\n");
 		return -EINVAL;
 	}
 
 	ret = regmap_update_bits(regmap, reg, field, field);
 	if (ret)
-		dev_err(dev, "failed to set legacy mode\n");
+		dev_err(dev, "failed to set unaligned access mode\n");
 
 	return ret;
 }
@@ -701,6 +716,11 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 	if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)
 		dra7xx->link_gen = 2;
 
+	// Errata i870 applies to RC as well as EP
+	ret = dra7xx_pcie_unaligned_memaccess(dev);
+	if (ret)
+		goto err_gpio;
+
 	switch (mode) {
 	case DW_PCIE_RC_TYPE:
 		dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
@@ -714,10 +734,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 		dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
 				   DEVICE_TYPE_EP);
 
-		ret = dra7xx_pcie_ep_legacy_mode(dev);
-		if (ret)
-			goto err_gpio;
-
 		ret = dra7xx_add_pcie_ep(dra7xx, pdev);
 		if (ret < 0)
 			goto err_gpio;
