/* This file was auto-generated by TI PinMux on 5/19/2017 at 5:21:57 PM. */ /* This file should only be used as a reference. Some pins/peripherals, */ /* depending on your use case, may need additional configuration. */ /* Some or all the pins from the following groups are not used by device tree vbat_adc1 ddr_emif1 thumb_usb1 */ ggb_mmc1_pins_default: ggb_mmc1_pins_default { pinctrl-single,pins = < 0x100 ( PIN_OUTPUT | MUX_MODE0 ) /* (G17) mmc0_clk.mmc0_clk */ 0x104 ( PIN_OUTPUT | MUX_MODE0 ) /* (G18) mmc0_cmd.mmc0_cmd */ 0xfc ( PIN_OUTPUT | MUX_MODE0 ) /* (G16) mmc0_dat0.mmc0_dat0 */ 0xf8 ( PIN_OUTPUT | MUX_MODE0 ) /* (G15) mmc0_dat1.mmc0_dat1 */ 0xf4 ( PIN_OUTPUT | MUX_MODE0 ) /* (F18) mmc0_dat2.mmc0_dat2 */ 0xf0 ( PIN_OUTPUT | MUX_MODE0 ) /* (F17) mmc0_dat3.mmc0_dat3 */ 0x138 ( PIN_OUTPUT | MUX_MODE3 ) /* (L16) gmii1_rxd2.mmc0_dat4 */ 0x134 ( PIN_OUTPUT | MUX_MODE3 ) /* (L17) gmii1_rxd3.mmc0_dat5 */ 0x130 ( PIN_OUTPUT | MUX_MODE3 ) /* (L18) gmii1_rxclk.mmc0_dat6 */ 0x12c ( PIN_OUTPUT | MUX_MODE3 ) /* (K18) gmii1_txclk.mmc0_dat7 */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ ggb_mmc1_pins_sleep: ggb_mmc1_pins_sleep { pinctrl-single,pins = < 0x100 ( ) /* (G17) mmc0_clk.mmc0_clk */ 0x104 ( ) /* (G18) mmc0_cmd.mmc0_cmd */ 0xfc ( ) /* (G16) mmc0_dat0.mmc0_dat0 */ 0xf8 ( ) /* (G15) mmc0_dat1.mmc0_dat1 */ 0xf4 ( ) /* (F18) mmc0_dat2.mmc0_dat2 */ 0xf0 ( ) /* (F17) mmc0_dat3.mmc0_dat3 */ 0x138 ( ) /* (L16) gmii1_rxd2.mmc0_dat4 */ 0x134 ( ) /* (L17) gmii1_rxd3.mmc0_dat5 */ 0x130 ( ) /* (L18) gmii1_rxclk.mmc0_dat6 */ 0x12c ( ) /* (K18) gmii1_txclk.mmc0_dat7 */ >; }; nand_gpmc1_pins_default: nand_gpmc1_pins_default { pinctrl-single,pins = < 0x1c ( PIN_OUTPUT | MUX_MODE0 ) /* (T9) gpmc_ad7.gpmc_ad7 */ 0x18 ( PIN_OUTPUT | MUX_MODE0 ) /* (R9) gpmc_ad6.gpmc_ad6 */ 0x14 ( PIN_OUTPUT | MUX_MODE0 ) /* (V8) gpmc_ad5.gpmc_ad5 */ 0x10 ( PIN_OUTPUT | MUX_MODE0 ) /* (U8) gpmc_ad4.gpmc_ad4 */ 0xc ( PIN_OUTPUT | MUX_MODE0 ) /* (T8) gpmc_ad3.gpmc_ad3 */ 0x8 ( PIN_OUTPUT | MUX_MODE0 ) /* (R8) gpmc_ad2.gpmc_ad2 */ 0x4 ( PIN_OUTPUT | MUX_MODE0 ) /* (V7) gpmc_ad1.gpmc_ad1 */ 0x0 ( PIN_OUTPUT | MUX_MODE0 ) /* (U7) gpmc_ad0.gpmc_ad0 */ 0x8c ( PIN_INPUT | MUX_MODE2 ) /* (V12) gpmc_clk.gpmc_wait1 */ 0x90 ( PIN_OUTPUT | MUX_MODE0 ) /* (R7) gpmc_advn_ale.gpmc_advn_ale */ 0x94 ( PIN_OUTPUT | MUX_MODE0 ) /* (T7) gpmc_oen_ren.gpmc_oen_ren */ 0x98 ( PIN_OUTPUT | MUX_MODE0 ) /* (U6) gpmc_wen.gpmc_wen */ 0x9c ( PIN_OUTPUT | MUX_MODE0 ) /* (T6) gpmc_be0n_cle.gpmc_be0n_cle */ 0x7c ( PIN_OUTPUT | MUX_MODE0 ) /* (V6) gpmc_csn0.gpmc_csn0 */ 0x80 ( PIN_OUTPUT | MUX_MODE0 ) /* (U9) gpmc_csn1.gpmc_csn1 */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ nand_gpmc1_pins_sleep: nand_gpmc1_pins_sleep { pinctrl-single,pins = < 0x1c ( ) /* (T9) gpmc_ad7.gpmc_ad7 */ 0x18 ( ) /* (R9) gpmc_ad6.gpmc_ad6 */ 0x14 ( ) /* (V8) gpmc_ad5.gpmc_ad5 */ 0x10 ( ) /* (U8) gpmc_ad4.gpmc_ad4 */ 0xc ( ) /* (T8) gpmc_ad3.gpmc_ad3 */ 0x8 ( ) /* (R8) gpmc_ad2.gpmc_ad2 */ 0x4 ( ) /* (V7) gpmc_ad1.gpmc_ad1 */ 0x0 ( ) /* (U7) gpmc_ad0.gpmc_ad0 */ 0x8c ( ) /* (V12) gpmc_clk.gpmc_wait1 */ 0x90 ( ) /* (R7) gpmc_advn_ale.gpmc_advn_ale */ 0x94 ( ) /* (T7) gpmc_oen_ren.gpmc_oen_ren */ 0x98 ( ) /* (U6) gpmc_wen.gpmc_wen */ 0x9c ( ) /* (T6) gpmc_be0n_cle.gpmc_be0n_cle */ 0x7c ( ) /* (V6) gpmc_csn0.gpmc_csn0 */ 0x80 ( ) /* (U9) gpmc_csn1.gpmc_csn1 */ >; }; main_board_uart1_pins_default: main_board_uart1_pins_default { pinctrl-single,pins = < 0x170 ( PIN_INPUT | MUX_MODE0 ) /* (E15) uart0_rxd.uart0_rxd */ 0x174 ( PIN_OUTPUT | MUX_MODE0 ) /* (E16) uart0_txd.uart0_txd */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ main_board_uart1_pins_sleep: main_board_uart1_pins_sleep { pinctrl-single,pins = < 0x170 ( ) /* (E15) uart0_rxd.uart0_rxd */ 0x174 ( ) /* (E16) uart0_txd.uart0_txd */ >; }; eth_mdio1_pins_default: eth_mdio1_pins_default { pinctrl-single,pins = < 0x14c ( PIN_OUTPUT | MUX_MODE0 ) /* (M18) mdio_clk.mdio_clk */ 0x148 ( PIN_INPUT | MUX_MODE0 ) /* (M17) mdio_data.mdio_data */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ eth_mdio1_pins_sleep: eth_mdio1_pins_sleep { pinctrl-single,pins = < 0x14c ( ) /* (M18) mdio_clk.mdio_clk */ 0x148 ( ) /* (M17) mdio_data.mdio_data */ >; }; rtc_spi1_pins_default: rtc_spi1_pins_default { pinctrl-single,pins = < 0x190 ( PIN_OUTPUT | MUX_MODE3 ) /* (A13) mcasp0_aclkx.spi1_sclk */ 0x194 ( PIN_INPUT | MUX_MODE3 ) /* (B13) mcasp0_fsx.spi1_d0 */ 0x198 ( PIN_OUTPUT | MUX_MODE3 ) /* (D12) mcasp0_axr0.spi1_d1 */ 0x19c ( PIN_OUTPUT | MUX_MODE3 ) /* (C12) mcasp0_ahclkr.spi1_cs0 */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ rtc_spi1_pins_sleep: rtc_spi1_pins_sleep { pinctrl-single,pins = < 0x190 ( ) /* (A13) mcasp0_aclkx.spi1_sclk */ 0x194 ( ) /* (B13) mcasp0_fsx.spi1_d0 */ 0x198 ( ) /* (D12) mcasp0_axr0.spi1_d1 */ 0x19c ( ) /* (C12) mcasp0_ahclkr.spi1_cs0 */ >; }; other_gpio1_pins_default: other_gpio1_pins_default { pinctrl-single,pins = < 0x88 ( PIN_OUTPUT | MUX_MODE7 ) /* (T13) gpmc_csn3.gpio2[0] */ 0x13c ( PIN_INPUT | MUX_MODE7 ) /* (L15) gmii1_rxd1.gpio2[20] */ 0x140 ( PIN_OUTPUT | MUX_MODE7 ) /* (M16) gmii1_rxd0.gpio2[21] */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ other_gpio1_pins_sleep: other_gpio1_pins_sleep { pinctrl-single,pins = < 0x88 ( ) /* (T13) gpmc_csn3.gpio2[0] */ 0x13c ( ) /* (L15) gmii1_rxd1.gpio2[20] */ 0x140 ( ) /* (M16) gmii1_rxd0.gpio2[21] */ >; }; other1_gpio2_pins_default: other1_gpio2_pins_default { pinctrl-single,pins = < 0x10c ( PIN_OUTPUT | MUX_MODE7 ) /* (H17) gmii1_crs.gpio3[1] */ 0x110 ( PIN_OUTPUT | MUX_MODE7 ) /* (J15) gmii1_rxer.gpio3[2] */ 0x114 ( PIN_OUTPUT | MUX_MODE7 ) /* (J16) gmii1_txen.gpio3[3] */ 0x1a0 ( PIN_INPUT | MUX_MODE7 ) /* (B12) mcasp0_aclkr.gpio3[18] */ 0x1a4 ( PIN_OUTPUT | MUX_MODE7 ) /* (C13) mcasp0_fsr.gpio3[19] */ 0x1a8 ( PIN_INPUT | MUX_MODE7 ) /* (D13) mcasp0_axr1.gpio3[20] */ 0x1ac ( PIN_OUTPUT | MUX_MODE7 ) /* (A14) mcasp0_ahclkx.gpio3[21] */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ other1_gpio2_pins_sleep: other1_gpio2_pins_sleep { pinctrl-single,pins = < 0x10c ( ) /* (H17) gmii1_crs.gpio3[1] */ 0x110 ( ) /* (J15) gmii1_rxer.gpio3[2] */ 0x114 ( ) /* (J16) gmii1_txen.gpio3[3] */ 0x1a0 ( ) /* (B12) mcasp0_aclkr.gpio3[18] */ 0x1a4 ( ) /* (C13) mcasp0_fsr.gpio3[19] */ 0x1a8 ( ) /* (D13) mcasp0_axr1.gpio3[20] */ 0x1ac ( ) /* (A14) mcasp0_ahclkx.gpio3[21] */ >; }; other3_gpio3_pins_default: other3_gpio3_pins_default { pinctrl-single,pins = < 0x150 ( PIN_INPUT | MUX_MODE7 ) /* (A17) spi0_sclk.gpio0[2] */ 0x154 ( PIN_INPUT | MUX_MODE7 ) /* (B17) spi0_d0.gpio0[3] */ 0x158 ( PIN_INPUT | MUX_MODE7 ) /* (B16) spi0_d1.gpio0[4] */ 0x15c ( PIN_INPUT | MUX_MODE7 ) /* (A16) spi0_cs0.gpio0[5] */ 0x180 ( PIN_INPUT | MUX_MODE7 ) /* (D16) uart1_rxd.gpio0[14] */ 0x184 ( PIN_INPUT | MUX_MODE7 ) /* (D15) uart1_txd.gpio0[15] */ 0x11c ( PIN_INPUT | MUX_MODE7 ) /* (J18) gmii1_txd3.gpio0[16] */ 0x120 ( PIN_INPUT | MUX_MODE7 ) /* (K15) gmii1_txd2.gpio0[17] */ 0x21c ( PIN_OUTPUT | MUX_MODE7 ) /* (F16) USB0_DRVVBUS.gpio0[18] */ 0x1b0 ( PIN_OUTPUT | MUX_MODE7 ) /* (A15) xdma_event_intr0.gpio0[19] */ 0x1b4 ( PIN_INPUT | MUX_MODE7 ) /* (D14) xdma_event_intr1.gpio0[20] */ 0x124 ( PIN_INPUT | MUX_MODE7 ) /* (K16) gmii1_txd1.gpio0[21] */ 0x128 ( PIN_OUTPUT | MUX_MODE7 ) /* (K17) gmii1_txd0.gpio0[28] */ 0x144 ( PIN_OUTPUT | MUX_MODE7 ) /* (H18) rmii1_refclk.gpio0[29] */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ other3_gpio3_pins_sleep: other3_gpio3_pins_sleep { pinctrl-single,pins = < 0x150 ( ) /* (A17) spi0_sclk.gpio0[2] */ 0x154 ( ) /* (B17) spi0_d0.gpio0[3] */ 0x158 ( ) /* (B16) spi0_d1.gpio0[4] */ 0x15c ( ) /* (A16) spi0_cs0.gpio0[5] */ 0x180 ( ) /* (D16) uart1_rxd.gpio0[14] */ 0x184 ( ) /* (D15) uart1_txd.gpio0[15] */ 0x11c ( ) /* (J18) gmii1_txd3.gpio0[16] */ 0x120 ( ) /* (K15) gmii1_txd2.gpio0[17] */ 0x21c ( ) /* (F16) USB0_DRVVBUS.gpio0[18] */ 0x1b0 ( ) /* (A15) xdma_event_intr0.gpio0[19] */ 0x1b4 ( ) /* (D14) xdma_event_intr1.gpio0[20] */ 0x124 ( ) /* (K16) gmii1_txd1.gpio0[21] */ 0x128 ( ) /* (K17) gmii1_txd0.gpio0[28] */ 0x144 ( ) /* (H18) rmii1_refclk.gpio0[29] */ >; }; myecap2_pins_default: myecap2_pins_default { pinctrl-single,pins = < 0x160 ( PIN_OUTPUT | MUX_MODE2 ) /* (C15) spi0_cs1.eCAP1_in_PWM1_out */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ myecap2_pins_sleep: myecap2_pins_sleep { pinctrl-single,pins = < 0x160 ( ) /* (C15) spi0_cs1.eCAP1_in_PWM1_out */ >; }; pmic_eeprom_i2c0_pins_default: pmic_eeprom_i2c0_pins_default { pinctrl-single,pins = < 0x18c ( PIN_OUTPUT | MUX_MODE0 ) /* (C16) I2C0_SCL.I2C0_SCL */ 0x188 ( PIN_OUTPUT | MUX_MODE0 ) /* (C17) I2C0_SDA.I2C0_SDA */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ pmic_eeprom_i2c0_pins_sleep: pmic_eeprom_i2c0_pins_sleep { pinctrl-single,pins = < 0x18c ( ) /* (C16) I2C0_SCL.I2C0_SCL */ 0x188 ( ) /* (C17) I2C0_SDA.I2C0_SDA */ >; }; touch_i2c2_pins_default: touch_i2c2_pins_default { pinctrl-single,pins = < 0x17c ( PIN_OUTPUT | MUX_MODE3 ) /* (D17) uart1_rtsn.I2C2_SCL */ 0x178 ( PIN_OUTPUT | MUX_MODE3 ) /* (D18) uart1_ctsn.I2C2_SDA */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ touch_i2c2_pins_sleep: touch_i2c2_pins_sleep { pinctrl-single,pins = < 0x17c ( ) /* (D17) uart1_rtsn.I2C2_SCL */ 0x178 ( ) /* (D18) uart1_ctsn.I2C2_SDA */ >; }; eth_mii1_pins_default: eth_mii1_pins_default { pinctrl-single,pins = < 0x78 ( PIN_INPUT | MUX_MODE1 ) /* (U18) gpmc_be1n.gmii2_col */ 0x70 ( PIN_INPUT | MUX_MODE1 ) /* (T17) gpmc_wait0.gmii2_crs */ 0x74 ( PIN_INPUT | MUX_MODE1 ) /* (U17) gpmc_wpn.gmii2_rxer */ 0x40 ( PIN_OUTPUT | MUX_MODE1 ) /* (R13) gpmc_a0.gmii2_txen */ 0x44 ( PIN_INPUT | MUX_MODE1 ) /* (V14) gpmc_a1.gmii2_rxdv */ 0x58 ( PIN_INPUT | MUX_MODE1 ) /* (U15) gpmc_a6.gmii2_txclk */ 0x5c ( PIN_INPUT | MUX_MODE1 ) /* (T15) gpmc_a7.gmii2_rxclk */ 0x54 ( PIN_OUTPUT | MUX_MODE1 ) /* (V15) gpmc_a5.gmii2_txd0 */ 0x50 ( PIN_OUTPUT | MUX_MODE1 ) /* (R14) gpmc_a4.gmii2_txd1 */ 0x4c ( PIN_OUTPUT | MUX_MODE1 ) /* (T14) gpmc_a3.gmii2_txd2 */ 0x48 ( PIN_OUTPUT | MUX_MODE1 ) /* (U14) gpmc_a2.gmii2_txd3 */ 0x6c ( PIN_INPUT | MUX_MODE1 ) /* (V17) gpmc_a11.gmii2_rxd0 */ 0x68 ( PIN_INPUT | MUX_MODE1 ) /* (T16) gpmc_a10.gmii2_rxd1 */ 0x64 ( PIN_INPUT | MUX_MODE1 ) /* (U16) gpmc_a9.gmii2_rxd2 */ 0x60 ( PIN_INPUT | MUX_MODE1 ) /* (V16) gpmc_a8.gmii2_rxd3 */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ eth_mii1_pins_sleep: eth_mii1_pins_sleep { pinctrl-single,pins = < 0x78 ( ) /* (U18) gpmc_be1n.gmii2_col */ 0x70 ( ) /* (T17) gpmc_wait0.gmii2_crs */ 0x74 ( ) /* (U17) gpmc_wpn.gmii2_rxer */ 0x40 ( ) /* (R13) gpmc_a0.gmii2_txen */ 0x44 ( ) /* (V14) gpmc_a1.gmii2_rxdv */ 0x58 ( ) /* (U15) gpmc_a6.gmii2_txclk */ 0x5c ( ) /* (T15) gpmc_a7.gmii2_rxclk */ 0x54 ( ) /* (V15) gpmc_a5.gmii2_txd0 */ 0x50 ( ) /* (R14) gpmc_a4.gmii2_txd1 */ 0x4c ( ) /* (T14) gpmc_a3.gmii2_txd2 */ 0x48 ( ) /* (U14) gpmc_a2.gmii2_txd3 */ 0x6c ( ) /* (V17) gpmc_a11.gmii2_rxd0 */ 0x68 ( ) /* (T16) gpmc_a10.gmii2_rxd1 */ 0x64 ( ) /* (U16) gpmc_a9.gmii2_rxd2 */ 0x60 ( ) /* (V16) gpmc_a8.gmii2_rxd3 */ >; }; thumb_usb1_pins_default: thumb_usb1_pins_default { pinctrl-single,pins = < 0x234 ( PIN_OUTPUT | MUX_MODE0 ) /* (F15) USB1_DRVVBUS.USB1_DRVVBUS */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ thumb_usb1_pins_sleep: thumb_usb1_pins_sleep { pinctrl-single,pins = < 0x234 ( ) /* (F15) USB1_DRVVBUS.USB1_DRVVBUS */ >; }; lcdc1_pins_default: lcdc1_pins_default { pinctrl-single,pins = < 0xe0 ( PIN_OUTPUT | MUX_MODE0 ) /* (U5) lcd_vsync.lcd_vsync */ 0xe4 ( PIN_OUTPUT | MUX_MODE0 ) /* (R5) lcd_hsync.lcd_hsync */ 0xe8 ( PIN_OUTPUT | MUX_MODE0 ) /* (V5) lcd_pclk.lcd_pclk */ 0xec ( PIN_OUTPUT | MUX_MODE0 ) /* (R6) lcd_ac_bias_en.lcd_ac_bias_en */ 0x118 ( PIN_OUTPUT | MUX_MODE1 ) /* (J17) gmii1_rxdv.lcd_memory_clk */ 0xa0 ( PIN_OUTPUT | MUX_MODE0 ) /* (R1) lcd_data0.lcd_data0 */ 0xa4 ( PIN_OUTPUT | MUX_MODE0 ) /* (R2) lcd_data1.lcd_data1 */ 0xa8 ( PIN_OUTPUT | MUX_MODE0 ) /* (R3) lcd_data2.lcd_data2 */ 0xac ( PIN_OUTPUT | MUX_MODE0 ) /* (R4) lcd_data3.lcd_data3 */ 0xb0 ( PIN_OUTPUT | MUX_MODE0 ) /* (T1) lcd_data4.lcd_data4 */ 0xb4 ( PIN_OUTPUT | MUX_MODE0 ) /* (T2) lcd_data5.lcd_data5 */ 0xb8 ( PIN_OUTPUT | MUX_MODE0 ) /* (T3) lcd_data6.lcd_data6 */ 0xbc ( PIN_OUTPUT | MUX_MODE0 ) /* (T4) lcd_data7.lcd_data7 */ 0xc0 ( PIN_OUTPUT | MUX_MODE0 ) /* (U1) lcd_data8.lcd_data8 */ 0xc4 ( PIN_OUTPUT | MUX_MODE0 ) /* (U2) lcd_data9.lcd_data9 */ 0xc8 ( PIN_OUTPUT | MUX_MODE0 ) /* (U3) lcd_data10.lcd_data10 */ 0xcc ( PIN_OUTPUT | MUX_MODE0 ) /* (U4) lcd_data11.lcd_data11 */ 0xd0 ( PIN_OUTPUT | MUX_MODE0 ) /* (V2) lcd_data12.lcd_data12 */ 0xd4 ( PIN_OUTPUT | MUX_MODE0 ) /* (V3) lcd_data13.lcd_data13 */ 0xd8 ( PIN_OUTPUT | MUX_MODE0 ) /* (V4) lcd_data14.lcd_data14 */ 0xdc ( PIN_OUTPUT | MUX_MODE0 ) /* (T5) lcd_data15.lcd_data15 */ 0x3c ( PIN_OUTPUT | MUX_MODE1 ) /* (U13) gpmc_ad15.lcd_data16 */ 0x38 ( PIN_OUTPUT | MUX_MODE1 ) /* (V13) gpmc_ad14.lcd_data17 */ 0x34 ( PIN_OUTPUT | MUX_MODE1 ) /* (R12) gpmc_ad13.lcd_data18 */ 0x30 ( PIN_OUTPUT | MUX_MODE1 ) /* (T12) gpmc_ad12.lcd_data19 */ 0x2c ( PIN_OUTPUT | MUX_MODE1 ) /* (U12) gpmc_ad11.lcd_data20 */ 0x28 ( PIN_OUTPUT | MUX_MODE1 ) /* (T11) gpmc_ad10.lcd_data21 */ 0x24 ( PIN_OUTPUT | MUX_MODE1 ) /* (T10) gpmc_ad9.lcd_data22 */ 0x20 ( PIN_OUTPUT | MUX_MODE1 ) /* (U10) gpmc_ad8.lcd_data23 */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ lcdc1_pins_sleep: lcdc1_pins_sleep { pinctrl-single,pins = < 0xe0 ( ) /* (U5) lcd_vsync.lcd_vsync */ 0xe4 ( ) /* (R5) lcd_hsync.lcd_hsync */ 0xe8 ( ) /* (V5) lcd_pclk.lcd_pclk */ 0xec ( ) /* (R6) lcd_ac_bias_en.lcd_ac_bias_en */ 0x118 ( ) /* (J17) gmii1_rxdv.lcd_memory_clk */ 0xa0 ( ) /* (R1) lcd_data0.lcd_data0 */ 0xa4 ( ) /* (R2) lcd_data1.lcd_data1 */ 0xa8 ( ) /* (R3) lcd_data2.lcd_data2 */ 0xac ( ) /* (R4) lcd_data3.lcd_data3 */ 0xb0 ( ) /* (T1) lcd_data4.lcd_data4 */ 0xb4 ( ) /* (T2) lcd_data5.lcd_data5 */ 0xb8 ( ) /* (T3) lcd_data6.lcd_data6 */ 0xbc ( ) /* (T4) lcd_data7.lcd_data7 */ 0xc0 ( ) /* (U1) lcd_data8.lcd_data8 */ 0xc4 ( ) /* (U2) lcd_data9.lcd_data9 */ 0xc8 ( ) /* (U3) lcd_data10.lcd_data10 */ 0xcc ( ) /* (U4) lcd_data11.lcd_data11 */ 0xd0 ( ) /* (V2) lcd_data12.lcd_data12 */ 0xd4 ( ) /* (V3) lcd_data13.lcd_data13 */ 0xd8 ( ) /* (V4) lcd_data14.lcd_data14 */ 0xdc ( ) /* (T5) lcd_data15.lcd_data15 */ 0x3c ( ) /* (U13) gpmc_ad15.lcd_data16 */ 0x38 ( ) /* (V13) gpmc_ad14.lcd_data17 */ 0x34 ( ) /* (R12) gpmc_ad13.lcd_data18 */ 0x30 ( ) /* (T12) gpmc_ad12.lcd_data19 */ 0x2c ( ) /* (U12) gpmc_ad11.lcd_data20 */ 0x28 ( ) /* (T11) gpmc_ad10.lcd_data21 */ 0x24 ( ) /* (T10) gpmc_ad9.lcd_data22 */ 0x20 ( ) /* (U10) gpmc_ad8.lcd_data23 */ >; }; eth_rmii1_pins_default: eth_rmii1_pins_default { pinctrl-single,pins = < 0x108 ( PIN_OUTPUT | MUX_MODE1 ) /* (H16) gmii1_col.rmii2_refclk */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ eth_rmii1_pins_sleep: eth_rmii1_pins_sleep { pinctrl-single,pins = < 0x108 ( ) /* (H16) gmii1_col.rmii2_refclk */ >; }; jtag_debugss1_pins_default: jtag_debugss1_pins_default { pinctrl-single,pins = < 0x1d0 ( PIN_INPUT | MUX_MODE0 ) /* (C11) TMS.TMS */ 0x1d4 ( PIN_INPUT | MUX_MODE0 ) /* (B11) TDI.TDI */ 0x1d8 ( PIN_OUTPUT | MUX_MODE0 ) /* (A11) TDO.TDO */ 0x1dc ( PIN_INPUT | MUX_MODE0 ) /* (A12) TCK.TCK */ 0x1e0 ( PIN_INPUT | MUX_MODE0 ) /* (B10) nTRST.nTRST */ 0x1e4 ( PIN_INPUT | MUX_MODE0 ) /* (C14) EMU0.EMU0 */ 0x1e8 ( PIN_INPUT | MUX_MODE0 ) /* (B14) EMU1.EMU1 */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ jtag_debugss1_pins_sleep: jtag_debugss1_pins_sleep { pinctrl-single,pins = < 0x1d0 ( ) /* (C11) TMS.TMS */ 0x1d4 ( ) /* (B11) TDI.TDI */ 0x1d8 ( ) /* (A11) TDO.TDO */ 0x1dc ( ) /* (A12) TCK.TCK */ 0x1e0 ( ) /* (B10) nTRST.nTRST */ 0x1e4 ( ) /* (C14) EMU0.EMU0 */ 0x1e8 ( ) /* (B14) EMU1.EMU1 */ >; };