From e7555a1328de66020f975c63246285a7ab2adf93 Mon Sep 17 00:00:00 2001
From: Brijesh Jadav <Brijesh.Jadav@ti.com>
Date: Mon, 12 Dec 2022 14:28:37 +0530
Subject: [PATCH 1/1] Added QoS parameters settings

Signed-off-by: Brijesh Jadav <Brijesh.Jadav@ti.com>
---
 arch/arm/mach-k3/include/mach/hardware.h      |   1 +
 .../mach-k3/include/mach/j721s2_qos_params.h  | 221 ++++++++++++++
 arch/arm/mach-k3/j721s2_init.c                | 285 ++++++++++++++++++
 3 files changed, 507 insertions(+)
 create mode 100644 arch/arm/mach-k3/include/mach/j721s2_qos_params.h

diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
index 73dc2d2d98..93129e5060 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -16,6 +16,7 @@

 #ifdef CONFIG_SOC_K3_J721S2
 #include "j721s2_hardware.h"
+#include "j721s2_qos_params.h"
 #endif

 #ifdef CONFIG_SOC_K3_AM642
diff --git a/arch/arm/mach-k3/include/mach/j721s2_qos_params.h b/arch/arm/mach-k3/include/mach/j721s2_qos_params.h
new file mode 100644
index 0000000000..3f46a6bed5
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/j721s2_qos_params.h
@@ -0,0 +1,221 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: J721E QoS params definitions
+ *
+ * (C) Copyright (C) 2021-2022 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#ifndef __ASM_ARCH_J721E_QOS_PARAMS_H
+#define __ASM_ARCH_J721E_QOS_PARAMS_H
+
+#define QOS_C66SS0_MDMA_ATYPE                (0U)
+#define QOS_C66SS1_MDMA_ATYPE                (0U)
+#define QOS_VPAC0_DATA0_ATYPE                (0U)
+#define QOS_VPAC0_DATA1_ATYPE                (0U)
+#define QOS_VPAC0_LDC0_ATYPE                 (0U)
+#define QOS_DMPAC0_DATA_ATYPE                (0U)
+#define QOS_DSS0_DMA_ATYPE                   (3U)
+#define QOS_DSS0_FBDC_ATYPE                  (0U)
+#define QOS_GPU0_M0_RD_ATYPE                 (0U)
+#define QOS_GPU0_M0_WR_ATYPE                 (0U)
+#define QOS_GPU0_M1_RD_ATYPE                 (0U)
+#define QOS_GPU0_M1_WR_ATYPE                 (0U)
+#define QOS_ENCODER0_RD_ATYPE                (0U)
+#define QOS_ENCODER0_WR_ATYPE                (0U)
+#define QOS_DECODER0_RD_ATYPE                (0U)
+#define QOS_DECODER0_WR_ATYPE                (0U)
+#define QOS_R5FSS0_CORE0_MEM_RD_ATYPE        (0U)
+#define QOS_R5FSS0_CORE0_MEM_WR_ATYPE        (0U)
+#define QOS_R5FSS0_CORE1_MEM_RD_ATYPE        (0U)
+#define QOS_R5FSS0_CORE1_MEM_WR_ATYPE        (0U)
+
+#define QOS_VPAC0_LDC0_ORDER_ID              (1U)
+#define QOS_C66SS0_MDMA_ORDER_ID             (5U)
+#define QOS_C66SS1_MDMA_ORDER_ID             (5U)
+#define QOS_ENCODER0_RD_ORDER_ID             (6U)
+#define QOS_ENCODER0_WR_ORDER_ID             (6U)
+#define QOS_DECODER0_RD_ORDER_ID             (6U)
+#define QOS_DECODER0_WR_ORDER_ID             (6U)
+#define QOS_GPU0_M0_RD_ORDER_ID              (7U)
+#define QOS_GPU0_M0_WR_ORDER_ID              (7U)
+#define QOS_GPU0_M1_RD_ORDER_ID              (7U)
+#define QOS_GPU0_M1_WR_ORDER_ID              (7U)
+#define QOS_DSS0_DMA_ORDER_ID                (15U)
+#define QOS_DSS0_FBDC_ORDER_ID               (10U)
+#define QOS_R5FSS0_CORE0_MEM_RD_ORDER_ID     (11U)
+#define QOS_R5FSS0_CORE0_MEM_WR_ORDER_ID     (11U)
+#define QOS_R5FSS0_CORE1_MEM_RD_ORDER_ID     (11U)
+#define QOS_R5FSS0_CORE1_MEM_WR_ORDER_ID     (11U)
+
+#define QOS_DSS0_DMA_PRIORITY                (1U)
+#define QOS_DSS0_FBDC_PRIORITY               (1U)
+#define QOS_VPAC0_LDC0_PRIORITY              (3U)
+#define QOS_C66SS0_MDMA_PRIORITY             (5U)
+#define QOS_C66SS1_MDMA_PRIORITY             (5U)
+#define QOS_ENCODER0_RD_PRIORITY             (6U)
+#define QOS_ENCODER0_WR_PRIORITY             (6U)
+#define QOS_DECODER0_RD_PRIORITY             (6U)
+#define QOS_DECODER0_WR_PRIORITY             (6U)
+#define QOS_GPU0_M0_RD_MMU_PRIORITY          (3U)
+#define QOS_GPU0_M0_RD_PRIORITY              (7U)
+#define QOS_GPU0_M0_WR_PRIORITY              (7U)
+#define QOS_GPU0_M1_RD_PRIORITY              (7U)
+#define QOS_GPU0_M1_RD_MMU_PRIORITY          (3U)
+#define QOS_GPU0_M1_WR_PRIORITY              (7U)
+#define QOS_R5FSS0_CORE0_MEM_RD_PRIORITY     (2U)
+#define QOS_R5FSS0_CORE0_MEM_WR_PRIORITY     (2U)
+#define QOS_R5FSS0_CORE1_MEM_RD_PRIORITY     (2U)
+#define QOS_R5FSS0_CORE1_MEM_WR_PRIORITY     (2U)
+
+#define QOS_ATYPE_MASK         0x30000000
+#define QOS_VIRTID_MASK            0x0fff0000
+#define QOS_PVU_CTX(virtid)        ((0x1 << 28) | (virtid << 16))
+#define QOS_SMMU_CTX(virtid)       ((0x2 << 28) | (virtid << 16))
+
+/* CBASS */
+
+#define QOS_C66SS0_MDMA                             0x45d81000
+#define QOS_C66SS0_MDMA_NUM_J_CH                    3
+#define QOS_C66SS0_MDMA_NUM_I_CH                    1
+#define QOS_C66SS0_MDMA_CBASS_GRP_MAP1(j)           (QOS_C66SS0_MDMA + 0x0 + (j) * 8)
+#define QOS_C66SS0_MDMA_CBASS_GRP_MAP2(j)           (QOS_C66SS0_MDMA + 0x4 + (j) * 8)
+#define QOS_C66SS0_MDMA_CBASS_MAP(i)                (QOS_C66SS0_MDMA + 0x100 + (i) * 4)
+
+#define QOS_C66SS1_MDMA                             0x45d81400
+#define QOS_C66SS1_MDMA_NUM_J_CH                    3
+#define QOS_C66SS1_MDMA_NUM_I_CH                    1
+#define QOS_C66SS1_MDMA_CBASS_GRP_MAP1(j)           (QOS_C66SS1_MDMA + 0x0 + (j) * 8)
+#define QOS_C66SS1_MDMA_CBASS_GRP_MAP2(j)           (QOS_C66SS1_MDMA + 0x4 + (j) * 8)
+#define QOS_C66SS1_MDMA_CBASS_MAP(i)                (QOS_C66SS1_MDMA + 0x100 + (i) * 4)
+
+#define QOS_R5FSS0_CORE0_MEM_RD                     0x45d84000
+#define QOS_R5FSS0_CORE0_MEM_RD_NUM_J_CH            3
+#define QOS_R5FSS0_CORE0_MEM_RD_NUM_I_CH            1
+#define QOS_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP1(j)   (QOS_R5FSS0_CORE0_MEM_RD + 0x0 + (j) * 8)
+#define QOS_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP2(j)   (QOS_R5FSS0_CORE0_MEM_RD + 0x4 + (j) * 8)
+#define QOS_R5FSS0_CORE0_MEM_RD_CBASS_MAP(i)        (QOS_R5FSS0_CORE0_MEM_RD + 0x100 + (i) * 4)
+
+#define QOS_R5FSS0_CORE1_MEM_RD                     0x45d84400
+#define QOS_R5FSS0_CORE1_MEM_RD_NUM_J_CH            3
+#define QOS_R5FSS0_CORE1_MEM_RD_NUM_I_CH            1
+#define QOS_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP1(j)   (QOS_R5FSS0_CORE1_MEM_RD + 0x0 + (j) * 8)
+#define QOS_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP2(j)   (QOS_R5FSS0_CORE1_MEM_RD + 0x4 + (j) * 8)
+#define QOS_R5FSS0_CORE1_MEM_RD_CBASS_MAP(i)        (QOS_R5FSS0_CORE1_MEM_RD + 0x100 + (i) * 4)
+
+#define QOS_R5FSS0_CORE0_MEM_WR                     0x45d84800
+#define QOS_R5FSS0_CORE0_MEM_WR_NUM_J_CH            3
+#define QOS_R5FSS0_CORE0_MEM_WR_NUM_I_CH            1
+#define QOS_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP1(j)   (QOS_R5FSS0_CORE0_MEM_WR + 0x0 + (j) * 8)
+#define QOS_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP2(j)   (QOS_R5FSS0_CORE0_MEM_WR + 0x4 + (j) * 8)
+#define QOS_R5FSS0_CORE0_MEM_WR_CBASS_MAP(i)        (QOS_R5FSS0_CORE0_MEM_WR + 0x100 + (i) * 4)
+
+#define QOS_R5FSS0_CORE1_MEM_WR                     0x45d84C00
+#define QOS_R5FSS0_CORE1_MEM_WR_NUM_J_CH            3
+#define QOS_R5FSS0_CORE1_MEM_WR_NUM_I_CH            1
+#define QOS_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP1(j)   (QOS_R5FSS0_CORE1_MEM_WR + 0x0 + (j) * 8)
+#define QOS_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP2(j)   (QOS_R5FSS0_CORE1_MEM_WR + 0x4 + (j) * 8)
+#define QOS_R5FSS0_CORE1_MEM_WR_CBASS_MAP(i)        (QOS_R5FSS0_CORE1_MEM_WR + 0x100 + (i) * 4)
+
+#define QOS_ENCODER0_WR                             0x45dc1000
+#define QOS_ENCODER0_WR_NUM_J_CH                    2
+#define QOS_ENCODER0_WR_NUM_I_CH                    5
+#define QOS_ENCODER0_WR_CBASS_GRP_MAP1(j)           (QOS_ENCODER0_WR + 0x0 + (j) * 8)
+#define QOS_ENCODER0_WR_CBASS_GRP_MAP2(j)           (QOS_ENCODER0_WR + 0x4 + (j) * 8)
+#define QOS_ENCODER0_WR_CBASS_MAP(i)                (QOS_ENCODER0_WR + 0x100 + (i) * 4)
+
+#define QOS_DECODER0_RD                             0x45dc0400
+#define QOS_DECODER0_RD_NUM_J_CH                    2
+#define QOS_DECODER0_RD_NUM_I_CH                    1
+#define QOS_DECODER0_RD_CBASS_GRP_MAP1(j)           (QOS_DECODER0_RD + 0x0 + (j) * 8)
+#define QOS_DECODER0_RD_CBASS_GRP_MAP2(j)           (QOS_DECODER0_RD + 0x4 + (j) * 8)
+#define QOS_DECODER0_RD_CBASS_MAP(i)                (QOS_DECODER0_RD + 0x100 + (i) * 4)
+
+#define QOS_DECODER0_WR                             0x45dc0800
+#define QOS_DECODER0_WR_NUM_J_CH                    2
+#define QOS_DECODER0_WR_NUM_I_CH                    1
+#define QOS_DECODER0_WR_CBASS_GRP_MAP1(j)           (QOS_DECODER0_WR + 0x0 + (j) * 8)
+#define QOS_DECODER0_WR_CBASS_GRP_MAP2(j)           (QOS_DECODER0_WR + 0x4 + (j) * 8)
+#define QOS_DECODER0_WR_CBASS_MAP(i)                (QOS_DECODER0_WR + 0x100 + (i) * 4)
+
+#define QOS_VPAC0_DATA0                             0x45dc1500
+#define QOS_VPAC0_DATA0_NUM_I_CH                    32
+#define QOS_VPAC0_DATA0_CBASS_MAP(i)                (QOS_VPAC0_DATA0 + (i) * 4)
+
+#define QOS_DMPAC0_DATA                             0x45dc0100
+#define QOS_DMPAC0_DATA_NUM_I_CH                    32
+#define QOS_DMPAC0_DATA_CBASS_MAP(i)                (QOS_DMPAC0_DATA + (i) * 4)
+
+#define QOS_ENCODER0_RD                             0x45dc0c00
+#define QOS_ENCODER0_RD_NUM_J_CH                    2
+#define QOS_ENCODER0_RD_NUM_I_CH                    5
+#define QOS_ENCODER0_RD_CBASS_GRP_MAP1(j)           (QOS_ENCODER0_RD + 0x0 + (j) * 8)
+#define QOS_ENCODER0_RD_CBASS_GRP_MAP2(j)           (QOS_ENCODER0_RD + 0x4 + (j) * 8)
+#define QOS_ENCODER0_RD_CBASS_MAP(i)                (QOS_ENCODER0_RD + 0x100 + (i) * 4)
+
+#define QOS_VPAC0_DATA1                             0x45dc1900
+#define QOS_VPAC0_DATA1_NUM_I_CH                    64
+#define QOS_VPAC0_DATA1_CBASS_MAP(i)                (QOS_VPAC0_DATA1 + (i) * 4)
+
+#define QOS_VPAC0_LDC0                              0x45dc1c00
+#define QOS_VPAC0_LDC0_NUM_J_CH                     2
+#define QOS_VPAC0_LDC0_NUM_I_CH                     3
+#define QOS_VPAC0_LDC0_CBASS_GRP_MAP1(j)            (QOS_VPAC0_LDC0 + 0x0 + (j) * 8)
+#define QOS_VPAC0_LDC0_CBASS_GRP_MAP2(j)            (QOS_VPAC0_LDC0 + 0x4 + (j) * 8)
+#define QOS_VPAC0_LDC0_CBASS_MAP(i)                 (QOS_VPAC0_LDC0 + 0x100 + (i) * 4)
+
+#define QOS_DSS0_DMA                                0x45dc2000
+#define QOS_DSS0_DMA_NUM_J_CH                       2
+#define QOS_DSS0_DMA_NUM_I_CH                       10
+#define QOS_DSS0_DMA_CBASS_GRP_MAP1(j)              (QOS_DSS0_DMA + 0x0 + (j) * 8)
+#define QOS_DSS0_DMA_CBASS_GRP_MAP2(j)              (QOS_DSS0_DMA + 0x4 + (j) * 8)
+#define QOS_DSS0_DMA_CBASS_MAP(i)                   (QOS_DSS0_DMA + 0x100 + (i) * 4)
+
+#define QOS_DSS0_FBDC                               0x45dc2400
+#define QOS_DSS0_FBDC_NUM_J_CH                      2
+#define QOS_DSS0_FBDC_NUM_I_CH                      10
+#define QOS_DSS0_FBDC_CBASS_GRP_MAP1(j)             (QOS_DSS0_FBDC + 0x0 + (j) * 8)
+#define QOS_DSS0_FBDC_CBASS_GRP_MAP2(j)             (QOS_DSS0_FBDC + 0x4 + (j) * 8)
+#define QOS_DSS0_FBDC_CBASS_MAP(i)                  (QOS_DSS0_FBDC + 0x100 + (i) * 4)
+
+#define QOS_GPU0_M0_RD                              0x45dc5000
+#define QOS_GPU0_M0_RD_NUM_J_CH                     2
+#define QOS_GPU0_M0_RD_NUM_I_CH                     48
+#define QOS_GPU0_M0_RD_CBASS_GRP_MAP1(j)            (QOS_GPU0_M0_RD + 0x0 + (j) * 8)
+#define QOS_GPU0_M0_RD_CBASS_GRP_MAP2(j)            (QOS_GPU0_M0_RD + 0x4 + (j) * 8)
+#define QOS_GPU0_M0_RD_CBASS_MAP(i)                 (QOS_GPU0_M0_RD + 0x100 + (i) * 4)
+
+#define QOS_GPU0_M0_WR                              0x45dc5800
+#define QOS_GPU0_M0_WR_NUM_J_CH                     2
+#define QOS_GPU0_M0_WR_NUM_I_CH                     48
+#define QOS_GPU0_M0_WR_CBASS_GRP_MAP1(j)            (QOS_GPU0_M0_WR + 0x0 + (j) * 8)
+#define QOS_GPU0_M0_WR_CBASS_GRP_MAP2(j)            (QOS_GPU0_M0_WR + 0x4 + (j) * 8)
+#define QOS_GPU0_M0_WR_CBASS_MAP(i)                 (QOS_GPU0_M0_WR + 0x100 + (i) * 4)
+
+#define QOS_GPU0_M1_RD                              0x45dc6000
+#define QOS_GPU0_M1_RD_NUM_J_CH                     2
+#define QOS_GPU0_M1_RD_NUM_I_CH                     48
+#define QOS_GPU0_M1_RD_CBASS_GRP_MAP1(j)            (QOS_GPU0_M1_RD + 0x0 + (j) * 8)
+#define QOS_GPU0_M1_RD_CBASS_GRP_MAP2(j)            (QOS_GPU0_M1_RD + 0x4 + (j) * 8)
+#define QOS_GPU0_M1_RD_CBASS_MAP(i)                 (QOS_GPU0_M1_RD + 0x100 + (i) * 4)
+
+#define QOS_GPU0_M1_WR                              0x45dc6800
+#define QOS_GPU0_M1_WR_NUM_J_CH                     2
+#define QOS_GPU0_M1_WR_NUM_I_CH                     48
+#define QOS_GPU0_M1_WR_CBASS_GRP_MAP1(j)            (QOS_GPU0_M1_WR + 0x0 + (j) * 8)
+#define QOS_GPU0_M1_WR_CBASS_GRP_MAP2(j)            (QOS_GPU0_M1_WR + 0x4 + (j) * 8)
+#define QOS_GPU0_M1_WR_CBASS_MAP(i)                 (QOS_GPU0_M1_WR + 0x100 + (i) * 4)
+
+#define QOS_MMC0_RD_CBASS_MAP(i)                    (0x45d9a100 + (i) * 4)
+#define QOS_MMC0_WR_CBASS_MAP(i)                    (0x45d9a500 + (i) * 4)
+#define QOS_MMC1_RD_CBASS_MAP(i)                    (0x45d82100 + (i) * 4)
+#define QOS_MMC1_WR_CBASS_MAP(i)                    (0x45d82500 + (i) * 4)
+
+#define QOS_D5520_RD_CBASS_MAP(i)                   (0x45dc0500 + (i) * 4)
+#define QOS_D5520_WR_CBASS_MAP(i)                   (0x45dc0900 + (i) * 4)
+
+/* NAVSS North Bridge (NB) */
+#define NAVSS0_NBSS_NB0_CFG_MMRS                    0x3702000
+#define NAVSS0_NBSS_NB1_CFG_MMRS                    0x3703000
+#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP            (NAVSS0_NBSS_NB0_CFG_MMRS + 0x10)
+#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP            (NAVSS0_NBSS_NB1_CFG_MMRS + 0x10)
+
+#endif
\ No newline at end of file
diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c
index 2a345fd6b7..d00de6dc52 100644
--- a/arch/arm/mach-k3/j721s2_init.c
+++ b/arch/arm/mach-k3/j721s2_init.c
@@ -76,6 +76,279 @@ struct fwl_data cbass_hc_cfg0_fwls[] = {
 };
 #endif

+void setup_navss_nb(void)
+{
+        /* Map orderid 8-15 to VBUSM.C thread 2 (real-time traffic) */
+        writel(2, NAVSS0_NBSS_NB0_CFG_NB_THREADMAP);
+        writel(4, NAVSS0_NBSS_NB1_CFG_NB_THREADMAP);
+}
+
+void setup_vpac_qos(void)
+{
+       unsigned int channel, group;
+
+       /* vpac data master 0  */
+       for (channel = 0; channel < QOS_VPAC0_DATA0_NUM_I_CH; ++channel) {
+
+               writel((QOS_VPAC0_DATA0_ATYPE << 28), (uintptr_t)QOS_VPAC0_DATA0_CBASS_MAP(channel));
+       }
+
+       /* vpac data master 1  */
+       for (channel = 0; channel < QOS_VPAC0_DATA1_NUM_I_CH; ++channel) {
+
+               writel((QOS_VPAC0_DATA1_ATYPE << 28), (uintptr_t)QOS_VPAC0_DATA1_CBASS_MAP(channel));
+       }
+
+       /* vpac ldc0  */
+       for (group = 0; group < QOS_VPAC0_LDC0_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_VPAC0_LDC0_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_VPAC0_LDC0_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_VPAC0_LDC0_NUM_I_CH; ++channel) {
+
+               writel((QOS_VPAC0_LDC0_ATYPE << 28) | (QOS_VPAC0_LDC0_PRIORITY << 12) | (QOS_VPAC0_LDC0_ORDER_ID << 4), (uintptr_t)QOS_VPAC0_LDC0_CBASS_MAP(channel));
+       }
+
+}
+
+void setup_dmpac_qos(void)
+{
+       unsigned int channel;
+
+       /* dmpac data  */
+       for (channel = 0; channel < QOS_DMPAC0_DATA_NUM_I_CH; ++channel) {
+
+               writel((QOS_DMPAC0_DATA_ATYPE << 28), (uintptr_t)QOS_DMPAC0_DATA_CBASS_MAP(channel));
+       }
+}
+
+void setup_dss_qos(void)
+{
+       unsigned int channel, group;
+
+       /* two master ports: dma and fbdc */
+       /* two groups: SRAM and DDR */
+       /* 10 channels: (pipe << 1) | is_second_buffer */
+
+       /* master port 1 (dma) */
+       for (group = 0; group < QOS_DSS0_DMA_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_DSS0_DMA_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_DSS0_DMA_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_DSS0_DMA_NUM_I_CH; ++channel) {
+
+               writel((QOS_DSS0_DMA_ATYPE << 28) | (QOS_DSS0_DMA_PRIORITY << 12) | (QOS_DSS0_DMA_ORDER_ID << 4), (uintptr_t)QOS_DSS0_DMA_CBASS_MAP(channel));
+       }
+
+       /* master port 2 (fbdc) */
+       for (group = 0; group < QOS_DSS0_FBDC_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_DSS0_FBDC_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_DSS0_FBDC_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_DSS0_FBDC_NUM_I_CH; ++channel) {
+
+               writel((QOS_DSS0_FBDC_ATYPE << 28) | (QOS_DSS0_FBDC_PRIORITY << 12) | (QOS_DSS0_FBDC_ORDER_ID << 4), (uintptr_t)QOS_DSS0_FBDC_CBASS_MAP(channel));
+       }
+}
+
+void setup_gpu_qos(void)
+{
+       unsigned int channel, group;
+
+       /* gpu m0 rd */
+       for (group = 0; group < QOS_GPU0_M0_RD_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_GPU0_M0_RD_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_GPU0_M0_RD_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_GPU0_M0_RD_NUM_I_CH; ++channel) {
+
+               if(channel == 0)
+               {
+                       writel((QOS_GPU0_M0_RD_ATYPE << 28) | (QOS_GPU0_M0_RD_MMU_PRIORITY << 12) | (QOS_GPU0_M0_RD_ORDER_ID << 4), (uintptr_t)QOS_GPU0_M0_RD_CBASS_MAP(channel));
+               }
+               else
+               {
+                       writel((QOS_GPU0_M0_RD_ATYPE << 28) | (QOS_GPU0_M0_RD_PRIORITY << 12) | (QOS_GPU0_M0_RD_ORDER_ID << 4), (uintptr_t)QOS_GPU0_M0_RD_CBASS_MAP(channel));
+               }
+       }
+
+       /* gpu m0 wr */
+       for (group = 0; group < QOS_GPU0_M0_WR_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_GPU0_M0_WR_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_GPU0_M0_WR_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_GPU0_M0_WR_NUM_I_CH; ++channel) {
+
+               writel((QOS_GPU0_M0_WR_ATYPE << 28) | (QOS_GPU0_M0_WR_PRIORITY << 12) | (QOS_GPU0_M0_WR_ORDER_ID << 4), (uintptr_t)QOS_GPU0_M0_WR_CBASS_MAP(channel));
+       }
+
+       /* gpu m1 rd */
+       for (group = 0; group < QOS_GPU0_M1_RD_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_GPU0_M1_RD_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_GPU0_M1_RD_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_GPU0_M1_RD_NUM_I_CH; ++channel) {
+
+               if(channel == 0)
+               {
+                       writel((QOS_GPU0_M1_RD_ATYPE << 28) | (QOS_GPU0_M1_RD_MMU_PRIORITY << 12) | (QOS_GPU0_M1_RD_ORDER_ID << 4), (uintptr_t)QOS_GPU0_M1_RD_CBASS_MAP(channel));
+               }
+               else
+               {
+                       writel((QOS_GPU0_M1_RD_ATYPE << 28) | (QOS_GPU0_M1_RD_PRIORITY << 12) | (QOS_GPU0_M1_RD_ORDER_ID << 4), (uintptr_t)QOS_GPU0_M1_RD_CBASS_MAP(channel));
+               }
+       }
+
+       /* gpu m1 wr */
+       for (group = 0; group < QOS_GPU0_M1_WR_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_GPU0_M1_WR_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_GPU0_M1_WR_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_GPU0_M1_WR_NUM_I_CH; ++channel) {
+
+               writel((QOS_GPU0_M1_WR_ATYPE << 28) | (QOS_GPU0_M1_WR_PRIORITY << 12) | (QOS_GPU0_M1_WR_ORDER_ID << 4), (uintptr_t)QOS_GPU0_M1_WR_CBASS_MAP(channel));
+       }
+}
+
+void setup_encoder_qos(void)
+{
+       unsigned int channel, group;
+
+       /* encoder rd */
+       for (group = 0; group < QOS_ENCODER0_RD_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_ENCODER0_RD_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_ENCODER0_RD_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_ENCODER0_RD_NUM_I_CH; ++channel) {
+
+               writel((QOS_ENCODER0_RD_ATYPE << 28) | (QOS_ENCODER0_RD_PRIORITY << 12) | (QOS_ENCODER0_RD_ORDER_ID << 4), (uintptr_t)QOS_ENCODER0_RD_CBASS_MAP(channel));
+       }
+
+       /* encoder wr */
+       for (group = 0; group < QOS_ENCODER0_WR_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_ENCODER0_WR_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_ENCODER0_WR_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_ENCODER0_WR_NUM_I_CH; ++channel) {
+
+               writel((QOS_ENCODER0_WR_ATYPE << 28) | (QOS_ENCODER0_WR_PRIORITY << 12) | (QOS_ENCODER0_WR_ORDER_ID << 4), (uintptr_t)QOS_ENCODER0_WR_CBASS_MAP(channel));
+       }
+}
+
+void setup_decoder_qos(void)
+{
+       unsigned int channel, group;
+
+       /* decoder rd */
+       for (group = 0; group < QOS_DECODER0_RD_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_DECODER0_RD_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_DECODER0_RD_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_DECODER0_RD_NUM_I_CH; ++channel) {
+
+               writel((QOS_DECODER0_RD_ATYPE << 28) | (QOS_DECODER0_RD_PRIORITY << 12) | (QOS_DECODER0_RD_ORDER_ID << 4), (uintptr_t)QOS_DECODER0_RD_CBASS_MAP(channel));
+       }
+
+       /* decoder wr */
+       for (group = 0; group < QOS_DECODER0_WR_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_DECODER0_WR_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_DECODER0_WR_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_DECODER0_WR_NUM_I_CH; ++channel) {
+
+               writel((QOS_DECODER0_WR_ATYPE << 28) | (QOS_DECODER0_WR_PRIORITY << 12) | (QOS_DECODER0_WR_ORDER_ID << 4), (uintptr_t)QOS_DECODER0_WR_CBASS_MAP(channel));
+       }
+}
+
+void setup_c66_qos(void)
+{
+       unsigned int channel, group;
+
+       /* c66_0 mdma */
+       for (group = 0; group < QOS_C66SS0_MDMA_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_C66SS0_MDMA_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_C66SS0_MDMA_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_C66SS0_MDMA_NUM_I_CH; ++channel) {
+
+               writel((QOS_C66SS0_MDMA_ATYPE << 28) | (QOS_C66SS0_MDMA_PRIORITY << 12) | (QOS_C66SS0_MDMA_ORDER_ID << 4), (uintptr_t)QOS_C66SS0_MDMA_CBASS_MAP(channel));
+       }
+
+       /* c66_1 mdma */
+       for (group = 0; group < QOS_C66SS1_MDMA_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_C66SS1_MDMA_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_C66SS1_MDMA_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_C66SS1_MDMA_NUM_I_CH; ++channel) {
+
+               writel((QOS_C66SS1_MDMA_ATYPE << 28) | (QOS_C66SS1_MDMA_PRIORITY << 12) | (QOS_C66SS1_MDMA_ORDER_ID << 4), (uintptr_t)QOS_C66SS1_MDMA_CBASS_MAP(channel));
+       }
+}
+
+void setup_main_r5f_qos(void)
+{
+       unsigned int channel, group;
+
+       /* R5FSS0 core0 - read */
+       for (group = 0; group < QOS_R5FSS0_CORE0_MEM_RD_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_R5FSS0_CORE0_MEM_RD_NUM_I_CH; ++channel) {
+
+               writel((QOS_R5FSS0_CORE0_MEM_RD_ATYPE << 28) | (QOS_R5FSS0_CORE0_MEM_RD_PRIORITY << 12) | (QOS_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4), (uintptr_t)QOS_R5FSS0_CORE0_MEM_RD_CBASS_MAP(channel));
+       }
+
+       /* R5FSS0 core0 - write */
+       for (group = 0; group < QOS_R5FSS0_CORE0_MEM_WR_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_R5FSS0_CORE0_MEM_WR_NUM_I_CH; ++channel) {
+
+               writel((QOS_R5FSS0_CORE0_MEM_WR_ATYPE << 28) | (QOS_R5FSS0_CORE0_MEM_WR_PRIORITY << 12) | (QOS_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4), (uintptr_t)QOS_R5FSS0_CORE0_MEM_WR_CBASS_MAP(channel));
+       }
+
+       /* R5FSS0 core1 - read */
+       for (group = 0; group < QOS_R5FSS0_CORE1_MEM_RD_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_R5FSS0_CORE1_MEM_RD_NUM_I_CH; ++channel) {
+
+               writel((QOS_R5FSS0_CORE1_MEM_RD_ATYPE << 28) | (QOS_R5FSS0_CORE1_MEM_RD_PRIORITY << 12) | (QOS_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4), (uintptr_t)QOS_R5FSS0_CORE1_MEM_RD_CBASS_MAP(channel));
+       }
+
+       /* R5FSS0 core1 - write */
+       for (group = 0; group < QOS_R5FSS0_CORE1_MEM_WR_NUM_J_CH; ++group) {
+               writel(0x76543210, (uintptr_t)QOS_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP1(group));
+               writel(0xfedcba98, (uintptr_t)QOS_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP2(group));
+       }
+
+       for (channel = 0; channel < QOS_R5FSS0_CORE1_MEM_WR_NUM_I_CH; ++channel) {
+
+               writel((QOS_R5FSS0_CORE1_MEM_WR_ATYPE << 28) | (QOS_R5FSS0_CORE1_MEM_WR_PRIORITY << 12) | (QOS_R5FSS0_CORE1_MEM_RD_ORDER_ID << 4), (uintptr_t)QOS_R5FSS0_CORE1_MEM_WR_CBASS_MAP(channel));
+       }
+
+}
+
+
 static void ctrl_mmr_unlock(void)
 {
    /* Unlock all WKUP_CTRL_MMR0 module registers */
@@ -232,6 +505,18 @@ void board_init_f(ulong dummy)
    remove_fwl_configs(navss_cbass0_fwls, ARRAY_SIZE(navss_cbass0_fwls));
 #endif

+   {
+       setup_navss_nb();
+       //setup_c66_qos();
+       setup_main_r5f_qos();
+       setup_vpac_qos();
+       setup_dmpac_qos();
+       setup_dss_qos();
+       setup_gpu_qos();
+       setup_encoder_qos();
+   }
+
+
    /* Output System Firmware version info */
    k3_sysfw_print_ver();

--
2.17.1

