-0-
These GELs are an adaptation of the internal GEL framework, modified for use/distribution to customers via the CSP.

To initialize clocks and ddr run the tests:
	 DO "~~~~/j7es_m3.cmm"
	 DO "~~~~/J721E.cmm"

After these menus to test the system will be installed.

It will be possible to attach to each core after the clocks/power is on by calling:
	j7es_a72.cmm
	j7es_c7x.cmm
	j7es_c66.cmm
	j7es_icssg.cmm
	j7es_m3.cmm
	j7es_r5.cmm

-1-
A ddr test executed from the A72 can be auto run by calling:
	dra829_a72_ddr_test.cmm

-2-
Scripts in the ./pdk_rtos_test/ directory allow for loading and running PDK FreeRTOS or TIRTOS examples.  These use TI-Firmware running on the TIFS-CortexM3

-3-
TRACE32 CORE names are as follows.

	; A72 (1x2)  : DRA829 (core.assign 1 2)
	; CR5 (3x2)  : DRA829-CR5-MCU DRA829-CR5-MAIN0 DRA829-CR5-MAIN1 (core.assign 1 2)
	; CM3 (1x1)  : DRA829-CM3
	; PRU (2x3x2): DRA829-ICSS0 DRA829-ICSS0-RTU DRA829-ICSS0-TX (core.assign 1 2)
	; C66 (2x1)  : DRA829-C66X (core.assign 1 2)
	; C7x (1x1)  : DRA829-C71X

To allow for multi-core concurrent trace decode the tools side requires a "system.config CORE" option. The CORE # convention follows the above:
	CM3 1
	A72x: 2 3
	CR5x: 4 5 6 7 8 9
	C66: 10 11
	C7x: 12
	ICSS1: 13 14 15 16 17 18
	ICSS2: 19 20 21 22 23 24

To select the 2nd C6x core the config file would use:
 	SYStem.CPU DRA829-C66X		; select C6x
 	SYStem.CONFIG CORE 11. 1.	; Core#12 on chip#1
	CORE.Assign 2.			; select 2nd C7x instance

NOTES: 
	Scripts which setup DDR only work after a power on reset and cannot be re-called as they depend on reset state.
	Bare metal scripts work with GP devices and HS-SE-WIR.  
	HS-SE-Firmware based devices will not allow M4 operations without a proper certificate with UID.
