// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ * * Product Link: https://www.ti.com/tool/J721EXCPXEVM */ /dts-v1/; #include "k3-j721e-som-p0.dtsi" #include #include #include #include / { compatible = "ti,j721e-evm", "ti,j721e"; model = "Texas Instruments J721e EVM"; aliases { serial0 = &wkup_uart0; serial1 = &mcu_uart0; serial2 = &main_uart0; serial7 = &main_uart5; spi3 = &main_spi3; spi5 = &main_spi5; ethernet0 = &cpsw_port1; mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; }; chosen { stdout-path = "serial2:115200n8"; bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait"; }; evm_12v0: fixedregulator-evm12v0 { /* main supply */ compatible = "regulator-fixed"; regulator-name = "evm_12v0"; regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; regulator-always-on; regulator-boot-on; }; vsys_3v3: fixedregulator-vsys3v3 { /* Output of LMS140 */ compatible = "regulator-fixed"; regulator-name = "vsys_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; vin-supply = <&evm_12v0>; regulator-always-on; regulator-boot-on; }; vsys_5v0: fixedregulator-vsys5v0 { /* Output of LM5140 */ compatible = "regulator-fixed"; regulator-name = "vsys_5v0"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; vin-supply = <&evm_12v0>; regulator-always-on; regulator-boot-on; }; vdd_mmc1: fixedregulator-sd { compatible = "regulator-fixed"; regulator-name = "vdd_mmc1"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; enable-active-high; vin-supply = <&vsys_3v3>; //gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; }; vdd_sd_dv_alt: gpio-regulator-tps659411 { compatible = "regulator-gpio"; pinctrl-names = "default"; pinctrl-0 = <&vdd_sd_dv_alt_pins_default>; regulator-name = "vdd_sd_dv"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; vin-supply = <&vsys_3v3>; gpios = <&main_gpio0 111 GPIO_ACTIVE_HIGH>; states = <1800000 0x0>, <3300000 0x1>; }; dp_pwr_3v3: regulator-dp-pwr { compatible = "regulator-fixed"; regulator-name = "dp-pwr"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; //gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */ enable-active-high; }; dp0: connector { compatible = "dp-connector"; label = "DP0"; type = "full-size"; dp-pwr-supply = <&dp_pwr_3v3>; port { dp_connector_in: endpoint { remote-endpoint = <&dp0_out>; }; }; }; pps_gpio { status = "okay"; compatible = "pps-gpio"; gpios = <&main_gpio1 13 GPIO_ACTIVE_HIGH>; }; codec_test: codec_test { compatible = "linux,snd-soc-dummy"; #sound-dai-cells = <0>; status="okay"; }; codec_audio0: sound0 { compatible = "simple-audio-card"; simple-audio-card,name = "FXN_A2B"; simple-audio-card,format = "i2s"; simple-audio-card,bitclock-master = <&sound_master0>; simple-audio-card,frame-master = <&sound_master0>; sound_master0: simple-audio-card,cpu { sound-dai = <&mcasp1>; system-clock-direction-out; }; simple-audio-card,codec { sound-dai = <&codec_test>; }; }; }; &main_pmx0 { main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */ J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ >; }; main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */ >; }; vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1c0, PIN_OUTPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */ >; }; dp0_pins_default: dp0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ >; }; mcasp10_pins_default: mcasp10-default-pins { pinctrl-single,pins = < //J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */ /*pin FOR I2C2 del 2025/02/25 */ //J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */ /*pin FOR I2C2 del 2025/02/25 */ //J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */ /*pin FOR UART3 del 2025/02/25 */ //J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */ /*pin FOR UART3 del 2025/02/25 */ //J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */ //J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */ // J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */ /* pin FOR SPI5 del 2025/02/27 */ // J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */ // J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */ /* pin FOR SPI5 del 2025/02/27 */ >; }; /* conflict gpio delete for /dev/gpiochip0 */ // audi_ext_refclk2_pins_default: audi-ext-refclk2-default-pins { // pinctrl-single,pins = < // J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */ // >; // }; // main域gpio0的设备树具体内容需要各位老师确认，有需要则打开注释，最后仍保留注释部分将从设备树中删除 // add main_gpio0_pins_default: main-gpio0-default-pins { pinctrl-single,pins = < // J721E_IOPAD(0x4, PIN_OUTPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */ // J721E_IOPAD(0x8, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */ // J721E_IOPAD(0xc, PIN_OUTPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ //J721E_IOPAD(0x10, PIN_OUTPUT_PULLDOWN, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */ // J721E_IOPAD(0x14, PIN_OUTPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */ // J721E_IOPAD(0x1c, PIN_OUTPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ J721E_IOPAD(0x28, PIN_INPUT, 7) /* (AG20) PRG1_PRU0_GPO9.GPIO0_10 */ J721E_IOPAD(0x2c, PIN_OUTPUT_PULLUP, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ // J721E_IOPAD(0x30, PIN_OUTPUT, 7) /* (AF24) PRG1_PRU0_GPO11.GPIO0_12 */ // J721E_IOPAD(0x34, PIN_OUTPUT, 7) /* (AJ24) PRG1_PRU0_GPO12.GPIO0_13 */ // J721E_IOPAD(0x38, PIN_INPUT, 7) /* (AG24) PRG1_PRU0_GPO13.GPIO0_14 */ // J721E_IOPAD(0x3c, PIN_OUTPUT, 7) /* (AD24) PRG1_PRU0_GPO14.GPIO0_15 */ // J721E_IOPAD(0x40, PIN_INPUT, 7) /* (AC24) PRG1_PRU0_GPO15.GPIO0_16 */ // J721E_IOPAD(0x44, PIN_INPUT, 7) /* (AE24) PRG1_PRU0_GPO16.GPIO0_17 */ // J721E_IOPAD(0x4c, PIN_INPUT, 7) /* (AJ21) PRG1_PRU0_GPO17.GPIO0_18 */ // J721E_IOPAD(0x50, PIN_INPUT, 7) /* (AE21) PRG1_PRU0_GPO18.GPIO0_19 */ // J721E_IOPAD(0x54, PIN_INPUT, 7) /* (AH21) PRG1_PRU0_GPO19.GPIO0_20 */ // J721E_IOPAD(0x58, PIN_INPUT, 7) /* (AE22) PRG1_PRU1_GPO0.GPIO0_21 */ // J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */ // J721E_IOPAD(0x60, PIN_INPUT, 7) /* (AF23) PRG1_PRU1_GPO2.GPIO0_23 */ // J721E_IOPAD(0x64, PIN_INPUT, 7) /* (AD23) PRG1_PRU1_GPO3.GPIO0_24 */ // J721E_IOPAD(0x68, PIN_INPUT, 7) /* (AH24) PRG1_PRU1_GPO4.GPIO0_25 */ // J721E_IOPAD(0x6c, PIN_INPUT, 7) /* (AG21) PRG1_PRU1_GPO5.GPIO0_26 */ // J721E_IOPAD(0x70, PIN_INPUT, 7) /* (AE23) PRG1_PRU1_GPO6.GPIO0_27 */ // J721E_IOPAD(0x74, PIN_INPUT, 7) /* (AC21) PRG1_PRU1_GPO7.GPIO0_28 */ // J721E_IOPAD(0x78, PIN_INPUT, 7) /* (Y23) PRG1_PRU1_GPO8.GPIO0_29 */ // J721E_IOPAD(0x7c, PIN_OUTPUT, 7) /* (AF21) PRG1_PRU1_GPO9.GPIO0_30 */ // J721E_IOPAD(0x80, PIN_OUTPUT, 7) /* (AB23) PRG1_PRU1_GPO10.GPIO0_31 */ // J721E_IOPAD(0x90, PIN_OUTPUT_PULLDOWN, 7) /* (AH26) PRG1_PRU1_GPO14.GPIO0_35 */ J721E_IOPAD(0x94, PIN_INPUT, 7) /* (AJ27) PRG1_PRU1_GPO15.GPIO0_36 */ J721E_IOPAD(0xa4, PIN_INPUT, 7) /* (AH22) PRG1_PRU1_GPO19.GPIO0_40 add for S32K SPI */ // J721E_IOPAD(0xa8, PIN_OUTPUT, 7) /* (AD19) PRG1_MDIO0_MDIO.GPIO0_41 */ // J721E_IOPAD(0xac, PIN_OUTPUT, 7) /* (AD18) PRG1_MDIO0_MDC.GPIO0_42 */ // J721E_IOPAD(0xb0, PIN_OUTPUT, 7) /* (AF28) PRG0_PRU0_GPO0.GPIO0_43 */ // J721E_IOPAD(0xb4, PIN_INPUT, 7) /* (AE28) PRG0_PRU0_GPO1.GPIO0_44 */ // J721E_IOPAD(0xb8, PIN_OUTPUT, 7) /* (AE27) PRG0_PRU0_GPO2.GPIO0_45 */ // J721E_IOPAD(0xbc, PIN_OUTPUT, 7) /* (AD26) PRG0_PRU0_GPO3.GPIO0_46 */ // J721E_IOPAD(0xc0, PIN_INPUT, 7) /* (AD25) PRG0_PRU0_GPO4.GPIO0_47 */ // J721E_IOPAD(0xc8, PIN_OUTPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */ // J721E_IOPAD(0xcc, PIN_OUTPUT, 7) /* (AC28) PRG0_PRU0_GPO7.GPIO0_50 */ // J721E_IOPAD(0xd0, PIN_INPUT, 7) /* (AC27) PRG0_PRU0_GPO8.GPIO0_51 */ // J721E_IOPAD(0xdc, PIN_OUTPUT, 7) /* (AJ28) PRG0_PRU0_GPO11.GPIO0_54 */ // J721E_IOPAD(0xe0, PIN_OUTPUT, 7) /* (AH27) PRG0_PRU0_GPO12.GPIO0_55 */ // J721E_IOPAD(0xe4, PIN_INPUT, 7) /* (AH29) PRG0_PRU0_GPO13.GPIO0_56 */ // J721E_IOPAD(0xe8, PIN_INPUT, 7) /* (AG28) PRG0_PRU0_GPO14.GPIO0_57 */ // J721E_IOPAD(0xec, PIN_INPUT, 7) /* (AG27) PRG0_PRU0_GPO15.GPIO0_58 */ // J721E_IOPAD(0xf0, PIN_OUTPUT, 7) /* (AH28) PRG0_PRU0_GPO16.GPIO0_59 */ // J721E_IOPAD(0xf8, PIN_OUTPUT, 7) /* (AB29) PRG0_PRU0_GPO18.GPIO0_61 */ // J721E_IOPAD(0xfc, PIN_INPUT, 7) /* (AB28) PRG0_PRU0_GPO19.GPIO0_62 */ // J721E_IOPAD(0x100, PIN_INPUT, 7) /* (AE29) PRG0_PRU1_GPO0.GPIO0_63 */ // J721E_IOPAD(0x104, PIN_INPUT, 7) /* (AD28) PRG0_PRU1_GPO1.GPIO0_64 */ J721E_IOPAD(0x130, PIN_INPUT, 7) /* (AF27) PRG0_PRU1_GPO12.GPIO0_75 */ J721E_IOPAD(0x134, PIN_OUTPUT_PULLUP, 7) /* (AF26) PRG0_PRU1_GPO13.GPIO0_76 */ // J721E_IOPAD(0x138, PIN_OUTPUT_PULLUP, 7) /* (AE25) PRG0_PRU1_GPO14.GPIO0_77 */ // J721E_IOPAD(0x13c, PIN_OUTPUT, 7) /* (AF29) PRG0_PRU1_GPO15.GPIO0_78 */ // J721E_IOPAD(0x140, PIN_INPUT, 7) /* (AG29) PRG0_PRU1_GPO16.GPIO0_79 */ // J721E_IOPAD(0x154, PIN_OUTPUT_PULLDOWN, 7) /* (AA27) PRG0_MDIO0_MDC.GPIO0_84 */ // J721E_IOPAD(0x168, PIN_OUTPUT, 7) /* (V27) RGMII5_TD1.GPIO0_89 */ J721E_IOPAD(0x16c, PIN_INPUT, 7) /* (U28) RGMII5_TD0.GPIO0_90 OPEN for SPI3_CS2 IRQ */ // J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 7) /* (U29) RGMII5_TXC.GPIO0_91 */ // J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 7) /* (U25) RGMII5_RXC.GPIO0_92 */ // J721E_IOPAD(0x178, PIN_OUTPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */ // J721E_IOPAD(0x17c, PIN_OUTPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */ // J721E_IOPAD(0x180, PIN_OUTPUT_PULLDOWN, 7) /* (R23) RGMII5_RD1.GPIO0_95 */ // J721E_IOPAD(0x184, PIN_OUTPUT_PULLDOWN, 7) /* (T23) RGMII5_RD0.GPIO0_96 */ // J721E_IOPAD(0x188, PIN_OUTPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ J721E_IOPAD(0x18c, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */ J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */ // J721E_IOPAD(0x194, PIN_OUTPUT, 7) /* (W28) RGMII6_TD2.GPIO0_100 */ // J721E_IOPAD(0x198, PIN_OUTPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ // J721E_IOPAD(0x19c, PIN_OUTPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ // J721E_IOPAD(0x1a0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ J721E_IOPAD(0x1a4, PIN_INPUT, 7) /* (W26) RGMII6_RXC.GPIO0_104 */ // J721E_IOPAD(0x1c0, PIN_OUTPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */ // J721E_IOPAD(0x1c4, PIN_OUTPUT, 7) /* (Y4) SPI0_CS1.GPIO0_112 */ // J721E_IOPAD(0x1c8, PIN_OUTPUT, 7) /* (AA1) SPI0_CLK.GPIO0_113 */ // J721E_IOPAD(0x1cc, PIN_OUTPUT, 7) /* (AB5) SPI0_D0.GPIO0_114 */ // J721E_IOPAD(0x1d0, PIN_OUTPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ // J721E_IOPAD(0x1dc, PIN_INPUT, 7) /* (Y1) SPI1_CLK.GPIO0_118 */ // J721E_IOPAD(0x1e0, PIN_INPUT, 7) /* (Y5) SPI1_D0.GPIO0_119 */ J721E_IOPAD(0x1e4, PIN_INPUT, 7) /* (Y2) SPI1_D1.GPIO0_120 */ >; }; // main域gpio1的设备树具体内容需要各位老师确认，有需要则打开注释，最后仍保留注释部分将从设备树中删除 // add main_gpio1_pins_default: main-gpio1-default-pins { pinctrl-single,pins = < // J721E_IOPAD(0x218, PIN_OUTPUT, 7) /* (W2) I3C0_SCL.GPIO1_5 */ // J721E_IOPAD(0x21c, PIN_INPUT, 7) /* (W1) I3C0_SDA.GPIO1_6 */ // J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ // J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ J721E_IOPAD(0x238, PIN_INPUT, 7) /* (V6) TIMER_IO0.GPIO1_13 ADD for PPS */ J721E_IOPAD(0x260, PIN_OUTPUT_PULLDOWN, 7) /* (T28) MMC2_DAT3.GPIO1_23 */ // J721E_IOPAD(0x264, PIN_INPUT, 7) /* (T29) MMC2_DAT2.GPIO1_24 */ //J721E_IOPAD(0x268, PIN_OUTPUT_PULLUP, 7) /* (T27) MMC2_DAT1.GPIO1_25 */ /*pin FOR TDA4_LG69T_RST del 2025/02/25 */ // J721E_IOPAD(0x26c, PIN_OUTPUT, 7) /* (T24) MMC2_DAT0.GPIO1_26 */ // J721E_IOPAD(0x270, PIN_INPUT, 7) /* (T26) MMC2_CLK.GPIO1_27 */ // J721E_IOPAD(0x274, PIN_INPUT, 7) /* (T25) MMC2_CMD.GPIO1_28 */ // J721E_IOPAD(0x290, PIN_OUTPUT, 7) /* (U6) USB0_DRVVBUS.GPIO1_29 */ // J721E_IOPAD(0x294, PIN_INPUT, 7) /* (AD1) MLB0_MLBSP.GPIO1_30 */ // J721E_IOPAD(0x298, PIN_INPUT, 7) /* (AC1) MLB0_MLBSN.GPIO1_31 */ // J721E_IOPAD(0x29c, PIN_INPUT, 7) /* (AC3) MLB0_MLBDP.GPIO1_32 */ // J721E_IOPAD(0x2a0, PIN_INPUT, 7) /* (AD3) MLB0_MLBDN.GPIO1_33 */ // J721E_IOPAD(0x2a4, PIN_INPUT, 7) /* (AD2) MLB0_MLBCP.GPIO1_34 */ // J721E_IOPAD(0x2a8, PIN_INPUT, 7) /* (AE2) MLB0_MLBCN.GPIO1_35 */ >; }; // add main_mcasp1_pins_default: main-mcasp1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x114, PIN_OUTPUT, 12) /* (AB27) PRG0_PRU1_GPO5.MCASP1_ACLKX */ J721E_IOPAD(0x120, PIN_OUTPUT, 12) /* (AA28) PRG0_PRU1_GPO8.MCASP1_AFSX */ J721E_IOPAD(0x110, PIN_INPUT, 12) /* (AD29) PRG0_PRU1_GPO4.MCASP1_AXR2 */ J721E_IOPAD(0x118, PIN_INPUT, 12) /* (AC26) PRG0_PRU1_GPO6.MCASP1_AXR3 */ J721E_IOPAD(0x128, PIN_OUTPUT, 12) /* (AA25) PRG0_PRU1_GPO10.MCASP1_AXR6 */ J721E_IOPAD(0x12c, PIN_OUTPUT, 12) /* (AG26) PRG0_PRU1_GPO11.MCASP1_AXR7 */ >; }; // add main_mmcsd1_pins_default: main-mmcsd1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */ J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */ >; }; // add main_pcie3_pins_default: main-pcie3-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x25c, PIN_INPUT, 6) /* (R28) MMC1_SDWP.PCIE3_CLKREQn */ >; }; // main_i2c1_exp4_pins_default: main-i2c1-exp4-default-pins { // pinctrl-single,pins = < // J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ // >; // }; main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ >; }; /* AG190W SPI <---> TDA4 SPI3 */ main_spi3_pins_default: main-spi3-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x144, PIN_INPUT, 4) /* (Y25) PRG0_PRU1_GPO17.SPI3_CLK */ J721E_IOPAD(0x11c, PIN_INPUT, 4) /* (AA24) PRG0_PRU1_GPO7.SPI3_CS0 */ J721E_IOPAD(0xd4, PIN_INPUT, 4) /* (AB26) PRG0_PRU0_GPO9.SPI3_CS1 */ J721E_IOPAD(0xd8, PIN_INPUT, 4) /* (AB25) PRG0_PRU0_GPO10.SPI3_CS2 */ J721E_IOPAD(0x124, PIN_INPUT, 4) /* (Y24) PRG0_PRU1_GPO9.SPI3_CS3 */ J721E_IOPAD(0x148, PIN_INPUT, 4) /* (AA26) PRG0_PRU1_GPO18.SPI3_D0 */ J721E_IOPAD(0x14c, PIN_INPUT, 4) /* (AA29) PRG0_PRU1_GPO19.SPI3_D1 */ >; }; /* Add for A2 Sample AG568N <---> TDA4 SPI5 */ main_spi5_pins_default: main_spi5-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1a0, PIN_INPUT, 3) /* (W29) RGMII6_TXC.SPI5_CLK */ J721E_IOPAD(0x1b4, PIN_INPUT, 3) /* (W25) RGMII6_RD0.SPI5_CS1 */ J721E_IOPAD(0x198, PIN_INPUT, 3) /* (V25) RGMII6_TD1.SPI5_D0 */ J721E_IOPAD(0x1b0, PIN_INPUT, 3) /* (W24) RGMII6_RD1.SPI5_D1 */ >; }; // add main_system0_pins_default: main-system0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x278, PIN_OUTPUT, 0) /* (T6) RESETSTATz */ J721E_IOPAD(0x280, PIN_INPUT, 0) /* (U4) SOC_SAFETY_ERRORn */ >; }; /* AG190W Uart3 <----> TDA4 Uart5 */ main_uart5_pins_default: main-uart5-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1d4, PIN_INPUT, 3) /* (Y3) SPI1_CS0.UART5_RXD */ J721E_IOPAD(0x1d8, PIN_OUTPUT, 3) /* (W4) SPI1_CS1.UART5_TXD */ >; }; }; &wkup_pmx0 { /delete-node/ pmic-irq-default-pins; mcu_fss0_ospi0_pins_default: mcu_fss0_ospi0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */ J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */ J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */ J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */ J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */ J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */ J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */ J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */ J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */ J721E_WKUP_IOPAD(0x3c, PIN_INPUT_PULLUP, 6) /* (B23) MCU_OSPI1_DQS.MCU_OSPI0_ECC_FAIL */ J721E_WKUP_IOPAD(0x38, PIN_OUTPUT_PULLUP, 6) /* (A23) MCU_OSPI1_LBCLKO.MCU_OSPI0_RESET_OUT0 */ >; }; mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ >; }; // modify // mcu_mdio_pins_default: mcu-mdio1-default-pins { // pinctrl-single,pins = < // J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */ // J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */ // >; // }; mcu_mdio_pins_default: mcu-mdio1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ >; }; // wkup域gpio0的设备树具体内容需要各位老师确认，有需要则打开注释，最后仍保留注释部分将从设备树中删除 wkup_gpio_pins_default: wkup-gpio-default-pins { pinctrl-single,pins = < // J721E_WKUP_IOPAD(0xbc, PIN_OUTPUT_PULLDOWN, 7) /* (F27) WKUP_GPIO0_3 */ /*pin Board_ID_EEPROM_WP del 2025/02/25 */ J721E_WKUP_IOPAD(0xc8, PIN_INPUT, 7) /* (F29) WKUP_GPIO0_6 */ // J721E_WKUP_IOPAD(0xcc, PIN_OUTPUT, 7) /* (G28) WKUP_GPIO0_7 */ // J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_8 */ // J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* (G26) WKUP_GPIO0_9 */ // J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (H26) WKUP_GPIO0_10 */ // J721E_WKUP_IOPAD(0xdc, PIN_OUTPUT, 7) /* (H27) WKUP_GPIO0_11 */ // J721E_WKUP_IOPAD(0x4, PIN_INPUT_PULLUP, 7) /* (C21) MCU_OSPI0_LBCLKO.WKUP_GPIO0_17 */ J721E_WKUP_IOPAD(0x34, PIN_INPUT, 7) /* (F22) MCU_OSPI1_CLK.WKUP_GPIO0_29 */ // J721E_WKUP_IOPAD(0x44, PIN_OUTPUT, 7) /* (G22) MCU_OSPI1_D1.WKUP_GPIO0_33 */ // J721E_WKUP_IOPAD(0x48, PIN_INPUT, 7) /* (D23) MCU_OSPI1_D2.WKUP_GPIO0_34 */ // J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 7) /* (C23) MCU_OSPI1_D3.WKUP_GPIO0_35 */ // J721E_WKUP_IOPAD(0x50, PIN_OUTPUT_PULLUP, 7) /* (C22) MCU_OSPI1_CSn0.WKUP_GPIO0_36 */ // J721E_WKUP_IOPAD(0x9c, PIN_INPUT, 7) /* (E25) MCU_SPI0_CS0.WKUP_GPIO0_55 */ // J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 7) /* (D26) MCU_I3C0_SCL.WKUP_GPIO0_60 */ // J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 7) /* (D25) MCU_I3C0_SDA.WKUP_GPIO0_61 */ // J721E_WKUP_IOPAD(0x108, PIN_OUTPUT_PULLDOWN, 7) /* (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */ /*pin BOOT_EEPROM_WP del 2025/02/25 */ >; }; // add mcu_rgmii1_pins_default: mcu-rgmii1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */ J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */ J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */ J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */ J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */ J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */ J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */ J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */ J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */ J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */ >; }; }; &main_spi3 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_spi3_pins_default>; spidev@0 { compatible = "ti,spi-evm"; spi-max-frequency = <3125000>; reg = <0>; spi-cpol = <1>; // CPOL = 1 spi-cpha = <1>; // CPHA = 1 }; spidev@1 { compatible = "ti,spi-evm"; spi-max-frequency = <3125000>; reg = <1>; spi-cpol = <0>; // CPOL = 0 spi-cpha = <1>; // CPHA = 1 }; spidev@2 { compatible = "ti,spi-evm"; spi-max-frequency = <3125000>; reg = <2>; spi-cpol = <0>; // CPOL = 0 spi-cpha = <0>; // CPHA = 0 // interrupts = ; }; spidev@3 { compatible = "ti,spi-evm"; spi-max-frequency = <3125000>; reg = <3>; spi-cpol = <0>; // CPOL = 0 spi-cpha = <1>; // CPHA = 1 }; }; &main_spi5 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_spi5_pins_default>; spidev@0 { compatible = "ti,spi-evm"; spi-max-frequency = <3125000>; reg = <1>; spi-cpol = <1>; // CPOL = 1 spi-cpha = <1>; // CPHA = 1 }; }; &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "reserved"; }; &mcu_uart0 { status = "reserved"; }; &main_i2c1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; a2b24xx: a2b24xx@0x68 { compatible = "adi,a2b24xx"; reg = <0x68>; }; }; &main_uart0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; /* Shared with ATF on this platform */ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; }; &main_uart1 { status = "disabled"; }; &main_uart2 { status = "disabled"; }; &main_uart4 { status = "disabled"; }; /* Add For AG190W Uart */ &main_uart5 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart5_pins_default>; }; &wkup_gpio0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wkup_gpio_pins_default>; }; &main_gpio0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_gpio0_pins_default>; }; &main_gpio1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_gpio1_pins_default>; }; &main_sdhci0 { /* eMMC */ status = "okay"; non-removable; ti,driver-strength-ohm = <50>; disable-wp; }; &main_sdhci1 { /* SD/MMC */ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; ti,driver-strength-ohm = <50>; disable-wp; no-1-8-v; sdhci-caps-mask = <0x8000000F 0x0>; }; &ufs_wrapper { status = "okay"; ufs@4e84000 { /* ufs */ status = "okay"; freq-table-hz = <26000000 26000000>, // 高速频率 <19200000 19200000>, // 低速频率1 <19200000 19200000>; // 低速频率2 }; }; &serdes_ln_ctrl { /*disable serdes for cpsw9g*/ idle-states = , , , , , , , ; }; &serdes_wiz3 { typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */ }; &serdes3 { serdes3_usb_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; cdns,phy-type = ; resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; status = "disabled"; /*disable serdes for cpsw9g*/ }; }; &ospi0 { status = "okay"; flash@0 { cdns,read-delay = <4>; }; }; &ospi1 { status = "disabled"; }; &tscadc0 { status = "okay"; adc { ti,adc-channels = <0 1 2 3 4 5 6 7>; }; }; &tscadc1 { status = "okay"; adc { ti,adc-channels = <0 1 2 3 4 5 6 7>; }; }; /* conflict gpio delete for /dev/gpiochip0 */ // &k3_clks { // /* Confiure AUDIO_EXT_REFCLK2 pin as output */ // pinctrl-names = "default"; // pinctrl-0 = <&audi_ext_refclk2_pins_default>; // }; &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; cpts@3d000 { /* Map HW4_TS_PUSH to GENF1 */ ti,pps = <3 1>; }; }; &davinci_mdio { phy2: ethernet-phy@2 { reg = <2>; mv88q2220-reset-gpios = <&main_gpio0 76 GPIO_ACTIVE_HIGH>; reset-assert-us = <10000>; // 10ms reset-deassert-us = <10000>; // 10ms }; }; &cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&phy2>; }; &dss { /* * These clock assignments are chosen to enable the following outputs: * * VP0 - DisplayPort SST * VP1 - DPI0 * VP2 - DSI * VP3 - DPI1 */ assigned-clocks = <&k3_clks 152 1>, <&k3_clks 152 4>, <&k3_clks 152 9>, <&k3_clks 152 13>; assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ <&k3_clks 152 6>, /* PLL19_HSDIV0 */ <&k3_clks 152 11>, /* PLL18_HSDIV0 */ <&k3_clks 152 18>; /* PLL23_HSDIV0 */ }; &dss_ports { port { dpi0_out: endpoint { remote-endpoint = <&dp0_in>; }; }; }; &dp0_ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dp0_in: endpoint { remote-endpoint = <&dpi0_out>; }; }; port@4 { reg = <4>; dp0_out: endpoint { remote-endpoint = <&dp_connector_in>; }; }; }; &mcasp1 { status = "okay"; #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&main_mcasp1_pins_default>; op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <2>; auxclk-fs-ratio = <256>; serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 0 0 2 2 0 0 1 1 0 0 0 0 >; tx-num-evt = <0>; rx-num-evt = <0>; }; &cmn_refclk1 { clock-frequency = <100000000>; }; &wiz0_pll1_refclk { assigned-clocks = <&wiz0_pll1_refclk>; assigned-clock-parents = <&cmn_refclk1>; status = "disabled";/*disable serdes for cpsw9g*/ }; &wiz0_refclk_dig { assigned-clocks = <&wiz0_refclk_dig>; assigned-clock-parents = <&cmn_refclk1>; status = "disabled"; }; &wiz1_pll1_refclk { assigned-clocks = <&wiz1_pll1_refclk>; assigned-clock-parents = <&cmn_refclk1>; status = "disabled"; }; &wiz1_refclk_dig { assigned-clocks = <&wiz1_refclk_dig>; assigned-clock-parents = <&cmn_refclk1>; status = "disabled"; }; &wiz2_pll1_refclk { assigned-clocks = <&wiz2_pll1_refclk>; assigned-clock-parents = <&cmn_refclk1>; status = "disabled"; }; &wiz2_refclk_dig { assigned-clocks = <&wiz2_refclk_dig>; assigned-clock-parents = <&cmn_refclk1>; status = "disabled"; }; &serdes0 { assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>; assigned-clock-parents = <&wiz0_pll1_refclk>; serdes0_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <1>; #phy-cells = <0>; cdns,phy-type = ; resets = <&serdes_wiz0 1>; status = "disabled"; }; }; &serdes1 { assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>; assigned-clock-parents = <&wiz1_pll1_refclk>; serdes1_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; cdns,phy-type = ; resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>; status = "disabled"; }; }; /*disable serdes for cpsw9g*/ &serdes_wiz0 { status = "disabled"; }; &serdes_wiz1 { status = "disabled"; }; &serdes_wiz2 { status = "disabled"; }; &serdes_wiz3 { status = "disabled"; }; &serdes2 { assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>; assigned-clock-parents = <&wiz2_pll1_refclk>; serdes2_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; cdns,phy-type = ; resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>; status = "disabled";/*disable serdes for cpsw9g*/ }; }; &serdes4 { torrent_phy_dp: phy@0 { reg = <0>; resets = <&serdes_wiz4 1>; cdns,phy-type = ; cdns,num-lanes = <4>; cdns,max-bit-rate = <2700>; #phy-cells = <0>; }; }; &mhdp { phys = <&torrent_phy_dp>; phy-names = "dpphy"; pinctrl-names = "default"; pinctrl-0 = <&dp0_pins_default>; }; &pcie0_rc { status = "okay"; //reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; num-lanes = <1>; }; &pcie1_rc { status = "okay"; //reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; phys = <&serdes1_pcie_link>; phy-names = "pcie-phy"; num-lanes = <2>; }; &pcie2_rc { status = "okay"; //reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; phys = <&serdes2_pcie_link>; phy-names = "pcie-phy"; num-lanes = <2>; }; #define K3_TS_OFFSET(pa, val) (0x4+(pa)*4) (0x10000 | val) ×ync_router { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_cpts>; /* Use Time Sync Router to map GENF1 input to HW4_TS_PUSH output */ mcu_cpsw_cpts: mcu-cpsw-cpts { pinctrl-single,pins = < /* pps [mcu cpsw cpts genf1] in17 -> out25 [mcu cpsw cpts hw4_push] */ K3_TS_OFFSET(25, 17) >; }; }; &wkup_i2c0 { /delete-node/ eeprom@50; /delete-node/ pmic@48; /delete-node/ pmic@4c; /*status = "reserved";*/ }; &cbass_main { phy@4580000 { status = "disable"; }; phy@4590000 { status = "disable"; }; dp-bridge@a000000 { status = "disable"; }; };