/dts-v1/;

/ {
	#address-cells = <0x02>;
	#size-cells = <0x02>;
	compatible = "company,6887_0650\0ti,am5728\0ti,dra7";
	interrupt-parent = <0x01>;
	model = "6887 0650 (SCOM)";

	chosen {
		stdout-path = "/ocp/interconnect@48000000/segment@0/target-module@20000/serial@0";
	};

	aliases {
		i2c0 = "/ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0";
		i2c1 = "/ocp/interconnect@48000000/segment@0/target-module@72000/i2c@0";
		i2c2 = "/ocp/interconnect@48000000/segment@0/target-module@60000/i2c@0";
		i2c3 = "/ocp/interconnect@48000000/segment@0/target-module@7a000/i2c@0";
		i2c4 = "/ocp/interconnect@48000000/segment@0/target-module@7c000/i2c@0";
		serial0 = "/ocp/interconnect@48000000/segment@0/target-module@6a000/serial@0";
		serial1 = "/ocp/interconnect@48000000/segment@0/target-module@6c000/serial@0";
		serial2 = "/ocp/interconnect@48000000/segment@0/target-module@20000/serial@0";
		serial3 = "/ocp/interconnect@48000000/segment@0/target-module@6e000/serial@0";
		serial4 = "/ocp/interconnect@48000000/segment@0/target-module@66000/serial@0";
		serial5 = "/ocp/interconnect@48000000/segment@0/target-module@68000/serial@0";
		serial6 = "/ocp/interconnect@48400000/segment@0/target-module@20000/serial@0";
		serial7 = "/ocp/interconnect@48400000/segment@0/target-module@22000/serial@0";
		serial8 = "/ocp/interconnect@48400000/segment@0/target-module@24000/serial@0";
		serial9 = "/ocp/interconnect@4ae00000/segment@20000/target-module@b000/serial@0";
		ethernet0 = "/ocp/interconnect@48400000/segment@0/target-module@84000/switch@0/ethernet-ports/port@1";
		ethernet1 = "/ocp/interconnect@48400000/segment@0/target-module@84000/switch@0/ethernet-ports/port@2";
		d_can0 = "/ocp/interconnect@4ae00000/segment@30000/target-module@c000/can@0";
		d_can1 = "/ocp/interconnect@48400000/segment@0/target-module@80000/can@0";
		spi0 = "/ocp/target-module@4b300000/spi@0";
		rproc0 = "/ocp/ipu@58820000";
		rproc1 = "/ocp/ipu@55020000";
		rproc2 = "/ocp/dsp@40800000";
		rproc3 = "/ocp/dsp@41000000";
	};

	timer {
		compatible = "arm,armv7-timer";
		status = "disabled";
		interrupts = <0x01 0x0d 0x308 0x01 0x0e 0x308 0x01 0x0b 0x308 0x01 0x0a 0x308>;
		interrupt-parent = <0x02>;
	};

	interrupt-controller@48211000 {
		compatible = "arm,cortex-a15-gic";
		interrupt-controller;
		#interrupt-cells = <0x03>;
		reg = <0x00 0x48211000 0x00 0x1000 0x00 0x48212000 0x00 0x2000 0x00 0x48214000 0x00 0x2000 0x00 0x48216000 0x00 0x2000>;
		interrupts = <0x01 0x09 0x304>;
		interrupt-parent = <0x02>;
		phandle = <0x02>;
	};

	interrupt-controller@48281000 {
		compatible = "ti,omap5-wugen-mpu\0ti,omap4-wugen-mpu";
		interrupt-controller;
		#interrupt-cells = <0x03>;
		reg = <0x00 0x48281000 0x00 0x1000>;
		interrupt-parent = <0x02>;
		phandle = <0x0a>;
	};

	cpus {
		#address-cells = <0x01>;
		#size-cells = <0x00>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x00>;
			operating-points-v2 = <0x03>;
			clocks = <0x04>;
			clock-names = "cpu";
			clock-latency = <0x493e0>;
			#cooling-cells = <0x02>;
			vbb-supply = <0x05>;
			phandle = <0xd3>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x01>;
			operating-points-v2 = <0x03>;
			clocks = <0x04>;
			clock-names = "cpu";
			clock-latency = <0x493e0>;
			#cooling-cells = <0x02>;
			vbb-supply = <0x05>;
		};
	};

	opp-table {
		compatible = "operating-points-v2-ti-cpu";
		syscon = <0x06>;
		opp-shared;
		phandle = <0x03>;

		opp_nom-1000000000 {
			opp-hz = <0x00 0x3b9aca00>;
			opp-microvolt = <0x102ca0 0xcf850 0x118c30 0x102ca0 0xcf850 0x118c30>;
			opp-supported-hw = <0xff 0x01>;
			opp-suspend;
		};

		opp_od-1176000000 {
			opp-hz = <0x00 0x46185600>;
			opp-microvolt = <0x11b340 0xd8108 0x11b340 0x11b340 0xd8108 0x11b340>;
			opp-supported-hw = <0xff 0x02>;
		};

		opp_high@1500000000 {
			opp-hz = <0x00 0x59682f00>;
			opp-microvolt = <0x127690 0xe7ef0 0x1312d0 0x127690 0xe7ef0 0x1312d0>;
			opp-supported-hw = <0xff 0x04>;
		};
	};

	ocp {
		compatible = "simple-pm-bus";
		power-domains = <0x07>;
		clocks = <0x08 0x00 0x00 0x09 0x00 0x00>;
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		ranges = <0x00 0x00 0x00 0xc0000000>;
		dma-ranges = <0x80000000 0x00 0x80000000 0x80000000>;
		phandle = <0xd5>;

		l3-noc@44000000 {
			compatible = "ti,dra7-l3-noc";
			reg = <0x44000000 0x1000 0x45000000 0x1000>;
			interrupts-extended = <0x01 0x00 0x04 0x04 0x0a 0x00 0x0a 0x04>;
		};

		interconnect@4a000000 {
			compatible = "ti,dra7-l4-cfg\0simple-pm-bus";
			power-domains = <0x0b>;
			clocks = <0x0c 0x00 0x00>;
			clock-names = "fck";
			reg = <0x4a000000 0x800 0x4a000800 0x800 0x4a001000 0x1000>;
			reg-names = "ap\0la\0ia0";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x4a000000 0x100000 0x100000 0x4a100000 0x100000 0x200000 0x4a200000 0x100000>;
			phandle = <0xd6>;

			segment@0 {
				compatible = "simple-pm-bus";
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				ranges = <0x00 0x00 0x800 0x800 0x800 0x800 0x1000 0x1000 0x1000 0x2000 0x2000 0x2000 0x4000 0x4000 0x1000 0x5000 0x5000 0x1000 0x6000 0x6000 0x1000 0x8000 0x8000 0x2000 0xa000 0xa000 0x1000 0x56000 0x56000 0x1000 0x57000 0x57000 0x1000 0x5e000 0x5e000 0x2000 0x60000 0x60000 0x1000 0x80000 0x80000 0x8000 0x88000 0x88000 0x1000 0xa0000 0xa0000 0x8000 0xa8000 0xa8000 0x1000 0xd9000 0xd9000 0x1000 0xda000 0xda000 0x1000 0xdd000 0xdd000 0x1000 0xde000 0xde000 0x1000 0xe0000 0xe0000 0x1000 0xe1000 0xe1000 0x1000 0xf4000 0xf4000 0x1000 0xf5000 0xf5000 0x1000 0xf6000 0xf6000 0x1000 0xf7000 0xf7000 0x1000 0x90000 0x90000 0x8000 0x98000 0x98000 0x1000>;

				target-module@2000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x2000 0x04>;
					reg-names = "rev";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x2000 0x2000>;

					scm@0 {
						compatible = "ti,dra7-scm-core\0simple-bus";
						reg = <0x00 0x2000>;
						#address-cells = <0x01>;
						#size-cells = <0x01>;
						ranges = <0x00 0x00 0x2000>;
						phandle = <0xd7>;

						scm_conf@0 {
							compatible = "syscon\0simple-bus";
							reg = <0x00 0x1400>;
							#address-cells = <0x01>;
							#size-cells = <0x01>;
							ranges = <0x00 0x00 0x1400>;
							phandle = <0x0d>;

							pbias_regulator@e00 {
								compatible = "ti,pbias-dra7\0ti,pbias-omap";
								reg = <0xe00 0x04>;
								syscon = <0x0d>;
								phandle = <0xd8>;

								pbias_mmc_omap5 {
									regulator-name = "pbias_mmc_omap5";
									regulator-min-microvolt = <0x1b7740>;
									regulator-max-microvolt = <0x325aa0>;
									phandle = <0x9b>;
								};
							};

							phy-gmii-sel {
								compatible = "ti,dra7xx-phy-gmii-sel";
								reg = <0x554 0x04>;
								#phy-cells = <0x01>;
								phandle = <0xad>;
							};

							clocks {
								#address-cells = <0x01>;
								#size-cells = <0x00>;
								phandle = <0xd9>;

								clock-dss-deshdcp-0@558 {
									#clock-cells = <0x00>;
									compatible = "ti,gate-clock";
									clock-output-names = "dss_deshdcp_clk";
									clocks = <0x0e>;
									ti,bit-shift = <0x00>;
									reg = <0x558>;
									phandle = <0xda>;
								};

								clock-ehrpwm0-tbclk-20@558 {
									#clock-cells = <0x00>;
									compatible = "ti,gate-clock";
									clock-output-names = "ehrpwm0_tbclk";
									clocks = <0x0f>;
									ti,bit-shift = <0x14>;
									reg = <0x558>;
									phandle = <0xa7>;
								};

								clock-ehrpwm1-tbclk-21@558 {
									#clock-cells = <0x00>;
									compatible = "ti,gate-clock";
									clock-output-names = "ehrpwm1_tbclk";
									clocks = <0x0f>;
									ti,bit-shift = <0x15>;
									reg = <0x558>;
									phandle = <0xa8>;
								};

								clock-ehrpwm2-tbclk-22@558 {
									#clock-cells = <0x00>;
									compatible = "ti,gate-clock";
									clock-output-names = "ehrpwm2_tbclk";
									clocks = <0x0f>;
									ti,bit-shift = <0x16>;
									reg = <0x558>;
									phandle = <0xa9>;
								};

								clock-sys-32k {
									#clock-cells = <0x00>;
									compatible = "ti,mux-clock";
									clock-output-names = "sys_32k_ck";
									clocks = <0x10 0x11 0x11 0x11>;
									ti,bit-shift = <0x08>;
									reg = <0x6c4>;
									phandle = <0x54>;
								};
							};
						};

						pinmux@1400 {
							compatible = "ti,dra7-padconf\0pinctrl-single";
							reg = <0x1400 0x468>;
							#address-cells = <0x01>;
							#size-cells = <0x00>;
							#pinctrl-cells = <0x01>;
							#interrupt-cells = <0x01>;
							interrupt-controller;
							pinctrl-single,register-width = <0x20>;
							pinctrl-single,function-mask = <0x3fffffff>;
							phandle = <0xdb>;

							mmc1_pins_default_no_clk_pu {
								pinctrl-single,pins = <0x354 0x40000 0x358 0x60000 0x35c 0x60000 0x360 0x60000 0x364 0x60000 0x368 0x60000>;
								phandle = <0x9c>;
							};

							mmc1_pins_default {
								pinctrl-single,pins = <0x354 0x60000 0x358 0x60000 0x35c 0x60000 0x360 0x60000 0x364 0x60000 0x368 0x60000>;
								phandle = <0xdc>;
							};

							mmc1_pins_sdr12 {
								pinctrl-single,pins = <0x354 0x60000 0x358 0x60000 0x35c 0x60000 0x360 0x60000 0x364 0x60000 0x368 0x60000>;
								phandle = <0xdd>;
							};

							mmc1_pins_hs {
								pinctrl-single,pins = <0x354 0x601b0 0x358 0x601b0 0x35c 0x601b0 0x360 0x601b0 0x364 0x601b0 0x368 0x601b0>;
								phandle = <0x9d>;
							};

							mmc1_pins_sdr25 {
								pinctrl-single,pins = <0x354 0x601b0 0x358 0x601b0 0x35c 0x601b0 0x360 0x601b0 0x364 0x601b0 0x368 0x601b0>;
								phandle = <0xde>;
							};

							mmc1_pins_sdr50 {
								pinctrl-single,pins = <0x354 0x601a0 0x358 0x601a0 0x35c 0x601a0 0x360 0x601a0 0x364 0x601a0 0x368 0x601a0>;
								phandle = <0xdf>;
							};

							mmc1_pins_ddr50 {
								pinctrl-single,pins = <0x354 0x60100 0x358 0x60100 0x35c 0x60100 0x360 0x60100 0x364 0x60100 0x368 0x60100>;
								phandle = <0xe0>;
							};

							mmc1_pins_sdr104 {
								pinctrl-single,pins = <0x354 0x60100 0x358 0x60100 0x35c 0x60100 0x360 0x60100 0x364 0x60100 0x368 0x60100>;
								phandle = <0xe1>;
							};

							mmc2_pins_default {
								pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>;
								phandle = <0x9e>;
							};

							mmc2_pins_hs {
								pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>;
								phandle = <0x9f>;
							};

							mmc2_pins_ddr_3_3v_rev11 {
								pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>;
								phandle = <0xe2>;
							};

							mmc2_pins_ddr_1_8v_rev11 {
								pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>;
								phandle = <0xe3>;
							};

							mmc2_pins_ddr_rev20 {
								pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>;
								phandle = <0xa0>;
							};

							mmc2_pins_hs200 {
								pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>;
								phandle = <0xe4>;
							};

							mmc4_pins_default {
								pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
								phandle = <0xe5>;
							};

							mmc4_pins_hs {
								pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
								phandle = <0xe6>;
							};

							mmc3_pins_default {
								pinctrl-single,pins = <0x37c 0x60100 0x380 0x60100 0x384 0x60100 0x388 0x60100 0x38c 0x60100 0x390 0x60100>;
								phandle = <0xe7>;
							};

							mmc3_pins_hs {
								pinctrl-single,pins = <0x37c 0x60100 0x380 0x60100 0x384 0x60100 0x388 0x60100 0x38c 0x60100 0x390 0x60100>;
								phandle = <0xe8>;
							};

							mmc3_pins_sdr12 {
								pinctrl-single,pins = <0x37c 0x60100 0x380 0x60100 0x384 0x60100 0x388 0x60100 0x38c 0x60100 0x390 0x60100>;
								phandle = <0xe9>;
							};

							mmc3_pins_sdr25 {
								pinctrl-single,pins = <0x37c 0x60100 0x380 0x60100 0x384 0x60100 0x388 0x60100 0x38c 0x60100 0x390 0x60100>;
								phandle = <0xea>;
							};

							mmc3_pins_sdr50 {
								pinctrl-single,pins = <0x37c 0x60100 0x380 0x60100 0x384 0x60100 0x388 0x60100 0x38c 0x60100 0x390 0x60100>;
								phandle = <0xeb>;
							};

							mmc4_pins_sdr12 {
								pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
								phandle = <0xec>;
							};

							mmc4_pins_sdr25 {
								pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
								phandle = <0xed>;
							};
						};

						scm_conf@1c04 {
							compatible = "syscon";
							reg = <0x1c04 0x20>;
							#syscon-cells = <0x02>;
							phandle = <0xb8>;
						};

						scm_conf@1c24 {
							compatible = "syscon";
							reg = <0x1c24 0x24>;
							phandle = <0x62>;
						};

						dma-router@b78 {
							compatible = "ti,dra7-dma-crossbar";
							reg = <0xb78 0xfc>;
							#dma-cells = <0x01>;
							dma-requests = <0xcd>;
							ti,dma-safe-map = <0x00>;
							dma-masters = <0x12>;
							phandle = <0x97>;
						};

						dma-router@c78 {
							compatible = "ti,dra7-dma-crossbar";
							reg = <0xc78 0x7c>;
							#dma-cells = <0x02>;
							dma-requests = <0xcc>;
							ti,dma-safe-map = <0x00>;
							dma-masters = <0x13>;
							phandle = <0xaa>;
						};
					};
				};

				target-module@5000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x5000 0x04>;
					reg-names = "rev";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x5000 0x1000>;

					cm_core_aon@0 {
						compatible = "ti,dra7-cm-core-aon\0simple-bus";
						#address-cells = <0x01>;
						#size-cells = <0x01>;
						reg = <0x00 0x2000>;
						ranges = <0x00 0x00 0x2000>;
						phandle = <0xee>;

						clocks {
							#address-cells = <0x01>;
							#size-cells = <0x00>;
							phandle = <0xef>;

							clock-atl-clkin0 {
								#clock-cells = <0x00>;
								compatible = "ti,dra7-atl-clock";
								clock-output-names = "atl_clkin0_ck";
								clocks = <0x14 0x00 0x1a>;
								phandle = <0xa3>;
							};

							clock-atl-clkin1 {
								#clock-cells = <0x00>;
								compatible = "ti,dra7-atl-clock";
								clock-output-names = "atl_clkin1_ck";
								clocks = <0x14 0x00 0x1a>;
								phandle = <0xa4>;
							};

							clock-atl-clkin2 {
								#clock-cells = <0x00>;
								compatible = "ti,dra7-atl-clock";
								clock-output-names = "atl_clkin2_ck";
								clocks = <0x14 0x00 0x1a>;
								phandle = <0xa5>;
							};

							clock-atl-clkin3 {
								#clock-cells = <0x00>;
								compatible = "ti,dra7-atl-clock";
								clock-output-names = "atl_clkin3_ck";
								clocks = <0x14 0x00 0x1a>;
								phandle = <0xa6>;
							};

							clock-hdmi-clkin {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "hdmi_clkin_ck";
								clock-frequency = <0x00>;
								phandle = <0x34>;
							};

							clock-mlb-clkin {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "mlb_clkin_ck";
								clock-frequency = <0x00>;
								phandle = <0x92>;
							};

							clock-mlbp-clkin {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "mlbp_clkin_ck";
								clock-frequency = <0x00>;
								phandle = <0x93>;
							};

							clock-pciesref-acs {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "pciesref_acs_clk_ck";
								clock-frequency = <0x5f5e100>;
								phandle = <0x44>;
							};

							clock-ref-clkin0 {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "ref_clkin0_ck";
								clock-frequency = <0x00>;
								phandle = <0xf0>;
							};

							clock-ref-clkin1 {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "ref_clkin1_ck";
								clock-frequency = <0x00>;
								phandle = <0xf1>;
							};

							clock-ref-clkin2 {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "ref_clkin2_ck";
								clock-frequency = <0x00>;
								phandle = <0xf2>;
							};

							clock-ref-clkin3 {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "ref_clkin3_ck";
								clock-frequency = <0x00>;
								phandle = <0xf3>;
							};

							clock-rmii {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "rmii_clk_ck";
								clock-frequency = <0x00>;
								phandle = <0xf4>;
							};

							clock-sdvenc-clkin {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "sdvenc_clkin_ck";
								clock-frequency = <0x00>;
								phandle = <0xf5>;
							};

							clock-secure-32k-clk-src {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "secure_32k_clk_src_ck";
								clock-frequency = <0x8000>;
								phandle = <0x7c>;
							};

							clock-sys-clk32-crystal {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "sys_clk32_crystal_ck";
								clock-frequency = <0x8000>;
								phandle = <0x10>;
							};

							clock-sys-clk32-pseudo {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "sys_clk32_pseudo_ck";
								clocks = <0x15>;
								clock-mult = <0x01>;
								clock-div = <0x262>;
								phandle = <0x11>;
							};

							clock-virt-12000000 {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "virt_12000000_ck";
								clock-frequency = <0xb71b00>;
								phandle = <0x6a>;
							};

							clock-virt-13000000 {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "virt_13000000_ck";
								clock-frequency = <0xc65d40>;
								phandle = <0xf6>;
							};

							clock-virt-16800000 {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "virt_16800000_ck";
								clock-frequency = <0x1005900>;
								phandle = <0x6c>;
							};

							clock-virt-19200000 {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "virt_19200000_ck";
								clock-frequency = <0x124f800>;
								phandle = <0x6d>;
							};

							clock-virt-20000000 {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "virt_20000000_ck";
								clock-frequency = <0x1312d00>;
								phandle = <0x6b>;
							};

							clock-virt-26000000 {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "virt_26000000_ck";
								clock-frequency = <0x18cba80>;
								phandle = <0x6e>;
							};

							clock-virt-27000000 {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "virt_27000000_ck";
								clock-frequency = <0x19bfcc0>;
								phandle = <0x6f>;
							};

							clock-virt-38400000 {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "virt_38400000_ck";
								clock-frequency = <0x249f000>;
								phandle = <0x70>;
							};

							clock-sys-clkin2 {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "sys_clkin2";
								clock-frequency = <0x1588800>;
								phandle = <0x71>;
							};

							clock-usb-otg-clkin {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "usb_otg_clkin_ck";
								clock-frequency = <0x00>;
								phandle = <0x79>;
							};

							clock-video1-clkin {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "video1_clkin_ck";
								clock-frequency = <0x00>;
								phandle = <0x3e>;
							};

							clock-video1-m2-clkin {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "video1_m2_clkin_ck";
								clock-frequency = <0x00>;
								phandle = <0x33>;
							};

							clock-video2-clkin {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "video2_clkin_ck";
								clock-frequency = <0x00>;
								phandle = <0x3f>;
							};

							clock-video2-m2-clkin {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "video2_m2_clkin_ck";
								clock-frequency = <0x00>;
								phandle = <0x32>;
							};

							clock@1e0 {
								#clock-cells = <0x00>;
								compatible = "ti,omap4-dpll-m4xen-clock";
								clock-output-names = "dpll_abe_ck";
								clocks = <0x16 0x17>;
								reg = <0x1e0 0x1e4 0x1ec 0x1e8>;
								phandle = <0x18>;
							};

							clock-dpll-abe-x2 {
								#clock-cells = <0x00>;
								compatible = "ti,omap4-dpll-x2-clock";
								clock-output-names = "dpll_abe_x2_ck";
								clocks = <0x18>;
								phandle = <0x19>;
							};

							clock-dpll-abe-m2x2-8@1f0 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_abe_m2x2_ck";
								clocks = <0x19>;
								ti,max-div = <0x1f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x1f0>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0x1a>;
							};

							clock-abe@108 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "abe_clk";
								clocks = <0x1a>;
								ti,max-div = <0x04>;
								reg = <0x108>;
								ti,index-power-of-two;
								phandle = <0x73>;
							};

							clock-dpll-abe-m2-8@1f0 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_abe_m2_ck";
								clocks = <0x18>;
								ti,max-div = <0x1f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x1f0>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0x75>;
							};

							clock-dpll-abe-m3x2-8@1f4 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_abe_m3x2_ck";
								clocks = <0x19>;
								ti,max-div = <0x1f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x1f4>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0x1b>;
							};

							clock-dpll-core-byp-mux-23@12c {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "dpll_core_byp_mux";
								clocks = <0x15 0x1b>;
								ti,bit-shift = <0x17>;
								reg = <0x12c>;
								phandle = <0x1c>;
							};

							clock@120 {
								#clock-cells = <0x00>;
								compatible = "ti,omap4-dpll-core-clock";
								clock-output-names = "dpll_core_ck";
								clocks = <0x15 0x1c>;
								reg = <0x120 0x124 0x12c 0x128>;
								phandle = <0x1d>;
							};

							clock-dpll-core-x2 {
								#clock-cells = <0x00>;
								compatible = "ti,omap4-dpll-x2-clock";
								clock-output-names = "dpll_core_x2_ck";
								clocks = <0x1d>;
								phandle = <0x1e>;
							};

							clock-dpll-core-h12x2-8@13c {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_core_h12x2_ck";
								clocks = <0x1e>;
								ti,max-div = <0x3f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x13c>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0x1f>;
							};

							clock-mpu-dpll-hs-clk-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "mpu_dpll_hs_clk_div";
								clocks = <0x1f>;
								clock-mult = <0x01>;
								clock-div = <0x01>;
								phandle = <0x20>;
							};

							clock@160 {
								#clock-cells = <0x00>;
								compatible = "ti,omap5-mpu-dpll-clock";
								clock-output-names = "dpll_mpu_ck";
								clocks = <0x15 0x20>;
								reg = <0x160 0x164 0x16c 0x168>;
								phandle = <0x04>;
							};

							clock-dpll-mpu-m2-8@170 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_mpu_m2_ck";
								clocks = <0x04>;
								ti,max-div = <0x1f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x170>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0x21>;
							};

							clock-mpu-dclk-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "mpu_dclk_div";
								clocks = <0x21>;
								clock-mult = <0x01>;
								clock-div = <0x01>;
								phandle = <0x80>;
							};

							clock-dsp-dpll-hs-clk-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "dsp_dpll_hs_clk_div";
								clocks = <0x1f>;
								clock-mult = <0x01>;
								clock-div = <0x01>;
								phandle = <0x22>;
							};

							clock-dpll-dsp-byp-mux-23@240 {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "dpll_dsp_byp_mux";
								clocks = <0x15 0x22>;
								ti,bit-shift = <0x17>;
								reg = <0x240>;
								phandle = <0x23>;
							};

							clock@234 {
								#clock-cells = <0x00>;
								compatible = "ti,omap4-dpll-clock";
								clock-output-names = "dpll_dsp_ck";
								clocks = <0x15 0x23>;
								reg = <0x234 0x238 0x240 0x23c>;
								assigned-clocks = <0x24>;
								assigned-clock-rates = <0x23c34600>;
								phandle = <0x24>;
							};

							clock-dpll-dsp-m2-8@244 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_dsp_m2_ck";
								clocks = <0x24>;
								ti,max-div = <0x1f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x244>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								assigned-clocks = <0x25>;
								assigned-clock-rates = <0x23c34600>;
								phandle = <0x25>;
							};

							clock-iva-dpll-hs-clk-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "iva_dpll_hs_clk_div";
								clocks = <0x1f>;
								clock-mult = <0x01>;
								clock-div = <0x01>;
								phandle = <0x26>;
							};

							clock-dpll-iva-byp-mux-23@1ac {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "dpll_iva_byp_mux";
								clocks = <0x15 0x26>;
								ti,bit-shift = <0x17>;
								reg = <0x1ac>;
								phandle = <0x27>;
							};

							clock@1a0 {
								#clock-cells = <0x00>;
								compatible = "ti,omap4-dpll-clock";
								clock-output-names = "dpll_iva_ck";
								clocks = <0x15 0x27>;
								reg = <0x1a0 0x1a4 0x1ac 0x1a8>;
								assigned-clocks = <0x28>;
								assigned-clock-rates = <0x45707d40>;
								phandle = <0x28>;
							};

							clock-dpll-iva-m2-8@1b0 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_iva_m2_ck";
								clocks = <0x28>;
								ti,max-div = <0x1f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x1b0>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								assigned-clocks = <0x29>;
								assigned-clock-rates = <0x17257f16>;
								phandle = <0x29>;
							};

							clock-iva-dclk {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "iva_dclk";
								clocks = <0x29>;
								clock-mult = <0x01>;
								clock-div = <0x01>;
								phandle = <0x82>;
							};

							clock-dpll-gpu-byp-mux-23@2e4 {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "dpll_gpu_byp_mux";
								clocks = <0x15 0x1b>;
								ti,bit-shift = <0x17>;
								reg = <0x2e4>;
								phandle = <0x2a>;
							};

							clock@2d8 {
								#clock-cells = <0x00>;
								compatible = "ti,omap4-dpll-clock";
								clock-output-names = "dpll_gpu_ck";
								clocks = <0x15 0x2a>;
								reg = <0x2d8 0x2dc 0x2e4 0x2e0>;
								assigned-clocks = <0x2b>;
								assigned-clock-rates = <0x4c1d7940>;
								phandle = <0x2b>;
							};

							clock-dpll-gpu-m2-8@2e8 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_gpu_m2_ck";
								clocks = <0x2b>;
								ti,max-div = <0x1f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x2e8>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								assigned-clocks = <0x2c>;
								assigned-clock-rates = <0x195f286b>;
								phandle = <0x2c>;
							};

							clock-dpll-core-m2-8@130 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_core_m2_ck";
								clocks = <0x1d>;
								ti,max-div = <0x1f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x130>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0x2d>;
							};

							clock-core-dpll-out-dclk-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "core_dpll_out_dclk_div";
								clocks = <0x2d>;
								clock-mult = <0x01>;
								clock-div = <0x01>;
								phandle = <0x84>;
							};

							clock-dpll-ddr-byp-mux-23@21c {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "dpll_ddr_byp_mux";
								clocks = <0x15 0x1b>;
								ti,bit-shift = <0x17>;
								reg = <0x21c>;
								phandle = <0x2e>;
							};

							clock@210 {
								#clock-cells = <0x00>;
								compatible = "ti,omap4-dpll-clock";
								clock-output-names = "dpll_ddr_ck";
								clocks = <0x15 0x2e>;
								reg = <0x210 0x214 0x21c 0x218>;
								phandle = <0x2f>;
							};

							clock-dpll-ddr-m2-8@220 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_ddr_m2_ck";
								clocks = <0x2f>;
								ti,max-div = <0x1f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x220>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0x76>;
							};

							clock-dpll-gmac-byp-mux-23@2b4 {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "dpll_gmac_byp_mux";
								clocks = <0x15 0x1b>;
								ti,bit-shift = <0x17>;
								reg = <0x2b4>;
								phandle = <0x30>;
							};

							clock@2a8 {
								#clock-cells = <0x00>;
								compatible = "ti,omap4-dpll-clock";
								clock-output-names = "dpll_gmac_ck";
								clocks = <0x15 0x30>;
								reg = <0x2a8 0x2ac 0x2b4 0x2b0>;
								phandle = <0x31>;
							};

							clock-dpll-gmac-m2-8@2b8 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_gmac_m2_ck";
								clocks = <0x31>;
								ti,max-div = <0x1f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x2b8>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0x77>;
							};

							clock-video2-dclk-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "video2_dclk_div";
								clocks = <0x32>;
								clock-mult = <0x01>;
								clock-div = <0x01>;
								phandle = <0x86>;
							};

							clock-video1-dclk-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "video1_dclk_div";
								clocks = <0x33>;
								clock-mult = <0x01>;
								clock-div = <0x01>;
								phandle = <0x87>;
							};

							clock-hdmi-dclk-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "hdmi_dclk_div";
								clocks = <0x34>;
								clock-mult = <0x01>;
								clock-div = <0x01>;
								phandle = <0x88>;
							};

							clock-per-dpll-hs-clk-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "per_dpll_hs_clk_div";
								clocks = <0x1b>;
								clock-mult = <0x01>;
								clock-div = <0x02>;
								phandle = <0x47>;
							};

							clock-usb-dpll-hs-clk-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "usb_dpll_hs_clk_div";
								clocks = <0x1b>;
								clock-mult = <0x01>;
								clock-div = <0x03>;
								phandle = <0x4b>;
							};

							clock-eve-dpll-hs-clk-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "eve_dpll_hs_clk_div";
								clocks = <0x1f>;
								clock-mult = <0x01>;
								clock-div = <0x01>;
								phandle = <0x35>;
							};

							clock-dpll-eve-byp-mux-23@290 {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "dpll_eve_byp_mux";
								clocks = <0x15 0x35>;
								ti,bit-shift = <0x17>;
								reg = <0x290>;
								phandle = <0x36>;
							};

							clock@284 {
								#clock-cells = <0x00>;
								compatible = "ti,omap4-dpll-clock";
								clock-output-names = "dpll_eve_ck";
								clocks = <0x15 0x36>;
								reg = <0x284 0x288 0x290 0x28c>;
								phandle = <0x37>;
							};

							clock-dpll-eve-m2-8@294 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_eve_m2_ck";
								clocks = <0x37>;
								ti,max-div = <0x1f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x294>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0x38>;
							};

							clock-eve-dclk-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "eve_dclk_div";
								clocks = <0x38>;
								clock-mult = <0x01>;
								clock-div = <0x01>;
								phandle = <0x91>;
							};

							clock-dpll-core-h13x2-8@140 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_core_h13x2_ck";
								clocks = <0x1e>;
								ti,max-div = <0x3f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x140>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0xf7>;
							};

							clock-dpll-core-h14x2-8@144 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_core_h14x2_ck";
								clocks = <0x1e>;
								ti,max-div = <0x3f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x144>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0x55>;
							};

							clock-dpll-core-h22x2-8@154 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_core_h22x2_ck";
								clocks = <0x1e>;
								ti,max-div = <0x3f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x154>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0x41>;
							};

							clock-dpll-core-h23x2-8@158 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_core_h23x2_ck";
								clocks = <0x1e>;
								ti,max-div = <0x3f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x158>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0x5a>;
							};

							clock-dpll-core-h24x2-8@15c {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_core_h24x2_ck";
								clocks = <0x1e>;
								ti,max-div = <0x3f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x15c>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0xf8>;
							};

							clock-dpll-ddr-x2 {
								#clock-cells = <0x00>;
								compatible = "ti,omap4-dpll-x2-clock";
								clock-output-names = "dpll_ddr_x2_ck";
								clocks = <0x2f>;
								phandle = <0x39>;
							};

							clock-dpll-ddr-h11x2-8@228 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_ddr_h11x2_ck";
								clocks = <0x39>;
								ti,max-div = <0x3f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x228>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0xf9>;
							};

							clock-dpll-dsp-x2 {
								#clock-cells = <0x00>;
								compatible = "ti,omap4-dpll-x2-clock";
								clock-output-names = "dpll_dsp_x2_ck";
								clocks = <0x24>;
								phandle = <0x3a>;
							};

							clock-dpll-dsp-m3x2-8@248 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_dsp_m3x2_ck";
								clocks = <0x3a>;
								ti,max-div = <0x1f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x248>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								assigned-clocks = <0x3b>;
								assigned-clock-rates = <0x17d78400>;
								phandle = <0x3b>;
							};

							clock-dpll-gmac-x2 {
								#clock-cells = <0x00>;
								compatible = "ti,omap4-dpll-x2-clock";
								clock-output-names = "dpll_gmac_x2_ck";
								clocks = <0x31>;
								phandle = <0x3c>;
							};

							clock-dpll-gmac-h11x2-8@2c0 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_gmac_h11x2_ck";
								clocks = <0x3c>;
								ti,max-div = <0x3f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x2c0>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0x3d>;
							};

							clock-dpll-gmac-h12x2-8@2c4 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_gmac_h12x2_ck";
								clocks = <0x3c>;
								ti,max-div = <0x3f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x2c4>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0xfa>;
							};

							clock-dpll-gmac-h13x2-8@2c8 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_gmac_h13x2_ck";
								clocks = <0x3c>;
								ti,max-div = <0x3f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x2c8>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0xd0>;
							};

							clock-dpll-gmac-m3x2-8@2bc {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_gmac_m3x2_ck";
								clocks = <0x3c>;
								ti,max-div = <0x1f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x2bc>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0xcf>;
							};

							clock-gmii-m-clk-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "gmii_m_clk_div";
								clocks = <0x3d>;
								clock-mult = <0x01>;
								clock-div = <0x02>;
								phandle = <0xfb>;
							};

							clock-hdmi-clk2-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "hdmi_clk2_div";
								clocks = <0x34>;
								clock-mult = <0x01>;
								clock-div = <0x01>;
								phandle = <0xfc>;
							};

							clock-hdmi-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "hdmi_div_clk";
								clocks = <0x34>;
								clock-mult = <0x01>;
								clock-div = <0x01>;
								phandle = <0xfd>;
							};

							clock-l3-iclk-div-4@100 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "l3_iclk_div";
								ti,max-div = <0x02>;
								ti,bit-shift = <0x04>;
								reg = <0x100>;
								clocks = <0x1f>;
								ti,index-power-of-two;
								phandle = <0x0e>;
							};

							clock-l4-root-clk-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "l4_root_clk_div";
								clocks = <0x0e>;
								clock-mult = <0x01>;
								clock-div = <0x02>;
								phandle = <0x0f>;
							};

							clock-video1-clk2-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "video1_clk2_div";
								clocks = <0x3e>;
								clock-mult = <0x01>;
								clock-div = <0x01>;
								phandle = <0xfe>;
							};

							clock-video1-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "video1_div_clk";
								clocks = <0x3e>;
								clock-mult = <0x01>;
								clock-div = <0x01>;
								phandle = <0xff>;
							};

							clock-video2-clk2-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "video2_clk2_div";
								clocks = <0x3f>;
								clock-mult = <0x01>;
								clock-div = <0x01>;
								phandle = <0x100>;
							};

							clock-video2-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "video2_div_clk";
								clocks = <0x3f>;
								clock-mult = <0x01>;
								clock-div = <0x01>;
								phandle = <0x101>;
							};

							clock-dummy {
								#clock-cells = <0x00>;
								compatible = "fixed-clock";
								clock-output-names = "dummy_ck";
								clock-frequency = <0x00>;
								phandle = <0x102>;
							};
						};

						clockdomains {
							phandle = <0x103>;
						};

						clock@300 {
							compatible = "ti,omap4-cm";
							clock-output-names = "mpu_cm";
							reg = <0x300 0x100>;
							#address-cells = <0x01>;
							#size-cells = <0x01>;
							ranges = <0x00 0x300 0x100>;
							phandle = <0x104>;

							clock@20 {
								compatible = "ti,clkctrl";
								clock-output-names = "mpu_clkctrl";
								reg = <0x20 0x04>;
								#clock-cells = <0x02>;
								phandle = <0xa2>;
							};
						};

						clock@400 {
							compatible = "ti,omap4-cm";
							clock-output-names = "dsp1_cm";
							reg = <0x400 0x100>;
							#address-cells = <0x01>;
							#size-cells = <0x01>;
							ranges = <0x00 0x400 0x100>;
							phandle = <0x105>;

							clock@20 {
								compatible = "ti,clkctrl";
								clock-output-names = "dsp1_clkctrl";
								reg = <0x20 0x04>;
								#clock-cells = <0x02>;
								phandle = <0xc4>;
							};
						};

						clock@500 {
							compatible = "ti,omap4-cm";
							clock-output-names = "ipu_cm";
							reg = <0x500 0x100>;
							#address-cells = <0x01>;
							#size-cells = <0x01>;
							ranges = <0x00 0x500 0x100>;
							phandle = <0x106>;

							clock@20 {
								compatible = "ti,clkctrl";
								clock-output-names = "ipu1_clkctrl";
								reg = <0x20 0x04>;
								#clock-cells = <0x02>;
								assigned-clocks = <0x40 0x00 0x18>;
								assigned-clock-parents = <0x41>;
								phandle = <0x40>;
							};

							clock@50 {
								compatible = "ti,clkctrl";
								clock-output-names = "ipu_clkctrl";
								reg = <0x50 0x34>;
								#clock-cells = <0x02>;
								phandle = <0x99>;
							};
						};

						clock@600 {
							compatible = "ti,omap4-cm";
							clock-output-names = "dsp2_cm";
							reg = <0x600 0x100>;
							#address-cells = <0x01>;
							#size-cells = <0x01>;
							ranges = <0x00 0x600 0x100>;
							phandle = <0x107>;

							clock@20 {
								compatible = "ti,clkctrl";
								clock-output-names = "dsp2_clkctrl";
								reg = <0x20 0x04>;
								#clock-cells = <0x02>;
								phandle = <0xca>;
							};
						};

						clock@700 {
							compatible = "ti,omap4-cm";
							clock-output-names = "rtc_cm";
							reg = <0x700 0x60>;
							#address-cells = <0x01>;
							#size-cells = <0x01>;
							ranges = <0x00 0x700 0x60>;
							phandle = <0x108>;

							clock@20 {
								compatible = "ti,clkctrl";
								clock-output-names = "rtc_clkctrl";
								reg = <0x20 0x28>;
								#clock-cells = <0x02>;
								phandle = <0xaf>;
							};
						};

						clock@760 {
							compatible = "ti,omap4-cm";
							clock-output-names = "vpe_cm";
							reg = <0x760 0x0c>;
							#address-cells = <0x01>;
							#size-cells = <0x01>;
							ranges = <0x00 0x760 0x0c>;
							phandle = <0x109>;

							clock@0 {
								compatible = "ti,clkctrl";
								clock-output-names = "vpe_clkctrl";
								reg = <0x00 0x0c>;
								#clock-cells = <0x02>;
								phandle = <0xb5>;
							};
						};
					};
				};

				target-module@8000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x8000 0x04>;
					reg-names = "rev";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x8000 0x2000>;

					cm_core@0 {
						compatible = "ti,dra7-cm-core\0simple-bus";
						#address-cells = <0x01>;
						#size-cells = <0x01>;
						reg = <0x00 0x3000>;
						ranges = <0x00 0x00 0x3000>;
						phandle = <0x10a>;

						clocks {
							#address-cells = <0x01>;
							#size-cells = <0x00>;
							phandle = <0x10b>;

							clock@200 {
								#clock-cells = <0x00>;
								compatible = "ti,omap4-dpll-clock";
								clock-output-names = "dpll_pcie_ref_ck";
								clocks = <0x15 0x15>;
								reg = <0x200 0x204 0x20c 0x208>;
								phandle = <0x42>;
							};

							clock-dpll-pcie-ref-m2ldo-8@210 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_pcie_ref_m2ldo_ck";
								clocks = <0x42>;
								ti,max-div = <0x1f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x210>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0x43>;
							};

							clock-apll-pcie-in-clk-mux-7@4ae06118 {
								compatible = "ti,mux-clock";
								clock-output-names = "apll_pcie_in_clk_mux";
								clocks = <0x43 0x44>;
								#clock-cells = <0x00>;
								reg = <0x21c 0x04>;
								ti,bit-shift = <0x07>;
								phandle = <0x45>;
							};

							clock@21c {
								#clock-cells = <0x00>;
								compatible = "ti,dra7-apll-clock";
								clock-output-names = "apll_pcie_ck";
								clocks = <0x45 0x42>;
								reg = <0x21c 0x220>;
								phandle = <0x46>;
							};

							clock-optfclk-pciephy-div-8@4a00821c {
								compatible = "ti,divider-clock";
								clock-output-names = "optfclk_pciephy_div";
								clocks = <0x46>;
								#clock-cells = <0x00>;
								reg = <0x21c>;
								ti,dividers = <0x02 0x01>;
								ti,bit-shift = <0x08>;
								ti,max-div = <0x02>;
								phandle = <0x64>;
							};

							clock-apll-pcie-clkvcoldo {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "apll_pcie_clkvcoldo";
								clocks = <0x46>;
								clock-mult = <0x01>;
								clock-div = <0x01>;
								phandle = <0x10c>;
							};

							clock-apll-pcie-clkvcoldo-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "apll_pcie_clkvcoldo_div";
								clocks = <0x46>;
								clock-mult = <0x01>;
								clock-div = <0x01>;
								phandle = <0x10d>;
							};

							clock-apll-pcie-m2 {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "apll_pcie_m2_ck";
								clocks = <0x46>;
								clock-mult = <0x01>;
								clock-div = <0x01>;
								phandle = <0x7b>;
							};

							clock-dpll-per-byp-mux-23@14c {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "dpll_per_byp_mux";
								clocks = <0x15 0x47>;
								ti,bit-shift = <0x17>;
								reg = <0x14c>;
								phandle = <0x48>;
							};

							clock@140 {
								#clock-cells = <0x00>;
								compatible = "ti,omap4-dpll-clock";
								clock-output-names = "dpll_per_ck";
								clocks = <0x15 0x48>;
								reg = <0x140 0x144 0x14c 0x148>;
								phandle = <0x49>;
							};

							clock-dpll-per-m2-8@150 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_per_m2_ck";
								clocks = <0x49>;
								ti,max-div = <0x1f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x150>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0x4a>;
							};

							clock-func-96m-aon-dclk-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "func_96m_aon_dclk_div";
								clocks = <0x4a>;
								clock-mult = <0x01>;
								clock-div = <0x01>;
								phandle = <0x89>;
							};

							clock-dpll-usb-byp-mux-23@18c {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "dpll_usb_byp_mux";
								clocks = <0x15 0x4b>;
								ti,bit-shift = <0x17>;
								reg = <0x18c>;
								phandle = <0x4c>;
							};

							clock@180 {
								#clock-cells = <0x00>;
								compatible = "ti,omap4-dpll-j-type-clock";
								clock-output-names = "dpll_usb_ck";
								clocks = <0x15 0x4c>;
								reg = <0x180 0x184 0x18c 0x188>;
								phandle = <0x4d>;
							};

							clock-dpll-usb-m2-8@190 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_usb_m2_ck";
								clocks = <0x4d>;
								ti,max-div = <0x7f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x190>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0x51>;
							};

							clock-dpll-pcie-ref-m2-8@210 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_pcie_ref_m2_ck";
								clocks = <0x42>;
								ti,max-div = <0x7f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x210>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0x7a>;
							};

							clock-dpll-per-x2 {
								#clock-cells = <0x00>;
								compatible = "ti,omap4-dpll-x2-clock";
								clock-output-names = "dpll_per_x2_ck";
								clocks = <0x49>;
								phandle = <0x4e>;
							};

							clock-dpll-per-h11x2-8@158 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_per_h11x2_ck";
								clocks = <0x4e>;
								ti,max-div = <0x3f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x158>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0x4f>;
							};

							clock-dpll-per-h12x2-8@15c {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_per_h12x2_ck";
								clocks = <0x4e>;
								ti,max-div = <0x3f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x15c>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0x10e>;
							};

							clock-dpll-per-h13x2-8@160 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_per_h13x2_ck";
								clocks = <0x4e>;
								ti,max-div = <0x3f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x160>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0x10f>;
							};

							clock-dpll-per-h14x2-8@164 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_per_h14x2_ck";
								clocks = <0x4e>;
								ti,max-div = <0x3f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x164>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0x56>;
							};

							clock-dpll-per-m2x2-8@150 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dpll_per_m2x2_ck";
								clocks = <0x4e>;
								ti,max-div = <0x1f>;
								ti,autoidle-shift = <0x08>;
								reg = <0x150>;
								ti,index-starts-at-one;
								ti,invert-autoidle-bit;
								phandle = <0x50>;
							};

							clock-dpll-usb-clkdcoldo {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "dpll_usb_clkdcoldo";
								clocks = <0x4d>;
								clock-mult = <0x01>;
								clock-div = <0x01>;
								phandle = <0x53>;
							};

							clock-func-128m {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "func_128m_clk";
								clocks = <0x4f>;
								clock-mult = <0x01>;
								clock-div = <0x02>;
								phandle = <0x110>;
							};

							clock-func-12m-fclk {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "func_12m_fclk";
								clocks = <0x50>;
								clock-mult = <0x01>;
								clock-div = <0x10>;
								phandle = <0x111>;
							};

							clock-func-24m {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "func_24m_clk";
								clocks = <0x4a>;
								clock-mult = <0x01>;
								clock-div = <0x04>;
								phandle = <0x112>;
							};

							clock-func-48m-fclk {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "func_48m_fclk";
								clocks = <0x50>;
								clock-mult = <0x01>;
								clock-div = <0x04>;
								phandle = <0x113>;
							};

							clock-func-96m-fclk {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "func_96m_fclk";
								clocks = <0x50>;
								clock-mult = <0x01>;
								clock-div = <0x02>;
								phandle = <0x114>;
							};

							clock-l3init-60m@104 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "l3init_60m_fclk";
								clocks = <0x51>;
								reg = <0x104>;
								ti,dividers = <0x01 0x08>;
								phandle = <0x115>;
							};

							clock-clkout2-8@6b0 {
								#clock-cells = <0x00>;
								compatible = "ti,gate-clock";
								clock-output-names = "clkout2_clk";
								clocks = <0x52>;
								ti,bit-shift = <0x08>;
								reg = <0x6b0>;
								phandle = <0x116>;
							};

							clock-l3init-960m-gfclk-8@6c0 {
								#clock-cells = <0x00>;
								compatible = "ti,gate-clock";
								clock-output-names = "l3init_960m_gfclk";
								clocks = <0x53>;
								ti,bit-shift = <0x08>;
								reg = <0x6c0>;
								phandle = <0x117>;
							};

							clock-usb-phy1-always-on-clk32k-8@640 {
								#clock-cells = <0x00>;
								compatible = "ti,gate-clock";
								clock-output-names = "usb_phy1_always_on_clk32k";
								clocks = <0x54>;
								ti,bit-shift = <0x08>;
								reg = <0x640>;
								phandle = <0x5f>;
							};

							clock-usb-phy2-always-on-clk32k-8@688 {
								#clock-cells = <0x00>;
								compatible = "ti,gate-clock";
								clock-output-names = "usb_phy2_always_on_clk32k";
								clocks = <0x54>;
								ti,bit-shift = <0x08>;
								reg = <0x688>;
								phandle = <0x60>;
							};

							clock-usb-phy3-always-on-clk32k-8@698 {
								#clock-cells = <0x00>;
								compatible = "ti,gate-clock";
								clock-output-names = "usb_phy3_always_on_clk32k";
								clocks = <0x54>;
								ti,bit-shift = <0x08>;
								reg = <0x698>;
								phandle = <0x61>;
							};

							clock-gpu-core-gclk-mux-24@1220 {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "gpu_core_gclk_mux";
								clocks = <0x55 0x56 0x2c>;
								ti,bit-shift = <0x18>;
								reg = <0x1220>;
								assigned-clocks = <0x57>;
								assigned-clock-parents = <0x2c>;
								phandle = <0x57>;
							};

							clock-gpu-hyd-gclk-mux-26@1220 {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "gpu_hyd_gclk_mux";
								clocks = <0x55 0x56 0x2c>;
								ti,bit-shift = <0x1a>;
								reg = <0x1220>;
								assigned-clocks = <0x58>;
								assigned-clock-parents = <0x2c>;
								phandle = <0x58>;
							};

							clock-l3instr-ts-gclk-div-24@e50 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "l3instr_ts_gclk_div";
								clocks = <0x59>;
								ti,bit-shift = <0x18>;
								reg = <0xe50>;
								ti,dividers = <0x08 0x10 0x20>;
								phandle = <0x118>;
							};

							clock-vip1-gclk-mux-24@1020 {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "vip1_gclk_mux";
								clocks = <0x0e 0x5a>;
								ti,bit-shift = <0x18>;
								reg = <0x1020>;
								phandle = <0x119>;
							};

							clock-vip2-gclk-mux-24@1028 {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "vip2_gclk_mux";
								clocks = <0x0e 0x5a>;
								ti,bit-shift = <0x18>;
								reg = <0x1028>;
								phandle = <0x11a>;
							};

							clock-vip3-gclk-mux-24@1030 {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "vip3_gclk_mux";
								clocks = <0x0e 0x5a>;
								ti,bit-shift = <0x18>;
								reg = <0x1030>;
								phandle = <0x11b>;
							};
						};

						clockdomains {
							phandle = <0x11c>;

							clock-coreaon-clkdm {
								compatible = "ti,clockdomain";
								clock-output-names = "coreaon_clkdm";
								clocks = <0x4d>;
								phandle = <0x11d>;
							};
						};

						clock@600 {
							compatible = "ti,omap4-cm";
							clock-output-names = "coreaon_cm";
							reg = <0x600 0x100>;
							#address-cells = <0x01>;
							#size-cells = <0x01>;
							ranges = <0x00 0x600 0x100>;
							phandle = <0x11e>;

							clock@20 {
								compatible = "ti,clkctrl";
								clock-output-names = "coreaon_clkctrl";
								reg = <0x20 0x1c>;
								#clock-cells = <0x02>;
								phandle = <0x65>;
							};
						};

						clock@700 {
							compatible = "ti,omap4-cm";
							clock-output-names = "l3main1_cm";
							reg = <0x700 0x100>;
							#address-cells = <0x01>;
							#size-cells = <0x01>;
							ranges = <0x00 0x700 0x100>;
							phandle = <0x11f>;

							clock@20 {
								compatible = "ti,clkctrl";
								clock-output-names = "l3main1_clkctrl";
								reg = <0x20 0x74>;
								#clock-cells = <0x02>;
								phandle = <0x08>;
							};
						};

						clock@900 {
							compatible = "ti,omap4-cm";
							clock-output-names = "ipu2_cm";
							reg = <0x900 0x100>;
							#address-cells = <0x01>;
							#size-cells = <0x01>;
							ranges = <0x00 0x900 0x100>;
							phandle = <0x120>;

							clock@20 {
								compatible = "ti,clkctrl";
								clock-output-names = "ipu2_clkctrl";
								reg = <0x20 0x04>;
								#clock-cells = <0x02>;
								phandle = <0xc0>;
							};
						};

						clock@a00 {
							compatible = "ti,omap4-cm";
							clock-output-names = "dma_cm";
							reg = <0xa00 0x100>;
							#address-cells = <0x01>;
							#size-cells = <0x01>;
							ranges = <0x00 0xa00 0x100>;
							phandle = <0x121>;

							clock@20 {
								compatible = "ti,clkctrl";
								clock-output-names = "dma_clkctrl";
								reg = <0x20 0x04>;
								#clock-cells = <0x02>;
								phandle = <0x5d>;
							};
						};

						clock@b00 {
							compatible = "ti,omap4-cm";
							clock-output-names = "emif_cm";
							reg = <0xb00 0x100>;
							#address-cells = <0x01>;
							#size-cells = <0x01>;
							ranges = <0x00 0xb00 0x100>;
							phandle = <0x122>;

							clock@20 {
								compatible = "ti,clkctrl";
								clock-output-names = "emif_clkctrl";
								reg = <0x20 0x04>;
								#clock-cells = <0x02>;
								phandle = <0x123>;
							};
						};

						clock@c00 {
							compatible = "ti,omap4-cm";
							clock-output-names = "atl_cm";
							reg = <0xc00 0x100>;
							#address-cells = <0x01>;
							#size-cells = <0x01>;
							ranges = <0x00 0xc00 0x100>;
							phandle = <0x124>;

							clock@0 {
								compatible = "ti,clkctrl";
								clock-output-names = "atl_clkctrl";
								reg = <0x00 0x04>;
								#clock-cells = <0x02>;
								phandle = <0x14>;
							};
						};

						clock@d00 {
							compatible = "ti,omap4-cm";
							clock-output-names = "l4cfg_cm";
							reg = <0xd00 0x100>;
							#address-cells = <0x01>;
							#size-cells = <0x01>;
							ranges = <0x00 0xd00 0x100>;
							phandle = <0x125>;

							clock@20 {
								compatible = "ti,clkctrl";
								clock-output-names = "l4cfg_clkctrl";
								reg = <0x20 0x84>;
								#clock-cells = <0x02>;
								phandle = <0x0c>;
							};
						};

						clock@e00 {
							compatible = "ti,omap4-cm";
							clock-output-names = "l3instr_cm";
							reg = <0xe00 0x100>;
							#address-cells = <0x01>;
							#size-cells = <0x01>;
							ranges = <0x00 0xe00 0x100>;
							phandle = <0x126>;

							clock@20 {
								compatible = "ti,clkctrl";
								clock-output-names = "l3instr_clkctrl";
								reg = <0x20 0x0c>;
								#clock-cells = <0x02>;
								phandle = <0x09>;
							};
						};

						clock@f00 {
							compatible = "ti,omap4-cm";
							clock-output-names = "iva_cm";
							reg = <0xf00 0x100>;
							#address-cells = <0x01>;
							#size-cells = <0x01>;
							ranges = <0x00 0xf00 0x100>;
							phandle = <0x127>;

							clock@20 {
								compatible = "ti,clkctrl";
								clock-output-names = "iva_clkctrl";
								reg = <0x20 0x0c>;
								#clock-cells = <0x02>;
								phandle = <0xc9>;
							};
						};

						clock@1000 {
							compatible = "ti,omap4-cm";
							clock-output-names = "cam_cm";
							reg = <0x1000 0x100>;
							#address-cells = <0x01>;
							#size-cells = <0x01>;
							ranges = <0x00 0x1000 0x100>;
							phandle = <0x128>;

							clock@20 {
								compatible = "ti,clkctrl";
								clock-output-names = "cam_clkctrl";
								reg = <0x20 0x2c>;
								#clock-cells = <0x02>;
								phandle = <0xb3>;
							};
						};

						clock@1100 {
							compatible = "ti,omap4-cm";
							clock-output-names = "dss_cm";
							reg = <0x1100 0x100>;
							#address-cells = <0x01>;
							#size-cells = <0x01>;
							ranges = <0x00 0x1100 0x100>;
							phandle = <0x129>;

							clock@20 {
								compatible = "ti,clkctrl";
								clock-output-names = "dss_clkctrl";
								reg = <0x20 0x14>;
								#clock-cells = <0x02>;
								phandle = <0xc7>;
							};
						};

						clock@1200 {
							compatible = "ti,omap4-cm";
							clock-output-names = "gpu_cm";
							reg = <0x1200 0x100>;
							#address-cells = <0x01>;
							#size-cells = <0x01>;
							ranges = <0x00 0x1200 0x100>;
							phandle = <0x12a>;

							clock@20 {
								compatible = "ti,clkctrl";
								clock-output-names = "gpu_clkctrl";
								reg = <0x20 0x04>;
								#clock-cells = <0x02>;
								phandle = <0xc6>;
							};
						};

						clock@1300 {
							compatible = "ti,omap4-cm";
							clock-output-names = "l3init_cm";
							reg = <0x1300 0x100>;
							#address-cells = <0x01>;
							#size-cells = <0x01>;
							ranges = <0x00 0x1300 0x100>;
							phandle = <0x12b>;

							clock@20 {
								compatible = "ti,clkctrl";
								clock-output-names = "l3init_clkctrl";
								reg = <0x20 0x6c 0xe0 0x14>;
								#clock-cells = <0x02>;
								phandle = <0x5e>;
							};

							clock@b0 {
								compatible = "ti,clkctrl";
								clock-output-names = "pcie_clkctrl";
								reg = <0xb0 0x0c>;
								#clock-cells = <0x02>;
								phandle = <0x63>;
							};

							clock@d0 {
								compatible = "ti,clkctrl";
								clock-output-names = "gmac_clkctrl";
								reg = <0xd0 0x04>;
								#clock-cells = <0x02>;
								phandle = <0xab>;
							};
						};

						clock@1700 {
							compatible = "ti,omap4-cm";
							clock-output-names = "l4per_cm";
							reg = <0x1700 0x300>;
							#address-cells = <0x01>;
							#size-cells = <0x01>;
							ranges = <0x00 0x1700 0x300>;
							phandle = <0x12c>;

							clock@28 {
								compatible = "ti,clkctrl";
								clock-output-names = "l4per_clkctrl";
								reg = <0x28 0x64 0xa0 0x24 0xf0 0x3c 0x140 0x1c 0x170 0x04>;
								#clock-cells = <0x02>;
								assigned-clocks = <0x5b 0x15c 0x18>;
								assigned-clock-parents = <0x5c>;
								phandle = <0x96>;
							};

							clock@1a0 {
								compatible = "ti,clkctrl";
								clock-output-names = "l4sec_clkctrl";
								reg = <0x1a0 0x2c>;
								#clock-cells = <0x02>;
								phandle = <0x9a>;
							};

							clock@c {
								compatible = "ti,clkctrl";
								clock-output-names = "l4per2_clkctrl";
								reg = <0x0c 0x04 0x18 0x0c 0x90 0x0c 0xc4 0x04 0x138 0x04 0x160 0x0c 0x178 0x24 0x1d0 0x3c>;
								#clock-cells = <0x02>;
								phandle = <0x5b>;
							};

							clock@14 {
								compatible = "ti,clkctrl";
								clock-output-names = "l4per3_clkctrl";
								reg = <0x14 0x04 0xc8 0x14 0x130 0x04>;
								#clock-cells = <0x02>;
								phandle = <0xae>;
							};
						};
					};
				};

				target-module@56000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x56000 0x04 0x5602c 0x04 0x56028 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x323>;
					ti,sysc-midle = <0x00 0x01 0x02 0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x5d 0x00 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x56000 0x1000>;

					dma-controller@0 {
						compatible = "ti,omap4430-sdma\0ti,omap-sdma";
						reg = <0x00 0x1000>;
						interrupts = <0x00 0x07 0x04 0x00 0x08 0x04 0x00 0x09 0x04 0x00 0x0a 0x04>;
						#dma-cells = <0x01>;
						dma-channels = <0x20>;
						dma-requests = <0x7f>;
						phandle = <0x12>;
					};
				};

				target-module@5e000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x5e000 0x2000>;
				};

				target-module@80000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x80000 0x04 0x80010 0x04 0x80014 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					ti,syss-mask = <0x01>;
					clocks = <0x5e 0xc0 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x80000 0x8000>;

					ocp2scp@0 {
						compatible = "ti,omap-ocp2scp";
						#address-cells = <0x01>;
						#size-cells = <0x01>;
						ranges = <0x00 0x00 0x8000>;
						reg = <0x00 0x20>;

						phy@4000 {
							compatible = "ti,dra7x-usb2\0ti,omap-usb2";
							reg = <0x4000 0x400>;
							syscon-phy-power = <0x0d 0x300>;
							clocks = <0x5f 0x5e 0xd0 0x08>;
							clock-names = "wkupclk\0refclk";
							#phy-cells = <0x00>;
							phandle = <0xb0>;
						};

						phy@5000 {
							compatible = "ti,dra7x-usb2-phy2\0ti,omap-usb2";
							reg = <0x5000 0x400>;
							syscon-phy-power = <0x0d 0xe74>;
							clocks = <0x60 0x5e 0x20 0x08>;
							clock-names = "wkupclk\0refclk";
							#phy-cells = <0x00>;
							phandle = <0xb2>;
						};

						phy@4400 {
							compatible = "ti,omap-usb3";
							reg = <0x4400 0x80 0x4800 0x64 0x4c00 0x40>;
							reg-names = "phy_rx\0phy_tx\0pll_ctrl";
							syscon-phy-power = <0x0d 0x370>;
							clocks = <0x61 0x15 0x5e 0xd0 0x08>;
							clock-names = "wkupclk\0sysclk\0refclk";
							#phy-cells = <0x00>;
							phandle = <0xb1>;
						};
					};
				};

				target-module@90000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x90000 0x04 0x90010 0x04 0x90014 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					ti,syss-mask = <0x01>;
					clocks = <0x5e 0xc8 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x90000 0x8000>;

					ocp2scp@0 {
						compatible = "ti,omap-ocp2scp";
						#address-cells = <0x01>;
						#size-cells = <0x01>;
						ranges = <0x00 0x00 0x8000>;
						reg = <0x00 0x20>;

						pciephy@4000 {
							compatible = "ti,phy-pipe3-pcie";
							reg = <0x4000 0x80 0x4400 0x64>;
							reg-names = "phy_rx\0phy_tx";
							syscon-phy-power = <0x62 0x1c>;
							syscon-pcs = <0x62 0x10>;
							clocks = <0x42 0x43 0x63 0x00 0x08 0x63 0x00 0x09 0x63 0x00 0x0a 0x64 0x15>;
							clock-names = "dpll_ref\0dpll_ref_m2\0wkupclk\0refclk\0div-clk\0phy-div\0sysclk";
							#phy-cells = <0x00>;
							phandle = <0xb6>;
						};

						pciephy@5000 {
							compatible = "ti,phy-pipe3-pcie";
							reg = <0x5000 0x80 0x5400 0x64>;
							reg-names = "phy_rx\0phy_tx";
							syscon-phy-power = <0x62 0x20>;
							syscon-pcs = <0x62 0x10>;
							clocks = <0x42 0x43 0x63 0x08 0x08 0x63 0x08 0x09 0x63 0x08 0x0a 0x64 0x15>;
							clock-names = "dpll_ref\0dpll_ref_m2\0wkupclk\0refclk\0div-clk\0phy-div\0sysclk";
							#phy-cells = <0x00>;
							status = "disabled";
							phandle = <0xb9>;
						};

						phy@6000 {
							compatible = "ti,phy-pipe3-sata";
							reg = <0x6000 0x80 0x6400 0x64 0x6800 0x40>;
							reg-names = "phy_rx\0phy_tx\0pll_ctrl";
							syscon-phy-power = <0x0d 0x374>;
							clocks = <0x15 0x5e 0x68 0x08>;
							clock-names = "sysclk\0refclk";
							syscon-pllreset = <0x0d 0x3fc>;
							#phy-cells = <0x00>;
							phandle = <0x67>;
						};
					};
				};

				target-module@a0000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xa0000 0x8000>;
				};

				target-module@d9000 {
					compatible = "ti,sysc-omap4-sr\0ti,sysc";
					reg = <0xd9038 0x04>;
					reg-names = "sysc";
					ti,sysc-mask = <0x4000000>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x65 0x08 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xd9000 0x1000>;
				};

				target-module@dd000 {
					compatible = "ti,sysc-omap4-sr\0ti,sysc";
					reg = <0xdd038 0x04>;
					reg-names = "sysc";
					ti,sysc-mask = <0x4000000>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x65 0x18 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xdd000 0x1000>;
				};

				target-module@e0000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xe0000 0x1000>;
				};

				target-module@f4000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0xf4000 0x04 0xf4010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x01>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x0c 0x10 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xf4000 0x1000>;

					mailbox@0 {
						compatible = "ti,omap4-mailbox";
						reg = <0x00 0x200>;
						interrupts = <0x00 0x15 0x04 0x00 0x87 0x04 0x00 0x86 0x04>;
						#mbox-cells = <0x01>;
						ti,mbox-num-users = <0x03>;
						ti,mbox-num-fifos = <0x08>;
						status = "disabled";
						phandle = <0x12d>;
					};
				};

				target-module@f6000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0xf6000 0x04 0xf6010 0x04 0xf6014 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x07>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					ti,syss-mask = <0x01>;
					clocks = <0x0c 0x08 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xf6000 0x1000>;

					spinlock@0 {
						compatible = "ti,omap4-hwspinlock";
						reg = <0x00 0x1000>;
						#hwlock-cells = <0x01>;
						phandle = <0x12e>;
					};
				};
			};

			segment@100000 {
				compatible = "simple-pm-bus";
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				ranges = <0x2000 0x102000 0x1000 0x3000 0x103000 0x1000 0x8000 0x108000 0x1000 0x9000 0x109000 0x1000 0x40000 0x140000 0x10000 0x50000 0x150000 0x1000 0x51000 0x151000 0x1000 0x52000 0x152000 0x1000 0x53000 0x153000 0x1000 0x54000 0x154000 0x1000 0x55000 0x155000 0x1000 0x56000 0x156000 0x1000 0x57000 0x157000 0x1000 0x58000 0x158000 0x1000 0x5b000 0x15b000 0x1000 0x5c000 0x15c000 0x1000 0x5d000 0x15d000 0x1000 0x5e000 0x15e000 0x1000 0x5f000 0x15f000 0x1000 0x60000 0x160000 0x1000 0x61000 0x161000 0x1000 0x62000 0x162000 0x1000 0x63000 0x163000 0x1000 0x64000 0x164000 0x1000 0x65000 0x165000 0x1000 0x66000 0x166000 0x1000 0x67000 0x167000 0x1000 0x68000 0x168000 0x1000 0x6d000 0x16d000 0x1000 0x6e000 0x16e000 0x1000 0x71000 0x171000 0x1000 0x72000 0x172000 0x1000 0x73000 0x173000 0x1000 0x74000 0x174000 0x1000 0x75000 0x175000 0x1000 0x76000 0x176000 0x1000 0x77000 0x177000 0x1000 0x78000 0x178000 0x1000 0x81000 0x181000 0x1000 0x82000 0x182000 0x1000 0x83000 0x183000 0x1000 0x84000 0x184000 0x1000 0x85000 0x185000 0x1000 0x86000 0x186000 0x1000 0x87000 0x187000 0x1000 0x88000 0x188000 0x1000 0x69000 0x169000 0x1000 0x6a000 0x16a000 0x1000 0x79000 0x179000 0x1000 0x7a000 0x17a000 0x1000 0x6b000 0x16b000 0x1000 0x6c000 0x16c000 0x1000 0x7b000 0x17b000 0x1000 0x7c000 0x17c000 0x1000 0x7d000 0x17d000 0x1000 0x7e000 0x17e000 0x1000 0x59000 0x159000 0x1000 0x5a000 0x15a000 0x1000>;

				target-module@2000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x2000 0x1000>;
				};

				target-module@8000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x8000 0x1000>;
				};

				target-module@40000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x400fc 0x04 0x41100 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-midle = <0x00 0x01 0x02>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					power-domains = <0x66>;
					clocks = <0x5e 0x68 0x00>;
					clock-names = "fck";
					#size-cells = <0x01>;
					#address-cells = <0x01>;
					ranges = <0x00 0x40000 0x10000>;

					sata@0 {
						compatible = "snps,dwc-ahci";
						reg = <0x00 0x1100 0x1100 0x08>;
						interrupts = <0x00 0x31 0x04>;
						phys = <0x67>;
						phy-names = "sata-phy";
						clocks = <0x5e 0x68 0x08>;
						ports-implemented = <0x01>;
						phandle = <0x12f>;
					};
				};

				target-module@51000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x51000 0x1000>;
				};

				target-module@53000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x53000 0x1000>;
				};

				target-module@55000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x55000 0x1000>;
				};

				target-module@57000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x57000 0x1000>;
				};

				target-module@59000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x59000 0x1000>;
				};

				target-module@5b000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x5b000 0x1000>;
				};

				target-module@5d000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x5d000 0x1000>;
				};

				target-module@5f000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x5f000 0x1000>;
				};

				target-module@61000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x61000 0x1000>;
				};

				target-module@63000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x63000 0x1000>;
				};

				target-module@65000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x65000 0x1000>;
				};

				target-module@67000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x67000 0x1000>;
				};

				target-module@69000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x69000 0x1000>;
				};

				target-module@6b000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x6b000 0x1000>;
				};

				target-module@6d000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x6d000 0x1000>;
				};

				target-module@71000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x71000 0x1000>;
				};

				target-module@73000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x73000 0x1000>;
				};

				target-module@75000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x75000 0x1000>;
				};

				target-module@77000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x77000 0x1000>;
				};

				target-module@79000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x79000 0x1000>;
				};

				target-module@7b000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x7b000 0x1000>;
				};

				target-module@7d000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x7d000 0x1000>;
				};

				target-module@81000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x81000 0x1000>;
				};

				target-module@83000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x83000 0x1000>;
				};

				target-module@85000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x85000 0x1000>;
				};

				target-module@87000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x87000 0x1000>;
				};
			};

			segment@200000 {
				compatible = "simple-pm-bus";
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				ranges = <0x18000 0x218000 0x1000 0x19000 0x219000 0x1000 0x00 0x200000 0x1000 0x1000 0x201000 0x1000 0xa000 0x20a000 0x1000 0xb000 0x20b000 0x1000 0xc000 0x20c000 0x1000 0xd000 0x20d000 0x1000 0xe000 0x20e000 0x1000 0xf000 0x20f000 0x1000 0x10000 0x210000 0x1000 0x11000 0x211000 0x1000 0x12000 0x212000 0x1000 0x13000 0x213000 0x1000 0x14000 0x214000 0x1000 0x15000 0x215000 0x1000 0x2a000 0x22a000 0x1000 0x2b000 0x22b000 0x1000 0x1c000 0x21c000 0x1000 0x1d000 0x21d000 0x1000 0x1e000 0x21e000 0x1000 0x1f000 0x21f000 0x1000 0x20000 0x220000 0x1000 0x21000 0x221000 0x1000 0x24000 0x224000 0x1000 0x25000 0x225000 0x1000 0x26000 0x226000 0x1000 0x27000 0x227000 0x1000 0x2c000 0x22c000 0x1000 0x2d000 0x22d000 0x1000 0x2e000 0x22e000 0x1000 0x2f000 0x22f000 0x1000 0x30000 0x230000 0x1000 0x31000 0x231000 0x1000 0x32000 0x232000 0x1000 0x33000 0x233000 0x1000 0x34000 0x234000 0x1000 0x35000 0x235000 0x1000 0x36000 0x236000 0x1000 0x37000 0x237000 0x1000 0x1a000 0x21a000 0x1000 0x1b000 0x21b000 0x1000>;

				target-module@0 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x00 0x1000>;
				};

				target-module@a000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xa000 0x1000>;
				};

				target-module@c000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xc000 0x1000>;
				};

				target-module@e000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xe000 0x1000>;
				};

				target-module@10000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x10000 0x1000>;
				};

				target-module@12000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x12000 0x1000>;
				};

				target-module@14000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x14000 0x1000>;
				};

				target-module@18000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x18000 0x1000>;
				};

				target-module@1a000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x1a000 0x1000>;
				};

				target-module@1c000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x1c000 0x1000>;
				};

				target-module@1e000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x1e000 0x1000>;
				};

				target-module@20000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x20000 0x1000>;
				};

				target-module@24000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x24000 0x1000>;
				};

				target-module@26000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x26000 0x1000>;
				};

				target-module@2a000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x2a000 0x1000>;
				};

				target-module@2c000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x2c000 0x1000>;
				};

				target-module@2e000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x2e000 0x1000>;
				};

				target-module@30000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x30000 0x1000>;
				};

				target-module@32000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x32000 0x1000>;
				};

				target-module@34000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x34000 0x1000>;
				};

				target-module@36000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x36000 0x1000>;
				};
			};
		};

		interconnect@4ae00000 {
			compatible = "ti,dra7-l4-wkup\0simple-pm-bus";
			power-domains = <0x68>;
			clocks = <0x69 0x00 0x00>;
			clock-names = "fck";
			reg = <0x4ae00000 0x800 0x4ae00800 0x800 0x4ae01000 0x1000>;
			reg-names = "ap\0la\0ia0";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x4ae00000 0x10000 0x10000 0x4ae10000 0x10000 0x20000 0x4ae20000 0x10000 0x30000 0x4ae30000 0x10000>;
			phandle = <0x130>;

			segment@0 {
				compatible = "simple-pm-bus";
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				ranges = <0x00 0x00 0x800 0x1000 0x1000 0x1000 0x800 0x800 0x800 0x6000 0x6000 0x2000 0x8000 0x8000 0x1000 0x4000 0x4000 0x1000 0x5000 0x5000 0x1000 0xc000 0xc000 0x1000 0xd000 0xd000 0x1000>;

				target-module@4000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x4000 0x04 0x4010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x69 0x30 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x4000 0x1000>;

					counter@0 {
						compatible = "ti,omap-counter32k";
						reg = <0x00 0x40>;
						phandle = <0x131>;
					};
				};

				target-module@6000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x6000 0x04>;
					reg-names = "rev";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x6000 0x2000>;

					prm@0 {
						compatible = "ti,dra7-prm\0simple-bus";
						reg = <0x00 0x3000>;
						interrupts = <0x00 0x06 0x04>;
						#address-cells = <0x01>;
						#size-cells = <0x01>;
						ranges = <0x00 0x00 0x3000>;
						phandle = <0x132>;

						clocks {
							#address-cells = <0x01>;
							#size-cells = <0x00>;
							phandle = <0x133>;

							clock-sys-clkin1@110 {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "sys_clkin1";
								clocks = <0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70>;
								reg = <0x110>;
								ti,index-starts-at-one;
								phandle = <0x15>;
							};

							clock-abe-dpll-sys-clk-mux@118 {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "abe_dpll_sys_clk_mux";
								clocks = <0x15 0x71>;
								reg = <0x118>;
								phandle = <0x72>;
							};

							clock-abe-dpll-bypass-clk-mux@114 {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "abe_dpll_bypass_clk_mux";
								clocks = <0x72 0x54>;
								reg = <0x114>;
								phandle = <0x17>;
							};

							clock-abe-dpll-clk-mux@10c {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "abe_dpll_clk_mux";
								clocks = <0x72 0x54>;
								reg = <0x10c>;
								phandle = <0x16>;
							};

							clock-abe-24m@11c {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "abe_24m_fclk";
								clocks = <0x1a>;
								reg = <0x11c>;
								ti,dividers = <0x08 0x10>;
								phandle = <0x5c>;
							};

							clock-aess@178 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "aess_fclk";
								clocks = <0x73>;
								reg = <0x178>;
								ti,max-div = <0x02>;
								phandle = <0x74>;
							};

							clock-abe-giclk-div@174 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "abe_giclk_div";
								clocks = <0x74>;
								reg = <0x174>;
								ti,max-div = <0x02>;
								phandle = <0x134>;
							};

							clock-abe-lp-clk-div@1d8 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "abe_lp_clk_div";
								clocks = <0x1a>;
								reg = <0x1d8>;
								ti,dividers = <0x10 0x20>;
								phandle = <0x94>;
							};

							clock-abe-sys-clk-div@120 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "abe_sys_clk_div";
								clocks = <0x15>;
								reg = <0x120>;
								ti,max-div = <0x02>;
								phandle = <0x135>;
							};

							clock-adc-gfclk-mux@1dc {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "adc_gfclk_mux";
								clocks = <0x15 0x71 0x54>;
								reg = <0x1dc>;
								phandle = <0x136>;
							};

							clock-sys-clk1-dclk-div@1c8 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "sys_clk1_dclk_div";
								clocks = <0x15>;
								ti,max-div = <0x40>;
								reg = <0x1c8>;
								ti,index-power-of-two;
								phandle = <0x7d>;
							};

							clock-sys-clk2-dclk-div@1cc {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "sys_clk2_dclk_div";
								clocks = <0x71>;
								ti,max-div = <0x40>;
								reg = <0x1cc>;
								ti,index-power-of-two;
								phandle = <0x7e>;
							};

							clock-per-abe-x1-dclk-div@1bc {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "per_abe_x1_dclk_div";
								clocks = <0x75>;
								ti,max-div = <0x40>;
								reg = <0x1bc>;
								ti,index-power-of-two;
								phandle = <0x7f>;
							};

							clock-dsp-gclk-div@18c {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "dsp_gclk_div";
								clocks = <0x25>;
								ti,max-div = <0x40>;
								reg = <0x18c>;
								ti,index-power-of-two;
								phandle = <0x81>;
							};

							clock-gpu-dclk@1a0 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "gpu_dclk";
								clocks = <0x2c>;
								ti,max-div = <0x40>;
								reg = <0x1a0>;
								ti,index-power-of-two;
								phandle = <0x83>;
							};

							clock-emif-phy-dclk-div@190 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "emif_phy_dclk_div";
								clocks = <0x76>;
								ti,max-div = <0x40>;
								reg = <0x190>;
								ti,index-power-of-two;
								phandle = <0x85>;
							};

							clock-gmac-250m-dclk-div@19c {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "gmac_250m_dclk_div";
								clocks = <0x77>;
								ti,max-div = <0x40>;
								reg = <0x19c>;
								ti,index-power-of-two;
								phandle = <0x78>;
							};

							clock-gmac-main {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "gmac_main_clk";
								clocks = <0x78>;
								clock-mult = <0x01>;
								clock-div = <0x02>;
								phandle = <0xac>;
							};

							clock-l3init-480m-dclk-div@1ac {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "l3init_480m_dclk_div";
								clocks = <0x51>;
								ti,max-div = <0x40>;
								reg = <0x1ac>;
								ti,index-power-of-two;
								phandle = <0x8a>;
							};

							clock-usb-otg-dclk-div@184 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "usb_otg_dclk_div";
								clocks = <0x79>;
								ti,max-div = <0x40>;
								reg = <0x184>;
								ti,index-power-of-two;
								phandle = <0x8b>;
							};

							clock-sata-dclk-div@1c0 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "sata_dclk_div";
								clocks = <0x15>;
								ti,max-div = <0x40>;
								reg = <0x1c0>;
								ti,index-power-of-two;
								phandle = <0x8c>;
							};

							clock-pcie2-dclk-div@1b8 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "pcie2_dclk_div";
								clocks = <0x7a>;
								ti,max-div = <0x40>;
								reg = <0x1b8>;
								ti,index-power-of-two;
								phandle = <0x8d>;
							};

							clock-pcie-dclk-div@1b4 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "pcie_dclk_div";
								clocks = <0x7b>;
								ti,max-div = <0x40>;
								reg = <0x1b4>;
								ti,index-power-of-two;
								phandle = <0x8e>;
							};

							clock-emu-dclk-div@194 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "emu_dclk_div";
								clocks = <0x15>;
								ti,max-div = <0x40>;
								reg = <0x194>;
								ti,index-power-of-two;
								phandle = <0x8f>;
							};

							clock-secure-32k-dclk-div@1c4 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "secure_32k_dclk_div";
								clocks = <0x7c>;
								ti,max-div = <0x40>;
								reg = <0x1c4>;
								ti,index-power-of-two;
								phandle = <0x90>;
							};

							clock-clkoutmux0-clk-mux@158 {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "clkoutmux0_clk_mux";
								clocks = <0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x78 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91>;
								reg = <0x158>;
								phandle = <0x137>;
							};

							clock-clkoutmux1-clk-mux@15c {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "clkoutmux1_clk_mux";
								clocks = <0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x78 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91>;
								reg = <0x15c>;
								phandle = <0x138>;
							};

							clock-clkoutmux2-clk-mux@160 {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "clkoutmux2_clk_mux";
								clocks = <0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x78 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91>;
								reg = <0x160>;
								phandle = <0x52>;
							};

							clock-custefuse-sys-gfclk-div {
								#clock-cells = <0x00>;
								compatible = "fixed-factor-clock";
								clock-output-names = "custefuse_sys_gfclk_div";
								clocks = <0x15>;
								clock-mult = <0x01>;
								clock-div = <0x02>;
								phandle = <0x139>;
							};

							clock-eve@180 {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "eve_clk";
								clocks = <0x38 0x3b>;
								reg = <0x180>;
								phandle = <0x13a>;
							};

							clock-hdmi-dpll-clk-mux@164 {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "hdmi_dpll_clk_mux";
								clocks = <0x15 0x71>;
								reg = <0x164>;
								phandle = <0x13b>;
							};

							clock-mlb@134 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "mlb_clk";
								clocks = <0x92>;
								ti,max-div = <0x40>;
								reg = <0x134>;
								ti,index-power-of-two;
								phandle = <0x13c>;
							};

							clock-mlbp@130 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "mlbp_clk";
								clocks = <0x93>;
								ti,max-div = <0x40>;
								reg = <0x130>;
								ti,index-power-of-two;
								phandle = <0x13d>;
							};

							clock-per-abe-x1-gfclk2-div@138 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "per_abe_x1_gfclk2_div";
								clocks = <0x75>;
								ti,max-div = <0x40>;
								reg = <0x138>;
								ti,index-power-of-two;
								phandle = <0x13e>;
							};

							clock-timer-sys-clk-div@144 {
								#clock-cells = <0x00>;
								compatible = "ti,divider-clock";
								clock-output-names = "timer_sys_clk_div";
								clocks = <0x15>;
								reg = <0x144>;
								ti,max-div = <0x02>;
								phandle = <0x98>;
							};

							clock-video1-dpll-clk-mux@168 {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "video1_dpll_clk_mux";
								clocks = <0x15 0x71>;
								reg = <0x168>;
								phandle = <0x13f>;
							};

							clock-video2-dpll-clk-mux@16c {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "video2_dpll_clk_mux";
								clocks = <0x15 0x71>;
								reg = <0x16c>;
								phandle = <0x140>;
							};

							clock-wkupaon-iclk-mux@108 {
								#clock-cells = <0x00>;
								compatible = "ti,mux-clock";
								clock-output-names = "wkupaon_iclk_mux";
								clocks = <0x15 0x94>;
								reg = <0x108>;
								phandle = <0x59>;
							};
						};

						clockdomains {
							phandle = <0x141>;
						};

						clock@1800 {
							compatible = "ti,omap4-cm";
							clock-output-names = "wkupaon_cm";
							reg = <0x1800 0x100>;
							#address-cells = <0x01>;
							#size-cells = <0x01>;
							ranges = <0x00 0x1800 0x100>;
							phandle = <0x142>;

							clock@20 {
								compatible = "ti,clkctrl";
								clock-output-names = "wkupaon_clkctrl";
								reg = <0x20 0x6c>;
								#clock-cells = <0x02>;
								phandle = <0x69>;
							};
						};

						prm@300 {
							compatible = "ti,dra7-prm-inst\0ti,omap-prm-inst";
							reg = <0x300 0x100>;
							#power-domain-cells = <0x00>;
							phandle = <0xa1>;
						};

						prm@400 {
							compatible = "ti,dra7-prm-inst\0ti,omap-prm-inst";
							reg = <0x400 0x100>;
							#reset-cells = <0x01>;
							#power-domain-cells = <0x00>;
							phandle = <0xc3>;
						};

						prm@500 {
							compatible = "ti,dra7-prm-inst\0ti,omap-prm-inst";
							reg = <0x500 0x100>;
							#reset-cells = <0x01>;
							#power-domain-cells = <0x00>;
							phandle = <0xbe>;
						};

						prm@628 {
							compatible = "ti,dra7-prm-inst\0ti,omap-prm-inst";
							reg = <0x628 0xd8>;
							#power-domain-cells = <0x00>;
							phandle = <0x0b>;
						};

						prm@700 {
							compatible = "ti,dra7-prm-inst\0ti,omap-prm-inst";
							reg = <0x700 0x100>;
							#reset-cells = <0x01>;
							#power-domain-cells = <0x00>;
							phandle = <0x07>;
						};

						prm@f00 {
							compatible = "ti,dra7-prm-inst\0ti,omap-prm-inst";
							reg = <0xf00 0x100>;
							#reset-cells = <0x01>;
							#power-domain-cells = <0x00>;
							phandle = <0xc8>;
						};

						prm@1000 {
							compatible = "ti,dra7-prm-inst\0ti,omap-prm-inst";
							reg = <0x1000 0x100>;
							#power-domain-cells = <0x00>;
							phandle = <0x143>;
						};

						prm@1100 {
							compatible = "ti,dra7-prm-inst\0ti,omap-prm-inst";
							reg = <0x1100 0x100>;
							#power-domain-cells = <0x00>;
							phandle = <0x144>;
						};

						prm@1200 {
							compatible = "ti,dra7-prm-inst\0ti,omap-prm-inst";
							reg = <0x1200 0x100>;
							#power-domain-cells = <0x00>;
							phandle = <0x145>;
						};

						prm@1300 {
							compatible = "ti,dra7-prm-inst\0ti,omap-prm-inst";
							reg = <0x1300 0x100>;
							#reset-cells = <0x01>;
							#power-domain-cells = <0x00>;
							phandle = <0x66>;
						};

						prm@1400 {
							compatible = "ti,dra7-prm-inst\0ti,omap-prm-inst";
							reg = <0x1400 0x100>;
							#power-domain-cells = <0x00>;
							phandle = <0x95>;
						};

						prm@1600 {
							compatible = "ti,dra7-prm-inst\0ti,omap-prm-inst";
							reg = <0x1600 0x100>;
							#power-domain-cells = <0x00>;
							phandle = <0x146>;
						};

						prm@1724 {
							compatible = "ti,dra7-prm-inst\0ti,omap-prm-inst";
							reg = <0x1724 0x100>;
							#power-domain-cells = <0x00>;
							phandle = <0x68>;
						};

						prm@1b00 {
							compatible = "ti,dra7-prm-inst\0ti,omap-prm-inst";
							reg = <0x1b00 0x40>;
							#reset-cells = <0x01>;
							#power-domain-cells = <0x00>;
							phandle = <0xcb>;
						};

						prm@1b40 {
							compatible = "ti,dra7-prm-inst\0ti,omap-prm-inst";
							reg = <0x1b40 0x40>;
							#power-domain-cells = <0x00>;
							phandle = <0x147>;
						};

						prm@1b80 {
							compatible = "ti,dra7-prm-inst\0ti,omap-prm-inst";
							reg = <0x1b80 0x40>;
							#power-domain-cells = <0x00>;
							phandle = <0x148>;
						};

						prm@1bc0 {
							compatible = "ti,dra7-prm-inst\0ti,omap-prm-inst";
							reg = <0x1bc0 0x40>;
							#power-domain-cells = <0x00>;
							phandle = <0x149>;
						};

						prm@1c00 {
							compatible = "ti,dra7-prm-inst\0ti,omap-prm-inst";
							reg = <0x1c00 0x60>;
							#power-domain-cells = <0x00>;
							phandle = <0x14a>;
						};

						prm@1c60 {
							compatible = "ti,dra7-prm-inst\0ti,omap-prm-inst";
							reg = <0x1c60 0x20>;
							#power-domain-cells = <0x00>;
							phandle = <0x14b>;
						};

						prm@1c80 {
							compatible = "ti,dra7-prm-inst\0ti,omap-prm-inst";
							reg = <0x1c80 0x80>;
							#power-domain-cells = <0x00>;
							phandle = <0xb4>;
						};
					};
				};

				target-module@c000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0xc000 0x04>;
					reg-names = "rev";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xc000 0x1000>;

					scm_conf@0 {
						compatible = "syscon";
						reg = <0x00 0x1000>;
						phandle = <0x06>;
					};
				};
			};

			segment@10000 {
				compatible = "simple-pm-bus";
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				ranges = <0x00 0x10000 0x1000 0x1000 0x11000 0x1000 0x4000 0x14000 0x1000 0x5000 0x15000 0x1000 0x8000 0x18000 0x1000 0x9000 0x19000 0x1000 0xc000 0x1c000 0x1000 0xd000 0x1d000 0x1000>;

				target-module@0 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x00 0x04 0x10 0x04 0x114 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x07>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x69 0x18 0x00 0x69 0x18 0x08>;
					clock-names = "fck\0dbclk";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x00 0x1000>;

					gpio@0 {
						compatible = "ti,omap4-gpio";
						reg = <0x00 0x200>;
						interrupts = <0x00 0x18 0x04>;
						gpio-controller;
						#gpio-cells = <0x02>;
						interrupt-controller;
						#interrupt-cells = <0x02>;
						phandle = <0x14c>;
					};
				};

				target-module@4000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x4000 0x04 0x4010 0x04 0x4014 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x22>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x69 0x10 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x4000 0x1000>;

					wdt@0 {
						compatible = "ti,omap3-wdt";
						reg = <0x00 0x80>;
						interrupts = <0x00 0x4b 0x04>;
						phandle = <0x14d>;
					};
				};

				target-module@8000 {
					compatible = "ti,sysc-omap4-timer\0ti,sysc";
					reg = <0x8000 0x04 0x8010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x69 0x20 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x8000 0x1000>;
					ti,no-reset-on-init;
					ti,no-idle;
					phandle = <0x14e>;

					timer@0 {
						compatible = "ti,omap5430-timer";
						reg = <0x00 0x80>;
						clocks = <0x69 0x20 0x18>;
						clock-names = "fck";
						interrupts = <0x00 0x20 0x04>;
						ti,timer-alwon;
						assigned-clocks = <0x69 0x20 0x18>;
						assigned-clock-parents = <0x54>;
						phandle = <0x14f>;
					};
				};

				target-module@c000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xc000 0x1000>;
				};
			};

			segment@20000 {
				compatible = "simple-pm-bus";
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				ranges = <0x6000 0x26000 0x1000 0xa000 0x2a000 0x1000 0x00 0x20000 0x1000 0x1000 0x21000 0x1000 0x2000 0x22000 0x1000 0x3000 0x23000 0x1000 0x7000 0x27000 0x400 0x8000 0x28000 0x800 0x9000 0x29000 0x100 0x8800 0x28800 0x200 0x8a00 0x28a00 0x100 0xb000 0x2b000 0x1000 0xc000 0x2c000 0x1000 0xf000 0x2f000 0x1000>;

				target-module@0 {
					compatible = "ti,sysc-omap4-timer\0ti,sysc";
					reg = <0x00 0x04 0x10 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x69 0x28 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x00 0x1000>;

					timer@0 {
						compatible = "ti,omap5430-timer";
						reg = <0x00 0x80>;
						interrupts = <0x00 0x5a 0x04>;
						ti,timer-alwon;
						ti,timer-secure;
						phandle = <0x150>;
					};
				};

				target-module@2000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x2000 0x1000>;
				};

				target-module@6000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x6000 0x1000 0x1000 0x7000 0x400 0x2000 0x8000 0x800 0x2800 0x8800 0x200 0x2a00 0x8a00 0x100 0x3000 0x9000 0x100>;
				};

				target-module@b000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0xb050 0x04 0xb054 0x04 0xb058 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x07>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x69 0x60 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xb000 0x1000>;

					serial@0 {
						compatible = "ti,dra742-uart";
						reg = <0x00 0x100>;
						interrupts = <0x00 0xdd 0x04>;
						clock-frequency = <0x2dc6c00>;
						status = "disabled";
						phandle = <0x151>;
					};
				};

				target-module@f000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xf000 0x1000>;
				};
			};

			segment@30000 {
				compatible = "simple-pm-bus";
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				ranges = <0xc000 0x3c000 0x2000 0xe000 0x3e000 0x1000 0x00 0x30000 0x1000 0x1000 0x31000 0x1000 0x2000 0x32000 0x1000 0x3000 0x33000 0x1000 0x4000 0x34000 0x1000 0x5000 0x35000 0x1000 0x6000 0x36000 0x1000 0x7000 0x37000 0x1000 0x8000 0x38000 0x1000 0x9000 0x39000 0x1000 0xa000 0x3a000 0x1000>;

				target-module@1000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x1000 0x1000>;
				};

				target-module@3000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x3000 0x1000>;
				};

				target-module@5000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x5000 0x1000>;
				};

				target-module@7000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x7000 0x1000>;
				};

				target-module@9000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x9000 0x1000>;
				};

				target-module@c000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0xc020 0x04>;
					reg-names = "rev";
					clocks = <0x69 0x68 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xc000 0x2000>;

					can@0 {
						compatible = "ti,dra7-d_can";
						reg = <0x00 0x2000>;
						syscon-raminit = <0x0d 0x558 0x00>;
						interrupts = <0x00 0xde 0x04>;
						clocks = <0x69 0x68 0x18>;
						status = "disabled";
						phandle = <0x152>;
					};
				};
			};
		};

		interconnect@48000000 {
			compatible = "ti,dra7-l4-per1\0simple-pm-bus";
			power-domains = <0x95>;
			clocks = <0x96 0x98 0x00>;
			clock-names = "fck";
			reg = <0x48000000 0x800 0x48000800 0x800 0x48001000 0x400 0x48001400 0x400 0x48001800 0x400 0x48001c00 0x400>;
			reg-names = "ap\0la\0ia0\0ia1\0ia2\0ia3";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x48000000 0x200000 0x200000 0x48200000 0x200000>;
			phandle = <0x153>;

			segment@0 {
				compatible = "simple-pm-bus";
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				ranges = <0x00 0x00 0x800 0x1000 0x1000 0x400 0x800 0x800 0x800 0x20000 0x20000 0x1000 0x21000 0x21000 0x1000 0x32000 0x32000 0x1000 0x33000 0x33000 0x1000 0x34000 0x34000 0x1000 0x35000 0x35000 0x1000 0x36000 0x36000 0x1000 0x37000 0x37000 0x1000 0x3e000 0x3e000 0x1000 0x3f000 0x3f000 0x1000 0x55000 0x55000 0x1000 0x56000 0x56000 0x1000 0x57000 0x57000 0x1000 0x58000 0x58000 0x1000 0x59000 0x59000 0x1000 0x5a000 0x5a000 0x1000 0x5b000 0x5b000 0x1000 0x5c000 0x5c000 0x1000 0x5d000 0x5d000 0x1000 0x5e000 0x5e000 0x1000 0x60000 0x60000 0x1000 0x6a000 0x6a000 0x1000 0x6b000 0x6b000 0x1000 0x6c000 0x6c000 0x1000 0x6d000 0x6d000 0x1000 0x6e000 0x6e000 0x1000 0x6f000 0x6f000 0x1000 0x70000 0x70000 0x1000 0x71000 0x71000 0x1000 0x72000 0x72000 0x1000 0x73000 0x73000 0x1000 0x61000 0x61000 0x1000 0x53000 0x53000 0x1000 0x54000 0x54000 0x1000 0xb2000 0xb2000 0x1000 0xb3000 0xb3000 0x1000 0x78000 0x78000 0x1000 0x79000 0x79000 0x1000 0x86000 0x86000 0x1000 0x87000 0x87000 0x1000 0x88000 0x88000 0x1000 0x89000 0x89000 0x1000 0x51000 0x51000 0x1000 0x52000 0x52000 0x1000 0x98000 0x98000 0x1000 0x99000 0x99000 0x1000 0x9a000 0x9a000 0x1000 0x9b000 0x9b000 0x1000 0x9c000 0x9c000 0x1000 0x9d000 0x9d000 0x1000 0x68000 0x68000 0x1000 0x69000 0x69000 0x1000 0x90000 0x90000 0x2000 0x92000 0x92000 0x1000 0xa4000 0xa4000 0x1000 0xa6000 0xa6000 0x1000 0xa8000 0xa8000 0x4000 0xac000 0xac000 0x1000 0xad000 0xad000 0x1000 0xae000 0xae000 0x1000 0x66000 0x66000 0x1000 0x67000 0x67000 0x1000 0xb4000 0xb4000 0x1000 0xb5000 0xb5000 0x1000 0xb8000 0xb8000 0x1000 0xb9000 0xb9000 0x1000 0xba000 0xba000 0x1000 0xbb000 0xbb000 0x1000 0xd1000 0xd1000 0x1000 0xd2000 0xd2000 0x1000 0xd5000 0xd5000 0x1000 0xd6000 0xd6000 0x1000 0xa2000 0xa2000 0x1000 0xa3000 0xa3000 0x1000 0x1400 0x1400 0x400 0x1800 0x1800 0x400 0x1c00 0x1c00 0x400 0xa5000 0xa5000 0x1000 0x7a000 0x7a000 0x1000 0x7b000 0x7b000 0x1000 0x7c000 0x7c000 0x1000 0x7d000 0x7d000 0x1000>;

				target-module@20000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x20050 0x04 0x20054 0x04 0x20058 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x07>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x96 0x128 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x20000 0x1000>;

					serial@0 {
						compatible = "ti,dra742-uart";
						reg = <0x00 0x100>;
						interrupts = <0x00 0x45 0x04>;
						clock-frequency = <0x2dc6c00>;
						status = "okay";
						dmas = <0x97 0x35 0x97 0x36>;
						dma-names = "tx\0rx";
						phandle = <0x154>;
					};
				};

				target-module@32000 {
					compatible = "ti,sysc-omap4-timer\0ti,sysc";
					reg = <0x32000 0x04 0x32010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x96 0x10 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x32000 0x1000>;

					timer@0 {
						compatible = "ti,omap5430-timer";
						reg = <0x00 0x80>;
						clocks = <0x96 0x10 0x18 0x98>;
						clock-names = "fck\0timer_sys_ck";
						interrupts = <0x00 0x21 0x04>;
						phandle = <0x155>;
					};
				};

				target-module@34000 {
					compatible = "ti,sysc-omap4-timer\0ti,sysc";
					reg = <0x34000 0x04 0x34010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x96 0x18 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x34000 0x1000>;
					phandle = <0x156>;

					timer@0 {
						compatible = "ti,omap5430-timer";
						reg = <0x00 0x80>;
						clocks = <0x96 0x18 0x18 0x98>;
						clock-names = "fck\0timer_sys_ck";
						interrupts = <0x00 0x22 0x04>;
						phandle = <0x157>;
					};
				};

				target-module@36000 {
					compatible = "ti,sysc-omap4-timer\0ti,sysc";
					reg = <0x36000 0x04 0x36010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x96 0x20 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x36000 0x1000>;
					phandle = <0x158>;

					timer@0 {
						compatible = "ti,omap5430-timer";
						reg = <0x00 0x80>;
						clocks = <0x96 0x20 0x18 0x98>;
						clock-names = "fck\0timer_sys_ck";
						interrupts = <0x00 0x23 0x04>;
						phandle = <0x159>;
					};
				};

				target-module@3e000 {
					compatible = "ti,sysc-omap4-timer\0ti,sysc";
					reg = <0x3e000 0x04 0x3e010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x96 0x28 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x3e000 0x1000>;

					timer@0 {
						compatible = "ti,omap5430-timer";
						reg = <0x00 0x80>;
						clocks = <0x96 0x28 0x18 0x98>;
						clock-names = "fck\0timer_sys_ck";
						interrupts = <0x00 0x28 0x04>;
						phandle = <0x15a>;
					};
				};

				target-module@51000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x51000 0x04 0x51010 0x04 0x51114 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x07>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x96 0xe8 0x00 0x96 0xe8 0x08>;
					clock-names = "fck\0dbclk";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x51000 0x1000>;
					phandle = <0x15b>;

					gpio@0 {
						compatible = "ti,omap4-gpio";
						reg = <0x00 0x200>;
						interrupts = <0x00 0x1e 0x04>;
						gpio-controller;
						#gpio-cells = <0x02>;
						interrupt-controller;
						#interrupt-cells = <0x02>;
						phandle = <0x15c>;
					};
				};

				target-module@53000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x53000 0x04 0x53010 0x04 0x53114 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x07>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x96 0xf0 0x00 0x96 0xf0 0x08>;
					clock-names = "fck\0dbclk";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x53000 0x1000>;

					gpio@0 {
						compatible = "ti,omap4-gpio";
						reg = <0x00 0x200>;
						interrupts = <0x00 0x74 0x04>;
						gpio-controller;
						#gpio-cells = <0x02>;
						interrupt-controller;
						#interrupt-cells = <0x02>;
						phandle = <0x15d>;
					};
				};

				target-module@55000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x55000 0x04 0x55010 0x04 0x55114 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x07>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x96 0x38 0x00 0x96 0x38 0x08>;
					clock-names = "fck\0dbclk";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x55000 0x1000>;
					phandle = <0x15e>;

					gpio@0 {
						compatible = "ti,omap4-gpio";
						reg = <0x00 0x200>;
						interrupts = <0x00 0x19 0x04>;
						gpio-controller;
						#gpio-cells = <0x02>;
						interrupt-controller;
						#interrupt-cells = <0x02>;
						phandle = <0x15f>;
					};
				};

				target-module@57000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x57000 0x04 0x57010 0x04 0x57114 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x07>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x96 0x40 0x00 0x96 0x40 0x08>;
					clock-names = "fck\0dbclk";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x57000 0x1000>;
					phandle = <0x160>;

					gpio@0 {
						compatible = "ti,omap4-gpio";
						reg = <0x00 0x200>;
						interrupts = <0x00 0x1a 0x04>;
						gpio-controller;
						#gpio-cells = <0x02>;
						interrupt-controller;
						#interrupt-cells = <0x02>;
						phandle = <0x161>;
					};
				};

				target-module@59000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x59000 0x04 0x59010 0x04 0x59114 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x07>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x96 0x48 0x00 0x96 0x48 0x08>;
					clock-names = "fck\0dbclk";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x59000 0x1000>;

					gpio@0 {
						compatible = "ti,omap4-gpio";
						reg = <0x00 0x200>;
						interrupts = <0x00 0x1b 0x04>;
						gpio-controller;
						#gpio-cells = <0x02>;
						interrupt-controller;
						#interrupt-cells = <0x02>;
						phandle = <0xd4>;
					};
				};

				target-module@5b000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x5b000 0x04 0x5b010 0x04 0x5b114 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x07>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x96 0x50 0x00 0x96 0x50 0x08>;
					clock-names = "fck\0dbclk";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x5b000 0x1000>;

					gpio@0 {
						compatible = "ti,omap4-gpio";
						reg = <0x00 0x200>;
						interrupts = <0x00 0x1c 0x04>;
						gpio-controller;
						#gpio-cells = <0x02>;
						interrupt-controller;
						#interrupt-cells = <0x02>;
						phandle = <0x162>;
					};
				};

				target-module@5d000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x5d000 0x04 0x5d010 0x04 0x5d114 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x07>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x96 0x58 0x00 0x96 0x58 0x08>;
					clock-names = "fck\0dbclk";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x5d000 0x1000>;

					gpio@0 {
						compatible = "ti,omap4-gpio";
						reg = <0x00 0x200>;
						interrupts = <0x00 0x1d 0x04>;
						gpio-controller;
						#gpio-cells = <0x02>;
						interrupt-controller;
						#interrupt-cells = <0x02>;
						phandle = <0x163>;
					};
				};

				target-module@60000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x60000 0x08 0x60010 0x08 0x60090 0x08>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x307>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x96 0x88 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x60000 0x1000>;

					i2c@0 {
						compatible = "ti,omap4-i2c";
						reg = <0x00 0x100>;
						interrupts = <0x00 0x38 0x04>;
						#address-cells = <0x01>;
						#size-cells = <0x00>;
						status = "disabled";
						phandle = <0x164>;
					};
				};

				target-module@66000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x66050 0x04 0x66054 0x04 0x66058 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x07>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x96 0x148 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x66000 0x1000>;

					serial@0 {
						compatible = "ti,dra742-uart";
						reg = <0x00 0x100>;
						interrupts = <0x00 0x64 0x04>;
						clock-frequency = <0x2dc6c00>;
						status = "disabled";
						dmas = <0x97 0x3f 0x97 0x40>;
						dma-names = "tx\0rx";
						phandle = <0x165>;
					};
				};

				target-module@68000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x68050 0x04 0x68054 0x04 0x68058 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x07>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x99 0x30 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x68000 0x1000>;

					serial@0 {
						compatible = "ti,dra742-uart";
						reg = <0x00 0x100>;
						interrupts = <0x00 0x65 0x04>;
						clock-frequency = <0x2dc6c00>;
						status = "disabled";
						dmas = <0x97 0x4f 0x97 0x50>;
						dma-names = "tx\0rx";
						phandle = <0x166>;
					};
				};

				target-module@6a000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x6a050 0x04 0x6a054 0x04 0x6a058 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x07>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x96 0x118 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x6a000 0x1000>;

					serial@0 {
						compatible = "ti,dra742-uart";
						reg = <0x00 0x100>;
						interrupts-extended = <0x01 0x00 0x43 0x04>;
						clock-frequency = <0x2dc6c00>;
						status = "disabled";
						dmas = <0x97 0x31 0x97 0x32>;
						dma-names = "tx\0rx";
						phandle = <0x167>;
					};
				};

				target-module@6c000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x6c050 0x04 0x6c054 0x04 0x6c058 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x07>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x96 0x120 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x6c000 0x1000>;

					serial@0 {
						compatible = "ti,dra742-uart";
						reg = <0x00 0x100>;
						interrupts = <0x00 0x44 0x04>;
						clock-frequency = <0x2dc6c00>;
						status = "disabled";
						dmas = <0x97 0x33 0x97 0x34>;
						dma-names = "tx\0rx";
						phandle = <0x168>;
					};
				};

				target-module@6e000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x6e050 0x04 0x6e054 0x04 0x6e058 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x07>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x96 0x130 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x6e000 0x1000>;

					serial@0 {
						compatible = "ti,dra742-uart";
						reg = <0x00 0x100>;
						interrupts = <0x00 0x41 0x04>;
						clock-frequency = <0x2dc6c00>;
						status = "disabled";
						dmas = <0x97 0x37 0x97 0x38>;
						dma-names = "tx\0rx";
						phandle = <0x169>;
					};
				};

				target-module@70000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x70000 0x08 0x70010 0x08 0x70090 0x08>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x307>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x96 0x78 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x70000 0x1000>;

					i2c@0 {
						compatible = "ti,omap4-i2c";
						reg = <0x00 0x100>;
						interrupts = <0x00 0x33 0x04>;
						#address-cells = <0x01>;
						#size-cells = <0x00>;
						status = "okay";
						clock-frequency = <0x61a80>;
						phandle = <0x16a>;
					};
				};

				target-module@72000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x72000 0x08 0x72010 0x08 0x72090 0x08>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x307>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x96 0x80 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x72000 0x1000>;

					i2c@0 {
						compatible = "ti,omap4-i2c";
						reg = <0x00 0x100>;
						interrupts = <0x00 0x34 0x04>;
						#address-cells = <0x01>;
						#size-cells = <0x00>;
						status = "disabled";
						phandle = <0x16b>;
					};
				};

				target-module@78000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x78000 0x04 0x78010 0x04 0x78014 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x303>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x96 0x30 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x78000 0x1000>;

					elm@0 {
						compatible = "ti,am3352-elm";
						reg = <0x00 0xfc0>;
						interrupts = <0x00 0x01 0x04>;
						status = "disabled";
						phandle = <0x16c>;
					};
				};

				target-module@7a000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x7a000 0x08 0x7a010 0x08 0x7a090 0x08>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x307>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x96 0x90 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x7a000 0x1000>;

					i2c@0 {
						compatible = "ti,omap4-i2c";
						reg = <0x00 0x100>;
						interrupts = <0x00 0x39 0x04>;
						#address-cells = <0x01>;
						#size-cells = <0x00>;
						status = "disabled";
						phandle = <0x16d>;
					};
				};

				target-module@7c000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x7c000 0x08 0x7c010 0x08 0x7c090 0x08>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x307>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x99 0x28 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x7c000 0x1000>;

					i2c@0 {
						compatible = "ti,omap4-i2c";
						reg = <0x00 0x100>;
						interrupts = <0x00 0x37 0x04>;
						#address-cells = <0x01>;
						#size-cells = <0x00>;
						status = "disabled";
						phandle = <0x16e>;
					};
				};

				target-module@86000 {
					compatible = "ti,sysc-omap4-timer\0ti,sysc";
					reg = <0x86000 0x04 0x86010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x96 0x00 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x86000 0x1000>;

					timer@0 {
						compatible = "ti,omap5430-timer";
						reg = <0x00 0x80>;
						clocks = <0x96 0x00 0x18 0x98>;
						clock-names = "fck\0timer_sys_ck";
						interrupts = <0x00 0x29 0x04>;
						phandle = <0x16f>;
					};
				};

				target-module@88000 {
					compatible = "ti,sysc-omap4-timer\0ti,sysc";
					reg = <0x88000 0x04 0x88010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x96 0x08 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x88000 0x1000>;

					timer@0 {
						compatible = "ti,omap5430-timer";
						reg = <0x00 0x80>;
						clocks = <0x96 0x08 0x18 0x98>;
						clock-names = "fck\0timer_sys_ck";
						interrupts = <0x00 0x2a 0x04>;
						phandle = <0x170>;
					};
				};

				target-module@90000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x91fe0 0x04 0x91fe4 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x01>;
					ti,sysc-sidle = <0x00 0x01>;
					clocks = <0x9a 0x20 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x90000 0x2000>;

					rng@0 {
						compatible = "ti,omap4-rng";
						reg = <0x00 0x2000>;
						interrupts = <0x00 0x2f 0x04>;
						clocks = <0x0e>;
						clock-names = "fck";
						phandle = <0x171>;
					};
				};

				target-module@98000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x98000 0x04 0x98010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x96 0xc8 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x98000 0x1000>;

					spi@0 {
						compatible = "ti,omap4-mcspi";
						reg = <0x00 0x200>;
						interrupts = <0x00 0x3c 0x04>;
						#address-cells = <0x01>;
						#size-cells = <0x00>;
						ti,spi-num-cs = <0x04>;
						dmas = <0x97 0x23 0x97 0x24 0x97 0x25 0x97 0x26 0x97 0x27 0x97 0x28 0x97 0x29 0x97 0x2a>;
						dma-names = "tx0\0rx0\0tx1\0rx1\0tx2\0rx2\0tx3\0rx3";
						status = "disabled";
						phandle = <0x172>;
					};
				};

				target-module@9a000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x9a000 0x04 0x9a010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x96 0xd0 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x9a000 0x1000>;

					spi@0 {
						compatible = "ti,omap4-mcspi";
						reg = <0x00 0x200>;
						interrupts = <0x00 0x3d 0x04>;
						#address-cells = <0x01>;
						#size-cells = <0x00>;
						ti,spi-num-cs = <0x02>;
						dmas = <0x97 0x2b 0x97 0x2c 0x97 0x2d 0x97 0x2e>;
						dma-names = "tx0\0rx0\0tx1\0rx1";
						status = "disabled";
						phandle = <0x173>;
					};
				};

				target-module@9c000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x9c000 0x04 0x9c010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-midle = <0x00 0x01 0x02 0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x5e 0x08 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x9c000 0x1000>;

					mmc@0 {
						compatible = "ti,dra7-sdhci";
						reg = <0x00 0x400>;
						interrupts = <0x00 0x4e 0x04>;
						status = "okay";
						pbias-supply = <0x9b>;
						max-frequency = <0xb71b000>;
						mmc-ddr-1_8v;
						mmc-ddr-3_3v;
						pinctrl-names = "default\0hs";
						pinctrl-0 = <0x9c>;
						pinctrl-1 = <0x9d>;
						phandle = <0x174>;
					};
				};

				target-module@a2000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xa2000 0x1000>;
				};

				target-module@a4000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xa4000 0x1000 0x1000 0xa5000 0x1000>;
				};

				target-module@a5000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0xa5030 0x04 0xa5034 0x04 0xa5038 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x9a 0x10 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xa5000 0x1000>;
					phandle = <0x175>;

					des@0 {
						compatible = "ti,omap4-des";
						reg = <0x00 0xa0>;
						interrupts = <0x00 0x4d 0x04>;
						dmas = <0x97 0x75 0x97 0x74>;
						dma-names = "tx\0rx";
						clocks = <0x0e>;
						clock-names = "fck";
						phandle = <0x176>;
					};
				};

				target-module@a8000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xa8000 0x4000>;
				};

				target-module@ad000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0xad000 0x04 0xad010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-midle = <0x00 0x01 0x02 0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x96 0xf8 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xad000 0x1000>;

					mmc@0 {
						compatible = "ti,dra7-sdhci";
						reg = <0x00 0x400>;
						interrupts = <0x00 0x59 0x04>;
						status = "disabled";
						max-frequency = <0x3d09000>;
						sdhci-caps-mask = <0x00 0x400000>;
						phandle = <0x177>;
					};
				};

				target-module@b2000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0xb2000 0x04 0xb2014 0x04 0xb2018 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x03>;
					ti,syss-mask = <0x01>;
					ti,no-reset-on-init;
					clocks = <0x96 0x60 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xb2000 0x1000>;

					1w@0 {
						compatible = "ti,omap3-1w";
						reg = <0x00 0x1000>;
						interrupts = <0x00 0x35 0x04>;
						phandle = <0x178>;
					};
				};

				target-module@b4000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0xb4000 0x04 0xb4010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-midle = <0x00 0x01 0x02 0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x5e 0x10 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xb4000 0x1000>;

					mmc@0 {
						compatible = "ti,dra7-sdhci";
						reg = <0x00 0x400>;
						interrupts = <0x00 0x51 0x04>;
						status = "disabled";
						max-frequency = <0xb71b000>;
						sdhci-caps-mask = <0x07 0x00>;
						mmc-hs200-1_8v;
						mmc-ddr-1_8v;
						mmc-ddr-3_3v;
						pinctrl-names = "default\0hs\0ddr_3_3v";
						pinctrl-0 = <0x9e>;
						pinctrl-1 = <0x9f>;
						pinctrl-2 = <0xa0>;
						phandle = <0x179>;
					};
				};

				target-module@b8000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0xb8000 0x04 0xb8010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x96 0xd8 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xb8000 0x1000>;

					spi@0 {
						compatible = "ti,omap4-mcspi";
						reg = <0x00 0x200>;
						interrupts = <0x00 0x56 0x04>;
						#address-cells = <0x01>;
						#size-cells = <0x00>;
						ti,spi-num-cs = <0x02>;
						dmas = <0x97 0x0f 0x97 0x10>;
						dma-names = "tx0\0rx0";
						status = "disabled";
						phandle = <0x17a>;
					};
				};

				target-module@ba000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0xba000 0x04 0xba010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x96 0xe0 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xba000 0x1000>;

					spi@0 {
						compatible = "ti,omap4-mcspi";
						reg = <0x00 0x200>;
						interrupts = <0x00 0x2b 0x04>;
						#address-cells = <0x01>;
						#size-cells = <0x00>;
						ti,spi-num-cs = <0x01>;
						dmas = <0x97 0x46 0x97 0x47>;
						dma-names = "tx0\0rx0";
						status = "disabled";
						phandle = <0x17b>;
					};
				};

				target-module@d1000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0xd1000 0x04 0xd1010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-midle = <0x00 0x01 0x02 0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x96 0x100 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xd1000 0x1000>;

					mmc@0 {
						compatible = "ti,dra7-sdhci";
						reg = <0x00 0x400>;
						interrupts = <0x00 0x5b 0x04>;
						status = "disabled";
						max-frequency = <0xb71b000>;
						sdhci-caps-mask = <0x00 0x400000>;
						phandle = <0x17c>;
					};
				};

				target-module@d5000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xd5000 0x1000>;
				};
			};

			segment@200000 {
				compatible = "simple-pm-bus";
				#address-cells = <0x01>;
				#size-cells = <0x01>;
			};
		};

		target-module@48210000 {
			compatible = "ti,sysc-omap4-simple\0ti,sysc";
			power-domains = <0xa1>;
			clocks = <0xa2 0x00 0x00>;
			clock-names = "fck";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x48210000 0x1f0000>;

			mpu {
				compatible = "ti,omap5-mpu";
			};
		};

		interconnect@48400000 {
			compatible = "ti,dra7-l4-per2\0simple-pm-bus";
			power-domains = <0x95>;
			clocks = <0x5b 0x00 0x00>;
			clock-names = "fck";
			reg = <0x48400000 0x800 0x48400800 0x800 0x48401000 0x400 0x48401400 0x400 0x48401800 0x400>;
			reg-names = "ap\0la\0ia0\0ia1\0ia2";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x48400000 0x400000 0x45800000 0x45800000 0x400000 0x45c00000 0x45c00000 0x400000 0x46000000 0x46000000 0x400000 0x48436000 0x48436000 0x400000 0x4843a000 0x4843a000 0x400000 0x4844c000 0x4844c000 0x400000 0x48450000 0x48450000 0x400000 0x48454000 0x48454000 0x400000>;
			phandle = <0x17d>;

			segment@0 {
				compatible = "simple-pm-bus";
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				ranges = <0x00 0x00 0x800 0x1000 0x1000 0x400 0x800 0x800 0x800 0x84000 0x84000 0x4000 0x1400 0x1400 0x400 0x1800 0x1800 0x400 0x88000 0x88000 0x1000 0x2c000 0x2c000 0x1000 0x2d000 0x2d000 0x1000 0x60000 0x60000 0x2000 0x62000 0x62000 0x1000 0x64000 0x64000 0x2000 0x66000 0x66000 0x1000 0x68000 0x68000 0x2000 0x6a000 0x6a000 0x1000 0x6c000 0x6c000 0x2000 0x6e000 0x6e000 0x1000 0x36000 0x36000 0x1000 0x37000 0x37000 0x1000 0x70000 0x70000 0x2000 0x72000 0x72000 0x1000 0x3a000 0x3a000 0x1000 0x3b000 0x3b000 0x1000 0x3c000 0x3c000 0x1000 0x3d000 0x3d000 0x1000 0x3e000 0x3e000 0x1000 0x3f000 0x3f000 0x1000 0x40000 0x40000 0x1000 0x41000 0x41000 0x1000 0x42000 0x42000 0x1000 0x43000 0x43000 0x1000 0x80000 0x80000 0x2000 0x82000 0x82000 0x1000 0x4a000 0x4a000 0x1000 0x4b000 0x4b000 0x1000 0x74000 0x74000 0x2000 0x76000 0x76000 0x1000 0x50000 0x50000 0x1000 0x51000 0x51000 0x1000 0x78000 0x78000 0x2000 0x7a000 0x7a000 0x1000 0x54000 0x54000 0x1000 0x55000 0x55000 0x1000 0x7c000 0x7c000 0x2000 0x7e000 0x7e000 0x1000 0x4c000 0x4c000 0x1000 0x4d000 0x4d000 0x1000 0x20000 0x20000 0x1000 0x21000 0x21000 0x1000 0x22000 0x22000 0x1000 0x23000 0x23000 0x1000 0x24000 0x24000 0x1000 0x25000 0x25000 0x1000 0x46000 0x46000 0x1000 0x47000 0x47000 0x1000 0x48000 0x48000 0x1000 0x49000 0x49000 0x1000 0x58000 0x58000 0x2000 0x5a000 0x5a000 0x1000 0x5b000 0x5b000 0x1000 0x5c000 0x5c000 0x1000 0x5d000 0x5d000 0x1000 0x5e000 0x5e000 0x1000 0x45800000 0x45800000 0x400000 0x45c00000 0x45c00000 0x400000 0x46000000 0x46000000 0x400000 0x48436000 0x48436000 0x400000 0x4843a000 0x4843a000 0x400000 0x4844c000 0x4844c000 0x400000 0x48450000 0x48450000 0x400000 0x48454000 0x48454000 0x400000>;

				target-module@20000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x20050 0x04 0x20054 0x04 0x20058 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x07>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x5b 0x1c4 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x20000 0x1000>;

					serial@0 {
						compatible = "ti,dra742-uart";
						reg = <0x00 0x100>;
						interrupts = <0x00 0xda 0x04>;
						clock-frequency = <0x2dc6c00>;
						status = "disabled";
						phandle = <0x17e>;
					};
				};

				target-module@22000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x22050 0x04 0x22054 0x04 0x22058 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x07>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x5b 0x1d4 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x22000 0x1000>;

					serial@0 {
						compatible = "ti,dra742-uart";
						reg = <0x00 0x100>;
						interrupts = <0x00 0xdb 0x04>;
						clock-frequency = <0x2dc6c00>;
						status = "disabled";
						phandle = <0x17f>;
					};
				};

				target-module@24000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x24050 0x04 0x24054 0x04 0x24058 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x07>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,syss-mask = <0x01>;
					clocks = <0x5b 0x1dc 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x24000 0x1000>;

					serial@0 {
						compatible = "ti,dra742-uart";
						reg = <0x00 0x100>;
						interrupts = <0x00 0xdc 0x04>;
						clock-frequency = <0x2dc6c00>;
						status = "disabled";
						phandle = <0x180>;
					};
				};

				target-module@2c000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x2c000 0x1000>;
				};

				target-module@36000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x36000 0x1000>;
				};

				target-module@3a000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x3a000 0x1000>;
				};

				target-module@3c000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x3c000 0x04>;
					reg-names = "rev";
					clocks = <0x14 0x00 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x3c000 0x1000>;
					status = "disabled";
					phandle = <0x181>;

					atl@0 {
						compatible = "ti,dra7-atl";
						reg = <0x00 0x3ff>;
						ti,provided-clocks = <0xa3 0xa4 0xa5 0xa6>;
						clocks = <0x14 0x00 0x1a>;
						clock-names = "fck";
						status = "disabled";
						phandle = <0x182>;
					};
				};

				target-module@3e000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x3e000 0x04 0x3e004 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x01>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x5b 0xb8 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x3e000 0x1000>;

					epwmss@0 {
						compatible = "ti,dra746-pwmss\0ti,am33xx-pwmss";
						reg = <0x00 0x30>;
						#address-cells = <0x01>;
						#size-cells = <0x01>;
						status = "disabled";
						ranges = <0x00 0x00 0x1000>;
						phandle = <0x183>;

						pwm@100 {
							compatible = "ti,dra746-ecap\0ti,am3352-ecap";
							#pwm-cells = <0x03>;
							reg = <0x100 0x80>;
							clocks = <0x0f>;
							clock-names = "fck";
							status = "disabled";
							phandle = <0x184>;
						};

						pwm@200 {
							compatible = "ti,dra746-ehrpwm\0ti,am3352-ehrpwm";
							#pwm-cells = <0x03>;
							reg = <0x200 0x80>;
							clocks = <0xa7 0x0f>;
							clock-names = "tbclk\0fck";
							status = "disabled";
							phandle = <0x185>;
						};
					};
				};

				target-module@40000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x40000 0x04 0x40004 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x01>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x5b 0x84 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x40000 0x1000>;

					epwmss@0 {
						compatible = "ti,dra746-pwmss\0ti,am33xx-pwmss";
						reg = <0x00 0x30>;
						#address-cells = <0x01>;
						#size-cells = <0x01>;
						status = "disabled";
						ranges = <0x00 0x00 0x1000>;
						phandle = <0x186>;

						pwm@100 {
							compatible = "ti,dra746-ecap\0ti,am3352-ecap";
							#pwm-cells = <0x03>;
							reg = <0x100 0x80>;
							clocks = <0x0f>;
							clock-names = "fck";
							status = "disabled";
							phandle = <0x187>;
						};

						pwm@200 {
							compatible = "ti,dra746-ehrpwm\0ti,am3352-ehrpwm";
							#pwm-cells = <0x03>;
							reg = <0x200 0x80>;
							clocks = <0xa8 0x0f>;
							clock-names = "tbclk\0fck";
							status = "disabled";
							phandle = <0x188>;
						};
					};
				};

				target-module@42000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x42000 0x04 0x42004 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x01>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x5b 0x8c 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x42000 0x1000>;

					epwmss@0 {
						compatible = "ti,dra746-pwmss\0ti,am33xx-pwmss";
						reg = <0x00 0x30>;
						#address-cells = <0x01>;
						#size-cells = <0x01>;
						status = "disabled";
						ranges = <0x00 0x00 0x1000>;
						phandle = <0x189>;

						pwm@100 {
							compatible = "ti,dra746-ecap\0ti,am3352-ecap";
							#pwm-cells = <0x03>;
							reg = <0x100 0x80>;
							clocks = <0x0f>;
							clock-names = "fck";
							status = "disabled";
							phandle = <0x18a>;
						};

						pwm@200 {
							compatible = "ti,dra746-ehrpwm\0ti,am3352-ehrpwm";
							#pwm-cells = <0x03>;
							reg = <0x200 0x80>;
							clocks = <0xa9 0x0f>;
							clock-names = "tbclk\0fck";
							status = "disabled";
							phandle = <0x18b>;
						};
					};
				};

				target-module@46000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x46000 0x1000>;
				};

				target-module@48000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x48000 0x1000>;
				};

				target-module@4a000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x4a000 0x1000>;
				};

				target-module@4c000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x4c000 0x1000>;
				};

				target-module@50000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x50000 0x1000>;
				};

				target-module@54000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x54000 0x1000>;
				};

				target-module@58000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x58000 0x2000>;
				};

				target-module@5b000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x5b000 0x1000>;
				};

				target-module@5d000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x5d000 0x1000>;
				};

				target-module@60000 {
					compatible = "ti,sysc-dra7-mcasp\0ti,sysc";
					reg = <0x60000 0x04 0x60004 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x99 0x00 0x00 0x99 0x00 0x18 0x99 0x00 0x1c>;
					clock-names = "fck\0ahclkx\0ahclkr";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x60000 0x2000 0x45800000 0x45800000 0x400000>;

					mcasp@0 {
						compatible = "ti,dra7-mcasp-audio";
						reg = <0x00 0x2000 0x45800000 0x1000>;
						reg-names = "mpu\0dat";
						interrupts = <0x00 0x68 0x04 0x00 0x67 0x04>;
						interrupt-names = "tx\0rx";
						dmas = <0xaa 0x81 0x01 0xaa 0x80 0x01>;
						dma-names = "tx\0rx";
						clocks = <0x99 0x00 0x00 0x99 0x00 0x18 0x99 0x00 0x1c>;
						clock-names = "fck\0ahclkx\0ahclkr";
						status = "disabled";
						phandle = <0x18c>;
					};
				};

				target-module@64000 {
					compatible = "ti,sysc-dra7-mcasp\0ti,sysc";
					reg = <0x64000 0x04 0x64004 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x5b 0x154 0x00 0x5b 0x154 0x18 0x5b 0x154 0x1c>;
					clock-names = "fck\0ahclkx\0ahclkr";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x64000 0x2000 0x45c00000 0x45c00000 0x400000>;

					mcasp@0 {
						compatible = "ti,dra7-mcasp-audio";
						reg = <0x00 0x2000 0x45c00000 0x1000>;
						reg-names = "mpu\0dat";
						interrupts = <0x00 0x95 0x04 0x00 0x94 0x04>;
						interrupt-names = "tx\0rx";
						dmas = <0xaa 0x83 0x01 0xaa 0x82 0x01>;
						dma-names = "tx\0rx";
						clocks = <0x5b 0x154 0x00 0x99 0x00 0x18 0x5b 0x154 0x1c>;
						clock-names = "fck\0ahclkx\0ahclkr";
						status = "disabled";
						phandle = <0x18d>;
					};
				};

				target-module@68000 {
					compatible = "ti,sysc-dra7-mcasp\0ti,sysc";
					reg = <0x68000 0x04 0x68004 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x5b 0x15c 0x00 0x5b 0x15c 0x18>;
					clock-names = "fck\0ahclkx";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x68000 0x2000 0x46000000 0x46000000 0x400000>;

					mcasp@0 {
						compatible = "ti,dra7-mcasp-audio";
						reg = <0x00 0x2000 0x46000000 0x1000>;
						reg-names = "mpu\0dat";
						interrupts = <0x00 0x97 0x04 0x00 0x96 0x04>;
						interrupt-names = "tx\0rx";
						dmas = <0xaa 0x85 0x01 0xaa 0x84 0x01>;
						dma-names = "tx\0rx";
						clocks = <0x5b 0x15c 0x00 0x5b 0x15c 0x18>;
						clock-names = "fck\0ahclkx";
						status = "disabled";
						phandle = <0x18e>;
					};
				};

				target-module@6c000 {
					compatible = "ti,sysc-dra7-mcasp\0ti,sysc";
					reg = <0x6c000 0x04 0x6c004 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x5b 0x18c 0x00 0x5b 0x18c 0x18>;
					clock-names = "fck\0ahclkx";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x6c000 0x2000 0x48436000 0x48436000 0x400000>;

					mcasp@0 {
						compatible = "ti,dra7-mcasp-audio";
						reg = <0x00 0x2000 0x48436000 0x1000>;
						reg-names = "mpu\0dat";
						interrupts = <0x00 0x99 0x04 0x00 0x98 0x04>;
						interrupt-names = "tx\0rx";
						dmas = <0xaa 0x87 0x01 0xaa 0x86 0x01>;
						dma-names = "tx\0rx";
						clocks = <0x5b 0x18c 0x00 0x5b 0x18c 0x18>;
						clock-names = "fck\0ahclkx";
						status = "disabled";
						phandle = <0x18f>;
					};
				};

				target-module@70000 {
					compatible = "ti,sysc-dra7-mcasp\0ti,sysc";
					reg = <0x70000 0x04 0x70004 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x5b 0x16c 0x00 0x5b 0x16c 0x18>;
					clock-names = "fck\0ahclkx";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x70000 0x2000 0x4843a000 0x4843a000 0x400000>;

					mcasp@0 {
						compatible = "ti,dra7-mcasp-audio";
						reg = <0x00 0x2000 0x4843a000 0x1000>;
						reg-names = "mpu\0dat";
						interrupts = <0x00 0x9b 0x04 0x00 0x9a 0x04>;
						interrupt-names = "tx\0rx";
						dmas = <0xaa 0x89 0x01 0xaa 0x88 0x01>;
						dma-names = "tx\0rx";
						clocks = <0x5b 0x16c 0x00 0x5b 0x16c 0x18>;
						clock-names = "fck\0ahclkx";
						status = "disabled";
						phandle = <0x190>;
					};
				};

				target-module@74000 {
					compatible = "ti,sysc-dra7-mcasp\0ti,sysc";
					reg = <0x74000 0x04 0x74004 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x5b 0x1f8 0x00 0x5b 0x1f8 0x18>;
					clock-names = "fck\0ahclkx";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x74000 0x2000 0x4844c000 0x4844c000 0x400000>;

					mcasp@0 {
						compatible = "ti,dra7-mcasp-audio";
						reg = <0x00 0x2000 0x4844c000 0x1000>;
						reg-names = "mpu\0dat";
						interrupts = <0x00 0x9d 0x04 0x00 0x9c 0x04>;
						interrupt-names = "tx\0rx";
						dmas = <0xaa 0x8b 0x01 0xaa 0x8a 0x01>;
						dma-names = "tx\0rx";
						clocks = <0x5b 0x1f8 0x00 0x5b 0x1f8 0x18>;
						clock-names = "fck\0ahclkx";
						status = "disabled";
						phandle = <0x191>;
					};
				};

				target-module@78000 {
					compatible = "ti,sysc-dra7-mcasp\0ti,sysc";
					reg = <0x78000 0x04 0x78004 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x5b 0x1fc 0x00 0x5b 0x1fc 0x18>;
					clock-names = "fck\0ahclkx";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x78000 0x2000 0x48450000 0x48450000 0x400000>;

					mcasp@0 {
						compatible = "ti,dra7-mcasp-audio";
						reg = <0x00 0x2000 0x48450000 0x1000>;
						reg-names = "mpu\0dat";
						interrupts = <0x00 0x9f 0x04 0x00 0x9e 0x04>;
						interrupt-names = "tx\0rx";
						dmas = <0xaa 0x8d 0x01 0xaa 0x8c 0x01>;
						dma-names = "tx\0rx";
						clocks = <0x5b 0x1fc 0x00 0x5b 0x1fc 0x18>;
						clock-names = "fck\0ahclkx";
						status = "disabled";
						phandle = <0x192>;
					};
				};

				target-module@7c000 {
					compatible = "ti,sysc-dra7-mcasp\0ti,sysc";
					reg = <0x7c000 0x04 0x7c004 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x5b 0x184 0x00 0x5b 0x184 0x18>;
					clock-names = "fck\0ahclkx";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x7c000 0x2000 0x48454000 0x48454000 0x400000>;

					mcasp@0 {
						compatible = "ti,dra7-mcasp-audio";
						reg = <0x00 0x2000 0x48454000 0x1000>;
						reg-names = "mpu\0dat";
						interrupts = <0x00 0xa1 0x04 0x00 0xa0 0x04>;
						interrupt-names = "tx\0rx";
						dmas = <0xaa 0x8f 0x01 0xaa 0x8e 0x01>;
						dma-names = "tx\0rx";
						clocks = <0x5b 0x184 0x00 0x5b 0x184 0x18>;
						clock-names = "fck\0ahclkx";
						status = "disabled";
						phandle = <0x193>;
					};
				};

				target-module@80000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x80020 0x04>;
					reg-names = "rev";
					clocks = <0x5b 0x1e4 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x80000 0x2000>;

					can@0 {
						compatible = "ti,dra7-d_can";
						reg = <0x00 0x2000>;
						syscon-raminit = <0x0d 0x558 0x01>;
						interrupts = <0x00 0xe1 0x04>;
						clocks = <0x15>;
						status = "disabled";
						phandle = <0x194>;
					};
				};

				target-module@84000 {
					compatible = "ti,sysc-omap4-simple\0ti,sysc";
					reg = <0x85200 0x04 0x85208 0x04 0x85204 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-mask = <0x00>;
					ti,sysc-midle = <0x00 0x01>;
					ti,sysc-sidle = <0x00 0x01>;
					ti,syss-mask = <0x01>;
					clocks = <0xab 0x00 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x84000 0x4000>;
					ti,no-idle;

					switch@0 {
						compatible = "ti,dra7-cpsw-switch\0ti,cpsw-switch";
						reg = <0x00 0x4000>;
						ranges = <0x00 0x00 0x4000>;
						clocks = <0xac>;
						clock-names = "fck";
						#address-cells = <0x01>;
						#size-cells = <0x01>;
						syscon = <0x0d>;
						status = "disabled";
						interrupts = <0x00 0x14e 0x04 0x00 0x14f 0x04 0x00 0x150 0x04 0x00 0x151 0x04>;
						interrupt-names = "rx_thresh\0rx\0tx\0misc";
						phandle = <0x195>;

						ethernet-ports {
							#address-cells = <0x01>;
							#size-cells = <0x00>;

							port@1 {
								reg = <0x01>;
								label = "port1";
								mac-address = [00 00 00 00 00 00];
								phys = <0xad 0x01>;
								status = "disabled";
								phandle = <0x196>;
							};

							port@2 {
								reg = <0x02>;
								label = "port2";
								mac-address = [00 00 00 00 00 00];
								phys = <0xad 0x02>;
								status = "disabled";
								phandle = <0x197>;
							};
						};

						mdio@1000 {
							compatible = "ti,cpsw-mdio\0ti,davinci_mdio";
							clocks = <0xac>;
							clock-names = "fck";
							#address-cells = <0x01>;
							#size-cells = <0x00>;
							bus_freq = <0xf4240>;
							reg = <0x1000 0x100>;
							phandle = <0x198>;
						};

						cpts {
							clocks = <0xab 0x00 0x19>;
							clock-names = "cpts";
						};
					};
				};
			};
		};

		interconnect@48800000 {
			compatible = "ti,dra7-l4-per3\0simple-pm-bus";
			power-domains = <0x95>;
			clocks = <0xae 0x00 0x00>;
			clock-names = "fck";
			reg = <0x48800000 0x800 0x48800800 0x800 0x48801000 0x400 0x48801400 0x400 0x48801800 0x400>;
			reg-names = "ap\0la\0ia0\0ia1\0ia2";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x48800000 0x200000>;
			phandle = <0x199>;

			segment@0 {
				compatible = "simple-pm-bus";
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				ranges = <0x00 0x00 0x800 0x800 0x800 0x800 0x1000 0x1000 0x400 0x1400 0x1400 0x400 0x1800 0x1800 0x400 0x20000 0x20000 0x1000 0x21000 0x21000 0x1000 0x22000 0x22000 0x1000 0x23000 0x23000 0x1000 0x24000 0x24000 0x1000 0x25000 0x25000 0x1000 0x26000 0x26000 0x1000 0x27000 0x27000 0x1000 0x28000 0x28000 0x1000 0x29000 0x29000 0x1000 0x2a000 0x2a000 0x1000 0x2b000 0x2b000 0x1000 0x2c000 0x2c000 0x1000 0x2d000 0x2d000 0x1000 0x2e000 0x2e000 0x1000 0x2f000 0x2f000 0x1000 0x170000 0x170000 0x10000 0x180000 0x180000 0x1000 0x190000 0x190000 0x10000 0x1a0000 0x1a0000 0x1000 0x1b0000 0x1b0000 0x10000 0x1c0000 0x1c0000 0x1000 0x1d0000 0x1d0000 0x10000 0x1e0000 0x1e0000 0x1000 0x38000 0x38000 0x1000 0x39000 0x39000 0x1000 0x5c000 0x5c000 0x1000 0x5d000 0x5d000 0x1000 0x3a000 0x3a000 0x1000 0x3b000 0x3b000 0x1000 0x3c000 0x3c000 0x1000 0x3d000 0x3d000 0x1000 0x3e000 0x3e000 0x1000 0x3f000 0x3f000 0x1000 0x40000 0x40000 0x1000 0x41000 0x41000 0x1000 0x42000 0x42000 0x1000 0x43000 0x43000 0x1000 0x44000 0x44000 0x1000 0x45000 0x45000 0x1000 0x46000 0x46000 0x1000 0x47000 0x47000 0x1000 0x48000 0x48000 0x1000 0x49000 0x49000 0x1000 0x4a000 0x4a000 0x1000 0x4b000 0x4b000 0x1000 0x4c000 0x4c000 0x1000 0x4d000 0x4d000 0x1000 0x4e000 0x4e000 0x1000 0x4f000 0x4f000 0x1000 0x50000 0x50000 0x1000 0x51000 0x51000 0x1000 0x52000 0x52000 0x1000 0x53000 0x53000 0x1000 0x54000 0x54000 0x1000 0x55000 0x55000 0x1000 0x56000 0x56000 0x1000 0x57000 0x57000 0x1000 0x58000 0x58000 0x1000 0x59000 0x59000 0x1000 0x5a000 0x5a000 0x1000 0x5b000 0x5b000 0x1000 0x64000 0x64000 0x1000 0x65000 0x65000 0x1000 0x5e000 0x5e000 0x1000 0x5f000 0x5f000 0x1000 0x60000 0x60000 0x1000 0x61000 0x61000 0x1000 0x62000 0x62000 0x1000 0x63000 0x63000 0x1000 0x140000 0x140000 0x20000 0x160000 0x160000 0x1000 0x16000 0x16000 0x1000 0x17000 0x17000 0x1000 0xc0000 0xc0000 0x20000 0xe0000 0xe0000 0x1000 0x4000 0x4000 0x1000 0x5000 0x5000 0x1000 0x80000 0x80000 0x20000 0xa0000 0xa0000 0x1000 0x100000 0x100000 0x20000 0x120000 0x120000 0x1000 0x10000 0x10000 0x1000 0x11000 0x11000 0x1000 0xa000 0xa000 0x1000 0xb000 0xb000 0x1000 0x1c000 0x1c000 0x1000 0x1d000 0x1d000 0x1000 0x1e000 0x1e000 0x1000 0x1f000 0x1f000 0x1000 0x2000 0x2000 0x1000 0x3000 0x3000 0x1000>;

				target-module@2000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x2000 0x04 0x2010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x01>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x0c 0x80 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x2000 0x1000>;

					mailbox@0 {
						compatible = "ti,omap4-mailbox";
						reg = <0x00 0x200>;
						interrupts = <0x00 0x17b 0x04 0x00 0x17c 0x04 0x00 0x17d 0x04 0x00 0x17e 0x04>;
						#mbox-cells = <0x01>;
						ti,mbox-num-users = <0x04>;
						ti,mbox-num-fifos = <0x0c>;
						status = "disabled";
						phandle = <0x19a>;
					};
				};

				target-module@4000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x4000 0x1000>;
				};

				target-module@a000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xa000 0x1000>;
				};

				target-module@10000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x10000 0x1000>;
				};

				target-module@16000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x16000 0x1000>;
				};

				target-module@1c000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x1c000 0x1000>;
				};

				target-module@1e000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x1e000 0x1000>;
				};

				target-module@20000 {
					compatible = "ti,sysc-omap4-timer\0ti,sysc";
					reg = <0x20000 0x04 0x20010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x99 0x08 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x20000 0x1000>;

					timer@0 {
						compatible = "ti,omap5430-timer";
						reg = <0x00 0x80>;
						clocks = <0x99 0x08 0x18 0x98>;
						clock-names = "fck\0timer_sys_ck";
						interrupts = <0x00 0x24 0x04>;
						phandle = <0x19b>;
					};
				};

				target-module@22000 {
					compatible = "ti,sysc-omap4-timer\0ti,sysc";
					reg = <0x22000 0x04 0x22010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x99 0x10 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x22000 0x1000>;

					timer@0 {
						compatible = "ti,omap5430-timer";
						reg = <0x00 0x80>;
						clocks = <0x99 0x10 0x18 0x98>;
						clock-names = "fck\0timer_sys_ck";
						interrupts = <0x00 0x25 0x04>;
						phandle = <0x19c>;
					};
				};

				target-module@24000 {
					compatible = "ti,sysc-omap4-timer\0ti,sysc";
					reg = <0x24000 0x04 0x24010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x99 0x18 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x24000 0x1000>;

					timer@0 {
						compatible = "ti,omap5430-timer";
						reg = <0x00 0x80>;
						clocks = <0x99 0x18 0x18 0x98>;
						clock-names = "fck\0timer_sys_ck";
						interrupts = <0x00 0x26 0x04>;
						phandle = <0x19d>;
					};
				};

				target-module@26000 {
					compatible = "ti,sysc-omap4-timer\0ti,sysc";
					reg = <0x26000 0x04 0x26010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x99 0x20 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x26000 0x1000>;

					timer@0 {
						compatible = "ti,omap5430-timer";
						reg = <0x00 0x80>;
						clocks = <0x99 0x20 0x18 0x98>;
						clock-names = "fck\0timer_sys_ck";
						interrupts = <0x00 0x27 0x04>;
						phandle = <0x19e>;
					};
				};

				target-module@28000 {
					compatible = "ti,sysc-omap4-timer\0ti,sysc";
					reg = <0x28000 0x04 0x28010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0xae 0xb4 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x28000 0x1000>;

					timer@0 {
						compatible = "ti,omap5430-timer";
						reg = <0x00 0x80>;
						clocks = <0xae 0xb4 0x18 0x98>;
						clock-names = "fck\0timer_sys_ck";
						interrupts = <0x00 0x153 0x04>;
						ti,timer-pwm;
						phandle = <0x19f>;
					};
				};

				target-module@2a000 {
					compatible = "ti,sysc-omap4-timer\0ti,sysc";
					reg = <0x2a000 0x04 0x2a010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0xae 0xbc 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x2a000 0x1000>;

					timer@0 {
						compatible = "ti,omap5430-timer";
						reg = <0x00 0x80>;
						clocks = <0xae 0xbc 0x18 0x98>;
						clock-names = "fck\0timer_sys_ck";
						interrupts = <0x00 0x154 0x04>;
						ti,timer-pwm;
						phandle = <0x1a0>;
					};
				};

				target-module@2c000 {
					compatible = "ti,sysc-omap4-timer\0ti,sysc";
					reg = <0x2c000 0x04 0x2c010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0xae 0xc4 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x2c000 0x1000>;
					ti,no-reset-on-init;
					ti,no-idle;
					phandle = <0x1a1>;

					timer@0 {
						compatible = "ti,omap5430-timer";
						reg = <0x00 0x80>;
						clocks = <0xae 0xc4 0x18 0x98>;
						clock-names = "fck\0timer_sys_ck";
						interrupts = <0x00 0x155 0x04>;
						ti,timer-pwm;
						assigned-clocks = <0xae 0xc4 0x18>;
						assigned-clock-parents = <0x98>;
						phandle = <0x1a2>;
					};
				};

				target-module@2e000 {
					compatible = "ti,sysc-omap4-timer\0ti,sysc";
					reg = <0x2e000 0x04 0x2e010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0xae 0x11c 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x2e000 0x1000>;
					ti,no-reset-on-init;
					ti,no-idle;
					phandle = <0x1a3>;

					timer@0 {
						compatible = "ti,omap5430-timer";
						reg = <0x00 0x80>;
						clocks = <0xae 0x11c 0x18 0x98>;
						clock-names = "fck\0timer_sys_ck";
						interrupts = <0x00 0x156 0x04>;
						ti,timer-pwm;
						assigned-clocks = <0xae 0x11c 0x18>;
						assigned-clock-parents = <0x98>;
						phandle = <0x1a4>;
					};
				};

				target-module@38000 {
					compatible = "ti,sysc-omap4-simple\0ti,sysc";
					reg = <0x38074 0x04 0x38078 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0xaf 0x24 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x38000 0x1000>;
					phandle = <0x1a5>;

					rtc@0 {
						compatible = "ti,am3352-rtc";
						reg = <0x00 0x100>;
						interrupts = <0x00 0xd9 0x04 0x00 0xd9 0x04>;
						clocks = <0x54>;
						phandle = <0x1a6>;
					};
				};

				target-module@3a000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x3a000 0x04 0x3a010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x01>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x0c 0x28 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x3a000 0x1000>;

					mailbox@0 {
						compatible = "ti,omap4-mailbox";
						reg = <0x00 0x200>;
						interrupts = <0x00 0xed 0x04 0x00 0xee 0x04 0x00 0xef 0x04 0x00 0xf0 0x04>;
						#mbox-cells = <0x01>;
						ti,mbox-num-users = <0x04>;
						ti,mbox-num-fifos = <0x0c>;
						status = "disabled";
						phandle = <0x1a7>;
					};
				};

				target-module@3c000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x3c000 0x04 0x3c010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x01>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x0c 0x30 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x3c000 0x1000>;

					mailbox@0 {
						compatible = "ti,omap4-mailbox";
						reg = <0x00 0x200>;
						interrupts = <0x00 0xf1 0x04 0x00 0xf2 0x04 0x00 0xf3 0x04 0x00 0xf4 0x04>;
						#mbox-cells = <0x01>;
						ti,mbox-num-users = <0x04>;
						ti,mbox-num-fifos = <0x0c>;
						status = "disabled";
						phandle = <0x1a8>;
					};
				};

				target-module@3e000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x3e000 0x04 0x3e010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x01>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x0c 0x38 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x3e000 0x1000>;

					mailbox@0 {
						compatible = "ti,omap4-mailbox";
						reg = <0x00 0x200>;
						interrupts = <0x00 0xf5 0x04 0x00 0xf6 0x04 0x00 0xf7 0x04 0x00 0xf8 0x04>;
						#mbox-cells = <0x01>;
						ti,mbox-num-users = <0x04>;
						ti,mbox-num-fifos = <0x0c>;
						status = "disabled";
						phandle = <0x1a9>;
					};
				};

				target-module@40000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x40000 0x04 0x40010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x01>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x0c 0x40 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x40000 0x1000>;

					mailbox@0 {
						compatible = "ti,omap4-mailbox";
						reg = <0x00 0x200>;
						interrupts = <0x00 0xf9 0x04 0x00 0xfa 0x04 0x00 0xfb 0x04 0x00 0xfc 0x04>;
						#mbox-cells = <0x01>;
						ti,mbox-num-users = <0x04>;
						ti,mbox-num-fifos = <0x0c>;
						status = "disabled";
						phandle = <0x1aa>;

						mbox-ipu1-ipc3x {
							ti,mbox-tx = <0x06 0x02 0x02>;
							ti,mbox-rx = <0x04 0x02 0x02>;
							status = "disabled";
							phandle = <0x1ab>;
						};

						mbox-dsp1-ipc3x {
							ti,mbox-tx = <0x05 0x02 0x02>;
							ti,mbox-rx = <0x01 0x02 0x02>;
							status = "disabled";
							phandle = <0x1ac>;
						};
					};
				};

				target-module@42000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x42000 0x04 0x42010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x01>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x0c 0x48 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x42000 0x1000>;

					mailbox@0 {
						compatible = "ti,omap4-mailbox";
						reg = <0x00 0x200>;
						interrupts = <0x00 0xfd 0x04 0x00 0xfe 0x04 0x00 0xff 0x04 0x00 0x100 0x04>;
						#mbox-cells = <0x01>;
						ti,mbox-num-users = <0x04>;
						ti,mbox-num-fifos = <0x0c>;
						status = "disabled";
						phandle = <0x1ad>;

						mbox-ipu2-ipc3x {
							ti,mbox-tx = <0x06 0x02 0x02>;
							ti,mbox-rx = <0x04 0x02 0x02>;
							status = "disabled";
							phandle = <0x1ae>;
						};

						mbox-dsp2-ipc3x {
							ti,mbox-tx = <0x05 0x02 0x02>;
							ti,mbox-rx = <0x01 0x02 0x02>;
							status = "disabled";
							phandle = <0x1af>;
						};
					};
				};

				target-module@44000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x44000 0x04 0x44010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x01>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x0c 0x50 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x44000 0x1000>;

					mailbox@0 {
						compatible = "ti,omap4-mailbox";
						reg = <0x00 0x200>;
						interrupts = <0x00 0x101 0x04 0x00 0x102 0x04 0x00 0x103 0x04 0x00 0x104 0x04>;
						#mbox-cells = <0x01>;
						ti,mbox-num-users = <0x04>;
						ti,mbox-num-fifos = <0x0c>;
						status = "disabled";
						phandle = <0x1b0>;
					};
				};

				target-module@46000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x46000 0x04 0x46010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x01>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x0c 0x58 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x46000 0x1000>;

					mailbox@0 {
						compatible = "ti,omap4-mailbox";
						reg = <0x00 0x200>;
						interrupts = <0x00 0x105 0x04 0x00 0x106 0x04 0x00 0x107 0x04 0x00 0x108 0x04>;
						#mbox-cells = <0x01>;
						ti,mbox-num-users = <0x04>;
						ti,mbox-num-fifos = <0x0c>;
						status = "disabled";
						phandle = <0x1b1>;
					};
				};

				target-module@48000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x48000 0x1000>;
				};

				target-module@4a000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x4a000 0x1000>;
				};

				target-module@4c000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x4c000 0x1000>;
				};

				target-module@4e000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x4e000 0x1000>;
				};

				target-module@50000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x50000 0x1000>;
				};

				target-module@52000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x52000 0x1000>;
				};

				target-module@54000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x54000 0x1000>;
				};

				target-module@56000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x56000 0x1000>;
				};

				target-module@58000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x58000 0x1000>;
				};

				target-module@5a000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x5a000 0x1000>;
				};

				target-module@5c000 {
					compatible = "ti,sysc";
					status = "disabled";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x5c000 0x1000>;
				};

				target-module@5e000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x5e000 0x04 0x5e010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x01>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x0c 0x60 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x5e000 0x1000>;

					mailbox@0 {
						compatible = "ti,omap4-mailbox";
						reg = <0x00 0x200>;
						interrupts = <0x00 0x109 0x04 0x00 0x10a 0x04 0x00 0x10b 0x04 0x00 0x10c 0x04>;
						#mbox-cells = <0x01>;
						ti,mbox-num-users = <0x04>;
						ti,mbox-num-fifos = <0x0c>;
						status = "disabled";
						phandle = <0x1b2>;
					};
				};

				target-module@60000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x60000 0x04 0x60010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x01>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x0c 0x68 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x60000 0x1000>;

					mailbox@0 {
						compatible = "ti,omap4-mailbox";
						reg = <0x00 0x200>;
						interrupts = <0x00 0x10d 0x04 0x00 0x10e 0x04 0x00 0x10f 0x04 0x00 0x110 0x04>;
						#mbox-cells = <0x01>;
						ti,mbox-num-users = <0x04>;
						ti,mbox-num-fifos = <0x0c>;
						status = "disabled";
						phandle = <0x1b3>;
					};
				};

				target-module@62000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x62000 0x04 0x62010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x01>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x0c 0x70 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x62000 0x1000>;

					mailbox@0 {
						compatible = "ti,omap4-mailbox";
						reg = <0x00 0x200>;
						interrupts = <0x00 0x111 0x04 0x00 0x112 0x04 0x00 0x113 0x04 0x00 0x114 0x04>;
						#mbox-cells = <0x01>;
						ti,mbox-num-users = <0x04>;
						ti,mbox-num-fifos = <0x0c>;
						status = "disabled";
						phandle = <0x1b4>;
					};
				};

				target-module@64000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x64000 0x04 0x64010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x01>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0x0c 0x78 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x64000 0x1000>;

					mailbox@0 {
						compatible = "ti,omap4-mailbox";
						reg = <0x00 0x200>;
						interrupts = <0x00 0x115 0x04 0x00 0x116 0x04 0x00 0x117 0x04 0x00 0x118 0x04>;
						#mbox-cells = <0x01>;
						ti,mbox-num-users = <0x04>;
						ti,mbox-num-fifos = <0x0c>;
						status = "disabled";
						phandle = <0x1b5>;
					};
				};

				target-module@80000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x80000 0x04 0x80010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x10000>;
					ti,sysc-midle = <0x00 0x01 0x02 0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x5e 0xd0 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x80000 0x20000>;

					omap_dwc3_1@0 {
						compatible = "ti,dwc3";
						reg = <0x00 0x10000>;
						interrupts = <0x00 0x48 0x04>;
						#address-cells = <0x01>;
						#size-cells = <0x01>;
						utmi-mode = <0x02>;
						ranges = <0x00 0x00 0x20000>;
						phandle = <0x1b6>;

						usb@10000 {
							compatible = "snps,dwc3";
							reg = <0x10000 0x17000>;
							interrupts = <0x00 0x47 0x04 0x00 0x47 0x04 0x00 0x48 0x04>;
							interrupt-names = "peripheral\0host\0otg";
							phys = <0xb0 0xb1>;
							phy-names = "usb2-phy\0usb3-phy";
							maximum-speed = "super-speed";
							dr_mode = "otg";
							snps,dis_u3_susphy_quirk;
							snps,dis_u2_susphy_quirk;
							phandle = <0x1b7>;
						};
					};
				};

				target-module@c0000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0xc0000 0x04 0xc0010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x10000>;
					ti,sysc-midle = <0x00 0x01 0x02 0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x5e 0x20 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0xc0000 0x20000>;

					omap_dwc3_2@0 {
						compatible = "ti,dwc3";
						reg = <0x00 0x10000>;
						interrupts = <0x00 0x57 0x04>;
						#address-cells = <0x01>;
						#size-cells = <0x01>;
						utmi-mode = <0x02>;
						ranges = <0x00 0x00 0x20000>;
						phandle = <0x1b8>;

						usb@10000 {
							compatible = "snps,dwc3";
							reg = <0x10000 0x17000>;
							interrupts = <0x00 0x49 0x04 0x00 0x49 0x04 0x00 0x57 0x04>;
							interrupt-names = "peripheral\0host\0otg";
							phys = <0xb2>;
							phy-names = "usb2-phy";
							maximum-speed = "high-speed";
							dr_mode = "otg";
							snps,dis_u3_susphy_quirk;
							snps,dis_u2_susphy_quirk;
							snps,dis_metastability_quirk;
							phandle = <0x1b9>;
						};
					};
				};

				target-module@100000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x100000 0x04 0x100010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x10000>;
					ti,sysc-midle = <0x00 0x01 0x02 0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x5e 0x28 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x100000 0x20000>;
					status = "disabled";
					phandle = <0x1ba>;

					omap_dwc3_3@0 {
						compatible = "ti,dwc3";
						reg = <0x00 0x10000>;
						interrupts = <0x00 0x158 0x04>;
						#address-cells = <0x01>;
						#size-cells = <0x01>;
						utmi-mode = <0x02>;
						ranges = <0x00 0x00 0x20000>;
						status = "disabled";
						phandle = <0x1bb>;

						usb@10000 {
							compatible = "snps,dwc3";
							reg = <0x10000 0x17000>;
							interrupts = <0x00 0x58 0x04 0x00 0x58 0x04 0x00 0x158 0x04>;
							interrupt-names = "peripheral\0host\0otg";
							maximum-speed = "high-speed";
							dr_mode = "otg";
							snps,dis_u3_susphy_quirk;
							snps,dis_u2_susphy_quirk;
							phandle = <0x1bc>;
						};
					};
				};

				target-module@170000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x170010 0x04>;
					reg-names = "sysc";
					ti,sysc-midle = <0x00 0x01 0x02>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0xb3 0x00 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x170000 0x10000>;
					status = "disabled";
				};

				target-module@190000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x190010 0x04>;
					reg-names = "sysc";
					ti,sysc-midle = <0x00 0x01 0x02>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0xb3 0x08 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x190000 0x10000>;
					status = "disabled";
				};

				target-module@1b0000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x1b0000 0x04 0x1b0010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-midle = <0x00 0x01 0x02>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					clocks = <0xb3 0x10 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x1b0000 0x10000>;
					status = "disabled";
				};

				target-module@1d0010 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x1d0010 0x04>;
					reg-names = "sysc";
					ti,sysc-midle = <0x00 0x01>;
					ti,sysc-sidle = <0x00 0x01 0x02>;
					power-domains = <0xb4>;
					clocks = <0xb5 0x04 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x1d0000 0x10000>;

					vpe@0 {
						compatible = "ti,dra7-vpe";
						reg = <0x00 0x120 0x700 0x80 0x5700 0x18 0xd000 0x400>;
						reg-names = "vpe_top\0sc\0csc\0vpdma";
						interrupts = <0x00 0x162 0x04>;
						phandle = <0x1bd>;
					};
				};

				target-module@140000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x140000 0x04 0x140010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-mask = <0x10000>;
					ti,sysc-midle = <0x00 0x01 0x02 0x03>;
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					clocks = <0x5e 0x30 0x00>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x140000 0x20000>;
					status = "disabled";
					phandle = <0x1be>;

					omap_dwc3_4@0 {
						compatible = "ti,dwc3";
						reg = <0x00 0x10000>;
						interrupts = <0x00 0x15a 0x04>;
						#address-cells = <0x01>;
						#size-cells = <0x01>;
						utmi-mode = <0x02>;
						ranges;
						status = "disabled";
						phandle = <0x1bf>;

						usb@10000 {
							compatible = "snps,dwc3";
							reg = <0x10000 0x17000>;
							interrupts = <0x00 0x159 0x04 0x00 0x159 0x04 0x00 0x15a 0x04>;
							interrupt-names = "peripheral\0host\0otg";
							maximum-speed = "high-speed";
							dr_mode = "otg";
							phandle = <0x1c0>;
						};
					};
				};
			};
		};

		target-module@51000000 {
			compatible = "ti,sysc-omap4\0ti,sysc";
			power-domains = <0x66>;
			resets = <0x66 0x00>;
			reset-names = "rstctrl";
			clocks = <0x63 0x00 0x00 0x63 0x00 0x09 0x63 0x00 0x0a>;
			clock-names = "fck\0phy-clk\0phy-clk-div";
			#size-cells = <0x01>;
			#address-cells = <0x01>;
			ranges = <0x51000000 0x51000000 0x3000 0x20000000 0x20000000 0x10000000>;
			dma-ranges;
			phandle = <0x1c1>;

			pcie@51000000 {
				reg = <0x51000000 0x2000 0x51002000 0x14c 0x20001000 0x2000>;
				reg-names = "rc_dbics\0ti_conf\0config";
				interrupts = <0x00 0xe8 0x04 0x00 0xe9 0x04>;
				#address-cells = <0x03>;
				#size-cells = <0x02>;
				device_type = "pci";
				ranges = <0x81000000 0x00 0x00 0x20003000 0x00 0x10000 0x82000000 0x00 0x20013000 0x20013000 0x00 0xffed000>;
				bus-range = <0x00 0xff>;
				#interrupt-cells = <0x01>;
				num-lanes = <0x01>;
				linux,pci-domain = <0x00>;
				phys = <0xb6>;
				phy-names = "pcie-phy0";
				ti,syscon-lane-sel = <0x62 0x18>;
				interrupt-map-mask = <0x00 0x00 0x00 0x07>;
				interrupt-map = <0x00 0x00 0x00 0x01 0xb7 0x01 0x00 0x00 0x00 0x02 0xb7 0x02 0x00 0x00 0x00 0x03 0xb7 0x03 0x00 0x00 0x00 0x04 0xb7 0x04>;
				ti,syscon-unaligned-access = <0xb8 0x14 0x01>;
				status = "disabled";
				compatible = "ti,dra746-pcie-rc\0ti,dra7-pcie";
				phandle = <0x1c2>;

				interrupt-controller {
					interrupt-controller;
					#address-cells = <0x00>;
					#interrupt-cells = <0x01>;
					phandle = <0xb7>;
				};
			};

			pcie_ep@51000000 {
				reg = <0x51000000 0x28 0x51002000 0x14c 0x51001000 0x28 0x20001000 0x10000000>;
				reg-names = "ep_dbics\0ti_conf\0ep_dbics2\0addr_space";
				interrupts = <0x00 0xe8 0x04>;
				num-lanes = <0x01>;
				num-ib-windows = <0x04>;
				num-ob-windows = <0x10>;
				phys = <0xb6>;
				phy-names = "pcie-phy0";
				ti,syscon-unaligned-access = <0xb8 0x14 0x01>;
				ti,syscon-lane-sel = <0x62 0x18>;
				status = "disabled";
				compatible = "ti,dra746-pcie-ep\0ti,dra7-pcie-ep";
				phandle = <0x1c3>;
			};
		};

		target-module@51800000 {
			compatible = "ti,sysc-omap4\0ti,sysc";
			clocks = <0x63 0x08 0x00 0x63 0x08 0x09 0x63 0x08 0x0a>;
			clock-names = "fck\0phy-clk\0phy-clk-div";
			power-domains = <0x66>;
			resets = <0x66 0x01>;
			reset-names = "rstctrl";
			#size-cells = <0x01>;
			#address-cells = <0x01>;
			ranges = <0x51800000 0x51800000 0x3000 0x30000000 0x30000000 0x10000000>;
			dma-ranges;
			status = "disabled";
			phandle = <0x1c4>;

			pcie@51800000 {
				reg = <0x51800000 0x2000 0x51802000 0x14c 0x30001000 0x2000>;
				reg-names = "rc_dbics\0ti_conf\0config";
				interrupts = <0x00 0x163 0x04 0x00 0x164 0x04>;
				#address-cells = <0x03>;
				#size-cells = <0x02>;
				device_type = "pci";
				ranges = <0x81000000 0x00 0x00 0x30003000 0x00 0x10000 0x82000000 0x00 0x30013000 0x30013000 0x00 0xffed000>;
				bus-range = <0x00 0xff>;
				#interrupt-cells = <0x01>;
				num-lanes = <0x01>;
				linux,pci-domain = <0x01>;
				phys = <0xb9>;
				phy-names = "pcie-phy0";
				interrupt-map-mask = <0x00 0x00 0x00 0x07>;
				interrupt-map = <0x00 0x00 0x00 0x01 0xba 0x01 0x00 0x00 0x00 0x02 0xba 0x02 0x00 0x00 0x00 0x03 0xba 0x03 0x00 0x00 0x00 0x04 0xba 0x04>;
				ti,syscon-unaligned-access = <0xb8 0x14 0x02>;
				compatible = "ti,dra746-pcie-rc\0ti,dra7-pcie";
				phandle = <0x1c5>;

				interrupt-controller {
					interrupt-controller;
					#address-cells = <0x00>;
					#interrupt-cells = <0x01>;
					phandle = <0xba>;
				};
			};
		};

		ocmcram@40300000 {
			compatible = "mmio-sram";
			reg = <0x40300000 0x80000>;
			ranges = <0x00 0x40300000 0x80000>;
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			phandle = <0x1c6>;

			sram-hs@0 {
				compatible = "ti,secure-ram";
				reg = <0x00 0x00>;
			};
		};

		ocmcram@40400000 {
			status = "disabled";
			compatible = "mmio-sram";
			reg = <0x40400000 0x100000>;
			ranges = <0x00 0x40400000 0x100000>;
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			phandle = <0x1c7>;
		};

		ocmcram@40500000 {
			status = "disabled";
			compatible = "mmio-sram";
			reg = <0x40500000 0x100000>;
			ranges = <0x00 0x40500000 0x100000>;
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			phandle = <0x1c8>;
		};

		bandgap@4a0021e0 {
			reg = <0x4a0021e0 0x0c 0x4a00232c 0x0c 0x4a002380 0x2c 0x4a0023c0 0x3c 0x4a002564 0x08 0x4a002574 0x50>;
			compatible = "ti,dra752-bandgap";
			interrupts = <0x00 0x79 0x04>;
			#thermal-sensor-cells = <0x01>;
			phandle = <0xd1>;
		};

		dsp_system@40d00000 {
			compatible = "syscon";
			reg = <0x40d00000 0x100>;
			phandle = <0xc5>;
		};

		padconf@4844a000 {
			compatible = "ti,dra7-iodelay";
			reg = <0x4844a000 0xd1c>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			#pinctrl-cells = <0x02>;
			phandle = <0x1c9>;

			mmc1_iodelay_ddr_rev11_conf {
				pinctrl-pin-array = <0x618 0x23c 0x21c 0x620 0x5f5 0x00 0x624 0x00 0x258 0x628 0x00 0x00 0x62c 0x37 0x00 0x630 0x193 0x78 0x634 0x00 0x00 0x638 0x00 0x00 0x63c 0x17 0x3c 0x640 0x00 0x00 0x644 0x00 0x00 0x648 0x19 0x3c 0x64c 0x00 0x00 0x650 0x00 0x00 0x654 0x00 0x00 0x658 0x00 0x00 0x65c 0x00 0x00>;
				phandle = <0x1ca>;
			};

			mmc1_iodelay_ddr50_rev20_conf {
				pinctrl-pin-array = <0x618 0x434 0x14a 0x620 0x4f7 0x00 0x624 0x2d2 0x00 0x628 0x00 0x00 0x62c 0x00 0x00 0x630 0x2ef 0x00 0x634 0x00 0x00 0x638 0x14 0x00 0x63c 0x100 0x00 0x640 0x00 0x00 0x644 0x00 0x00 0x648 0x107 0x00 0x64c 0x00 0x00 0x650 0x00 0x00 0x654 0x00 0x00 0x658 0x00 0x00 0x65c 0x00 0x00>;
				phandle = <0x1cb>;
			};

			mmc1_iodelay_sdr104_rev11_conf {
				pinctrl-pin-array = <0x620 0x427 0x11 0x628 0x00 0x00 0x62c 0x17 0x00 0x634 0x00 0x00 0x638 0x00 0x00 0x640 0x00 0x00 0x644 0x02 0x00 0x64c 0x00 0x00 0x650 0x00 0x00 0x658 0x00 0x00 0x65c 0x00 0x00>;
				phandle = <0x1cc>;
			};

			mmc1_iodelay_sdr104_rev20_conf {
				pinctrl-pin-array = <0x620 0x258 0x190 0x628 0x00 0x00 0x62c 0x00 0x00 0x634 0x00 0x00 0x638 0x1e 0x00 0x640 0x00 0x00 0x644 0x00 0x00 0x64c 0x00 0x00 0x650 0x00 0x00 0x658 0x00 0x00 0x65c 0x00 0x00>;
				phandle = <0x1cd>;
			};

			mmc2_iodelay_hs200_rev11_conf {
				pinctrl-pin-array = <0x190 0x26d 0x258 0x194 0x12c 0x00 0x1a8 0x2e3 0x258 0x1ac 0xf0 0x00 0x1b4 0x32c 0x258 0x1b8 0xf0 0x00 0x1c0 0x3ba 0x258 0x1c4 0x3c 0x00 0x1d0 0x53c 0x1a4 0x1d8 0x3a7 0x258 0x1dc 0x00 0x00 0x1e4 0x20d 0x258 0x1e8 0x78 0x00 0x1f0 0x2ff 0x258 0x1f4 0xe1 0x00 0x1fc 0x235 0x258 0x200 0x3c 0x00 0x364 0x3c9 0x258 0x368 0xb4 0x00>;
				phandle = <0x1ce>;
			};

			mmc2_iodelay_hs200_rev20_conf {
				pinctrl-pin-array = <0x190 0x112 0x00 0x194 0xa2 0x00 0x1a8 0x191 0x00 0x1ac 0x49 0x00 0x1b4 0x1d1 0x00 0x1b8 0x73 0x00 0x1c0 0x279 0x00 0x1c4 0x2f 0x00 0x1d0 0x3a7 0x118 0x1d8 0x26d 0x00 0x1dc 0x00 0x00 0x1e4 0xb7 0x00 0x1e8 0x00 0x00 0x1f0 0x1d3 0x00 0x1f4 0x00 0x00 0x1fc 0x106 0x00 0x200 0x2e 0x00 0x364 0x2ac 0x00 0x368 0x4c 0x00>;
				phandle = <0x1cf>;
			};

			mmc2_iodelay_ddr_3_3v_rev11_conf {
				pinctrl-pin-array = <0x18c 0x00 0x78 0x190 0x00 0x00 0x194 0xae 0x00 0x1a4 0x109 0x168 0x1a8 0x00 0x00 0x1ac 0xa8 0x00 0x1b0 0x00 0x78 0x1b4 0x00 0x00 0x1b8 0x88 0x00 0x1bc 0x00 0x78 0x1c0 0x00 0x00 0x1c4 0x00 0x00 0x1c8 0x11f 0x1a4 0x1d0 0x36f 0x00 0x1d4 0x90 0xf0 0x1d8 0x00 0x00 0x1dc 0x00 0x00 0x1e0 0x00 0x00 0x1e4 0x00 0x00 0x1e8 0x22 0x00 0x1ec 0x00 0x78 0x1f0 0x00 0x00 0x1f4 0x78 0x00 0x1f8 0x78 0xb4 0x1fc 0x00 0x00 0x200 0x00 0x00 0x360 0x00 0x00 0x364 0x00 0x00 0x368 0x0b 0x00>;
				phandle = <0x1d0>;
			};

			mmc2_iodelay_ddr_1_8v_rev11_conf {
				pinctrl-pin-array = <0x18c 0x00 0x00 0x190 0x00 0x00 0x194 0xae 0x00 0x1a4 0x112 0xf0 0x1a8 0x00 0x00 0x1ac 0xa8 0x00 0x1b0 0x00 0x3c 0x1b4 0x00 0x00 0x1b8 0x88 0x00 0x1bc 0x00 0x3c 0x1c0 0x00 0x00 0x1c4 0x00 0x00 0x1c8 0x202 0x168 0x1d0 0x36f 0x00 0x1d4 0xbb 0x78 0x1d8 0x00 0x00 0x1dc 0x00 0x00 0x1e0 0x00 0x00 0x1e4 0x00 0x00 0x1e8 0x22 0x00 0x1ec 0x00 0x3c 0x1f0 0x00 0x00 0x1f4 0x78 0x00 0x1f8 0x79 0x3c 0x1fc 0x00 0x00 0x200 0x00 0x00 0x360 0x00 0x00 0x364 0x00 0x00 0x368 0x0b 0x00>;
				phandle = <0x1d1>;
			};

			mmc3_iodelay_manual1_conf {
				pinctrl-pin-array = <0x678 0x196 0x00 0x680 0x293 0x00 0x684 0x00 0x00 0x688 0x00 0x00 0x68c 0x00 0x00 0x690 0x82 0x00 0x694 0x00 0x00 0x698 0x00 0x00 0x69c 0xa9 0x00 0x6a0 0x00 0x00 0x6a4 0x00 0x00 0x6a8 0x00 0x00 0x6ac 0x00 0x00 0x6b0 0x00 0x00 0x6b4 0x1c9 0x00 0x6b8 0x00 0x00 0x6bc 0x00 0x00>;
				phandle = <0x1d2>;
			};

			mmc4_iodelay_ds_rev11_conf {
				pinctrl-pin-array = <0x840 0x00 0x00 0x848 0x00 0x00 0x84c 0x60 0x00 0x850 0x00 0x00 0x854 0x00 0x00 0x870 0x246 0x00 0x874 0x00 0x00 0x878 0x00 0x00 0x87c 0x187 0x00 0x880 0x00 0x00 0x884 0x00 0x00 0x888 0x231 0x00 0x88c 0x00 0x00 0x890 0x00 0x00 0x894 0x24c 0x00 0x898 0x00 0x00 0x89c 0x00 0x00>;
				phandle = <0x1d3>;
			};

			mmc4_iodelay_ds_rev20_conf {
				pinctrl-pin-array = <0x840 0x00 0x00 0x848 0x00 0x00 0x84c 0x133 0x00 0x850 0x00 0x00 0x854 0x00 0x00 0x870 0x311 0x00 0x874 0x00 0x00 0x878 0x00 0x00 0x87c 0x265 0x00 0x880 0x00 0x00 0x884 0x00 0x00 0x888 0x2ab 0x00 0x88c 0x00 0x00 0x890 0x00 0x00 0x894 0x343 0x00 0x898 0x00 0x00 0x89c 0x00 0x00>;
				phandle = <0x1d4>;
			};

			mmc4_iodelay_sdr12_hs_sdr25_rev11_conf {
				pinctrl-pin-array = <0x840 0x00 0x00 0x848 0xa5b 0x00 0x84c 0x624 0x00 0x850 0x00 0x00 0x854 0x00 0x00 0x870 0x779 0x00 0x874 0x00 0x00 0x878 0x00 0x00 0x87c 0x6b9 0x00 0x880 0x00 0x00 0x884 0x00 0x00 0x888 0x763 0x00 0x88c 0x00 0x00 0x890 0x00 0x00 0x894 0x77f 0x00 0x898 0x00 0x00 0x89c 0x00 0x00>;
				phandle = <0x1d5>;
			};

			mmc4_iodelay_sdr12_hs_sdr25_rev20_conf {
				pinctrl-pin-array = <0x840 0x00 0x00 0x848 0x47b 0x00 0x84c 0x72a 0x00 0x850 0x00 0x00 0x854 0x00 0x00 0x870 0x875 0x00 0x874 0x00 0x00 0x878 0x00 0x00 0x87c 0x789 0x40 0x880 0x00 0x00 0x884 0x00 0x00 0x888 0x78f 0x80 0x88c 0x00 0x00 0x890 0x00 0x00 0x894 0x87c 0x2c 0x898 0x00 0x00 0x89c 0x00 0x00>;
				phandle = <0x1d6>;
			};
		};

		target-module@43300000 {
			compatible = "ti,sysc-omap4\0ti,sysc";
			reg = <0x43300000 0x04 0x43300010 0x04>;
			reg-names = "rev\0sysc";
			ti,sysc-midle = <0x00 0x01 0x02>;
			ti,sysc-sidle = <0x00 0x01 0x02>;
			clocks = <0x08 0x50 0x00>;
			clock-names = "fck";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x43300000 0x100000>;

			dma@0 {
				compatible = "ti,edma3-tpcc";
				reg = <0x00 0x100000>;
				reg-names = "edma3_cc";
				interrupts = <0x00 0x169 0x04 0x00 0x168 0x04 0x00 0x167 0x04>;
				interrupt-names = "edma3_ccint\0edma3_mperr\0edma3_ccerrint";
				dma-requests = <0x40>;
				#dma-cells = <0x02>;
				ti,tptcs = <0xbb 0x07 0xbc 0x00>;
				phandle = <0x13>;
			};
		};

		target-module@43400000 {
			compatible = "ti,sysc-omap4\0ti,sysc";
			reg = <0x43400000 0x04 0x43400010 0x04>;
			reg-names = "rev\0sysc";
			ti,sysc-midle = <0x00 0x01 0x02>;
			ti,sysc-sidle = <0x00 0x01 0x02>;
			clocks = <0x08 0x58 0x00>;
			clock-names = "fck";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x43400000 0x100000>;

			dma@0 {
				compatible = "ti,edma3-tptc";
				reg = <0x00 0x100000>;
				interrupts = <0x00 0x172 0x04>;
				interrupt-names = "edma3_tcerrint";
				phandle = <0xbb>;
			};
		};

		target-module@43500000 {
			compatible = "ti,sysc-omap4\0ti,sysc";
			reg = <0x43500000 0x04 0x43500010 0x04>;
			reg-names = "rev\0sysc";
			ti,sysc-midle = <0x00 0x01 0x02>;
			ti,sysc-sidle = <0x00 0x01 0x02>;
			clocks = <0x08 0x60 0x00>;
			clock-names = "fck";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x43500000 0x100000>;

			dma@0 {
				compatible = "ti,edma3-tptc";
				reg = <0x00 0x100000>;
				interrupts = <0x00 0x173 0x04>;
				interrupt-names = "edma3_tcerrint";
				phandle = <0xbc>;
			};
		};

		target-module@4e000000 {
			compatible = "ti,sysc-omap2\0ti,sysc";
			reg = <0x4e000000 0x04 0x4e000010 0x04>;
			reg-names = "rev\0sysc";
			ti,sysc-sidle = <0x00 0x01 0x02>;
			ranges = <0x00 0x4e000000 0x2000000>;
			#size-cells = <0x01>;
			#address-cells = <0x01>;

			dmm@0 {
				compatible = "ti,omap5-dmm";
				reg = <0x00 0x800>;
				interrupts = <0x00 0x6c 0x04>;
			};
		};

		ipu@58820000 {
			compatible = "ti,dra7-ipu";
			reg = <0x58820000 0x10000>;
			reg-names = "l2ram";
			iommus = <0xbd>;
			status = "disabled";
			resets = <0xbe 0x00 0xbe 0x01>;
			clocks = <0x40 0x00 0x00>;
			firmware-name = "dra7-ipu1-fw.xem4";
			phandle = <0x1d7>;
		};

		ipu@55020000 {
			compatible = "ti,dra7-ipu";
			reg = <0x55020000 0x10000>;
			reg-names = "l2ram";
			iommus = <0xbf>;
			status = "disabled";
			resets = <0x07 0x00 0x07 0x01>;
			clocks = <0xc0 0x00 0x00>;
			firmware-name = "dra7-ipu2-fw.xem4";
			phandle = <0x1d8>;
		};

		dsp@40800000 {
			compatible = "ti,dra7-dsp";
			reg = <0x40800000 0x48000 0x40e00000 0x8000 0x40f00000 0x8000>;
			reg-names = "l2ram\0l1pram\0l1dram";
			ti,bootreg = <0x0d 0x55c 0x0a>;
			iommus = <0xc1 0xc2>;
			status = "disabled";
			resets = <0xc3 0x00>;
			clocks = <0xc4 0x00 0x00>;
			firmware-name = "dra7-dsp1-fw.xe66";
			phandle = <0x1d9>;
		};

		target-module@40d01000 {
			compatible = "ti,sysc-omap2\0ti,sysc";
			reg = <0x40d01000 0x04 0x40d01010 0x04 0x40d01014 0x04>;
			reg-names = "rev\0sysc\0syss";
			ti,sysc-sidle = <0x00 0x01 0x02>;
			ti,sysc-mask = <0x303>;
			clocks = <0xc4 0x00 0x00>;
			clock-names = "fck";
			resets = <0xc3 0x01>;
			reset-names = "rstctrl";
			ranges = <0x00 0x40d01000 0x1000>;
			#size-cells = <0x01>;
			#address-cells = <0x01>;

			mmu@0 {
				compatible = "ti,dra7-dsp-iommu";
				reg = <0x00 0x100>;
				interrupts = <0x00 0x17 0x04>;
				#iommu-cells = <0x00>;
				ti,syscon-mmuconfig = <0xc5 0x00>;
				phandle = <0xc1>;
			};
		};

		target-module@40d02000 {
			compatible = "ti,sysc-omap2\0ti,sysc";
			reg = <0x40d02000 0x04 0x40d02010 0x04 0x40d02014 0x04>;
			reg-names = "rev\0sysc\0syss";
			ti,sysc-sidle = <0x00 0x01 0x02>;
			ti,sysc-mask = <0x303>;
			clocks = <0xc4 0x00 0x00>;
			clock-names = "fck";
			resets = <0xc3 0x01>;
			reset-names = "rstctrl";
			ranges = <0x00 0x40d02000 0x1000>;
			#size-cells = <0x01>;
			#address-cells = <0x01>;

			mmu@0 {
				compatible = "ti,dra7-dsp-iommu";
				reg = <0x00 0x100>;
				interrupts = <0x00 0x91 0x04>;
				#iommu-cells = <0x00>;
				ti,syscon-mmuconfig = <0xc5 0x01>;
				phandle = <0xc2>;
			};
		};

		target-module@58882000 {
			compatible = "ti,sysc-omap2\0ti,sysc";
			reg = <0x58882000 0x04 0x58882010 0x04 0x58882014 0x04>;
			reg-names = "rev\0sysc\0syss";
			ti,sysc-sidle = <0x00 0x01 0x02>;
			ti,sysc-mask = <0x303>;
			clocks = <0x40 0x00 0x00>;
			clock-names = "fck";
			resets = <0xbe 0x02>;
			reset-names = "rstctrl";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x58882000 0x100>;

			mmu@0 {
				compatible = "ti,dra7-iommu";
				reg = <0x00 0x100>;
				interrupts = <0x00 0x18b 0x04>;
				#iommu-cells = <0x00>;
				ti,iommu-bus-err-back;
				phandle = <0xbd>;
			};
		};

		target-module@55082000 {
			compatible = "ti,sysc-omap2\0ti,sysc";
			reg = <0x55082000 0x04 0x55082010 0x04 0x55082014 0x04>;
			reg-names = "rev\0sysc\0syss";
			ti,sysc-sidle = <0x00 0x01 0x02>;
			ti,sysc-mask = <0x303>;
			clocks = <0xc0 0x00 0x00>;
			clock-names = "fck";
			resets = <0x07 0x02>;
			reset-names = "rstctrl";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x55082000 0x100>;

			mmu@0 {
				compatible = "ti,dra7-iommu";
				reg = <0x00 0x100>;
				interrupts = <0x00 0x18c 0x04>;
				#iommu-cells = <0x00>;
				ti,iommu-bus-err-back;
				phandle = <0xbf>;
			};
		};

		regulator-abb-mpu {
			compatible = "ti,abb-v3";
			regulator-name = "abb_mpu";
			#address-cells = <0x00>;
			#size-cells = <0x00>;
			clocks = <0x15>;
			ti,settling-time = <0x32>;
			ti,clock-cycles = <0x10>;
			reg = <0x4ae07ddc 0x04 0x4ae07de0 0x04 0x4ae06014 0x04 0x4a003b20 0x0c 0x4ae0c158 0x04>;
			reg-names = "setup-address\0control-address\0int-address\0efuse-address\0ldo-address";
			ti,tranxdone-status-mask = <0x80>;
			ti,ldovbb-override-mask = <0x400>;
			ti,ldovbb-vset-mask = <0x1f>;
			ti,abb_info = <0x102ca0 0x00 0x00 0x00 0x2000000 0x1f00000 0x11b340 0x00 0x04 0x00 0x2000000 0x1f00000 0x127690 0x00 0x08 0x00 0x2000000 0x1f00000>;
			phandle = <0x05>;
		};

		regulator-abb-ivahd {
			compatible = "ti,abb-v3";
			regulator-name = "abb_ivahd";
			#address-cells = <0x00>;
			#size-cells = <0x00>;
			clocks = <0x15>;
			ti,settling-time = <0x32>;
			ti,clock-cycles = <0x10>;
			reg = <0x4ae07e34 0x04 0x4ae07e24 0x04 0x4ae06010 0x04 0x4a0025cc 0x0c 0x4a002470 0x04>;
			reg-names = "setup-address\0control-address\0int-address\0efuse-address\0ldo-address";
			ti,tranxdone-status-mask = <0x40000000>;
			ti,ldovbb-override-mask = <0x400>;
			ti,ldovbb-vset-mask = <0x1f>;
			ti,abb_info = <0x101918 0x00 0x00 0x00 0x2000000 0x1f00000 0x118c30 0x00 0x04 0x00 0x2000000 0x1f00000 0x1312d0 0x00 0x08 0x00 0x2000000 0x1f00000>;
			phandle = <0x1da>;
		};

		regulator-abb-dspeve {
			compatible = "ti,abb-v3";
			regulator-name = "abb_dspeve";
			#address-cells = <0x00>;
			#size-cells = <0x00>;
			clocks = <0x15>;
			ti,settling-time = <0x32>;
			ti,clock-cycles = <0x10>;
			reg = <0x4ae07e30 0x04 0x4ae07e20 0x04 0x4ae06010 0x04 0x4a0025e0 0x0c 0x4a00246c 0x04>;
			reg-names = "setup-address\0control-address\0int-address\0efuse-address\0ldo-address";
			ti,tranxdone-status-mask = <0x20000000>;
			ti,ldovbb-override-mask = <0x400>;
			ti,ldovbb-vset-mask = <0x1f>;
			ti,abb_info = <0x101918 0x00 0x00 0x00 0x2000000 0x1f00000 0x118c30 0x00 0x04 0x00 0x2000000 0x1f00000 0x1312d0 0x00 0x08 0x00 0x2000000 0x1f00000>;
			phandle = <0x1db>;
		};

		regulator-abb-gpu {
			compatible = "ti,abb-v3";
			regulator-name = "abb_gpu";
			#address-cells = <0x00>;
			#size-cells = <0x00>;
			clocks = <0x15>;
			ti,settling-time = <0x32>;
			ti,clock-cycles = <0x10>;
			reg = <0x4ae07de4 0x04 0x4ae07de8 0x04 0x4ae06010 0x04 0x4a003b08 0x0c 0x4ae0c154 0x04>;
			reg-names = "setup-address\0control-address\0int-address\0efuse-address\0ldo-address";
			ti,tranxdone-status-mask = <0x10000000>;
			ti,ldovbb-override-mask = <0x400>;
			ti,ldovbb-vset-mask = <0x1f>;
			ti,abb_info = <0x10a1d0 0x00 0x00 0x00 0x2000000 0x1f00000 0x127690 0x00 0x04 0x00 0x2000000 0x1f00000 0x138800 0x00 0x08 0x00 0x2000000 0x1f00000>;
			phandle = <0x1dc>;
		};

		target-module@4b300000 {
			compatible = "ti,sysc-omap4\0ti,sysc";
			reg = <0x4b300000 0x04 0x4b300010 0x04>;
			reg-names = "rev\0sysc";
			ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
			clocks = <0x5b 0x12c 0x00>;
			clock-names = "fck";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x4b300000 0x1000 0x5c000000 0x5c000000 0x4000000>;

			spi@0 {
				compatible = "ti,dra7xxx-qspi";
				reg = <0x00 0x100 0x5c000000 0x4000000>;
				reg-names = "qspi_base\0qspi_mmap";
				syscon-chipselects = <0x0d 0x558>;
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				clocks = <0x5b 0x12c 0x19>;
				clock-names = "fck";
				num-cs = <0x04>;
				interrupts = <0x00 0x157 0x04>;
				status = "disabled";
				phandle = <0x1dd>;
			};
		};

		target-module@50000000 {
			compatible = "ti,sysc-omap2\0ti,sysc";
			reg = <0x50000000 0x04 0x50000010 0x04 0x50000014 0x04>;
			reg-names = "rev\0sysc\0syss";
			ti,sysc-sidle = <0x00 0x01 0x02>;
			ti,syss-mask = <0x01>;
			clocks = <0x08 0x08 0x00>;
			clock-names = "fck";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x50000000 0x50000000 0x1000 0x00 0x00 0x40000000>;

			gpmc@50000000 {
				compatible = "ti,am3352-gpmc";
				reg = <0x50000000 0x37c>;
				interrupts = <0x00 0x0f 0x04>;
				dmas = <0xaa 0x04 0x00>;
				dma-names = "rxtx";
				gpmc,num-cs = <0x08>;
				gpmc,num-waitpins = <0x02>;
				#address-cells = <0x02>;
				#size-cells = <0x01>;
				interrupt-controller;
				#interrupt-cells = <0x02>;
				gpio-controller;
				#gpio-cells = <0x02>;
				status = "disabled";
				phandle = <0x1de>;
			};
		};

		target-module@56000000 {
			compatible = "ti,sysc-omap4\0ti,sysc";
			reg = <0x5600fe00 0x04 0x5600fe10 0x04>;
			reg-names = "rev\0sysc";
			ti,sysc-midle = <0x00 0x01 0x02>;
			ti,sysc-sidle = <0x00 0x01 0x02>;
			clocks = <0xc6 0x00 0x00>;
			clock-names = "fck";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x56000000 0x2000000>;
			phandle = <0x1df>;
		};

		crossbar@4a002a48 {
			compatible = "ti,irq-crossbar";
			reg = <0x4a002a48 0x130>;
			interrupt-controller;
			interrupt-parent = <0x0a>;
			#interrupt-cells = <0x03>;
			ti,max-irqs = <0xa0>;
			ti,max-crossbar-sources = <0x190>;
			ti,reg-size = <0x02>;
			ti,irqs-reserved = <0x00 0x01 0x02 0x03 0x05 0x06 0x83 0x84>;
			ti,irqs-skip = <0x0a 0x85 0x8b 0x8c>;
			ti,irqs-safe-map = <0x00>;
			phandle = <0x01>;
		};

		target-module@58000000 {
			compatible = "ti,sysc-omap2\0ti,sysc";
			reg = <0x58000000 0x04 0x58000014 0x04>;
			reg-names = "rev\0syss";
			ti,syss-mask = <0x01>;
			clocks = <0xc7 0x00 0x00 0xc7 0x00 0x09 0xc7 0x00 0x0a 0xc7 0x00 0x0b>;
			clock-names = "fck\0hdmi_clk\0sys_clk\0tv_clk";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x58000000 0x800000>;

			dss@0 {
				compatible = "ti,dra7-dss";
				status = "disabled";
				syscon-pll-ctrl = <0x0d 0x538>;
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				ranges = <0x00 0x00 0x800000>;
				reg = <0x00 0x80 0x4054 0x04 0x4300 0x20 0x9054 0x04 0x9300 0x20>;
				reg-names = "dss\0pll1_clkctrl\0pll1\0pll2_clkctrl\0pll2";
				clocks = <0xc7 0x00 0x08 0xc7 0x00 0x0c 0xc7 0x00 0x0d>;
				clock-names = "fck\0video1_clk\0video2_clk";
				phandle = <0x1e0>;

				target-module@1000 {
					compatible = "ti,sysc-omap2\0ti,sysc";
					reg = <0x1000 0x04 0x1010 0x04 0x1014 0x04>;
					reg-names = "rev\0sysc\0syss";
					ti,sysc-sidle = <0x00 0x01 0x02>;
					ti,sysc-midle = <0x00 0x01 0x02>;
					ti,sysc-mask = <0x307>;
					ti,syss-mask = <0x01>;
					clocks = <0xc7 0x00 0x08>;
					clock-names = "fck";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x1000 0x1000>;

					dispc@0 {
						compatible = "ti,dra7-dispc";
						reg = <0x00 0x1000>;
						interrupts = <0x00 0x14 0x04>;
						clocks = <0xc7 0x00 0x08>;
						clock-names = "fck";
						syscon-pol = <0x0d 0x534>;
					};
				};

				target-module@40000 {
					compatible = "ti,sysc-omap4\0ti,sysc";
					reg = <0x40000 0x04 0x40010 0x04>;
					reg-names = "rev\0sysc";
					ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
					ti,sysc-mask = <0x01>;
					clocks = <0xc7 0x00 0x09 0xc7 0x00 0x08>;
					clock-names = "fck\0dss_clk";
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x40000 0x40000>;

					encoder@0 {
						compatible = "ti,dra7-hdmi";
						reg = <0x00 0x200 0x200 0x80 0x300 0x80 0x20000 0x19000>;
						reg-names = "wp\0pll\0phy\0core";
						interrupts = <0x00 0x60 0x04>;
						status = "disabled";
						clocks = <0xc7 0x00 0x09 0xc7 0x00 0x0a>;
						clock-names = "fck\0sys_clk";
						dmas = <0x97 0x4c>;
						dma-names = "audio_tx";
						phandle = <0x1e1>;
					};
				};
			};
		};

		target-module@59000000 {
			compatible = "ti,sysc-omap4\0ti,sysc";
			reg = <0x59000020 0x04>;
			reg-names = "rev";
			clocks = <0xc7 0x10 0x00>;
			clock-names = "fck";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x59000000 0x1000>;

			gpu@0 {
				compatible = "vivante,gc";
				reg = <0x00 0x700>;
				interrupts = <0x00 0x78 0x04>;
				clocks = <0xc7 0x10 0x00>;
				clock-names = "core";
				phandle = <0x1e2>;
			};
		};

		target-module@4b500000 {
			compatible = "ti,sysc-omap2\0ti,sysc";
			reg = <0x4b500080 0x04 0x4b500084 0x04 0x4b500088 0x04>;
			reg-names = "rev\0sysc\0syss";
			ti,sysc-mask = <0x03>;
			ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
			ti,syss-mask = <0x01>;
			clocks = <0x9a 0x00 0x00>;
			clock-names = "fck";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x4b500000 0x1000>;
			phandle = <0x1e3>;

			aes@0 {
				compatible = "ti,omap4-aes";
				reg = <0x00 0xa0>;
				interrupts = <0x00 0x50 0x04>;
				dmas = <0xaa 0x6f 0x00 0xaa 0x6e 0x00>;
				dma-names = "tx\0rx";
				clocks = <0x0e>;
				clock-names = "fck";
				phandle = <0x1e4>;
			};
		};

		target-module@4b700000 {
			compatible = "ti,sysc-omap2\0ti,sysc";
			reg = <0x4b700080 0x04 0x4b700084 0x04 0x4b700088 0x04>;
			reg-names = "rev\0sysc\0syss";
			ti,sysc-mask = <0x03>;
			ti,sysc-sidle = <0x00 0x01 0x02 0x03>;
			ti,syss-mask = <0x01>;
			clocks = <0x9a 0x08 0x00>;
			clock-names = "fck";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x4b700000 0x1000>;
			phandle = <0x1e5>;

			aes@0 {
				compatible = "ti,omap4-aes";
				reg = <0x00 0xa0>;
				interrupts = <0x00 0x3b 0x04>;
				dmas = <0xaa 0x72 0x00 0xaa 0x71 0x00>;
				dma-names = "tx\0rx";
				clocks = <0x0e>;
				clock-names = "fck";
				phandle = <0x1e6>;
			};
		};

		target-module@4b101000 {
			compatible = "ti,sysc-omap3-sham\0ti,sysc";
			reg = <0x4b101100 0x04 0x4b101110 0x04 0x4b101114 0x04>;
			reg-names = "rev\0sysc\0syss";
			ti,sysc-mask = <0x03>;
			ti,sysc-sidle = <0x00 0x01 0x02>;
			ti,syss-mask = <0x01>;
			clocks = <0x9a 0x28 0x00>;
			clock-names = "fck";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x4b101000 0x1000>;
			phandle = <0x1e7>;

			sham@0 {
				compatible = "ti,omap5-sham";
				reg = <0x00 0x300>;
				interrupts = <0x00 0x2e 0x04>;
				dmas = <0xaa 0x77 0x00>;
				dma-names = "rx";
				clocks = <0x0e>;
				clock-names = "fck";
				phandle = <0x1e8>;
			};
		};

		target-module@42701000 {
			compatible = "ti,sysc-omap3-sham\0ti,sysc";
			reg = <0x42701100 0x04 0x42701110 0x04 0x42701114 0x04>;
			reg-names = "rev\0sysc\0syss";
			ti,sysc-mask = <0x03>;
			ti,sysc-sidle = <0x00 0x01 0x02>;
			ti,syss-mask = <0x01>;
			clocks = <0x9a 0x58 0x00>;
			clock-names = "fck";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x42701000 0x1000>;
			phandle = <0x1e9>;

			sham@0 {
				compatible = "ti,omap5-sham";
				reg = <0x00 0x300>;
				interrupts = <0x00 0xa3 0x04>;
				dmas = <0xaa 0xa5 0x00>;
				dma-names = "rx";
				clocks = <0x0e>;
				clock-names = "fck";
				phandle = <0x1ea>;
			};
		};

		target-module@5a000000 {
			compatible = "ti,sysc-omap4\0ti,sysc";
			reg = <0x5a05a400 0x04 0x5a05a410 0x04>;
			reg-names = "rev\0sysc";
			ti,sysc-midle = <0x00 0x01 0x02>;
			ti,sysc-sidle = <0x00 0x01 0x02>;
			power-domains = <0xc8>;
			resets = <0xc8 0x02>;
			reset-names = "rstctrl";
			clocks = <0xc9 0x00 0x00>;
			clock-names = "fck";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x5a000000 0x5a000000 0x1000000 0x5b000000 0x5b000000 0x1000000>;
			phandle = <0x1eb>;

			iva {
				compatible = "ti,ivahd";
			};
		};

		opp-supply@4a003b20 {
			compatible = "ti,omap5-opp-supply";
			reg = <0x4a003b20 0x0c>;
			ti,efuse-settings = <0x102ca0 0x00 0x11b340 0x04 0x127690 0x08>;
			ti,absolute-max-voltage-uv = <0x16e360>;
			phandle = <0x1ec>;
		};

		dsp_system@41500000 {
			compatible = "syscon";
			reg = <0x41500000 0x100>;
			phandle = <0xcc>;
		};

		target-module@41501000 {
			compatible = "ti,sysc-omap2\0ti,sysc";
			reg = <0x41501000 0x04 0x41501010 0x04 0x41501014 0x04>;
			reg-names = "rev\0sysc\0syss";
			ti,sysc-sidle = <0x00 0x01 0x02>;
			ti,sysc-mask = <0x303>;
			clocks = <0xca 0x00 0x00>;
			clock-names = "fck";
			resets = <0xcb 0x01>;
			reset-names = "rstctrl";
			ranges = <0x00 0x41501000 0x1000>;
			#size-cells = <0x01>;
			#address-cells = <0x01>;

			mmu@0 {
				compatible = "ti,dra7-dsp-iommu";
				reg = <0x00 0x100>;
				interrupts = <0x00 0x92 0x04>;
				#iommu-cells = <0x00>;
				ti,syscon-mmuconfig = <0xcc 0x00>;
				phandle = <0xcd>;
			};
		};

		target-module@41502000 {
			compatible = "ti,sysc-omap2\0ti,sysc";
			reg = <0x41502000 0x04 0x41502010 0x04 0x41502014 0x04>;
			reg-names = "rev\0sysc\0syss";
			ti,sysc-sidle = <0x00 0x01 0x02>;
			ti,sysc-mask = <0x303>;
			clocks = <0xca 0x00 0x00>;
			clock-names = "fck";
			resets = <0xcb 0x01>;
			reset-names = "rstctrl";
			ranges = <0x00 0x41502000 0x1000>;
			#size-cells = <0x01>;
			#address-cells = <0x01>;

			mmu@0 {
				compatible = "ti,dra7-dsp-iommu";
				reg = <0x00 0x100>;
				interrupts = <0x00 0x93 0x04>;
				#iommu-cells = <0x00>;
				ti,syscon-mmuconfig = <0xcc 0x01>;
				phandle = <0xce>;
			};
		};

		dsp@41000000 {
			compatible = "ti,dra7-dsp";
			reg = <0x41000000 0x48000 0x41600000 0x8000 0x41700000 0x8000>;
			reg-names = "l2ram\0l1pram\0l1dram";
			ti,bootreg = <0x0d 0x560 0x0a>;
			iommus = <0xcd 0xce>;
			status = "disabled";
			resets = <0xcb 0x00>;
			clocks = <0xca 0x00 0x00>;
			firmware-name = "dra7-dsp2-fw.xe66";
			phandle = <0x1ed>;
		};

		target-module@4b226000 {
			compatible = "ti,sysc-pruss\0ti,sysc";
			reg = <0x4b226000 0x04 0x4b226004 0x04>;
			reg-names = "rev\0sysc";
			ti,sysc-mask = <0x30>;
			ti,sysc-midle = <0x00 0x01 0x02>;
			ti,sysc-sidle = <0x00 0x01 0x02>;
			clocks = <0x5b 0x0c 0x00>;
			clock-names = "fck";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x4b200000 0x80000>;
			phandle = <0x1ee>;

			pruss@0 {
				compatible = "ti,am5728-pruss";
				reg = <0x00 0x80000>;
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				ranges;
				phandle = <0x1ef>;

				memories@0 {
					reg = <0x00 0x2000 0x2000 0x2000 0x10000 0x8000>;
					reg-names = "dram0\0dram1\0shrdram2";
					phandle = <0x1f0>;
				};

				cfg@26000 {
					compatible = "ti,pruss-cfg\0syscon";
					reg = <0x26000 0x2000>;
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x26000 0x2000>;
					phandle = <0x1f1>;

					clocks {
						#address-cells = <0x01>;
						#size-cells = <0x00>;

						iepclk-mux@30 {
							reg = <0x30>;
							#clock-cells = <0x00>;
							clocks = <0xcf 0xd0>;
							phandle = <0x1f2>;
						};
					};
				};

				mii-rt@32000 {
					compatible = "ti,pruss-mii\0syscon";
					reg = <0x32000 0x58>;
					phandle = <0x1f3>;
				};

				interrupt-controller@20000 {
					compatible = "ti,pruss-intc";
					reg = <0x20000 0x2000>;
					interrupt-controller;
					#interrupt-cells = <0x03>;
					interrupts = <0x00 0xba 0x04 0x00 0xbb 0x04 0x00 0xbc 0x04 0x00 0xbd 0x04 0x00 0xbe 0x04 0x00 0xbf 0x04 0x00 0xc0 0x04 0x00 0xc1 0x04>;
					interrupt-names = "host_intr0\0host_intr1\0host_intr2\0host_intr3\0host_intr4\0host_intr5\0host_intr6\0host_intr7";
					phandle = <0x1f4>;
				};

				pru@34000 {
					compatible = "ti,am5728-pru";
					reg = <0x34000 0x3000 0x22000 0x400 0x22400 0x100>;
					reg-names = "iram\0control\0debug";
					firmware-name = "am57xx-pru1_0-fw";
					phandle = <0x1f5>;
				};

				pru@38000 {
					compatible = "ti,am5728-pru";
					reg = <0x38000 0x3000 0x24000 0x400 0x24400 0x100>;
					reg-names = "iram\0control\0debug";
					firmware-name = "am57xx-pru1_1-fw";
					phandle = <0x1f6>;
				};

				mdio@32400 {
					compatible = "ti,davinci_mdio";
					#address-cells = <0x01>;
					#size-cells = <0x00>;
					clocks = <0xd0>;
					clock-names = "fck";
					bus_freq = <0xf4240>;
					reg = <0x32400 0x90>;
					status = "disabled";
					phandle = <0x1f7>;
				};
			};
		};

		target-module@4b2a6000 {
			compatible = "ti,sysc-pruss\0ti,sysc";
			reg = <0x4b2a6000 0x04 0x4b2a6004 0x04>;
			reg-names = "rev\0sysc";
			ti,sysc-mask = <0x30>;
			ti,sysc-midle = <0x00 0x01 0x02>;
			ti,sysc-sidle = <0x00 0x01 0x02>;
			clocks = <0x5b 0x14 0x00>;
			clock-names = "fck";
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			ranges = <0x00 0x4b280000 0x80000>;
			phandle = <0x1f8>;

			pruss@0 {
				compatible = "ti,am5728-pruss";
				reg = <0x00 0x80000>;
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				ranges;
				phandle = <0x1f9>;

				memories@0 {
					reg = <0x00 0x2000 0x2000 0x2000 0x10000 0x8000>;
					reg-names = "dram0\0dram1\0shrdram2";
					phandle = <0x1fa>;
				};

				cfg@26000 {
					compatible = "ti,pruss-cfg\0syscon";
					reg = <0x26000 0x2000>;
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					ranges = <0x00 0x26000 0x2000>;
					phandle = <0x1fb>;

					clocks {
						#address-cells = <0x01>;
						#size-cells = <0x00>;

						iepclk-mux@30 {
							reg = <0x30>;
							#clock-cells = <0x00>;
							clocks = <0xcf 0xd0>;
							phandle = <0x1fc>;
						};
					};
				};

				mii-rt@32000 {
					compatible = "ti,pruss-mii\0syscon";
					reg = <0x32000 0x58>;
					phandle = <0x1fd>;
				};

				interrupt-controller@20000 {
					compatible = "ti,pruss-intc";
					reg = <0x20000 0x2000>;
					interrupt-controller;
					#interrupt-cells = <0x03>;
					interrupts = <0x00 0xc4 0x04 0x00 0xc5 0x04 0x00 0xc6 0x04 0x00 0xc7 0x04 0x00 0xc8 0x04 0x00 0xc9 0x04 0x00 0xca 0x04 0x00 0xcb 0x04>;
					interrupt-names = "host_intr0\0host_intr1\0host_intr2\0host_intr3\0host_intr4\0host_intr5\0host_intr6\0host_intr7";
					phandle = <0x1fe>;
				};

				pru@34000 {
					compatible = "ti,am5728-pru";
					reg = <0x34000 0x3000 0x22000 0x400 0x22400 0x100>;
					reg-names = "iram\0control\0debug";
					firmware-name = "am57xx-pru2_0-fw";
					phandle = <0x1ff>;
				};

				pru@38000 {
					compatible = "ti,am5728-pru";
					reg = <0x38000 0x3000 0x24000 0x400 0x24400 0x100>;
					reg-names = "iram\0control\0debug";
					firmware-name = "am57xx-pru2_1-fw";
					phandle = <0x200>;
				};

				mdio@32400 {
					compatible = "ti,davinci_mdio";
					#address-cells = <0x01>;
					#size-cells = <0x00>;
					clocks = <0xd0>;
					clock-names = "fck";
					bus_freq = <0xf4240>;
					reg = <0x32400 0x90>;
					status = "disabled";
					phandle = <0x201>;
				};
			};
		};
	};

	thermal-zones {
		phandle = <0x202>;

		cpu_thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0xd1 0x00>;
			coefficients = <0x00 0x7d0>;
			phandle = <0x203>;

			trips {
				phandle = <0x204>;

				cpu_alert {
					temperature = <0x186a0>;
					hysteresis = <0x7d0>;
					type = "passive";
					phandle = <0xd2>;
				};

				cpu_crit {
					temperature = <0x1d4c0>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0x205>;
				};
			};

			cooling-maps {
				phandle = <0x206>;

				map0 {
					trip = <0xd2>;
					cooling-device = <0xd3 0xffffffff 0xffffffff>;
				};
			};
		};

		gpu_thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0xd1 0x01>;
			coefficients = <0x00 0x7d0>;
			phandle = <0x207>;

			trips {

				gpu_crit {
					temperature = <0x1d4c0>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0x208>;
				};
			};
		};

		core_thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0xd1 0x02>;
			coefficients = <0x00 0x7d0>;
			phandle = <0x209>;

			trips {

				core_crit {
					temperature = <0x1d4c0>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0x20a>;
				};
			};
		};

		dspeve_thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0xd1 0x03>;
			coefficients = <0x00 0x7d0>;
			phandle = <0x20b>;

			trips {

				dspeve_crit {
					temperature = <0x1d4c0>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0x20c>;
				};
			};
		};

		iva_thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0xd1 0x04>;
			coefficients = <0x00 0x7d0>;
			phandle = <0x20d>;

			trips {

				iva_crit {
					temperature = <0x1d4c0>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0x20e>;
				};
			};
		};
	};

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupt-parent = <0x0a>;
		interrupts = <0x00 0x83 0x04 0x00 0x84 0x04>;
	};

	status-leds {
		compatible = "gpio-leds";

		cpu0-led {
			label = "led:red:cpu";
			gpios = <0xd4 0x09 0x00>;
			linux,default-trigger = "cpu0";
			default-state = "off";
		};

		mmc0-led {
			label = "led:green:mmc";
			gpios = <0xd4 0x0a 0x00>;
			linux,default-trigger = "mmc0";
			default-state = "off";
		};
	};

	__symbols__ {
		gic = "/interrupt-controller@48211000";
		wakeupgen = "/interrupt-controller@48281000";
		cpu0 = "/cpus/cpu@0";
		cpu0_opp_table = "/opp-table";
		ocp = "/ocp";
		l4_cfg = "/ocp/interconnect@4a000000";
		scm = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0";
		scm_conf = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@0";
		pbias_regulator = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@0/pbias_regulator@e00";
		pbias_mmc_reg = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@0/pbias_regulator@e00/pbias_mmc_omap5";
		phy_gmii_sel = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@0/phy-gmii-sel";
		scm_conf_clocks = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@0/clocks";
		dss_deshdcp_clk = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@0/clocks/clock-dss-deshdcp-0@558";
		ehrpwm0_tbclk = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@0/clocks/clock-ehrpwm0-tbclk-20@558";
		ehrpwm1_tbclk = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@0/clocks/clock-ehrpwm1-tbclk-21@558";
		ehrpwm2_tbclk = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@0/clocks/clock-ehrpwm2-tbclk-22@558";
		sys_32k_ck = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@0/clocks/clock-sys-32k";
		dra7_pmx_core = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400";
		mmc1_pins_default_no_clk_pu = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc1_pins_default_no_clk_pu";
		mmc1_pins_default = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc1_pins_default";
		mmc1_pins_sdr12 = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc1_pins_sdr12";
		mmc1_pins_hs = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc1_pins_hs";
		mmc1_pins_sdr25 = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc1_pins_sdr25";
		mmc1_pins_sdr50 = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc1_pins_sdr50";
		mmc1_pins_ddr50 = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc1_pins_ddr50";
		mmc1_pins_sdr104 = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc1_pins_sdr104";
		mmc2_pins_default = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc2_pins_default";
		mmc2_pins_hs = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc2_pins_hs";
		mmc2_pins_ddr_3_3v_rev11 = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc2_pins_ddr_3_3v_rev11";
		mmc2_pins_ddr_1_8v_rev11 = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc2_pins_ddr_1_8v_rev11";
		mmc2_pins_ddr_rev20 = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc2_pins_ddr_rev20";
		mmc2_pins_hs200 = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc2_pins_hs200";
		mmc4_pins_default = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc4_pins_default";
		mmc4_pins_hs = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc4_pins_hs";
		mmc3_pins_default = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc3_pins_default";
		mmc3_pins_hs = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc3_pins_hs";
		mmc3_pins_sdr12 = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc3_pins_sdr12";
		mmc3_pins_sdr25 = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc3_pins_sdr25";
		mmc3_pins_sdr50 = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc3_pins_sdr50";
		mmc4_pins_sdr12 = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc4_pins_sdr12";
		mmc4_pins_sdr25 = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/pinmux@1400/mmc4_pins_sdr25";
		scm_conf1 = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@1c04";
		scm_conf_pcie = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/scm_conf@1c24";
		sdma_xbar = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/dma-router@b78";
		edma_xbar = "/ocp/interconnect@4a000000/segment@0/target-module@2000/scm@0/dma-router@c78";
		cm_core_aon = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0";
		cm_core_aon_clocks = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks";
		atl_clkin0_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-atl-clkin0";
		atl_clkin1_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-atl-clkin1";
		atl_clkin2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-atl-clkin2";
		atl_clkin3_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-atl-clkin3";
		hdmi_clkin_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-hdmi-clkin";
		mlb_clkin_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-mlb-clkin";
		mlbp_clkin_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-mlbp-clkin";
		pciesref_acs_clk_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-pciesref-acs";
		ref_clkin0_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-ref-clkin0";
		ref_clkin1_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-ref-clkin1";
		ref_clkin2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-ref-clkin2";
		ref_clkin3_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-ref-clkin3";
		rmii_clk_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-rmii";
		sdvenc_clkin_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-sdvenc-clkin";
		secure_32k_clk_src_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-secure-32k-clk-src";
		sys_clk32_crystal_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-sys-clk32-crystal";
		sys_clk32_pseudo_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-sys-clk32-pseudo";
		virt_12000000_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-virt-12000000";
		virt_13000000_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-virt-13000000";
		virt_16800000_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-virt-16800000";
		virt_19200000_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-virt-19200000";
		virt_20000000_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-virt-20000000";
		virt_26000000_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-virt-26000000";
		virt_27000000_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-virt-27000000";
		virt_38400000_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-virt-38400000";
		sys_clkin2 = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-sys-clkin2";
		usb_otg_clkin_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-usb-otg-clkin";
		video1_clkin_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-video1-clkin";
		video1_m2_clkin_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-video1-m2-clkin";
		video2_clkin_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-video2-clkin";
		video2_m2_clkin_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-video2-m2-clkin";
		dpll_abe_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@1e0";
		dpll_abe_x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-abe-x2";
		dpll_abe_m2x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-abe-m2x2-8@1f0";
		abe_clk = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-abe@108";
		dpll_abe_m2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-abe-m2-8@1f0";
		dpll_abe_m3x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-abe-m3x2-8@1f4";
		dpll_core_byp_mux = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-core-byp-mux-23@12c";
		dpll_core_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@120";
		dpll_core_x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-core-x2";
		dpll_core_h12x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-core-h12x2-8@13c";
		mpu_dpll_hs_clk_div = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-mpu-dpll-hs-clk-div";
		dpll_mpu_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@160";
		dpll_mpu_m2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-mpu-m2-8@170";
		mpu_dclk_div = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-mpu-dclk-div";
		dsp_dpll_hs_clk_div = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dsp-dpll-hs-clk-div";
		dpll_dsp_byp_mux = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-dsp-byp-mux-23@240";
		dpll_dsp_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@234";
		dpll_dsp_m2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-dsp-m2-8@244";
		iva_dpll_hs_clk_div = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-iva-dpll-hs-clk-div";
		dpll_iva_byp_mux = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-iva-byp-mux-23@1ac";
		dpll_iva_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@1a0";
		dpll_iva_m2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-iva-m2-8@1b0";
		iva_dclk = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-iva-dclk";
		dpll_gpu_byp_mux = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-gpu-byp-mux-23@2e4";
		dpll_gpu_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@2d8";
		dpll_gpu_m2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-gpu-m2-8@2e8";
		dpll_core_m2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-core-m2-8@130";
		core_dpll_out_dclk_div = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-core-dpll-out-dclk-div";
		dpll_ddr_byp_mux = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-ddr-byp-mux-23@21c";
		dpll_ddr_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@210";
		dpll_ddr_m2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-ddr-m2-8@220";
		dpll_gmac_byp_mux = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-gmac-byp-mux-23@2b4";
		dpll_gmac_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@2a8";
		dpll_gmac_m2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-gmac-m2-8@2b8";
		video2_dclk_div = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-video2-dclk-div";
		video1_dclk_div = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-video1-dclk-div";
		hdmi_dclk_div = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-hdmi-dclk-div";
		per_dpll_hs_clk_div = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-per-dpll-hs-clk-div";
		usb_dpll_hs_clk_div = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-usb-dpll-hs-clk-div";
		eve_dpll_hs_clk_div = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-eve-dpll-hs-clk-div";
		dpll_eve_byp_mux = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-eve-byp-mux-23@290";
		dpll_eve_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock@284";
		dpll_eve_m2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-eve-m2-8@294";
		eve_dclk_div = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-eve-dclk-div";
		dpll_core_h13x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-core-h13x2-8@140";
		dpll_core_h14x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-core-h14x2-8@144";
		dpll_core_h22x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-core-h22x2-8@154";
		dpll_core_h23x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-core-h23x2-8@158";
		dpll_core_h24x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-core-h24x2-8@15c";
		dpll_ddr_x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-ddr-x2";
		dpll_ddr_h11x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-ddr-h11x2-8@228";
		dpll_dsp_x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-dsp-x2";
		dpll_dsp_m3x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-dsp-m3x2-8@248";
		dpll_gmac_x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-gmac-x2";
		dpll_gmac_h11x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-gmac-h11x2-8@2c0";
		dpll_gmac_h12x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-gmac-h12x2-8@2c4";
		dpll_gmac_h13x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-gmac-h13x2-8@2c8";
		dpll_gmac_m3x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dpll-gmac-m3x2-8@2bc";
		gmii_m_clk_div = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-gmii-m-clk-div";
		hdmi_clk2_div = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-hdmi-clk2-div";
		hdmi_div_clk = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-hdmi-div";
		l3_iclk_div = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-l3-iclk-div-4@100";
		l4_root_clk_div = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-l4-root-clk-div";
		video1_clk2_div = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-video1-clk2-div";
		video1_div_clk = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-video1-div";
		video2_clk2_div = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-video2-clk2-div";
		video2_div_clk = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-video2-div";
		dummy_ck = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clocks/clock-dummy";
		cm_core_aon_clockdomains = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clockdomains";
		mpu_cm = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@300";
		mpu_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@300/clock@20";
		dsp1_cm = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@400";
		dsp1_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@400/clock@20";
		ipu_cm = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@500";
		ipu1_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@500/clock@20";
		ipu_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@500/clock@50";
		dsp2_cm = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@600";
		dsp2_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@600/clock@20";
		rtc_cm = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@700";
		rtc_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@700/clock@20";
		vpe_cm = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@760";
		vpe_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@5000/cm_core_aon@0/clock@760/clock@0";
		cm_core = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0";
		cm_core_clocks = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks";
		dpll_pcie_ref_ck = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock@200";
		dpll_pcie_ref_m2ldo_ck = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-pcie-ref-m2ldo-8@210";
		apll_pcie_in_clk_mux = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-apll-pcie-in-clk-mux-7@4ae06118";
		apll_pcie_ck = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock@21c";
		optfclk_pciephy_div = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-optfclk-pciephy-div-8@4a00821c";
		apll_pcie_clkvcoldo = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-apll-pcie-clkvcoldo";
		apll_pcie_clkvcoldo_div = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-apll-pcie-clkvcoldo-div";
		apll_pcie_m2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-apll-pcie-m2";
		dpll_per_byp_mux = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-per-byp-mux-23@14c";
		dpll_per_ck = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock@140";
		dpll_per_m2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-per-m2-8@150";
		func_96m_aon_dclk_div = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-func-96m-aon-dclk-div";
		dpll_usb_byp_mux = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-usb-byp-mux-23@18c";
		dpll_usb_ck = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock@180";
		dpll_usb_m2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-usb-m2-8@190";
		dpll_pcie_ref_m2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-pcie-ref-m2-8@210";
		dpll_per_x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-per-x2";
		dpll_per_h11x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-per-h11x2-8@158";
		dpll_per_h12x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-per-h12x2-8@15c";
		dpll_per_h13x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-per-h13x2-8@160";
		dpll_per_h14x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-per-h14x2-8@164";
		dpll_per_m2x2_ck = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-per-m2x2-8@150";
		dpll_usb_clkdcoldo = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-dpll-usb-clkdcoldo";
		func_128m_clk = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-func-128m";
		func_12m_fclk = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-func-12m-fclk";
		func_24m_clk = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-func-24m";
		func_48m_fclk = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-func-48m-fclk";
		func_96m_fclk = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-func-96m-fclk";
		l3init_60m_fclk = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-l3init-60m@104";
		clkout2_clk = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-clkout2-8@6b0";
		l3init_960m_gfclk = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-l3init-960m-gfclk-8@6c0";
		usb_phy1_always_on_clk32k = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-usb-phy1-always-on-clk32k-8@640";
		usb_phy2_always_on_clk32k = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-usb-phy2-always-on-clk32k-8@688";
		usb_phy3_always_on_clk32k = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-usb-phy3-always-on-clk32k-8@698";
		gpu_core_gclk_mux = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-gpu-core-gclk-mux-24@1220";
		gpu_hyd_gclk_mux = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-gpu-hyd-gclk-mux-26@1220";
		l3instr_ts_gclk_div = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-l3instr-ts-gclk-div-24@e50";
		vip1_gclk_mux = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-vip1-gclk-mux-24@1020";
		vip2_gclk_mux = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-vip2-gclk-mux-24@1028";
		vip3_gclk_mux = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clocks/clock-vip3-gclk-mux-24@1030";
		cm_core_clockdomains = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clockdomains";
		coreaon_clkdm = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clockdomains/clock-coreaon-clkdm";
		coreaon_cm = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@600";
		coreaon_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@600/clock@20";
		l3main1_cm = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@700";
		l3main1_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@700/clock@20";
		ipu2_cm = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@900";
		ipu2_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@900/clock@20";
		dma_cm = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@a00";
		dma_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@a00/clock@20";
		emif_cm = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@b00";
		emif_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@b00/clock@20";
		atl_cm = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@c00";
		atl_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@c00/clock@0";
		l4cfg_cm = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@d00";
		l4cfg_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@d00/clock@20";
		l3instr_cm = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@e00";
		l3instr_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@e00/clock@20";
		iva_cm = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@f00";
		iva_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@f00/clock@20";
		cam_cm = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1000";
		cam_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1000/clock@20";
		dss_cm = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1100";
		dss_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1100/clock@20";
		gpu_cm = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1200";
		gpu_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1200/clock@20";
		l3init_cm = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1300";
		l3init_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1300/clock@20";
		pcie_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1300/clock@b0";
		gmac_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1300/clock@d0";
		l4per_cm = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1700";
		l4per_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1700/clock@28";
		l4sec_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1700/clock@1a0";
		l4per2_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1700/clock@c";
		l4per3_clkctrl = "/ocp/interconnect@4a000000/segment@0/target-module@8000/cm_core@0/clock@1700/clock@14";
		sdma = "/ocp/interconnect@4a000000/segment@0/target-module@56000/dma-controller@0";
		usb2_phy1 = "/ocp/interconnect@4a000000/segment@0/target-module@80000/ocp2scp@0/phy@4000";
		usb2_phy2 = "/ocp/interconnect@4a000000/segment@0/target-module@80000/ocp2scp@0/phy@5000";
		usb3_phy1 = "/ocp/interconnect@4a000000/segment@0/target-module@80000/ocp2scp@0/phy@4400";
		pcie1_phy = "/ocp/interconnect@4a000000/segment@0/target-module@90000/ocp2scp@0/pciephy@4000";
		pcie2_phy = "/ocp/interconnect@4a000000/segment@0/target-module@90000/ocp2scp@0/pciephy@5000";
		sata_phy = "/ocp/interconnect@4a000000/segment@0/target-module@90000/ocp2scp@0/phy@6000";
		mailbox1 = "/ocp/interconnect@4a000000/segment@0/target-module@f4000/mailbox@0";
		hwspinlock = "/ocp/interconnect@4a000000/segment@0/target-module@f6000/spinlock@0";
		sata = "/ocp/interconnect@4a000000/segment@100000/target-module@40000/sata@0";
		l4_wkup = "/ocp/interconnect@4ae00000";
		counter32k = "/ocp/interconnect@4ae00000/segment@0/target-module@4000/counter@0";
		prm = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0";
		prm_clocks = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks";
		sys_clkin1 = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-sys-clkin1@110";
		abe_dpll_sys_clk_mux = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-abe-dpll-sys-clk-mux@118";
		abe_dpll_bypass_clk_mux = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-abe-dpll-bypass-clk-mux@114";
		abe_dpll_clk_mux = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-abe-dpll-clk-mux@10c";
		abe_24m_fclk = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-abe-24m@11c";
		aess_fclk = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-aess@178";
		abe_giclk_div = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-abe-giclk-div@174";
		abe_lp_clk_div = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-abe-lp-clk-div@1d8";
		abe_sys_clk_div = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-abe-sys-clk-div@120";
		adc_gfclk_mux = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-adc-gfclk-mux@1dc";
		sys_clk1_dclk_div = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-sys-clk1-dclk-div@1c8";
		sys_clk2_dclk_div = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-sys-clk2-dclk-div@1cc";
		per_abe_x1_dclk_div = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-per-abe-x1-dclk-div@1bc";
		dsp_gclk_div = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-dsp-gclk-div@18c";
		gpu_dclk = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-gpu-dclk@1a0";
		emif_phy_dclk_div = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-emif-phy-dclk-div@190";
		gmac_250m_dclk_div = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-gmac-250m-dclk-div@19c";
		gmac_main_clk = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-gmac-main";
		l3init_480m_dclk_div = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-l3init-480m-dclk-div@1ac";
		usb_otg_dclk_div = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-usb-otg-dclk-div@184";
		sata_dclk_div = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-sata-dclk-div@1c0";
		pcie2_dclk_div = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-pcie2-dclk-div@1b8";
		pcie_dclk_div = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-pcie-dclk-div@1b4";
		emu_dclk_div = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-emu-dclk-div@194";
		secure_32k_dclk_div = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-secure-32k-dclk-div@1c4";
		clkoutmux0_clk_mux = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-clkoutmux0-clk-mux@158";
		clkoutmux1_clk_mux = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-clkoutmux1-clk-mux@15c";
		clkoutmux2_clk_mux = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-clkoutmux2-clk-mux@160";
		custefuse_sys_gfclk_div = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-custefuse-sys-gfclk-div";
		eve_clk = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-eve@180";
		hdmi_dpll_clk_mux = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-hdmi-dpll-clk-mux@164";
		mlb_clk = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-mlb@134";
		mlbp_clk = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-mlbp@130";
		per_abe_x1_gfclk2_div = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-per-abe-x1-gfclk2-div@138";
		timer_sys_clk_div = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-timer-sys-clk-div@144";
		video1_dpll_clk_mux = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-video1-dpll-clk-mux@168";
		video2_dpll_clk_mux = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-video2-dpll-clk-mux@16c";
		wkupaon_iclk_mux = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clocks/clock-wkupaon-iclk-mux@108";
		prm_clockdomains = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clockdomains";
		wkupaon_cm = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clock@1800";
		wkupaon_clkctrl = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/clock@1800/clock@20";
		prm_mpu = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@300";
		prm_dsp1 = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@400";
		prm_ipu = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@500";
		prm_coreaon = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@628";
		prm_core = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@700";
		prm_iva = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@f00";
		prm_cam = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1000";
		prm_dss = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1100";
		prm_gpu = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1200";
		prm_l3init = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1300";
		prm_l4per = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1400";
		prm_custefuse = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1600";
		prm_wkupaon = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1724";
		prm_dsp2 = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1b00";
		prm_eve1 = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1b40";
		prm_eve2 = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1b80";
		prm_eve3 = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1bc0";
		prm_eve4 = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1c00";
		prm_rtc = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1c60";
		prm_vpe = "/ocp/interconnect@4ae00000/segment@0/target-module@6000/prm@0/prm@1c80";
		scm_wkup = "/ocp/interconnect@4ae00000/segment@0/target-module@c000/scm_conf@0";
		gpio1 = "/ocp/interconnect@4ae00000/segment@10000/target-module@0/gpio@0";
		wdt2 = "/ocp/interconnect@4ae00000/segment@10000/target-module@4000/wdt@0";
		timer1_target = "/ocp/interconnect@4ae00000/segment@10000/target-module@8000";
		timer1 = "/ocp/interconnect@4ae00000/segment@10000/target-module@8000/timer@0";
		timer12 = "/ocp/interconnect@4ae00000/segment@20000/target-module@0/timer@0";
		uart10 = "/ocp/interconnect@4ae00000/segment@20000/target-module@b000/serial@0";
		dcan1 = "/ocp/interconnect@4ae00000/segment@30000/target-module@c000/can@0";
		l4_per1 = "/ocp/interconnect@48000000";
		uart3 = "/ocp/interconnect@48000000/segment@0/target-module@20000/serial@0";
		timer2 = "/ocp/interconnect@48000000/segment@0/target-module@32000/timer@0";
		timer3_target = "/ocp/interconnect@48000000/segment@0/target-module@34000";
		timer3 = "/ocp/interconnect@48000000/segment@0/target-module@34000/timer@0";
		timer4_target = "/ocp/interconnect@48000000/segment@0/target-module@36000";
		timer4 = "/ocp/interconnect@48000000/segment@0/target-module@36000/timer@0";
		timer9 = "/ocp/interconnect@48000000/segment@0/target-module@3e000/timer@0";
		gpio7_target = "/ocp/interconnect@48000000/segment@0/target-module@51000";
		gpio7 = "/ocp/interconnect@48000000/segment@0/target-module@51000/gpio@0";
		gpio8 = "/ocp/interconnect@48000000/segment@0/target-module@53000/gpio@0";
		gpio2_target = "/ocp/interconnect@48000000/segment@0/target-module@55000";
		gpio2 = "/ocp/interconnect@48000000/segment@0/target-module@55000/gpio@0";
		gpio3_target = "/ocp/interconnect@48000000/segment@0/target-module@57000";
		gpio3 = "/ocp/interconnect@48000000/segment@0/target-module@57000/gpio@0";
		gpio4 = "/ocp/interconnect@48000000/segment@0/target-module@59000/gpio@0";
		gpio5 = "/ocp/interconnect@48000000/segment@0/target-module@5b000/gpio@0";
		gpio6 = "/ocp/interconnect@48000000/segment@0/target-module@5d000/gpio@0";
		i2c3 = "/ocp/interconnect@48000000/segment@0/target-module@60000/i2c@0";
		uart5 = "/ocp/interconnect@48000000/segment@0/target-module@66000/serial@0";
		uart6 = "/ocp/interconnect@48000000/segment@0/target-module@68000/serial@0";
		uart1 = "/ocp/interconnect@48000000/segment@0/target-module@6a000/serial@0";
		uart2 = "/ocp/interconnect@48000000/segment@0/target-module@6c000/serial@0";
		uart4 = "/ocp/interconnect@48000000/segment@0/target-module@6e000/serial@0";
		i2c1 = "/ocp/interconnect@48000000/segment@0/target-module@70000/i2c@0";
		i2c2 = "/ocp/interconnect@48000000/segment@0/target-module@72000/i2c@0";
		elm = "/ocp/interconnect@48000000/segment@0/target-module@78000/elm@0";
		i2c4 = "/ocp/interconnect@48000000/segment@0/target-module@7a000/i2c@0";
		i2c5 = "/ocp/interconnect@48000000/segment@0/target-module@7c000/i2c@0";
		timer10 = "/ocp/interconnect@48000000/segment@0/target-module@86000/timer@0";
		timer11 = "/ocp/interconnect@48000000/segment@0/target-module@88000/timer@0";
		rng = "/ocp/interconnect@48000000/segment@0/target-module@90000/rng@0";
		mcspi1 = "/ocp/interconnect@48000000/segment@0/target-module@98000/spi@0";
		mcspi2 = "/ocp/interconnect@48000000/segment@0/target-module@9a000/spi@0";
		mmc1 = "/ocp/interconnect@48000000/segment@0/target-module@9c000/mmc@0";
		des_target = "/ocp/interconnect@48000000/segment@0/target-module@a5000";
		des = "/ocp/interconnect@48000000/segment@0/target-module@a5000/des@0";
		mmc3 = "/ocp/interconnect@48000000/segment@0/target-module@ad000/mmc@0";
		hdqw1w = "/ocp/interconnect@48000000/segment@0/target-module@b2000/1w@0";
		mmc2 = "/ocp/interconnect@48000000/segment@0/target-module@b4000/mmc@0";
		mcspi3 = "/ocp/interconnect@48000000/segment@0/target-module@b8000/spi@0";
		mcspi4 = "/ocp/interconnect@48000000/segment@0/target-module@ba000/spi@0";
		mmc4 = "/ocp/interconnect@48000000/segment@0/target-module@d1000/mmc@0";
		l4_per2 = "/ocp/interconnect@48400000";
		uart7 = "/ocp/interconnect@48400000/segment@0/target-module@20000/serial@0";
		uart8 = "/ocp/interconnect@48400000/segment@0/target-module@22000/serial@0";
		uart9 = "/ocp/interconnect@48400000/segment@0/target-module@24000/serial@0";
		atl_tm = "/ocp/interconnect@48400000/segment@0/target-module@3c000";
		atl = "/ocp/interconnect@48400000/segment@0/target-module@3c000/atl@0";
		epwmss0 = "/ocp/interconnect@48400000/segment@0/target-module@3e000/epwmss@0";
		ecap0 = "/ocp/interconnect@48400000/segment@0/target-module@3e000/epwmss@0/pwm@100";
		ehrpwm0 = "/ocp/interconnect@48400000/segment@0/target-module@3e000/epwmss@0/pwm@200";
		epwmss1 = "/ocp/interconnect@48400000/segment@0/target-module@40000/epwmss@0";
		ecap1 = "/ocp/interconnect@48400000/segment@0/target-module@40000/epwmss@0/pwm@100";
		ehrpwm1 = "/ocp/interconnect@48400000/segment@0/target-module@40000/epwmss@0/pwm@200";
		epwmss2 = "/ocp/interconnect@48400000/segment@0/target-module@42000/epwmss@0";
		ecap2 = "/ocp/interconnect@48400000/segment@0/target-module@42000/epwmss@0/pwm@100";
		ehrpwm2 = "/ocp/interconnect@48400000/segment@0/target-module@42000/epwmss@0/pwm@200";
		mcasp1 = "/ocp/interconnect@48400000/segment@0/target-module@60000/mcasp@0";
		mcasp2 = "/ocp/interconnect@48400000/segment@0/target-module@64000/mcasp@0";
		mcasp3 = "/ocp/interconnect@48400000/segment@0/target-module@68000/mcasp@0";
		mcasp4 = "/ocp/interconnect@48400000/segment@0/target-module@6c000/mcasp@0";
		mcasp5 = "/ocp/interconnect@48400000/segment@0/target-module@70000/mcasp@0";
		mcasp6 = "/ocp/interconnect@48400000/segment@0/target-module@74000/mcasp@0";
		mcasp7 = "/ocp/interconnect@48400000/segment@0/target-module@78000/mcasp@0";
		mcasp8 = "/ocp/interconnect@48400000/segment@0/target-module@7c000/mcasp@0";
		dcan2 = "/ocp/interconnect@48400000/segment@0/target-module@80000/can@0";
		mac_sw = "/ocp/interconnect@48400000/segment@0/target-module@84000/switch@0";
		cpsw_port1 = "/ocp/interconnect@48400000/segment@0/target-module@84000/switch@0/ethernet-ports/port@1";
		cpsw_port2 = "/ocp/interconnect@48400000/segment@0/target-module@84000/switch@0/ethernet-ports/port@2";
		davinci_mdio_sw = "/ocp/interconnect@48400000/segment@0/target-module@84000/switch@0/mdio@1000";
		l4_per3 = "/ocp/interconnect@48800000";
		mailbox13 = "/ocp/interconnect@48800000/segment@0/target-module@2000/mailbox@0";
		timer5 = "/ocp/interconnect@48800000/segment@0/target-module@20000/timer@0";
		timer6 = "/ocp/interconnect@48800000/segment@0/target-module@22000/timer@0";
		timer7 = "/ocp/interconnect@48800000/segment@0/target-module@24000/timer@0";
		timer8 = "/ocp/interconnect@48800000/segment@0/target-module@26000/timer@0";
		timer13 = "/ocp/interconnect@48800000/segment@0/target-module@28000/timer@0";
		timer14 = "/ocp/interconnect@48800000/segment@0/target-module@2a000/timer@0";
		timer15_target = "/ocp/interconnect@48800000/segment@0/target-module@2c000";
		timer15 = "/ocp/interconnect@48800000/segment@0/target-module@2c000/timer@0";
		timer16_target = "/ocp/interconnect@48800000/segment@0/target-module@2e000";
		timer16 = "/ocp/interconnect@48800000/segment@0/target-module@2e000/timer@0";
		rtctarget = "/ocp/interconnect@48800000/segment@0/target-module@38000";
		rtc = "/ocp/interconnect@48800000/segment@0/target-module@38000/rtc@0";
		mailbox2 = "/ocp/interconnect@48800000/segment@0/target-module@3a000/mailbox@0";
		mailbox3 = "/ocp/interconnect@48800000/segment@0/target-module@3c000/mailbox@0";
		mailbox4 = "/ocp/interconnect@48800000/segment@0/target-module@3e000/mailbox@0";
		mailbox5 = "/ocp/interconnect@48800000/segment@0/target-module@40000/mailbox@0";
		mbox_ipu1_ipc3x = "/ocp/interconnect@48800000/segment@0/target-module@40000/mailbox@0/mbox-ipu1-ipc3x";
		mbox_dsp1_ipc3x = "/ocp/interconnect@48800000/segment@0/target-module@40000/mailbox@0/mbox-dsp1-ipc3x";
		mailbox6 = "/ocp/interconnect@48800000/segment@0/target-module@42000/mailbox@0";
		mbox_ipu2_ipc3x = "/ocp/interconnect@48800000/segment@0/target-module@42000/mailbox@0/mbox-ipu2-ipc3x";
		mbox_dsp2_ipc3x = "/ocp/interconnect@48800000/segment@0/target-module@42000/mailbox@0/mbox-dsp2-ipc3x";
		mailbox7 = "/ocp/interconnect@48800000/segment@0/target-module@44000/mailbox@0";
		mailbox8 = "/ocp/interconnect@48800000/segment@0/target-module@46000/mailbox@0";
		mailbox9 = "/ocp/interconnect@48800000/segment@0/target-module@5e000/mailbox@0";
		mailbox10 = "/ocp/interconnect@48800000/segment@0/target-module@60000/mailbox@0";
		mailbox11 = "/ocp/interconnect@48800000/segment@0/target-module@62000/mailbox@0";
		mailbox12 = "/ocp/interconnect@48800000/segment@0/target-module@64000/mailbox@0";
		omap_dwc3_1 = "/ocp/interconnect@48800000/segment@0/target-module@80000/omap_dwc3_1@0";
		usb1 = "/ocp/interconnect@48800000/segment@0/target-module@80000/omap_dwc3_1@0/usb@10000";
		omap_dwc3_2 = "/ocp/interconnect@48800000/segment@0/target-module@c0000/omap_dwc3_2@0";
		usb2 = "/ocp/interconnect@48800000/segment@0/target-module@c0000/omap_dwc3_2@0/usb@10000";
		usb3_tm = "/ocp/interconnect@48800000/segment@0/target-module@100000";
		omap_dwc3_3 = "/ocp/interconnect@48800000/segment@0/target-module@100000/omap_dwc3_3@0";
		usb3 = "/ocp/interconnect@48800000/segment@0/target-module@100000/omap_dwc3_3@0/usb@10000";
		vpe = "/ocp/interconnect@48800000/segment@0/target-module@1d0010/vpe@0";
		usb4_tm = "/ocp/interconnect@48800000/segment@0/target-module@140000";
		omap_dwc3_4 = "/ocp/interconnect@48800000/segment@0/target-module@140000/omap_dwc3_4@0";
		usb4 = "/ocp/interconnect@48800000/segment@0/target-module@140000/omap_dwc3_4@0/usb@10000";
		axi0 = "/ocp/target-module@51000000";
		pcie1_rc = "/ocp/target-module@51000000/pcie@51000000";
		pcie1_intc = "/ocp/target-module@51000000/pcie@51000000/interrupt-controller";
		pcie1_ep = "/ocp/target-module@51000000/pcie_ep@51000000";
		axi1 = "/ocp/target-module@51800000";
		pcie2_rc = "/ocp/target-module@51800000/pcie@51800000";
		pcie2_intc = "/ocp/target-module@51800000/pcie@51800000/interrupt-controller";
		ocmcram1 = "/ocp/ocmcram@40300000";
		ocmcram2 = "/ocp/ocmcram@40400000";
		ocmcram3 = "/ocp/ocmcram@40500000";
		bandgap = "/ocp/bandgap@4a0021e0";
		dsp1_system = "/ocp/dsp_system@40d00000";
		dra7_iodelay_core = "/ocp/padconf@4844a000";
		mmc1_iodelay_ddr_rev11_conf = "/ocp/padconf@4844a000/mmc1_iodelay_ddr_rev11_conf";
		mmc1_iodelay_ddr_rev20_conf = "/ocp/padconf@4844a000/mmc1_iodelay_ddr50_rev20_conf";
		mmc1_iodelay_sdr104_rev11_conf = "/ocp/padconf@4844a000/mmc1_iodelay_sdr104_rev11_conf";
		mmc1_iodelay_sdr104_rev20_conf = "/ocp/padconf@4844a000/mmc1_iodelay_sdr104_rev20_conf";
		mmc2_iodelay_hs200_rev11_conf = "/ocp/padconf@4844a000/mmc2_iodelay_hs200_rev11_conf";
		mmc2_iodelay_hs200_rev20_conf = "/ocp/padconf@4844a000/mmc2_iodelay_hs200_rev20_conf";
		mmc2_iodelay_ddr_3_3v_rev11_conf = "/ocp/padconf@4844a000/mmc2_iodelay_ddr_3_3v_rev11_conf";
		mmc2_iodelay_ddr_1_8v_rev11_conf = "/ocp/padconf@4844a000/mmc2_iodelay_ddr_1_8v_rev11_conf";
		mmc3_iodelay_manual1_rev11_conf = "/ocp/padconf@4844a000/mmc3_iodelay_manual1_conf";
		mmc3_iodelay_manual1_rev20_conf = "/ocp/padconf@4844a000/mmc3_iodelay_manual1_conf";
		mmc4_iodelay_ds_rev11_conf = "/ocp/padconf@4844a000/mmc4_iodelay_ds_rev11_conf";
		mmc4_iodelay_ds_rev20_conf = "/ocp/padconf@4844a000/mmc4_iodelay_ds_rev20_conf";
		mmc4_iodelay_sdr12_hs_sdr25_rev11_conf = "/ocp/padconf@4844a000/mmc4_iodelay_sdr12_hs_sdr25_rev11_conf";
		mmc4_iodelay_sdr12_hs_sdr25_rev20_conf = "/ocp/padconf@4844a000/mmc4_iodelay_sdr12_hs_sdr25_rev20_conf";
		edma = "/ocp/target-module@43300000/dma@0";
		edma_tptc0 = "/ocp/target-module@43400000/dma@0";
		edma_tptc1 = "/ocp/target-module@43500000/dma@0";
		ipu1 = "/ocp/ipu@58820000";
		ipu2 = "/ocp/ipu@55020000";
		dsp1 = "/ocp/dsp@40800000";
		mmu0_dsp1 = "/ocp/target-module@40d01000/mmu@0";
		mmu1_dsp1 = "/ocp/target-module@40d02000/mmu@0";
		mmu_ipu1 = "/ocp/target-module@58882000/mmu@0";
		mmu_ipu2 = "/ocp/target-module@55082000/mmu@0";
		abb_mpu = "/ocp/regulator-abb-mpu";
		abb_ivahd = "/ocp/regulator-abb-ivahd";
		abb_dspeve = "/ocp/regulator-abb-dspeve";
		abb_gpu = "/ocp/regulator-abb-gpu";
		qspi = "/ocp/target-module@4b300000/spi@0";
		gpmc = "/ocp/target-module@50000000/gpmc@50000000";
		gpu_tm = "/ocp/target-module@56000000";
		crossbar_mpu = "/ocp/crossbar@4a002a48";
		dss = "/ocp/target-module@58000000/dss@0";
		hdmi = "/ocp/target-module@58000000/dss@0/target-module@40000/encoder@0";
		bb2d = "/ocp/target-module@59000000/gpu@0";
		aes1_target = "/ocp/target-module@4b500000";
		aes1 = "/ocp/target-module@4b500000/aes@0";
		aes2_target = "/ocp/target-module@4b700000";
		aes2 = "/ocp/target-module@4b700000/aes@0";
		sham1_target = "/ocp/target-module@4b101000";
		sham1 = "/ocp/target-module@4b101000/sham@0";
		sham2_target = "/ocp/target-module@42701000";
		sham2 = "/ocp/target-module@42701000/sham@0";
		iva_hd_target = "/ocp/target-module@5a000000";
		opp_supply_mpu = "/ocp/opp-supply@4a003b20";
		dsp2_system = "/ocp/dsp_system@41500000";
		mmu0_dsp2 = "/ocp/target-module@41501000/mmu@0";
		mmu1_dsp2 = "/ocp/target-module@41502000/mmu@0";
		dsp2 = "/ocp/dsp@41000000";
		pruss1_tm = "/ocp/target-module@4b226000";
		pruss1 = "/ocp/target-module@4b226000/pruss@0";
		pruss1_mem = "/ocp/target-module@4b226000/pruss@0/memories@0";
		pruss1_cfg = "/ocp/target-module@4b226000/pruss@0/cfg@26000";
		pruss1_iepclk_mux = "/ocp/target-module@4b226000/pruss@0/cfg@26000/clocks/iepclk-mux@30";
		pruss1_mii_rt = "/ocp/target-module@4b226000/pruss@0/mii-rt@32000";
		pruss1_intc = "/ocp/target-module@4b226000/pruss@0/interrupt-controller@20000";
		pru1_0 = "/ocp/target-module@4b226000/pruss@0/pru@34000";
		pru1_1 = "/ocp/target-module@4b226000/pruss@0/pru@38000";
		pruss1_mdio = "/ocp/target-module@4b226000/pruss@0/mdio@32400";
		pruss2_tm = "/ocp/target-module@4b2a6000";
		pruss2 = "/ocp/target-module@4b2a6000/pruss@0";
		pruss2_mem = "/ocp/target-module@4b2a6000/pruss@0/memories@0";
		pruss2_cfg = "/ocp/target-module@4b2a6000/pruss@0/cfg@26000";
		pruss2_iepclk_mux = "/ocp/target-module@4b2a6000/pruss@0/cfg@26000/clocks/iepclk-mux@30";
		pruss2_mii_rt = "/ocp/target-module@4b2a6000/pruss@0/mii-rt@32000";
		pruss2_intc = "/ocp/target-module@4b2a6000/pruss@0/interrupt-controller@20000";
		pru2_0 = "/ocp/target-module@4b2a6000/pruss@0/pru@34000";
		pru2_1 = "/ocp/target-module@4b2a6000/pruss@0/pru@38000";
		pruss2_mdio = "/ocp/target-module@4b2a6000/pruss@0/mdio@32400";
		thermal_zones = "/thermal-zones";
		cpu_thermal = "/thermal-zones/cpu_thermal";
		cpu_trips = "/thermal-zones/cpu_thermal/trips";
		cpu_alert0 = "/thermal-zones/cpu_thermal/trips/cpu_alert";
		cpu_crit = "/thermal-zones/cpu_thermal/trips/cpu_crit";
		cpu_cooling_maps = "/thermal-zones/cpu_thermal/cooling-maps";
		gpu_thermal = "/thermal-zones/gpu_thermal";
		gpu_crit = "/thermal-zones/gpu_thermal/trips/gpu_crit";
		core_thermal = "/thermal-zones/core_thermal";
		core_crit = "/thermal-zones/core_thermal/trips/core_crit";
		dspeve_thermal = "/thermal-zones/dspeve_thermal";
		dspeve_crit = "/thermal-zones/dspeve_thermal/trips/dspeve_crit";
		iva_thermal = "/thermal-zones/iva_thermal";
		iva_crit = "/thermal-zones/iva_thermal/trips/iva_crit";
	};
};