-0-
These GELs are an adaptation of the internal GEL framework, modified for use/distribution to customers via the CSP.

To check all cores for a bare metal system (no user code in ospi or sdcard) call the script:
	DO "~~~~/am62_allcoretype_connect.cmm"
This script initializes clocks using the Cortex-M4-0 the opens a new GUI per core. A modified version of this script can be used to start any subset of cores.  Simply comment out the cores not desired.

-1-
A platform level DDR test can be run by calling:
	DO "~~~~/am62_ddr_test.cmm"

-2-
Scripts in the ./pdk_rtos_test/ directory allow for loading and running PDK FreeRTOS or TIRTOS examples.  These use TI-Firmware running on the TIFS-CortexM4

-3-
TRACE32 CORE names are as follows.
	; A53 (1x4) : AM625X (core.assign 1. 2. 3. 4.)
	; CR5 (1x1) : AM625X-CR5
	; CM4 (3x1) : AM625X-CM4-SMS0 AM625X-CM4-SMS1 AM625X-CM4-BLAZAR
	; PRU (1x2) : AM625X-ICSS0 (core.assign 1. 2.)

To allow for multi-core concurrent trace decode the tools side requires a "system.config CORE" option. The CORE # convention follows the above:
  	A53 1 2 3 4
  	CR5 5
  	CM4-SS0 6
  	CM4-SS1 7
  	CM4-BLAZAR 8
  	PRU 10 11 

To select the 2nd PRU core the config file would use:
 	SYStem.CPU AM625X-ICSS0		; select ICSS-PRU
 	SYStem.CONFIG CORE 11. 1.	; Core#12 on chip#1
	CORE.Assign 2.			; select 2nd PRU instance
NOTES: 
	Scripts which setup DDR only work after a power on reset and cannot be re-called as they depend on reset state.
	Bare metal scripts work with GP devices and HS-SE-WIR.  
	HS-SE-Firmware based devices will not allow M4 operations without a proper certificate with UID.
