/**
 * \file  AM62_PLL_MMR.gel
 *
 * \brief GEL File with register definitions for AM62_PLL.GEL
 */

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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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//PLL controller register offsets
#define PLL_CTRL_PLLCTL_OFFSET      0x0100
#define PLL_CTRL_OCSEL_OFFSET       0x0104
#define PLL_CTRL_PREDIV_OFFSET      0x0114
#define PLL_CTRL_PLLDIV1_OFFSET     0x0118
#define PLL_CTRL_PLLDIV2_OFFSET     0x011C
#define PLL_CTRL_PLLDIV3_OFFSET     0x0120
#define PLL_CTRL_OSCDIV1_OFFSET     0x0124
#define PLL_CTRL_POSTDIV_OFFSET     0x0128
#define PLL_CTRL_BPDIV_OFFSET       0x012C
#define PLL_CTRL_PLLCMD_OFFSET      0x0138
#define PLL_CTRL_PLLSTAT_OFFSET     0x013C
#define PLL_CTRL_ALNCTL_OFFSET      0x0140
#define PLL_CTRL_CKEN_OFFSET        0x0148
#define PLL_CTRL_CKSTAT_OFFSET      0x014C
#define PLL_CTRL_SYSTAT_OFFSET      0x0150
#define PLL_CTRL_PLLDIV4_OFFSET     0x0160
#define PLL_CTRL_PLLDIV5_OFFSET     0x0164
#define PLL_CTRL_PLLDIV6_OFFSET     0x0168
#define PLL_CTRL_PLLDIV7_OFFSET     0x016C
#define PLL_CTRL_PLLDIV8_OFFSET     0x0170
#define PLL_CTRL_PLLDIV9_OFFSET     0x0174
#define PLL_CTRL_PLLDIV10_OFFSET    0x0178
#define PLL_CTRL_PLLDIV11_OFFSET    0x017C
#define PLL_CTRL_PLLDIV12_OFFSET    0x0180
#define PLL_CTRL_PLLDIV13_OFFSET    0x0184
#define PLL_CTRL_PLLDIV14_OFFSET    0x0188
#define PLL_CTRL_PLLDIV15_OFFSET    0x018C
#define PLL_CTRL_PLLDIV16_OFFSET    0x0190

//PLL Index Map
#define MAIN_PLL_INDEX		0
#define PER0_PLL_INDEX		1
#define PER1_PLL_INDEX		2
#define ARM0_PLL_INDEX		8
#define DDR_PLL_INDEX		12
#define SMS_PLL_INDEX	    15
#define DSS0_PLL_INDEX	    16
#define DSS1_PLL_INDEX	    17
#define MCU_PLL_INDEX	    0

//OFFSETS
#define PLL_PID 			(0x00)
#define PLL_CONFIG 			(0x08)
#define CONTROL 			(0x20)
#define STATUS				(0x24)
#define FREQ_CONTROL_0 		(0x30)
#define FREQ_CONTROL_1 		(0x34)
#define OUTPUT_DIV_CONTROL 	(0x38)
#define SSMOD_CONTROL 		(0x40)
#define SSMOD_SPREAD		(0x44)
#define CAL_CONTROL			(0x60)
#define CAL_STATUS 			(0x64)
#define HSDIV_0_CONTROL 	(0x80)
#define HSDIV_1_CONTROL 	(0x84)
#define HSDIV_2_CONTROL 	(0x88)
#define HSDIV_3_CONTROL 	(0x8C)
#define HSDIV_4_CONTROL 	(0x90)
#define HSDIV_5_CONTROL 	(0x94)
#define HSDIV_6_CONTROL 	(0x98)
#define HSDIV_7_CONTROL 	(0x9C)
#define HSDIV_8_CONTROL 	(0xA0)
#define HSDIV_9_CONTROL 	(0xA4)

//OFCs
#define SPECIAL_CONFIG 0
#define OFC1 		   1
#define UC1_1		   2
#define UC1_2 		   3
#define UC1_3		   4
#define UC1_5		   5
#define UC1_1_DDR472MHz          6
#define UC1_2_DDR472MHz          7

//Special Programming Indices
#define NONE                 0
#define Pulsar_400MHz_400MHz 1
#define DDR_333              2
#define DSS_27               3
#define DSS_165              4
#define DSS_138_5            5
#define DSS_64               6
#define DSS_92_25            7
#define DSS_29_75            8
#define ARM0_100MHz          9
#define ARM0_200MHz          10
#define ARM0_300MHz          11
#define ARM0_400MHz          12
#define ARM0_500MHz          13
#define ARM0_600MHz          14
#define ARM0_700MHz          15
#define ARM0_800MHz          16
#define ARM0_900MHz          17
#define ARM0_1000MHz         18
#define ARM0_1100MHz         19
#define ARM0_1200MHz         20
#define ARM0_1300MHz         21
#define ARM0_1400MHz         22
#define ARM0_1250MHz         23