Step 1:  Create file am62x_ddr_top_ddr4.gel or am62x_ddr_top_lpddr4.gel or am62x_ddr_top_sipddr4.cmm

Step 2: Add header setting DDR4 mode to target type (LPDDR4 or DDR4)

#define DDR4 	 1
#define LPDDR4 	 2
#define MHZ25    1
int DDR_MODE;	//set in DDR GEL functions based on board
unsigned int AM62_DDRSS_SS_BASE;	
unsigned int AM62_DDRSS_CTL_BASE;
unsigned int WKUP_CTRL_MMR0_CFG0_BASE;
unsigned int DDR_MODE = LPDDR4;

Step 3: Inline files:

./si_configs/{AM62x-LP4-50-800.gel or AM62x-DDR4-1600MTs.gel or AM62x_SiP-LP4-50-800.gel}
./ip/DDR/CTLPHY/v1/reg_offsets/CTLPHY_addr_map_sfr_offs_ew_16bit.gel
./ip/DDR/TI/v1/ddrss_ti_wrapper.gel
./ip/DDR/CTLPHY/v1/ddrss_ctlphy_cfg.gel
./AM62_DDRSS/am62x_ddr_top.gel

Step 4:
	Add Global helpers
	Comment out load/unloads

Step 5:  Pull to top:

//FSP MAIN_CTRL_MMR register offsets
#define CHNG_DDR4_FSP_REQ 		0x14000	// Change LPDDR4 FSP Request Register - initiate a LPDDR4 frequency set point change to the DDR Controller (r/w)
#define CHNG_DDR4_FSP_ACK		0x14004 // Change LPDDR4 FSP Acknowledge Register - DDR Controller to acknowledge the LPDDR4 frequency set point shange request (read only)
#define DDR4_FSP_CLKCHNG_REQ	0x14080 // LPDDR4 FSP Clock Change Request Register - DDR Controller to request the DDR PLL clock frequency change (read only)
#define DDR4_FSP_CLKCHNG_ACK	0x140C0 // LPDDR4 FSP Clock Change Acknowledge Register - acknowledge a DDR PLL clock frequency change to the DDR Controller (r/w)

#define static
#define void
#define uint32_t                  unsigned int
#define HW_WR_REG32(addr, data)   *(uint32_t *) (addr) = (uint32_t) (data)
#define HW_RD_REG32(addr)         *(uint32_t *) (addr)
#define CLR_BITS(input,mask,shift) 		(input & ~(mask<<shift))
#define SET_BITS(input,mask,shift) 		(input | (mask<<shift))
#define PUT_BITS(input,val,mask,shift)	((input & ~(mask<<shift)) | (val<<shift))
#define min(a,b) ((a<b)?a:b)
#define max(a,b) ((a>b)?a:b)
//#define AUTO_TEMP_RANGE 1 //not implemented - need to manually uncomment the section in the DDR controller configuration gel file.
#define R5FSS_VIM_PID 	(0x2FFF0000)
#define VIM_PID_VALUE	(0x60900001)

Step 6: Add common call name
	GLOBAL &path_ddr_init_cmm
	&path_ddr_init_cmm=OS.PPF()

	Call config from outer CMM
	-->  AM62_DDR_Initialization_ECC_Disabled