Peripherals can be frozen when a core is put into debug halt if a suspend
signal is associated between a core and a peripheral.  This can be useful
for debug of peripherals that have running timers, watchdogs, or DMAs.

1: The first step is to associate a CPU's debug entry with a peripheral:

Suspend CPU mapping:
============================
Suspend Router: @APB:0x9D300000 | @AXI:0x7:0x3D300000

CPU Suspend Input mappings:
-----------------------------
0     => unused
1-4   => A53-0,A53-1,A53-2,A53-3
5-22  => reserved
23    => Device Manager R5
24    => Blazar CM4 (MCU)
25    => SMS CM4_0 TIFS
26    => SMS CM4_1 HSM
27-31 => reserved

Peripheral Outputs (0-63 slots):
---------------------------------
main dmtimers main_0 to main_8 mapped to slots 8 to 15
mcu timers mcu_0 to mcu_4 are mapped to slots 15 to 20
wkup timers wkup_0 to wkup_1 are mapped to slots 21 to 22
gtc is mapped to slot 0 (gtc feeds multiple clocks, eg: A53-arch-timer)

MAIN-TIMER0 is in slot 8 (8+1) x 4 = 64 = 0x24
  @APB:0x9D300024        - debug address plane
  @AXI:0x7:0x3D300024    - 64bit-system address

stop timer if "DM R5" is halted:
  Data.Set EAPB:0x9D300024 %LE %Long (0x10000|23.)
  Data.Set AXI:0x7:0x3D300024 %LE %Long (0x10000|23.)

stop timer if "A53-0" is halted
  Data.Set EAPB:0x9D300024 %LE %Long (0x10000|1.)
  Data.Set AXI:0x7:0x3D300024 %LE %Long (0x10000|1.)

2: The second step is to enable the peripheral to react to the suspend signal.
Many peripherals have a 'freeze' or halt bit control in their register space.
For example, for the GTC, GTC_CNTCR.HDBG[1] needs to be set.
 Data.Set EZAXI:0x00A90000 %LE %Long 0x3
For a TIMER a TICOP_CFG.EMUFREE flag needs to be cleared
