// * MTP300 GEL File // Enable for when Manually using CCS and AVV Framework style memory map #define SYSTEM_RESET_BEFORE_FILE_LOAD_ENABLE (0) #define ON_RESET_CODE_ENABLE (1) #define ON_TARGET_CONNECT_CODE_ENABLE (1) #define ON_FILE_LOAD_CODE_ENABLE (1) #define AVV_MEM_MAP (0) #define DDR3_BASE_ADDRESS 0x80000000 // Global Register and constant definitions #define REF_CLOCK_KHZ 122880 // Global timeout value #define GTIMEOUT 2000 //***************************************************** // Power definitions #define PSC_BASE 0x02350000 #define PSC_PTCMD *( unsigned int* )( PSC_BASE+0x120 ) #define PSC_PTSTAT *( unsigned int* )( PSC_BASE+0x128 ) #define PSC_PDCTL_BASE ( PSC_BASE+0x300 ) #define PSC_MDSTAT_BASE ( PSC_BASE+0x800 ) #define PSC_MDCTL_BASE ( PSC_BASE+0xA00 ) // Modules on power domain 0 #define LPSC_SMARTRFLX (1) #define LPSC_DDR3 (2) #define LPSC_TCP3E (3) #define LPSC_VCP2A (4) // Modules on power domain 1 #define LPSC_DEBUG (5) #define LPSC_TETB (6) // Modules on power domain 2 #define LPSC_PA (7) #define LPSC_SGMII (8) #define LPSC_SA (9) // Modules on power domain 3 #define LPSC_PCIE (10) // Modules on power domain 4 #define LPSC_SRIO (11) // Modules on power domain 5 #define LPSC_HYPER (12) // Modules on power domain 6 #define LPSC_RESERV (13) // Modules on power domain 7 #define LPSC_MSMCRAM (14) // Modules on power domain 8 #define LPSC_RACA_RACB (15) #define LPSC_TAC (16) // Modules on power domain 9 #define LPSC_FFTCA_FFTCB (17) // Modules on power domain 10 #define LPSC_AIF2 (18) // Modules on power domain 11 #define LPSC_TCP3DA (19) // Modules on power domain 12 #define LPSC_VCP2B (20) #define LPSC_VCP2C (21) #define LPSC_VCP2D (22) // Modules on power domain 13 #define LPSC_C0_TIM0 (23) // Modules on power domain 14 #define LPSC_C1_TIM1 (24) #define LPSC_C1_RSA (25) // Modules on power domain 15 #define LPSC_C2_TIM2 (26) #define LPSC_C2_RSA (27) // Modules on power domain 16 #define LPSC_C3_TIM3 (28) // Modules on power domain 17 #define LPSC_TCP3dB (29) // Modules on power domain 18 #define LPSC_BCP_FFTCC_TCP3DC (30) // Power domains definitions #define PD0 (0) // Power Domain-0 #define PD1 (1) // Power Domain-1 #define PD2 (2) // Power Domain-2 #define PD3 (3) // Power Domain-3 #define PD4 (4) // Power Domain-4 #define PD5 (5) // Power Domain-5 #define PD6 (6) // Power Domain-6 #define PD7 (7) // Power Domain-7 #define PD8 (8) // Power Domain-8 #define PD9 (9) // Power Domain-9 #define PD10 (10) // Power Domain-10 #define PD11 (11) // Power Domain-11 #define PD12 (12) // Power Domain-12 #define PD13 (13) // Power Domain-13 #define PD14 (14) // Power Domain-14 #define PD15 (15) // Power Domain-15 #define PD16 (16) // Power Domain-16 #define PD17 (17) // Power Domain-17 #define PD18 (18) // Power Domain-18 #define PSC_SYNCRESET (0x1) #define PSC_DISABLE (0x2) #define PSC_ENABLE (0x3) //***************************************************** // BOOT and CONFIG dsp system modules Definitions #define CHIP_LEVEL_REG 0x02620000 #define DEVSTAT (*(unsigned int*)(CHIP_LEVEL_REG + 0x0020)) #define KICK0 (*(unsigned int*)(CHIP_LEVEL_REG + 0x0038)) #define KICK1 (*(unsigned int*)(CHIP_LEVEL_REG + 0x003C)) #define TINPSEL (*(unsigned int*)(CHIP_LEVEL_REG + 0x0300)) #define TOUTPSEL (*(unsigned int*)(CHIP_LEVEL_REG + 0x0304)) #define MAINPLLCTL0 (*(unsigned int*)(CHIP_LEVEL_REG + 0x0328)) #define MAINPLLCTL1 (*(unsigned int*)(CHIP_LEVEL_REG + 0x032C)) #define DDR3PLLCTL0 (*(unsigned int*)(CHIP_LEVEL_REG + 0x0330)) #define DDR3PLLCTL1 (*(unsigned int*)(CHIP_LEVEL_REG + 0x0334)) #define PAPLLCTL0 (*(unsigned int*)(CHIP_LEVEL_REG + 0x0338)) #define PAPLLCTL1 (*(unsigned int*)(CHIP_LEVEL_REG + 0x033C)) #define OBSCLKCTL (*(unsigned int*)(CHIP_LEVEL_REG + 0x03AC)) // DDR3 tuning registers #define DATA0_GTLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x043C)) #define DATA1_GTLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0440)) #define DATA2_GTLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0444)) #define DATA3_GTLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0448)) #define DATA4_GTLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x044C)) #define DATA5_GTLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0450)) #define DATA6_GTLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0454)) #define DATA7_GTLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0458)) #define DATA8_GTLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x045C)) #define DATA0_WRLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x040C)) #define DATA1_WRLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0410)) #define DATA2_WRLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0414)) #define DATA3_WRLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0418)) #define DATA4_WRLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x041C)) #define DATA5_WRLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0420)) #define DATA6_WRLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0424)) #define DATA7_WRLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x0428)) #define DATA8_WRLVL_INIT_RATIO (*(unsigned int*)(CHIP_LEVEL_REG + 0x042C)) #define DDR3_CONFIG_REG_0 (*(unsigned int*)(CHIP_LEVEL_REG + 0x0404)) #define DDR3_CONFIG_REG_12 (*(unsigned int*)(CHIP_LEVEL_REG + 0x0434)) #define DDR3_CONFIG_REG_23 (*(unsigned int*)(CHIP_LEVEL_REG + 0x0460)) #define DDR3_CONFIG_REG_24 (*(unsigned int*)(CHIP_LEVEL_REG + 0x0464)) #define SGMII_SERDES_CFGPLL (*(unsigned int*)(CHIP_LEVEL_REG + 0x340)) #define SGMII_SERDES_CFGRX0 (*(unsigned int*)(CHIP_LEVEL_REG + 0x344)) #define SGMII_SERDES_CFGTX0 (*(unsigned int*)(CHIP_LEVEL_REG + 0x348)) #define SGMII_SERDES_CFGRX1 (*(unsigned int*)(CHIP_LEVEL_REG + 0x34C)) #define SGMII_SERDES_CFGTX1 (*(unsigned int*)(CHIP_LEVEL_REG + 0x350)) #define KICK0_UNLOCK (0x83E70B13) #define KICK1_UNLOCK (0x95A4F1E0) #define KICK_LOCK 0 /* PA PLL Observation Clock Control Register */ #define PA_PLL_OBS_CLK_SEL_MASK (1 << 4) /* OBSCLKCTL Register Bit 4 - set to 0 to see PA PLL reference (input) clock, set to 1 to see PA PLL output*/ #define PA_PLL_OBS_CLK_EN_MASK (1 << 5) /* OBSCLKCTL Register Bit 5 - set to 1 to enable power to PA PLL observation clock*/ /* PA PLL Registers */ #define BYPASS_BIT_SHIFT 23 #define CLKF_BIT_SHIFT 6 #define PASSCLKSEL_MASK (1 << 17) /* Tells the configuration of the PASSCLKSEL pin */ #define PA_PLL_BYPASS_MASK (1 << BYPASS_BIT_SHIFT) /* Tells whether the PA PLL is in BYPASS mode or not */ #define PA_PLL_CLKOD_MASK (0x00780000) /* Tells the output divider value for the PA PLL */ #define PA_PLL_CLKF_MASK (0x0007FFC0) /* Tells the multiplier value for the PA PLL */ #define PA_PLL_CLKR_MASK (0x0000003F) /* Tells the divider value for the PA PLL */ //***************************************************** // Timeout definitions int _GEL_Global_Timeout1 = 0; #define TIMEOUT_ID 10 //***************************************************** // Extended Memory Controller (XMC) Configuration #define XMC_BASE_ADDR (0x08000000) #define XMPAX2_L (*(unsigned int*)(XMC_BASE_ADDR + 0x00000010)) #define XMPAX2_H (*(unsigned int*)(XMC_BASE_ADDR + 0x00000014)) // DDR3 definitions #define DDR_BASE_ADDR 0x21000000 #define DDR_MIDR (*(unsigned int*)(DDR_BASE_ADDR + 0x00000000)) #define DDR_SDCFG (*(unsigned int*)(DDR_BASE_ADDR + 0x00000008)) #define DDR_SDRFC (*(unsigned int*)(DDR_BASE_ADDR + 0x00000010)) #define DDR_SDTIM1 (*(unsigned int*)(DDR_BASE_ADDR + 0x00000018)) #define DDR_SDTIM2 (*(unsigned int*)(DDR_BASE_ADDR + 0x00000020)) #define DDR_SDTIM3 (*(unsigned int*)(DDR_BASE_ADDR + 0x00000028)) #define DDR_PMCTL (*(unsigned int*)(DDR_BASE_ADDR + 0x00000038)) #define DDR_ZQCFG (*(unsigned int*)(DDR_BASE_ADDR + 0x000000C8)) #define DDR_RDWR_LVL_RMP_CTRL (*(unsigned int*)(DDR_BASE_ADDR + 0x000000D8)) #define DDR_TMPALRT (*(unsigned int*)(DDR_BASE_ADDR + 0x000000CC)) #define DDR_RDWR_LVL_CTRL (*(unsigned int*)(DDR_BASE_ADDR + 0x000000DC)) #define DDR_DDRPHYC (*(unsigned int*)(DDR_BASE_ADDR + 0x000000E4)) #define RD_DQS_SLAVE_RATIO_1333 0x34 #define WR_DQS_SLAVE_RATIO_1333 0x45 #define WR_DATA_SLAVE_RATIO_1333 0x85 #define FIFO_WE_SLAVE_RATIO_1333 0xBC #define RD_DQS_SLAVE_RATIO_1066 0x34 #define WR_DQS_SLAVE_RATIO_1066 0x37 #define WR_DATA_SLAVE_RATIO_1066 0x77 #define FIFO_WE_SLAVE_RATIO_1066 0xA0 //***************************************************** // PLL 1 definitions (DSP clk and subsystems) #define PLL1_BASE 0x02310000 #define PLL1_PLLCTL (*(unsigned int*)(PLL1_BASE + 0x100)) // PLL1 Control #define PLL1_SECCTL (*(unsigned int*)(PLL1_BASE + 0x108)) // PLL1 Sec Control #define PLL1_PLLM (*(unsigned int*)(PLL1_BASE + 0x110)) // PLL1 Multiplier #define PLL1_DIV1 (*(unsigned int*)(PLL1_BASE + 0x118)) // DIV1 divider #define PLL1_DIV2 (*(unsigned int*)(PLL1_BASE + 0x11C)) // DIV2 divider #define PLL1_DIV3 (*(unsigned int*)(PLL1_BASE + 0x120)) // DIV3 divider #define PLL1_CMD (*(unsigned int*)(PLL1_BASE + 0x138)) // CMD control #define PLL1_STAT (*(unsigned int*)(PLL1_BASE + 0x13C)) // STAT control #define PLL1_ALNCTL (*(unsigned int*)(PLL1_BASE + 0x140)) // ALNCTL control #define PLL1_DCHANGE (*(unsigned int*)(PLL1_BASE + 0x144)) // DCHANGE status #define PLL1_CKEN (*(unsigned int*)(PLL1_BASE + 0x148)) // CKEN control #define PLL1_CKSTAT (*(unsigned int*)(PLL1_BASE + 0x14C)) // CKSTAT status #define PLL1_SYSTAT (*(unsigned int*)(PLL1_BASE + 0x150)) // SYSTAT status #define PLL1_DIV4 (*(unsigned int*)(PLL1_BASE + 0x160)) // DIV4 divider #define PLL1_DIV5 (*(unsigned int*)(PLL1_BASE + 0x164)) // DIV5 divider #define PLL1_DIV6 (*(unsigned int*)(PLL1_BASE + 0x168)) // DIV6 divider #define PLL1_DIV7 (*(unsigned int*)(PLL1_BASE + 0x16C)) // DIV7 divider #define PLL1_DIV8 (*(unsigned int*)(PLL1_BASE + 0x170)) // DIV8 divider #define PLL1_DIV9 (*(unsigned int*)(PLL1_BASE + 0x174)) // DIV9 divider #define PLL1_DIV10 (*(unsigned int*)(PLL1_BASE + 0x178)) // DIV10 divider #define PLL1_DIV11 (*(unsigned int*)(PLL1_BASE + 0x17C)) // DIV11 divider #define PLL1_DIV12 (*(unsigned int*)(PLL1_BASE + 0x180)) // DIV12 divider #define PLL1_DIV13 (*(unsigned int*)(PLL1_BASE + 0x184)) // DIV13 divider #define PLL1_DIV14 (*(unsigned int*)(PLL1_BASE + 0x188)) // DIV14 divider #define PLL1_DIV15 (*(unsigned int*)(PLL1_BASE + 0x18C)) // DIV15 divider #define PLL1_DIV16 (*(unsigned int*)(PLL1_BASE + 0x190)) // DIV16 divider //***************************************************** // CACHE definitions #define CACHE_BASE 0x01840000 #define CACHE_L2CFG (*( unsigned int* )( CACHE_BASE )) #define CACHE_L1PCFG (*( unsigned int* )( CACHE_BASE + 0x0020 )) #define CACHE_L1DCFG (*( unsigned int* )( CACHE_BASE + 0x0040 )) #define L2WBINV (CACHE_BASE + 0x5004) // L2WBINV Control #define L2INV (CACHE_BASE + 0x5008) // L2INV Control #define L1PINV (CACHE_BASE + 0x5028) // L1PINV Control #define L1DWBINV (CACHE_BASE + 0x5044) // L1DWBINV Control #define L1DINV (CACHE_BASE + 0x5048) // L1DINV Control //***************************************************** // EDMA3 definitions #define EDMA3_TPCC0_BASE 0x02700000 #define IERH_0 (EDMA3_TPCC0_BASE + 0x1054) // IERH Control #define EERH_0 (EDMA3_TPCC0_BASE + 0x1024) // EERH Control #define ICRH_0 (EDMA3_TPCC0_BASE + 0x1074) // ICRH Control #define ECRH_0 (EDMA3_TPCC0_BASE + 0x100C) // ECRH Control #define IER_0 (EDMA3_TPCC0_BASE + 0x1050) // IER Control #define EER_0 (EDMA3_TPCC0_BASE + 0x1020) // EER Control #define ICR_0 (EDMA3_TPCC0_BASE + 0x1070) // ICR Control #define ECR_0 (EDMA3_TPCC0_BASE + 0x1008) // ECR Control #define IECRH_0 (EDMA3_TPCC0_BASE + 0x105C) // IECRH Control #define IECR_0 (EDMA3_TPCC0_BASE + 0x1058) // IECR Control #define EECRH_0 (EDMA3_TPCC0_BASE + 0x102C) // EECRH Control #define EECR_0 (EDMA3_TPCC0_BASE + 0x1028) // EECR Control #define EDMA3_TPCC1_BASE 0x02720000 #define IERH_1 (EDMA3_TPCC1_BASE + 0x1054) // IERH Control #define EERH_1 (EDMA3_TPCC1_BASE + 0x1024) // EERH Control #define ICRH_1 (EDMA3_TPCC1_BASE + 0x1074) // ICRH Control #define ECRH_1 (EDMA3_TPCC1_BASE + 0x100C) // ECRH Control #define IER_1 (EDMA3_TPCC1_BASE + 0x1050) // IER Control #define EER_1 (EDMA3_TPCC1_BASE + 0x1020) // EER Control #define ICR_1 (EDMA3_TPCC1_BASE + 0x1070) // ICR Control #define ECR_1 (EDMA3_TPCC1_BASE + 0x1008) // ECR Control #define IECRH_1 (EDMA3_TPCC1_BASE + 0x105C) // IECRH Control #define IECR_1 (EDMA3_TPCC1_BASE + 0x1058) // IECR Control #define EECRH_1 (EDMA3_TPCC1_BASE + 0x102C) // EECRH Control #define EECR_1 (EDMA3_TPCC1_BASE + 0x1028) // EECR Control #define EDMA3_TPCC2_BASE 0x02740000 #define IERH_2 (EDMA3_TPCC2_BASE + 0x1054) // IERH Control #define EERH_2 (EDMA3_TPCC2_BASE + 0x1024) // EERH Control #define ICRH_2 (EDMA3_TPCC2_BASE + 0x1074) // ICRH Control #define ECRH_2 (EDMA3_TPCC2_BASE + 0x100C) // ECRH Control #define IER_2 (EDMA3_TPCC2_BASE + 0x1050) // IER Control #define EER_2 (EDMA3_TPCC2_BASE + 0x1020) // EER Control #define ICR_2 (EDMA3_TPCC2_BASE + 0x1070) // ICR Control #define ECR_2 (EDMA3_TPCC2_BASE + 0x1008) // ECR Control #define IECRH_2 (EDMA3_TPCC2_BASE + 0x105C) // IECRH Control #define IECR_2 (EDMA3_TPCC2_BASE + 0x1058) // IECR Control #define EECRH_2 (EDMA3_TPCC2_BASE + 0x102C) // EECRH Control #define EECR_2 (EDMA3_TPCC2_BASE + 0x1028) // EECR Control //***************************************************** // GPIO definitions #define GPIO_BASE 0x02320000 #define GPIO_BITEN (*(unsigned int*)(GPIO_BASE + 0x0008)) // BITEN Control #define GPIO_DIR (*(unsigned int*)(GPIO_BASE + 0x0010)) // DIR Control #define GPIO_OUT_DATA (*(unsigned int*)(GPIO_BASE + 0x0014)) // OUT_DATA Control #define GPIO_IN_DATA (*(unsigned int*)(GPIO_BASE + 0x0020)) // IN_DATA Register #define GPIO_CLR_RIS_TRIG (*(unsigned int*)(GPIO_BASE + 0x0028)) // CLR_RIS_TRIG Control #define GPIO_CLR_FAL_TRIG (*(unsigned int*)(GPIO_BASE + 0x0030)) // CLR_FAL_TRIG Control #define GPIO_DEFAULT_DIR 0xFFFF2CFF // GP08,GP09,GP12,GP14,GP15 (Nand) are outputs #define GPIO_DEFAULT_OUT 0x0000D000 // GP15, GP14, GP12 default to HIGH // Used for eeprom programming #define LITTLE_END 1 #define BIG_END 2 // SGMII definitions #define SGMII_SERDES_BASE 0x02090000 #define SGMII_SLIVER_BASE1 0x02090900 #define SGMII_SLIVER_BASE2 0x02090940 #define SGMII_SERDES_CONTROL_PORT1 (*(unsigned int*)(SGMII_SERDES_BASE + 0x210)) #define SGMII_SERDES_MR_ADV_PORT1 (*(unsigned int*)(SGMII_SERDES_BASE + 0x218)) #define SGMII_SERDES_AUX_CFG_PORT1 (*(unsigned int*)(SGMII_SERDES_BASE + 0x238)) #define SGMII_SERDES_CONTROL_PORT0 (*(unsigned int*)(SGMII_SERDES_BASE + 0x110)) #define SGMII_SERDES_MR_ADV_PORT0 (*(unsigned int*)(SGMII_SERDES_BASE + 0x118)) #define SGMII_SERDES_AUX_CFG_PORT0 (*(unsigned int*)(SGMII_SERDES_BASE + 0x138)) #define SGMII_SLIVER_MACCONTROL1 (*(unsigned int*)(SGMII_SLIVER_BASE1 + 0x004)) #define SGMII_SLIVER_MAXLEN1 (*(unsigned int*)(SGMII_SLIVER_BASE1 + 0x010)) #define SGMII_SLIVER_MACCONTROL2 (*(unsigned int*)(SGMII_SLIVER_BASE2 + 0x004)) #define SGMII_SLIVER_MAXLEN2 (*(unsigned int*)(SGMII_SLIVER_BASE2 + 0x010)) #define CPSW3G_BASE 0x02090800 #define CPSW3G_CONTROL_REG (*(unsigned int*)(CPSW3G_BASE + 0x004)) #define CPSW3G_STAT_PORT_REG (*(unsigned int*)(CPSW3G_BASE + 0x00C)) #define CPSW3G_ALE_CONTROL_REG (*(unsigned int*)(CPSW3G_BASE + 0x608)) #define CPSW3G_ALE_PORT_0_CTL_REG (*(unsigned int*)(CPSW3G_BASE + 0x640)) #define CPSW3G_ALE_PORT_1_CTL_REG (*(unsigned int*)(CPSW3G_BASE + 0x644)) #define CPSW3G_ALE_PORT_2_CTL_REG (*(unsigned int*)(CPSW3G_BASE + 0x648)) #define CPSW3G_ALE_PORT_STATE_FORWARD 0x3 //TIMER 0 definitions #define TIMER0_CNTLO (*(unsigned int*)(0x02200010)) #define TIMER0_CNTHI (*(unsigned int*)(0x02200014)) #define TIMER0_PRDLO (*(unsigned int*)(0x02200018)) #define TIMER0_PRDHI (*(unsigned int*)(0x0220001C)) #define TIMER0_TCR (*(unsigned int*)(0x02200020)) #define TIMER0_TGCR (*(unsigned int*)(0x02200024)) #define PLL_REINIT_MAX_COUNT (10) /* * The delay function is called from wherever a delay is needed. The parameter is the * delay period (in milliseconds) */ Delay_milli_seconds(myDelay) { Set_Timeout(myDelay); while(Get_Timeout()); Kill_Timeout(); } /** * @brief Simple DDR3 test * * @details * This function performs a simple DDR3 test for a memory range * specified below and returns -1 for failure and 0 for success. */ #define DDR3_TEST_START_ADDRESS (0x80000000) #define DDR3_TEST_END_ADDRESS (DDR3_TEST_START_ADDRESS + (4 * 100)) // Flag for i2c eeprom programming process int i2cprog=0; /*--------------------------------------------------------------*/ /* EVMC6670L MENU */ /*--------------------------------------------------------------*/ menuitem "LC_EVM_C6670_Functions"; /**************************************************************************** * * NAME * OnPreFileLoaded * * PURPOSE: * Called by CCS when you do in menu File->LoadProgram, File->LoadSymbols, * etc, before loading anything. * * USAGE * This routine is a callback routine and called by CCS only. * * RETURN VALUE * NONE * * REFERENCE * ****************************************************************************/ OnPreFileLoaded() { if (ON_FILE_LOAD_CODE_ENABLE == 1) { // System reset to assure reliablity between projects if (SYSTEM_RESET_BEFORE_FILE_LOAD_ENABLE == 1) { GEL_TextOut( "System Reset...\n" ); GEL_AdvancedReset("System Reset"); GEL_TextOut( "System Reset... Done.\n" ); // Let core get stable from reset Wait_Soft(4000); } // Disable interrupts IER = 0; // Is used to be sure dsp is ready to load a file // Can be comment out if not needed... (Must be used if using DDR, see OnReset() which is called by CCS when GEL_Reset() is executed) //GEL_TextOut( "GEL Reset...\n" ); GEL_Reset(); //GEL_TextOut( "GEL Reset... Done.\n" ); // Slow down the speed at which the cores get their code loaded to maintain JTAG stability when using multiple cores simultaneously. Wait_Soft(5000 + (DNUM * 10000)); } } /**************************************************************************** * * NAME * StartUp * * PURPOSE: * Perform CCS Memory Map configuration. * This function is called each time CCS is started. * * USAGE * This routine is a callback routine and called by CCS only. * * RETURN VALUE * NONE * * REFERENCE * ****************************************************************************/ StartUp( ) { Setup_Memory_Map( ); } /*--------------------------------------------------------------*/ /* OnTargetConnect() */ /* This function is called by CCS when you do Debug->Connect on */ /* CCS 3.X. */ /*--------------------------------------------------------------*/ OnTargetConnect() { /*------------------------------------------------------*/ /* GEL_Reset() is used to deal with the worst case */ /* senario of unknown target state. If for some reason */ /* a reset is not desired upon target connection, */ /* GEL_Reset() may be removed and replaced with */ /* something "less brutal" like a cache initialization */ /* function. */ /*------------------------------------------------------*/ //GEL_Reset(); //Set_DSP_Cache(); /* DDR PLL settings for 1333 MHz */ unsigned int PLLM_DDR = 19; unsigned int PLLD_DDR = 0; if (ON_TARGET_CONNECT_CODE_ENABLE == 1) { if (DNUM == 0) { // Validates if emulation boot mode if (DEVSTAT & 0x0000000E) { //GEL_TextOut("Initialize DDR3 since bootmode = %x \n",,,,,(DEVSTAT >> 1 ) & 0xF); // Setup Pll2 DDR3 PLL @ 667 MHz Init_Pll2(PLLM_DDR, PLLD_DDR); //GEL_TextOut( "DDR begin (1333 auto)\n"); xmc_setup(); ddr3_setup_auto_lvl_1333(0); //GEL_TextOut( "DDR done\n"); } } // Slow down the speed at which the cores connect to maintain JTAG stability when using multiple cores simultaneously. Wait_Soft(5000 + (DNUM * 5000)); } } /*--------------------------------------------------------------*/ /* OnReset() */ /* This function is called by CCS when you do Debug->Reset. */ /* The goal is to put the C6x into a known good state with */ /* respect to cache, edma and interrupts. */ /*--------------------------------------------------------------*/ OnReset( int nErrorCode ) { } /*--------------------------------------------------------------*/ /* xmc_setup() */ /* XMC MPAX register setting to access DDR3 config space */ /*--------------------------------------------------------------*/ #define XMC_BASE_ADDR (0x08000000) #define XMPAX2_L (*(int*)(XMC_BASE_ADDR + 0x00000010)) #define XMPAX2_H (*(int*)(XMC_BASE_ADDR + 0x00000014)) xmc_setup() { /* mapping for ddr emif registers XMPAX*2 */ XMPAX2_L = 0x100000FF; /* replacement addr + perm*/ XMPAX2_H = 0x2100000B; /* base addr + seg size (64KB)*/ //"1B"-->"B" by xj //GEL_TextOut("XMC setup complete.\n","2"); } /*--------------------------------------------------------------*/ /* ddr3_setup() */ /* DDR3 initialization */ /*--------------------------------------------------------------*/ int flag; ddr3_setup_auto_lvl_1333() { int i,TEMP,startlo, stoplo,starthi, stophi; KICK0 = KICK0_UNLOCK; KICK1 = KICK1_UNLOCK; /* Wait for PLL to lock = min 500 ref clock cycles. With refclk = 100MHz, = 5000 ns = 5us */ Delay_milli_seconds(1); /***************** 3.2 DDR3 PLL Configuration ************/ /* Done before */ /**************** 3.0 Leveling Register Configuration ********************/ /* Using partial automatic leveling due to errata */ /**************** 3.3 Leveling register configuration ********************/ DDR3_CONFIG_REG_0 &= ~(0x007FE000); // clear ctrl_slave_ratio field DDR3_CONFIG_REG_0 |= 0x00200000; // set ctrl_slave_ratio to 0x100 DDR3_CONFIG_REG_12 |= 0x08000000; // Set invert_clkout = 1 DDR3_CONFIG_REG_0 |= 0xF; // set dll_lock_diff to 15 //From 4.2.1 Executing Partial Automatic Leveling -- Start DDR3_CONFIG_REG_23 |= 0x00000200; //Set bit 9 = 1 to use forced ratio leveling for read DQS //From 4.2.1 Executing Partial Automatic Leveling -- End //Values with invertclkout = 1 /**************** 3.3 Partial Automatic Leveling ********************/ DATA0_WRLVL_INIT_RATIO = 0x5E; DATA1_WRLVL_INIT_RATIO = 0x5E; DATA2_WRLVL_INIT_RATIO = 0x5E; DATA3_WRLVL_INIT_RATIO = 0x51; DATA4_WRLVL_INIT_RATIO = 0x38; DATA5_WRLVL_INIT_RATIO = 0x3A; DATA6_WRLVL_INIT_RATIO = 0x24; DATA7_WRLVL_INIT_RATIO = 0x20; DATA8_WRLVL_INIT_RATIO = 0x44; DATA0_GTLVL_INIT_RATIO = 0xDD; DATA1_GTLVL_INIT_RATIO = 0xDD; DATA2_GTLVL_INIT_RATIO = 0xBE; DATA3_GTLVL_INIT_RATIO = 0xCA; DATA4_GTLVL_INIT_RATIO = 0xA9; DATA5_GTLVL_INIT_RATIO = 0xA7; DATA6_GTLVL_INIT_RATIO = 0x9E; DATA7_GTLVL_INIT_RATIO = 0xA1; DATA8_GTLVL_INIT_RATIO = 0xBA; //Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0 DDR_DDRPHYC &= ~(0x00008000); DDR_DDRPHYC |= (0x00008000); DDR_DDRPHYC &= ~(0x00008000); /***************** 3.4 Basic Controller and DRAM Configuration ************/ DDR_SDRFC = 0x00005162; // enable configuration /* DDR_SDTIM1 = 0x1113783C; */ TEMP = 0; TEMP |= 0x8 << 25; // T_RP bit field 28:25 TEMP |= 0x8 << 21; // T_RCD bit field 24:21 TEMP |= 0x9 << 17; // T_WR bit field 20:17 TEMP |= 0x17 << 12; // T_RAS bit field 16:12 TEMP |= 0x20 << 6; // T_RC bit field 11:6 TEMP |= 0x7 << 3; // T_RRD bit field 5:3 TEMP |= 0x4; // T_WTR bit field 2:0 DDR_SDTIM1 = TEMP; /* DDR_SDTIM2 = 0x30717FE3; */ TEMP = 0; TEMP |= 0x3 << 28; // T_XP bit field 30:28 TEMP |= 0x71 << 16; // T_XSNR bit field 24:16 TEMP |= 0x1ff << 6; // T_XSRD bit field 15:6 TEMP |= 0x4 << 3; // T_RTP bit field 5:3 TEMP |= 0x3; // T_CKE bit field 2:0 DDR_SDTIM2 = TEMP; /* DDR_SDTIM3 = 0x559F86AF; */ TEMP = 0; TEMP |= 0x5 << 28; // T_PDLL_UL bit field 31:28 (fixed value) TEMP |= 0x5 << 24; // T_CSTA bit field 27:24 (fixed value) TEMP |= 0x4 << 21; // T_CKESR bit field 23:21 TEMP |= 0x3f << 15; // T_ZQCS bit field 20:15 TEMP |= 0x6a << 4; // T_RFC bit field 12:4 TEMP |= 0xf; // T_RAS_MAX bit field 3:0 (fixed value) DDR_SDTIM3 = TEMP; DDR_DDRPHYC = 0x0010010F; DDR_ZQCFG = 0x70073214; DDR_PMCTL = 0x0; DDR_SDRFC = 0x00005162; // enable configuration /* DDR_SDCFG = 0x63062A32; */ /* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 //0x63222A32; // last config write DRAM init occurs */ TEMP = 0; TEMP |= 0x3 << 29; // SDRAM_TYPE bit field 31:29 (fixed value) TEMP |= 0x0 << 27; // IBANK_POS bit field 28:27 TEMP |= 0x3 << 24; // DDR_TERM bit field 26:24 TEMP |= 0x0 << 21; // DYN_ODT bit field 22:21 TEMP |= 0x1 << 18; // SDRAM_DRIVE bit field 19:18 TEMP |= 0x2 << 16; // CWL bit field 17:16 TEMP |= 0x0 << 14; // NM bit field 15:14 TEMP |= 0xA << 10; // CL bit field 13:10 TEMP |= 0x4 << 7; // ROWSIZE bit field 9:7 TEMP |= 0x3 << 4; // IBANK bit field 6:4 TEMP |= 0x0 << 3; // EBANK bit field 3:3 TEMP |= 0x2; // PAGESIZE bit field 2:0 DDR_SDCFG = TEMP; //Wait 600us for HW init to complete Delay_milli_seconds(1); DDR_SDRFC = 0x00001450; //Refresh rate = (7.8*666MHz) /**************** 4.2.1 Executing Partial Automatic Leveling ********************/ DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling DDR_RDWR_LVL_CTRL = 0x80000000; //Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value //(0x34) instead //Wait for min 1048576 DDR clock cycles for leveling to complete = 1048576 * 1.5ns = 1572864ns = 1.57ms. //Actual time = ~10-15 ms Delay_milli_seconds(1); //GEL_TextOut("\nDDR3 initialization is complete.\n"); } /**************************************************************************** * * NAME * Reset * * PURPOSE: * Performs the Gel Reset * * USAGE * This function can be called as below. * GEL_Reset() * * RETURN VALUE * NONE * * REFERENCE * ****************************************************************************/ hotmenu Reset() { GEL_Reset(); } /**************************************************************************** * * NAME * Init XMC * * PURPOSE: * Performs the Extended Memory Controller Setup * * USAGE * This function can be called as below. * InitXMC() * * RETURN VALUE * NONE * * REFERENCE * ****************************************************************************/ hotmenu InitXMC() { xmc_setup(); } /**************************************************************************** * * NAME * Init Emif * * PURPOSE: * Performs the External Memory Interface initialization * * USAGE * This function can be called as below. * InitEmif() * * RETURN VALUE * NONE * * REFERENCE * ****************************************************************************/ hotmenu InitEmif() { ddr3_setup_auto_lvl_1333(0); } prog_pll1_values(unsigned int pll_multiplier, unsigned int pll_divider, unsigned int odiv) { int TEMP; /* Check the Range for the parameters */ if (odiv > 15) { GEL_TextOut ( " invalid output divide range, should be less than 15... \n"); } if (pll_multiplier > 4095) { GEL_TextOut ( " invalid pll multiplier range, should be less than 4095... \n"); } if (pll_divider > 63) { GEL_TextOut ( " invalid pll multiplier range, should be less than 63... \n"); } /* Set the PLL Multiplier, Divider, BWADJ * * The PLLM[5:0] bits of the multiplier are controlled by the PLLM Register * * inside the PLL Controller and the PLLM[12:6] bits are controlled by the * * chip-level MAINPLLCTL0 Register. * * PLL Control Register (PLLM) Layout * * |31...6 |5...0 | * * |Reserved |PLLM | * * * * Main PLL Control Register (MAINPLLCTL0) * * |31...24 |23...19 |18...12 | 11...6 |5...0 | * * |BWADJ[7:0]| Reserved |PLLM[12:6] | Reserved | PLLD | */ /* Set pll multipler (13 bit field) */ PLL1_PLLM = (pll_multiplier & 0x0000003F); /* bits[5:0] */ TEMP = (pll_multiplier & 0x1FC0) >> 6;/* bits[12:6] */ MAINPLLCTL0 &=~(0x0007F000); /*Clear PLLM field */ MAINPLLCTL0 |=((TEMP << 12) & 0x0007F000); /* Set the BWADJ (12 bit field) * * BWADJ[11:8] and BWADJ[7:0] are located in MAINPLLCTL0 and MAINPLLCTL1 * * registers. BWADJ[11:0] should be programmed to a value equal to half of * * PLLM[12:0] value (round down if PLLM has an odd value) * * Example: If PLLM = 15, then BWADJ = 7 */ TEMP = ((pll_multiplier + 1) >> 1) - 1; /* Divide the pllm by 2 */ MAINPLLCTL0 &=~(0xFF000000); /* Clear the BWADJ Field */ MAINPLLCTL0 |= ((TEMP << 24) & 0xFF000000); MAINPLLCTL1 &=~(0x0000000F); /* Clear the BWADJ field */ MAINPLLCTL1 |= ((TEMP >> 8) & 0x0000000F); /* Set the pll divider (6 bit field) * * PLLD[5:0] is located in MAINPLLCTL0 */ MAINPLLCTL0 &= ~(0x0000003F); /* Clear the Field */ MAINPLLCTL0 |= (pll_divider & 0x0000003F); /* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */ PLL1_SECCTL &= ~(0x00780000); /* Clear the field */ PLL1_SECCTL |= ((odiv << 19) & 0x00780000) ; } /**************************************************************************** * * NAME * Set_Timeout * * PURPOSE: * Starts a timeout period of msec. The running timeout period can be * query with Get_Timeout. To kill a running timeout before the end, * call Kill_Timeout. Only one timeout period can be used at any time. * A timeout period can be used to measure a period of time while doing * anything else. Not accurate, sets timer at least as big as desired. * * USAGE * This routine can be called as: * * Set_Timeout(msec) * * msec - (i) timeout period in msec (not very precise < sec range) * * RETURN VALUE * NONE * * REFERENCE * ****************************************************************************/ Set_Timeout(msec) { // Cancel the current timer if not already expired GEL_CancelTimer(TIMEOUT_ID); // Starts the timeout period _GEL_Global_Timeout1=1; // Setup a callback routine with specified timeout GEL_SetTimer(msec, TIMEOUT_ID, "_Timeout_Callback()"); } /**************************************************************************** * * NAME * Get_Timeout * * PURPOSE: * Query the running state of a timeout period started by Set_Timeout. * (see Set_Timeout for more info). * * USAGE * This routine can be called as: * * Get_Timeout() * * RETURN VALUE * 0:expired, 1:running * * REFERENCE * ****************************************************************************/ Get_Timeout() { if (!_GEL_Global_Timeout1) { // Cancel the current timer GEL_CancelTimer(TIMEOUT_ID); } // Return the global timeout status 1=running, 0=expired return _GEL_Global_Timeout1; } /**************************************************************************** * * NAME * Kill_Timeout * * PURPOSE: * Cancel a running timeout period before it expires * (see Set_Timeout for more info). * * USAGE * This routine can be called as: * * Kill_Timeout() * * RETURN VALUE * NONE * * REFERENCE * ****************************************************************************/ Kill_Timeout() { // Cancel the current timer GEL_CancelTimer(TIMEOUT_ID); // The timeout period is expired _GEL_Global_Timeout1=0; } /**************************************************************************** * * NAME * _Timeout_Callback * * PURPOSE: * Internal Callback function used by Set_timeout * (see Set_Timeout for more info). * * USAGE * This routine must not be called by itself. * * RETURN VALUE * NONE * * REFERENCE * ****************************************************************************/ _Timeout_Callback() { // The timeout period is expired _GEL_Global_Timeout1=0; } /**************************************************************************** * * NAME * Setup_Memory_Map * * PURPOSE: * Setup the Memory Map for EVMC6670L. * Defined memory location avoid debugger access outside these locations. * * USAGE * This routine can be called as: * * Setup_Memory_Map() * * RETURN VALUE * NONE * * REFERENCE * Based on TMS320C6670 datasheet. * ****************************************************************************/ hotmenu Setup_Memory_Map( ) { //GEL_TextOut("Setup_Memory_Map...\n",,); GEL_MapOn( ); GEL_MapReset( ); if (AVV_MEM_MAP == 1) { GEL_MapAddStr( 0x00800000, 0, 0x00004000, "PRAM", 0 ); // Local L2 SRAM L2RAM_INPUT_DAT_MEM GEL_MapAddStr( 0x00804000, 0, 0x00000040, "PRAM", 0 ); // Local L2 SRAM L2RAM_TEST_RESULTS GEL_MapAddStr( 0x00804040, 0, 0x000fbfc0, "R|W|AS4", 0 ); // Local L2 SRAM } else { GEL_MapAddStr( 0x00800000, 0, 0x00100000, "R|W|AS4", 0 ); // Local L2 SRAM } GEL_MapAddStr( 0x00E00000, 0, 0x00008000, "R|W|AS4", 0 ); // Local L1P SRAM GEL_MapAddStr( 0x00F00000, 0, 0x00008000, "R|W|AS4", 0 ); // Local L1D SRAM GEL_MapAddStr( 0x01000000, 0, 0x01C00000, "R|W|AS4", 0 ); // C66x CorePac Registers GEL_MapAddStr( 0x01D00000, 0, 0x00000080, "R|W|AS4", 0 ); // Tracer 0 GEL_MapAddStr( 0x01D08000, 0, 0x00000080, "R|W|AS4", 0 ); // Tracer 1 GEL_MapAddStr( 0x01D10000, 0, 0x00000080, "R|W|AS4", 0 ); // Tracer 2 GEL_MapAddStr( 0x01D18000, 0, 0x00000080, "R|W|AS4", 0 ); // Tracer 3 GEL_MapAddStr( 0x01D20000, 0, 0x00000080, "R|W|AS4", 0 ); // Tracer 4 GEL_MapAddStr( 0x01D28000, 0, 0x00000080, "R|W|AS4", 0 ); // Tracer 5 GEL_MapAddStr( 0x01D30000, 0, 0x00000080, "R|W|AS4", 0 ); // Tracer 6 GEL_MapAddStr( 0x01D38000, 0, 0x00000080, "R|W|AS4", 0 ); // Tracer 7 GEL_MapAddStr( 0x01D40000, 0, 0x00000080, "R|W|AS4", 0 ); // Tracer 8 GEL_MapAddStr( 0x01D48000, 0, 0x00000080, "R|W|AS4", 0 ); // Tracer 9 GEL_MapAddStr( 0x01D50000, 0, 0x00000080, "R|W|AS4", 0 ); // Tracer 10 GEL_MapAddStr( 0x01D58000, 0, 0x00000080, "R|W|AS4", 0 ); // Tracer 11 GEL_MapAddStr( 0x01D60000, 0, 0x00000080, "R|W|AS4", 0 ); // Tracer 12 GEL_MapAddStr( 0x01D68000, 0, 0x00000080, "R|W|AS4", 0 ); // Tracer 13 GEL_MapAddStr( 0x01D70000, 0, 0x00000080, "R|W|AS4", 0 ); // Tracer 14 GEL_MapAddStr( 0x01D78000, 0, 0x00000080, "R|W|AS4", 0 ); // Tracer 15 GEL_MapAddStr( 0x01F00000, 0, 0x00080000, "R|W|AS4", 0 ); // AIF2 Control GEL_MapAddStr( 0x01F80000, 0, 0x00010000, "R|W|AS4", 0 ); // RAC_B - FEI Control GEL_MapAddStr( 0x01F90000, 0, 0x00010000, "R|W|AS4", 0 ); // RAC_B - BEI Control GEL_MapAddStr( 0x01FA0000, 0, 0x00020000, "R|W|AS4", 0 ); // RAC_B - GCCP 0 Control GEL_MapAddStr( 0x01FC0000, 0, 0x00020000, "R|W|AS4", 0 ); // RAC_B - GCCP 1 Control GEL_MapAddStr( 0x02000000, 0, 0x00090000, "R|W|AS4", 0 ); // Packet Accelerator Configuration GEL_MapAddStr( 0x02090000, 0, 0x00030000, "R|W|AS4", 0 ); // Ethernet Switch Subsystem Configuration GEL_MapAddStr( 0x020C0000, 0, 0x00040000, "R|W|AS4", 0 ); // Crypto Subsystem Configuration GEL_MapAddStr( 0x02100000, 0, 0x00010000, "R|W|AS4", 0 ); // RAC_A - FEI Control GEL_MapAddStr( 0x02110000, 0, 0x00010000, "R|W|AS4", 0 ); // RAC_A - BEI Control GEL_MapAddStr( 0x02120000, 0, 0x00020000, "R|W|AS4", 0 ); // RAC_A - GCCP 0 Control GEL_MapAddStr( 0x02140000, 0, 0x00020000, "R|W|AS4", 0 ); // RAC_A - GCCP 1 Control GEL_MapAddStr( 0x02180000, 0, 0x00008000, "R|W|AS4", 0 ); // TAC - FEI Control GEL_MapAddStr( 0x02188000, 0, 0x00008000, "R|W|AS4", 0 ); // TAC - BEI Control GEL_MapAddStr( 0x02190000, 0, 0x00010000, "R|W|AS4", 0 ); // TAC - SGCCP 0 Control GEL_MapAddStr( 0x021A0000, 0, 0x00010000, "R|W|AS4", 0 ); // TAC - SGCCP 1 Control GEL_MapAddStr( 0x021C0000, 0, 0x00000400, "R|W|AS4", 0 ); // TCP3d-A GEL_MapAddStr( 0x021C8000, 0, 0x00000400, "R|W|AS4", 0 ); // TCP3d-B GEL_MapAddStr( 0x021D0000, 0, 0x00000100, "R|W|AS4", 0 ); // VCP2-A GEL_MapAddStr( 0x021D4000, 0, 0x00000100, "R|W|AS4", 0 ); // VCP2-B GEL_MapAddStr( 0x021D8000, 0, 0x00000100, "R|W|AS4", 0 ); // VCP2-C GEL_MapAddStr( 0x021DC000, 0, 0x00000100, "R|W|AS4", 0 ); // VCP2-D GEL_MapAddStr( 0x021E0000, 0, 0x00001000, "R|W|AS4", 0 ); // TCP3e GEL_MapAddStr( 0x021F0000, 0, 0x00000800, "R|W|AS4", 0 ); // FFTC-A Configuration GEL_MapAddStr( 0x021F4000, 0, 0x00000800, "R|W|AS4", 0 ); // FFTC-B Configuration GEL_MapAddStr( 0x02200000, 0, 0x00000080, "R|W|AS4", 0 ); // Timer0 GEL_MapAddStr( 0x02210000, 0, 0x00000080, "R|W|AS4", 0 ); // Timer1 GEL_MapAddStr( 0x02220000, 0, 0x00000080, "R|W|AS4", 0 ); // Timer2 GEL_MapAddStr( 0x02230000, 0, 0x00000080, "R|W|AS4", 0 ); // Timer3 GEL_MapAddStr( 0x02240000, 0, 0x00000080, "R|W|AS4", 0 ); // Timer4 GEL_MapAddStr( 0x02250000, 0, 0x00000080, "R|W|AS4", 0 ); // Timer5 GEL_MapAddStr( 0x02260000, 0, 0x00000080, "R|W|AS4", 0 ); // Timer6 GEL_MapAddStr( 0x02270000, 0, 0x00000080, "R|W|AS4", 0 ); // Timer7 GEL_MapAddStr( 0x02310000, 0, 0x00000200, "R|W|AS4", 0 ); // PLL Controller GEL_MapAddStr( 0x02320000, 0, 0x00000100, "R|W|AS4", 0 ); // GPIO GEL_MapAddStr( 0x02330000, 0, 0x00000400, "R|W|AS4", 0 ); // SmartReflex GEL_MapAddStr( 0x02350000, 0, 0x00001000, "R|W|AS4", 0 ); // Power Sleep Controller GEL_MapAddStr( 0x02360000, 0, 0x00000400, "R|W|AS4", 0 ); // Memory Protection Unit (MPU) 0 GEL_MapAddStr( 0x02368000, 0, 0x00000400, "R|W|AS4", 0 ); // Memory Protection Unit (MPU) 1 GEL_MapAddStr( 0x02370000, 0, 0x00000400, "R|W|AS4", 0 ); // Memory Protection Unit (MPU) 2 GEL_MapAddStr( 0x02378000, 0, 0x00000400, "R|W|AS4", 0 ); // Memory Protection Unit (MPU) 3 GEL_MapAddStr( 0x02380000, 0, 0x00000400, "R|W|AS4", 0 ); // Memory Protection Unit (MPU) 4 GEL_MapAddStr( 0x02440000, 0, 0x00004000, "R|W|AS4", 0 ); // DSP Trace Formatter 0 GEL_MapAddStr( 0x02450000, 0, 0x00004000, "R|W|AS4", 0 ); // DSP Trace Formatter 1 GEL_MapAddStr( 0x02460000, 0, 0x00004000, "R|W|AS4", 0 ); // DSP Trace Formatter 2 GEL_MapAddStr( 0x02470000, 0, 0x00004000, "R|W|AS4", 0 ); // DSP Trace Formatter 3 GEL_MapAddStr( 0x02530000, 0, 0x00000080, "R|W|AS4", 0 ); // I2C Data & Control GEL_MapAddStr( 0x02540000, 0, 0x00000040, "R|W|AS4", 0 ); // UART GEL_MapAddStr( 0x02600000, 0, 0x00002000, "R|W|AS4", 0 ); // Secondary Interrupt Controller (INTC) 0 GEL_MapAddStr( 0x02604000, 0, 0x00002000, "R|W|AS4", 0 ); // Secondary Interrupt Controller (INTC) 1 GEL_MapAddStr( 0x02608000, 0, 0x00002000, "R|W|AS4", 0 ); // Secondary Interrupt Controller (INTC) 2 GEL_MapAddStr( 0x02620000, 0, 0x00000400, "R|W|AS4", 0 ); // Chip-Level Registers GEL_MapAddStr( 0x02640000, 0, 0x00000800, "R|W|AS4", 0 ); // Semaphore GEL_MapAddStr( 0x02700000, 0, 0x00008000, "R|W|AS4", 0 ); // EDMA Channel Controller (TPCC) 0 GEL_MapAddStr( 0x02720000, 0, 0x00008000, "R|W|AS4", 0 ); // EDMA Channel Controller (TPCC) 1 GEL_MapAddStr( 0x02740000, 0, 0x00008000, "R|W|AS4", 0 ); // EDMA Channel Controller (TPCC) 2 GEL_MapAddStr( 0x02760000, 0, 0x00000400, "R|W|AS4", 0 ); // EDMA TPCC0 Transfer Controller (TPTC) 0 GEL_MapAddStr( 0x02768000, 0, 0x00000400, "R|W|AS4", 0 ); // EDMA TPCC0 Transfer Controller (TPTC) 1 GEL_MapAddStr( 0x02770000, 0, 0x00000400, "R|W|AS4", 0 ); // EDMA TPCC1 Transfer Controller (TPTC) 0 GEL_MapAddStr( 0x02778000, 0, 0x00000400, "R|W|AS4", 0 ); // EDMA TPCC1 Transfer Controller (TPTC) 1 GEL_MapAddStr( 0x02780000, 0, 0x00000400, "R|W|AS4", 0 ); // EDMA TPCC1 Transfer Controller (TPTC) 2 GEL_MapAddStr( 0x02788000, 0, 0x00000400, "R|W|AS4", 0 ); // EDMA TPCC1 Transfer Controller (TPTC) 3 GEL_MapAddStr( 0x02790000, 0, 0x00000400, "R|W|AS4", 0 ); // EDMA TPCC2 Transfer Controller (TPTC) 0 GEL_MapAddStr( 0x02798000, 0, 0x00000400, "R|W|AS4", 0 ); // EDMA TPCC2 Transfer Controller (TPTC) 1 GEL_MapAddStr( 0x027A0000, 0, 0x00000400, "R|W|AS4", 0 ); // EDMA TPCC2 Transfer Controller (TPTC) 2 GEL_MapAddStr( 0x027A8000, 0, 0x00000400, "R|W|AS4", 0 ); // EDMA TPCC2 Transfer Controller (TPTC) 3 GEL_MapAddStr( 0x027D0000, 0, 0x00004000, "R|W|AS4", 0 ); // TI Embedded Trace Buffer (TETB) - Core 0 GEL_MapAddStr( 0x027E0000, 0, 0x00004000, "R|W|AS4", 0 ); // TI Embedded Trace Buffer (TETB) - Core 1 GEL_MapAddStr( 0x027F0000, 0, 0x00004000, "R|W|AS4", 0 ); // TI Embedded Trace Buffer (TETB) - Core 2 GEL_MapAddStr( 0x02800000, 0, 0x00004000, "R|W|AS4", 0 ); // TI Embedded Trace Buffer (TETB) - Core 3 GEL_MapAddStr( 0x02850000, 0, 0x00008000, "R|W|AS4", 0 ); // TI Embedded Trace Buffer (TETB) - System GEL_MapAddStr( 0x02900000, 0, 0x00008000, "R|W|AS4", 0 ); // Serial RapidIO Configuration GEL_MapAddStr( 0x02A00000, 0, 0x00100000, "R|W|AS4", 0 ); // Queue Manager Subsystem Configuration GEL_MapAddStr( 0x08000000, 0, 0x00010000, "R|W|AS4", 0 ); // Extended Memory Controller (XMC) Configuration GEL_MapAddStr( 0x0BC00000, 0, 0x00100000, "R|W|AS4", 0 ); // Multicore Shared Memory Controller (MSMC) Config GEL_MapAddStr( 0x0C000000, 0, 0x00200000, "R|W|AS4", 0 ); // Multicore Shared Memory (MSM) GEL_MapAddStr( 0x10800000, 0, 0x00100000, "R|W|AS4", 0 ); // Core0 L2 SRAM GEL_MapAddStr( 0x10E00000, 0, 0x00008000, "R|W|AS4", 0 ); // Core0 L1P SRAM GEL_MapAddStr( 0x10F00000, 0, 0x00008000, "R|W|AS4", 0 ); // Core0 L1D SRAM GEL_MapAddStr( 0x11800000, 0, 0x00100000, "R|W|AS4", 0 ); // Core1 L2 SRAM GEL_MapAddStr( 0x11E00000, 0, 0x00008000, "R|W|AS4", 0 ); // Core1 L1P SRAM GEL_MapAddStr( 0x11F00000, 0, 0x00008000, "R|W|AS4", 0 ); // Core1 L1D SRAM GEL_MapAddStr( 0x12800000, 0, 0x00100000, "R|W|AS4", 0 ); // Core2 L2 SRAM GEL_MapAddStr( 0x12E00000, 0, 0x00008000, "R|W|AS4", 0 ); // Core2 L1P SRAM GEL_MapAddStr( 0x12F00000, 0, 0x00008000, "R|W|AS4", 0 ); // Core2 L1D SRAM GEL_MapAddStr( 0x13800000, 0, 0x00100000, "R|W|AS4", 0 ); // Core3 L2 SRAM GEL_MapAddStr( 0x13E00000, 0, 0x00008000, "R|W|AS4", 0 ); // Core3 L1P SRAM GEL_MapAddStr( 0x13F00000, 0, 0x00008000, "R|W|AS4", 0 ); // Core3 L1D SRAM GEL_MapAddStr( 0x20000000, 0, 0x00100000, "R|W|AS4", 0 ); // System Trace Manager (STM) Configuration GEL_MapAddStr( 0x20200000, 0, 0x00400000, "R|W|AS4", 0 ); // RAC_B Data GEL_MapAddStr( 0x20600000, 0, 0x00100000, "R|W|AS4", 0 ); // TCP3d-B Data GEL_MapAddStr( 0x20800000, 0, 0x00100000, "R|W|AS4", 0 ); // TCP3d-A Data GEL_MapAddStr( 0x20900000, 0, 0x00002000, "R|W|AS4", 0 ); // TCP3e Data Write Port GEL_MapAddStr( 0x20902000, 0, 0x00002000, "R|W|AS4", 0 ); // TCP3e Data Read Port GEL_MapAddStr( 0x20B00000, 0, 0x00020000, "R|W|AS4", 0 ); // Boot ROM GEL_MapAddStr( 0x20BF0000, 0, 0x00000400, "R|W|AS4", 0 ); // SPI GEL_MapAddStr( 0x21000000, 0, 0x00000100, "R|W|AS4", 0 ); // DDR3 EMIF Configuration GEL_MapAddStr( 0x21400000, 0, 0x00000080, "R|W|AS4", 0 ); // Hyperlink Config (local) /* Uncomment the following line to see the hyperlink remote config registers. * Accessing the remote registers, even indirectly (by dragging a memory window * to be big enough to cover the remote registers) will result in a fatal error if * hyperlink is powered on but the link has not been established. */ // GEL_MapAddStr( 0x21400080, 0, 0x00000080, "R|W|AS4", 0 ); // Hyperlink Config (remote) GEL_MapAddStr( 0x21800000, 0, 0x00008000, "R|W|AS4", 0 ); // PCIe Config GEL_MapAddStr( 0x22A00000, 0, 0x00010000, "R|W|AS4", 0 ); // VCP2_A GEL_MapAddStr( 0x22B00000, 0, 0x00010000, "R|W|AS4", 0 ); // VCP2_B GEL_MapAddStr( 0x22C00000, 0, 0x00010000, "R|W|AS4", 0 ); // VCP2_C GEL_MapAddStr( 0x22D00000, 0, 0x00010000, "R|W|AS4", 0 ); // VCP2_D GEL_MapAddStr( 0x33200000, 0, 0x00400000, "R|W|AS4", 0 ); // RAC_A Data GEL_MapAddStr( 0x34000000, 0, 0x00200000, "R|W|AS4", 0 ); // Queue Manager Subsystem Data GEL_MapAddStr( 0x34C00000, 0, 0x00030000, "R|W|AS4", 0 ); // TAC Data GEL_MapAddStr( 0x35020000, 0, 0x00000400, "R|W|AS4", 0 ); // TCP3d_C config GEL_MapAddStr( 0x35040000, 0, 0x00000800, "R|W|AS4", 0 ); // FFTC_C config GEL_MapAddStr( 0x35200000, 0, 0x00020000, "R|W|AS4", 0 ); // BCP config GEL_MapAddStr( 0x35600000, 0, 0x00100000, "R|W|AS4", 0 ); // TCP3d_C data GEL_MapAddStr( 0x40000000, 0, 0x10000000, "R|W|AS4", 0 ); // Hyperlink Data GEL_MapAddStr( 0x50000000, 0, 0x10000000, "R|W|AS4", 0 ); // SRIO Data GEL_MapAddStr( 0x60000000, 0, 0x10000000, "R|W|AS4", 0 ); // PCIe Data GEL_MapAddStr( 0x80000000, 0, 0x80000000, "R|W|AS4", 0 ); // DDR3 EMIF Data //GEL_TextOut( "Setup_Memory_Map... Done.\n" ); } /**************************************************************************** * * NAME * Wait_Soft * * PURPOSE: * Wait for a specified delay in number of empty loop. * * USAGE * This routine can be called as: * * Wait_Soft(nloop) * * nloop - (i) number of empty loop to do for delay * * RETURN VALUE * NONE * * REFERENCE * ****************************************************************************/ Wait_Soft( int nloop ) { int i; // 1 sec ~ 40000 loop on P4 3.4GHz for( i = 0 ; i < nloop ; i++ ) { } } /**************************************************************************** * * NAME * Init_Pll2 (unsigned int multiplier, unsigned int divider) * * PURPOSE: * Setup PLL 2 frequency for DDR3 clock. * The Frequency is based on an external ddr3 clk input ref of 66.65 MHz clock. * * USAGE * This routine can be called as: * * Init_Pll2( unsigned int multiplier, unsigned int divider) * * multiplier - (i) Multiplier * divider - (i) Divider * Note that the values above are actual register values, i.e., * the computed values - 1 * RETURN VALUE * None * * REFERENCE * ****************************************************************************/ Init_Pll2(unsigned int multiplier, unsigned int divider) { unsigned int temp, i; //GEL_TextOut ( "DDR3 PLL (PLL2) Setup ... \n"); /*Unlock Boot Config*/ KICK0 = 0x83E70B13; KICK1 = 0x95A4F1E0; if (DNUM == 0) { /* Usage Note 9: For optimal PLL operation, the ENSAT bit in the PLL control * * registers for the Main PLL, DDR3 PLL, and PA PLL should be set to 1. * * The PLL initialization sequence in the boot ROM sets this bit to 0 and * * could lead to non-optimal PLL operation. Software can set the bit to the * * optimal value of 1 after boot * * DDR3PLLCTL1 Bit map * * |31...7 |6 |5 4 |3...0 | * * |Reserved |ENSAT |Reserved |BWADJ[11:8]| */ DDR3PLLCTL1 |= 0x00000040; /* Put the PLL in PLL Mode * * DDR3PLLCTL0 Bit map * * |31...24 |23 |22...19 |18...6 |5...0 | * * |BWADJ[7:0] |BYPASS |Reserved |PLLM |PLLD | */ DDR3PLLCTL0 |= 0x00800000; /* Set the Bit 23 */ /* Wait for the PLL Reset time (min: 5 us) */ //Delay_milli_seconds(1); /* Program the necessary multipliers/dividers and BW adjustments */ /* Set the divider values */ DDR3PLLCTL0 &= ~(0x0000003F); DDR3PLLCTL0 |= (divider & 0x0000003F); /* Set the Multipler values */ DDR3PLLCTL0 &= ~(0x0007FFC0); DDR3PLLCTL0 |= ((multiplier << 6) & 0x0007FFC0 ); /* Set the BWADJ */ temp = ((multiplier + 1) >> 1) - 1; DDR3PLLCTL0 &= ~(0xFF000000); DDR3PLLCTL0 |= ((temp << 24) & 0xFF000000); DDR3PLLCTL1 &= ~(0x0000000F); DDR3PLLCTL1 |= ((temp >> 8) & 0x0000000F); /* In PLL Controller, reset the PLL (bit 13 in DDR3PLLCTL1 register) */ DDR3PLLCTL1 |= 0x00002000; /* Wait for the PLL Reset time (min: 5 us) */ Delay_milli_seconds(1); /*In DDR3PLLCTL1, write PLLRST = 0 to bring PLL out of reset */ DDR3PLLCTL1 &= ~(0x00002000); /* Wait at least 500 * REFCLK cycles * PLLD (this is the PLL lock time) */ Delay_milli_seconds(1); /* Put the PLL in PLL Mode * * DDR3PLLCTL0 Bit map * * |31...24 |23 |22...19 |18...6 |5...0 | * * |BWADJ[7:0] |BYPASS |Reserved |PLLM |PLLD | */ DDR3PLLCTL0 &= ~(0x00800000); /* ReSet the Bit 23 */ //GEL_TextOut( "DDR3 PLL Setup... Done.\n" ); } else { GEL_TextOut("DSP core #%d cannot set DDR3 PLL\n",,2,,,DNUM); } }