/**
 * \file  edma.c
 *
 * \brief EDMA support for evmAM335x platform
 */

/*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*/
/*
*  Redistribution and use in source and binary forms, with or without
*  modification, are permitted provided that the following conditions
*  are met:
*
*    Redistributions of source code must retain the above copyright
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated nor the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/


#include "hw_control_AM335x.h"
#include "soc_AM335x.h"
#include "hw_cm_per.h"
#include "hw_types.h"

//GD include aggiunti per le nuove funzioni di gestione del DMA
#include "edma.h"
#include "interrupt.h"
#include <ti/sysbios/hal/Hwi.h>
#include <xdc/runtime/Error.h>

//GD variabili aggiunte per le nuove funzioni di gestione del DMA
static unsigned int EDMA3ClkConfigDone = false;
static unsigned int EDMA3IntConfigDone = false;

//GD funzioni aggiunte per le nuove funzioni di gestione del DMA
/* EDMA callback function array */
static void (*cb_Fxn[EDMA3_NUM_TCC]) (unsigned int tcc, unsigned int status);
/* EDMA callback error function array */
static void (*cb_ErrFxn[EDMA3_NUM_TCC]) (unsigned int tcc, unsigned int status);
static void Edma3CompletionIsr(UArg arg);
static void Edma3CCErrorIsr(UArg arg);

/**
 *  \brief    This function maps the crossbar events. 
 *
 *  \param    baseAdd         It is the Control Module Address.
 *
 *  \param    crossBarEvent   It is the crossBar event number.
 *
 *  \param    Channel         It is the channel number to which cross bar
 *                            event needs to be mapped.
 */

unsigned int EDMA3CrossBarChannelMap(unsigned int baseAdd, unsigned int crossBarEvent,
                                     unsigned int Channel)
{

    unsigned int offset;
    unsigned int select;
    unsigned int n = 0;

    /* offset of the TPCC_MUX to be configured */
    offset = Channel / 4;

    /* 
    ** Each TPCC_MUX register has four event mux which can be used for
    ** cross bar mapping.Thus "select" variable is used to select,
    ** which of the event mux out of four,for a given TPCC_MUX register 
    ** to be used.
    */
    select = Channel - offset * 4;

    switch(select)
    {
         case 0:
              n = 0;
         break;

         case 1:
              n = 8;
         break;

         case 2:
              n = 16;
         break;

         case 3:
              n = 24;
         break;

         default:
         break;
    }
    
    /* 'n' specifies the offset of the event mux */
    HWREG(baseAdd + TPCC_MUX(offset)) &= ~(crossBarEvent << n);

    HWREG(baseAdd + TPCC_MUX(offset)) |= crossBarEvent << n;

    return 0;
}


 /**  
 * \brief  This API returns a unique number which identifies itself  
 *         with the EDMA IP in AM335x SoC.  
 * \param  None  
 * \return This returns a number '2' which is unique to EDMA IP in AM335x.
 */
unsigned int EDMAVersionGet(void)
{
    return 2;
}

/*
** This function enables the system L3 clocks.
** This also enables the clocks for EDMA instance.
*/

void EDMAModuleClkConfig(void)
{
	//GD
	// Verifica per eseguire la funzione una volta sola
	if (EDMA3ClkConfigDone == true)
		return;
	else
		EDMA3ClkConfigDone = true;

	/* Configuring L3 Interface Clocks. */

    /* Writing to MODULEMODE field of CM_PER_L3_CLKCTRL register. */
    HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) |=
          CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE;

    /* Waiting for MODULEMODE field to reflect the written value. */
    while(CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE !=
          (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) &
           CM_PER_L3_CLKCTRL_MODULEMODE));

    /* Writing to MODULEMODE field of CM_PER_L3_INSTR_CLKCTRL register. */
    HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) |=
          CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE;

    /* Waiting for MODULEMODE field to reflect the written value. */
    while(CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE !=
          (HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) &
           CM_PER_L3_INSTR_CLKCTRL_MODULEMODE));

    /* Writing to CLKTRCTRL field of CM_PER_L3_CLKSTCTRL register. */
    HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) |=
          CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    /* Waiting for CLKTRCTRL field to reflect the written value. */
    while(CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
          (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
           CM_PER_L3_CLKSTCTRL_CLKTRCTRL));

    // /* Writing to CLKTRCTRL field of CM_PER_OCPWP_L3_CLKSTCTRL register. */
    // HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) |=
          // CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    // /*Waiting for CLKTRCTRL field to reflect the written value. */
    // while(CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
          // (HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
           // CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL));

    /* Writing to CLKTRCTRL field of CM_PER_L3S_CLKSTCTRL register. */
    HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) |=
          CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    /*Waiting for CLKTRCTRL field to reflect the written value. */
    while(CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
          (HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
           CM_PER_L3S_CLKSTCTRL_CLKTRCTRL));

    /* Checking fields for necessary values.  */

    /* Waiting for IDLEST field in CM_PER_L3_CLKCTRL register to be set to 0x0. */
    while((CM_PER_L3_CLKCTRL_IDLEST_FUNC << CM_PER_L3_CLKCTRL_IDLEST_SHIFT)!=
          (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) &
           CM_PER_L3_CLKCTRL_IDLEST));

    /*
    ** Waiting for IDLEST field in CM_PER_L3_INSTR_CLKCTRL register to attain the
    ** desired value.
    */
    while((CM_PER_L3_INSTR_CLKCTRL_IDLEST_FUNC <<
           CM_PER_L3_INSTR_CLKCTRL_IDLEST_SHIFT)!=
          (HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) &
           CM_PER_L3_INSTR_CLKCTRL_IDLEST));

    /*
    ** Waiting for CLKACTIVITY_L3_GCLK field in CM_PER_L3_CLKSTCTRL register to
    ** attain the desired value.
    */
    while(CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK !=
          (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
           CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK));

    /*
    ** Waiting for CLKACTIVITY_OCPWP_L3_GCLK field in CM_PER_OCPWP_L3_CLKSTCTRL
    ** register to attain the desired value.
    */
    // while(CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK !=
          // (HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
           // CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK));

    /*
    ** Waiting for CLKACTIVITY_L3S_GCLK field in CM_PER_L3S_CLKSTCTRL register
    ** to attain the desired value.
    */
    while(CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK !=
          (HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
          CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK));

    /* Configuring clocks for EDMA3 TPCC and TPTCs. */

    /* Writing to MODULEMODE field of CM_PER_TPCC_CLKCTRL register. */
    HWREG(SOC_CM_PER_REGS + CM_PER_TPCC_CLKCTRL) |=
          CM_PER_TPCC_CLKCTRL_MODULEMODE_ENABLE;

    /* Waiting for MODULEMODE field to reflect the written value. */
    while(CM_PER_TPCC_CLKCTRL_MODULEMODE_ENABLE !=
          (HWREG(SOC_CM_PER_REGS + CM_PER_TPCC_CLKCTRL) &
          CM_PER_TPCC_CLKCTRL_MODULEMODE));

    /* Writing to MODULEMODE field of CM_PER_TPTC0_CLKCTRL register. */
    HWREG(SOC_CM_PER_REGS + CM_PER_TPTC0_CLKCTRL) |=
          CM_PER_TPTC0_CLKCTRL_MODULEMODE_ENABLE;

    /* Waiting for MODULEMODE field to reflect the written value. */
    while(CM_PER_TPTC0_CLKCTRL_MODULEMODE_ENABLE !=
          (HWREG(SOC_CM_PER_REGS + CM_PER_TPTC0_CLKCTRL) &
           CM_PER_TPTC0_CLKCTRL_MODULEMODE));

    /* Writing to MODULEMODE field of CM_PER_TPTC1_CLKCTRL register. */
    HWREG(SOC_CM_PER_REGS + CM_PER_TPTC1_CLKCTRL) |=
          CM_PER_TPTC1_CLKCTRL_MODULEMODE_ENABLE;

    /* Waiting for MODULEMODE field to reflect the written value. */
    while(CM_PER_TPTC1_CLKCTRL_MODULEMODE_ENABLE !=
          (HWREG(SOC_CM_PER_REGS + CM_PER_TPTC1_CLKCTRL) &
           CM_PER_TPTC1_CLKCTRL_MODULEMODE));

    /* Writing to MODULEMODE field of CM_PER_TPTC2_CLKCTRL register. */
    HWREG(SOC_CM_PER_REGS + CM_PER_TPTC2_CLKCTRL) |=
          CM_PER_TPTC2_CLKCTRL_MODULEMODE_ENABLE;

    /* Waiting for MODULEMODE field to reflect the written value. */
    while(CM_PER_TPTC2_CLKCTRL_MODULEMODE_ENABLE !=
          (HWREG(SOC_CM_PER_REGS + CM_PER_TPTC2_CLKCTRL) &
           CM_PER_TPTC2_CLKCTRL_MODULEMODE));

    //GD
    /*	DMA in non-idle mode	*/
    /* Era definito originariamente così:
    	HWREG(0x49800010) = 0x00000028;
    	HWREG(0x49900010) = 0x00000028;
    	HWREG(0x49a00010) = 0x00000028;
    */
    /* !  Il registro 0x10 non era documentato fino alla versione G del Technical Reference Manual
     * Per metterlo in non idle mode - non standby mode il valore è 0x14 ; 0x28 è la modalità smart
     */
	HWREG(0x49800010) = 0x00000014;
	HWREG(0x49900010) = 0x00000014;
	HWREG(0x49a00010) = 0x00000014;
	/* Lamborghini aveva fatto così, ma per includere i define bisogna modificare N files...
    HWREG(SOC_EDMA30TC_0_REGS + EDMA3TC_SYSCONFIG) =
 		   (EDMA3TC_SYSCONFIG_IDLEMODE_NONE << EDMA3TC_SYSCONFIG_IDLEMODE_SHIFT) |
 		   (EDMA3TC_SYSCONFIG_STANDBYMODE_NONE << EDMA3TC_SYSCONFIG_STANDBYMODE_SHIFT);
    HWREG(SOC_EDMA30TC_1_REGS + EDMA3TC_SYSCONFIG) =
 		   (EDMA3TC_SYSCONFIG_IDLEMODE_NONE << EDMA3TC_SYSCONFIG_IDLEMODE_SHIFT) |
 		   (EDMA3TC_SYSCONFIG_STANDBYMODE_NONE << EDMA3TC_SYSCONFIG_STANDBYMODE_SHIFT);
    HWREG(SOC_EDMA30TC_2_REGS + EDMA3TC_SYSCONFIG) =
 		   (EDMA3TC_SYSCONFIG_IDLEMODE_NONE << EDMA3TC_SYSCONFIG_IDLEMODE_SHIFT) |
 		   (EDMA3TC_SYSCONFIG_STANDBYMODE_NONE << EDMA3TC_SYSCONFIG_STANDBYMODE_SHIFT); */

    /*
    ** Waiting for IDLEST field in CM_PER_TPCC_CLKCTRL register to attain the
    ** desired value.
    */
    while((CM_PER_TPCC_CLKCTRL_IDLEST_FUNC <<
           CM_PER_TPCC_CLKCTRL_IDLEST_SHIFT) !=
           (HWREG(SOC_CM_PER_REGS + CM_PER_TPCC_CLKCTRL) &
            CM_PER_TPCC_CLKCTRL_IDLEST));

    /*
    ** Waiting for IDLEST field in CM_PER_TPTC0_CLKCTRL register to attain the
    ** desired value.
    */
    while((CM_PER_TPTC0_CLKCTRL_IDLEST_FUNC <<
           CM_PER_TPTC0_CLKCTRL_IDLEST_SHIFT) !=
           (HWREG(SOC_CM_PER_REGS + CM_PER_TPTC0_CLKCTRL) &
            CM_PER_TPTC0_CLKCTRL_IDLEST));

    /*
    ** Waiting for STBYST field in CM_PER_TPTC0_CLKCTRL register to attain the
    ** desired value.
    */
    while((CM_PER_TPTC0_CLKCTRL_STBYST_FUNC <<
           CM_PER_TPTC0_CLKCTRL_STBYST_SHIFT) !=
           (HWREG(SOC_CM_PER_REGS + CM_PER_TPTC0_CLKCTRL) &
            CM_PER_TPTC0_CLKCTRL_STBYST));

    /*
    ** Waiting for IDLEST field in CM_PER_TPTC1_CLKCTRL register to attain the
    ** desired value.
    */
    while((CM_PER_TPTC1_CLKCTRL_IDLEST_FUNC <<
           CM_PER_TPTC1_CLKCTRL_IDLEST_SHIFT) !=
           (HWREG(SOC_CM_PER_REGS + CM_PER_TPTC1_CLKCTRL) &
            CM_PER_TPTC1_CLKCTRL_IDLEST));

    /*
    ** Waiting for STBYST field in CM_PER_TPTC1_CLKCTRL register to attain the
    ** desired value.
    */
    while((CM_PER_TPTC1_CLKCTRL_STBYST_FUNC <<
           CM_PER_TPTC1_CLKCTRL_STBYST_SHIFT) !=
           (HWREG(SOC_CM_PER_REGS + CM_PER_TPTC1_CLKCTRL) &
            CM_PER_TPTC1_CLKCTRL_STBYST));

    /*
    ** Waiting for IDLEST field in CM_PER_TPTC2_CLKCTRL register to attain the
    ** desired value.
    */
    while((CM_PER_TPTC2_CLKCTRL_IDLEST_FUNC <<
           CM_PER_TPTC2_CLKCTRL_IDLEST_SHIFT) !=
           (HWREG(SOC_CM_PER_REGS + CM_PER_TPTC2_CLKCTRL) &
            CM_PER_TPTC2_CLKCTRL_IDLEST));

    /*
    ** Waiting for STBYST field in CM_PER_TPTC2_CLKCTRL register to attain the
    ** desired value.
    */
    while((CM_PER_TPTC2_CLKCTRL_STBYST_FUNC <<
           CM_PER_TPTC2_CLKCTRL_STBYST_SHIFT) !=
           (HWREG(SOC_CM_PER_REGS + CM_PER_TPTC2_CLKCTRL) &
            CM_PER_TPTC2_CLKCTRL_STBYST));
}

/******************************************************************************/
//GD
// Da qui in poi ci sono funzioni che negli esempi erano a livello applicativo.
// Sono state spostate qui in modo da rendere il DMA accessibile in maniera ordinata
// da diversi punti del software.
/******************************************************************************/

/******************************************************************************/
/*
** This function configures EDMA3 interrupts.
*/
int EDMA3IntConfigure(void)
{
    Hwi_Params hwiParams;
    Hwi_Handle hwiHandle;
    Error_Block eb;

	//GD
	// Verifica per eseguire la funzione una volta sola
	if (EDMA3IntConfigDone == true)
		return 0;	// Non si ritorna in ogni caso un errore perchè potrebbe esserci più di un'inizializzazione
	else
		EDMA3IntConfigDone = true;

	/*Parametri dell' EDMA3 transfer completion int*/
    Hwi_Params_init(&hwiParams);
    hwiParams.arg = SYS_INT_EDMACOMPINT;
    hwiParams.priority = SYS_INT_EDMACOMPINT;
    hwiParams.enableInt = false;
    Error_init(&eb);

    /* Registrazione dell' EDMA3 Channel Controller transfer completion interrupt.  */
    hwiHandle = Hwi_create(SYS_INT_EDMACOMPINT, Edma3CompletionIsr, &hwiParams, &eb);
    if (Error_check(&eb) || (hwiHandle == NULL))
    {
    	return -1;
    }

    /*Parametri dell' EDMA3 error int*/
    Hwi_Params_init(&hwiParams);
    hwiParams.arg = SYS_INT_EDMAERRINT;
    hwiParams.priority = SYS_INT_EDMAERRINT;
    hwiParams.enableInt = false;
    Error_init(&eb);

    /* Registrazione dell' EDMA3 Channel Controller Error Interrupt.   */
    hwiHandle = Hwi_create(SYS_INT_EDMAERRINT, Edma3CCErrorIsr, &hwiParams, &eb);
    if (Error_check(&eb) || (hwiHandle == NULL))
    {
    	return -1;
    }

    /* Abilitazione del completion interrupt ed error interrupt*/
    Hwi_enableInterrupt(SYS_INT_EDMACOMPINT);
    Hwi_enableInterrupt(SYS_INT_EDMAERRINT);

    return 0;
}

/******************************************************************************/
/*
** Inizializza il puntatore a funzione della callback realtiva al canale specificato
*/
void EDMA_RegisterCallback( void (*cbf)(unsigned int tcc, unsigned int status), unsigned short Channel )
{
	if (Channel< EDMA3_NUM_TCC)
	{
		cb_Fxn[Channel] = cbf;
	}
	else
	{
		/* Todo: Errore da gestire */
		while (1);
	}
}

/******************************************************************************/
/*
** Inizializza il puntatore a funzione della callback per gestioni d'errore realtiva al canale specificato
*/
void EDMA_RegisterErrorCallback( void (*cbf)(unsigned int tcc, unsigned int status), unsigned short Channel )
{
	if (Channel< EDMA3_NUM_TCC)
	{
		cb_ErrFxn[Channel] = cbf;
	}
	else
	{
		/* Todo: Errore da gestire */
		while (1);
	}
}

/******************************************************************************/
/*
** Transfer Completion ISR
*/
static void Edma3CompletionIsr(UArg arg)
{
    volatile unsigned int pendingIrqs_l;
    volatile unsigned int pendingIrqs_h;
    volatile unsigned int isIPR_l = 0;
    volatile unsigned int isIPR_h = 0;

    unsigned int indexl;
    unsigned int Cnt = 0;

    indexl = 1;

	isIPR_l = EDMA3GetIntrStatus(SOC_EDMA30CC_0_REGS);
    isIPR_h = EDMA3IntrStatusHighGet(SOC_EDMA30CC_0_REGS);

    if ((isIPR_l != 0) || (isIPR_h != 0))
    {
        while ((Cnt < EDMA3CC_COMPL_HANDLER_RETRY_COUNT)&& (indexl != 0u))
        {
            indexl = 0u;

            pendingIrqs_l = EDMA3GetIntrStatus(SOC_EDMA30CC_0_REGS);
            pendingIrqs_h = EDMA3IntrStatusHighGet(SOC_EDMA30CC_0_REGS);
            while ((pendingIrqs_l!=0) ||(pendingIrqs_h!=0))
            {
            	// Controllo i canali 0-31
                if((pendingIrqs_l & 1u) == TRUE)
                {
                    /**
                    * If the user has not given any callback function
                    * while requesting the TCC, its TCC specific bit
                    * in the IPR register will NOT be cleared.
                    */
                    /* here write to ICR to clear the corresponding IPR bits */

                    EDMA3ClrIntr(SOC_EDMA30CC_0_REGS, indexl);

                    if (cb_Fxn[indexl] != NULL)
                    {
                    	(*cb_Fxn[indexl])(indexl, EDMA3_XFER_COMPLETE);
                    }
                }
                pendingIrqs_l >>= 1u;

            	// Controllo i canali 32-63
                if((pendingIrqs_h & 1u) == TRUE)
                {
                    /**
                    * If the user has not given any callback function
                    * while requesting the TCC, its TCC specific bit
                    * in the IPR register will NOT be cleared.
                    */
                    /* here write to ICR to clear the corresponding IPR bits */

                    EDMA3ClrIntr(SOC_EDMA30CC_0_REGS, 32+indexl);

                    if (cb_Fxn[32+indexl] != NULL)
                    {
                        (*cb_Fxn[32+indexl])(32+indexl, EDMA3_XFER_COMPLETE);
                    }
                }
                pendingIrqs_h >>= 1u;


                ++indexl;
           }
           Cnt++;
        }
    }
}

/******************************************************************************/
/*
** Transfer Error ISR
*/
static void Edma3CCErrorIsr(UArg arg)
{
    volatile unsigned int pendingIrqs = 0;
    unsigned int evtqueNum = 0;
    unsigned int index = 1;
    unsigned int Cnt = 0;


    if((0 != EDMA3GetErrIntrStatus(SOC_EDMA30CC_0_REGS)) ||
	   (0 != EDMA3ErrIntrHighStatusGet(SOC_EDMA30CC_0_REGS)) ||
       (0 != EDMA3QdmaGetErrIntrStatus(SOC_EDMA30CC_0_REGS)) ||	//aggiunto perchè serve al profibus
       (0 != (EDMA3GetCCErrStatus(SOC_EDMA30CC_0_REGS))))
    {
        /* Loop for EDMA3CC_ERR_HANDLER_RETRY_COUNT number of time, breaks
           when no pending interrupt is found */
        while ((Cnt < EDMA3CC_ERR_HANDLER_RETRY_COUNT) && (index != 0u))
        {
            //==== SCANDISCE LA WORD BASSA ====
        	index = 0u;
            pendingIrqs = EDMA3GetErrIntrStatus(SOC_EDMA30CC_0_REGS);

            while (pendingIrqs)
            {
                /*Process all the pending interrupts*/
                if((pendingIrqs & 1u)==TRUE)
                {
                    /* Writing to EMCR to clear the corresponding EMR bits.
                       Also clearing any Secondary events in SER. */
                    EDMA3ClrMissEvt(SOC_EDMA30CC_0_REGS, index);

                    if (cb_ErrFxn[index] != NULL)
                    {
                    	(*cb_ErrFxn[index])(index, EDMA3_CC_DMA_EVT_MISS);
                    }
                }
                ++index;
                pendingIrqs >>= 1u;
            }

            //==== SCANDISCE LA WORD ALTA ====
            index = 32u;
            pendingIrqs = EDMA3ErrIntrHighStatusGet(SOC_EDMA30CC_0_REGS);

            while (pendingIrqs)
            {
                /*Process all the pending interrupts*/
                if((pendingIrqs & 1u)==TRUE)
                {
                    /* Writing to EMCR to clear the corresponding EMR bits.
                       Also clearing any Secondary events in SER. */
                    EDMA3ClrMissEvt(SOC_EDMA30CC_0_REGS, index);

                    if (cb_ErrFxn[index] != NULL)
                    {
                        (*cb_ErrFxn[index])(index, EDMA3_CC_DMA_EVT_MISS);
                    }
                }
                ++index;
                pendingIrqs >>= 1u;
            }

            //====  ====
            index = 0u;
            pendingIrqs = EDMA3GetCCErrStatus(SOC_EDMA30CC_0_REGS);
            if (pendingIrqs != 0u)
            {
                /* Process all the pending CC error interrupts. */
                /* Queue threshold error for different event queues. */
                for (evtqueNum = 0u; evtqueNum < EDMA3_0_NUM_EVTQUE; evtqueNum++)
                {
                    if((pendingIrqs & (1u << evtqueNum)) != 0u)
                    {
                        /* Clear the error interrupt. */
                        EDMA3ClrCCErr(SOC_EDMA30CC_0_REGS, (1u << evtqueNum));
                    }
                }

                /* Transfer completion code error. */
                if ((pendingIrqs & (1 << EDMA3CC_CCERR_TCCERR_SHIFT)) != 0u)
                {
                    EDMA3ClrCCErr(SOC_EDMA30CC_0_REGS,
                                  (0x01u << EDMA3CC_CCERR_TCCERR_SHIFT));
                }
                ++index;
            }

            Cnt++;
        }

        /* Enable error to be evaluated again */
        EDMA3CCErrorEvaluate(SOC_EDMA30CC_0_REGS);
    }

}

