/**
* @file pruss_register.h
*
* @brief Contains PRUSS register macros
*
* \par
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
* \par
*/
#ifndef _PRUSS_REGISTER_H_
#define _PRUSS_REGISTER_H_

/**
* @def PRUSS_BASE
*      PRUSS Base Address
*/
#define PRUSS_BASE		0x4a300000
/**
* @def PRUSS_INTC
*      PRUSS INTC Offset
*/
#define	PRUSS_INTC			0x20000
/**
* @def PRUSS_PRU0_CTRL
*      PRU0 Control Register Offset
*/
#define	PRUSS_PRU0_CTRL		0x22000
/**
* @def PRUSS_PRU1_CTRL
*      PRU1 Control Register Offset
*/
#define	PRUSS_PRU1_CTRL		0x24000
/**
* @def PRUSS_CFG
*      PRUSS Config register Offset
*/
/**PRUSS Config register Offset*/
#define PRUSS_CFG			0x26000
/**
* @def PRUSS_MII_RT_CFG
*      PRUSS MII RT CFG Offset
*/
#define PRUSS_MII_RT_CFG	0x32000

/*
 * INTC registers
 */
/**
* @def INTC_SECR0
*      System Interrupt Statues Enabled/Clear Register 1 offset
*/
#define INTC_SECR0		0x280
/**
* @def INTC_SECR1
*      System Interrupt Statues Enabled/Clear Register 2 offset
*/
#define INTC_SECR1		0x284


/*
 * PRU Control
 */
/**
* @def PRUSS_PRU0_CTRL_CONTROL
*      PRU0 PDSP Control Register Offset
*/
#define PRUSS_PRU0_CTRL_CONTROL		(PRUSS_PRU0_CTRL + 0x00)
/**
* @def PRUSS_PRU0_CTRL_STATUS
*      PRU0 PDSP Status Register Offset
*/
#define PRUSS_PRU0_CTRL_STATUS		(PRUSS_PRU0_CTRL + 0x04)
/**
* @def PRUSS_PRU0_CTRL_WAKEUP_EN
*      PRU0 PDSP Wakeup Enable Register Offset
*/
#define PRUSS_PRU0_CTRL_WAKEUP_EN	(PRUSS_PRU0_CTRL + 0x08)
/**
* @def PRUSS_PRU0_CTRL_CYCLE
*      PRU0 PDSP Cycle Count Register Offset
*/
#define PRUSS_PRU0_CTRL_CYCLE		(PRUSS_PRU0_CTRL + 0x0C)
/**
* @def PRUSS_PRU0_CTRL_STALL
*      PRU0 PDSP Stall Count Register Offset
*/
#define PRUSS_PRU0_CTRL_STALL		(PRUSS_PRU0_CTRL + 0x10)
/**
* @def PRUSS_PRU0_CTRL_CTBIR0
*      PRU0 PDSP Constant Table Block Index0 Register Offset
*/
#define PRUSS_PRU0_CTRL_CTBIR0		(PRUSS_PRU0_CTRL + 0x20)
/**
* @def PRUSS_PRU0_CTRL_CTBIR1
*      PRU0 PDSP Constant Table Block Index1 Register Offset
*/
#define PRUSS_PRU0_CTRL_CTBIR1		(PRUSS_PRU0_CTRL + 0x24)
/**
* @def PRUSS_PRU0_CTRL_CTPPR0
*      PRU0 PDSP Constant Table Programmable Pointer  Register0 Offset
*/
#define PRUSS_PRU0_CTRL_CTPPR0		(PRUSS_PRU0_CTRL + 0x28)
/**
* @def PRUSS_PRU0_CTRL_CTPPR1
*      PRU0 PDSP Constant Table Programmable Pointer  Register1 Offset
*/
#define PRUSS_PRU0_CTRL_CTPPR1		(PRUSS_PRU0_CTRL + 0x2C)
/**
* @def PRUSS_PRU1_CTRL_CONTROL
*      PRU1 PDSP Control Register Offset
*/
#define PRUSS_PRU1_CTRL_CONTROL		(PRUSS_PRU1_CTRL + 0x00)
/**
* @def PRUSS_PRU1_CTRL_STATUS
*      PRU1 PDSP Status Register Offset
*/
#define PRUSS_PRU1_CTRL_STATUS		(PRUSS_PRU1_CTRL + 0x04)
/**
* @def PRUSS_PRU1_CTRL_WAKEUP_EN
*      PRU1 PDSP Wakeup Enable Register Offset
*/
#define PRUSS_PRU1_CTRL_WAKEUP_EN	(PRUSS_PRU1_CTRL + 0x08)
/**
* @def PRUSS_PRU1_CTRL_CYCLE
*      PRU1 PDSP Cycle Count Register Offset
*/
#define PRUSS_PRU1_CTRL_CYCLE		(PRUSS_PRU1_CTRL + 0x0C)
/**
* @def PRUSS_PRU1_CTRL_STALL
*      PRU1 PDSP Stall Count Register Offset
*/
#define PRUSS_PRU1_CTRL_STALL		(PRUSS_PRU1_CTRL + 0x10)
/**
* @def PRUSS_PRU1_CTRL_CTBIR0
*      PRU1 PDSP Constant Table Block Index0 Register Offset
*/
#define PRUSS_PRU1_CTRL_CTBIR0		(PRUSS_PRU1_CTRL + 0x20)
/**
* @def PRUSS_PRU1_CTRL_CTBIR1
*      PRU1 PDSP Constant Table Block Index1 Register Offset
*/
#define PRUSS_PRU1_CTRL_CTBIR1		(PRUSS_PRU1_CTRL + 0x24)
/**
* @def PRUSS_PRU1_CTRL_CTPPR0
*      PRU1 PDSP Constant Table Programmable Pointer  Register0 Offset
*/
#define PRUSS_PRU1_CTRL_CTPPR0		(PRUSS_PRU1_CTRL + 0x28)
/**
* @def PRUSS_PRU1_CTRL_CTPPR1
*      PRU1 PDSP Constant Table Programmable Pointer  Register1 Offset
*/
#define PRUSS_PRU1_CTRL_CTPPR1		(PRUSS_PRU1_CTRL + 0x2C)



/*
 * CFG Register
 */
/**
* @def PRUSS_CFG_REVID
*      PRUSS CFG Register Revision Offset
*/
#define PRUSS_CFG_REVID		(PRUSS_CFG + 0x00)
/**
* @def PRUSS_CFG_SYSCFG
*      PRUSS CFG Register Syscfg Offset
*/
#define PRUSS_CFG_SYSCFG	(PRUSS_CFG + 0x04)
/**
* @def PRUSS_CFG_GPCFG0
*      PRUSS CFG Register GPConfiguration0 Offset
*/
#define PRUSS_CFG_GPCFG0	(PRUSS_CFG + 0x08)
/**
* @def PRUSS_CFG_GPCFG1
*      PRUSS CFG Register GPConfiguration1 Offset
*/
#define PRUSS_CFG_GPCFG1	(PRUSS_CFG + 0x0C)
/**
* @def PRUSS_CFG_CGR
*      PRUSS CFG Register Clock gating Offset
*/
#define PRUSS_CFG_CGR		(PRUSS_CFG + 0x10)
/**
* @def PRUSS_CFG_ISRP
*      PRUSS CFG Register IRQ  Status Raw Parity Offset
*/
#define PRUSS_CFG_ISRP		(PRUSS_CFG + 0x14)
/**
* @def PRUSS_CFG_ISP
*      PRUSS CFG Register IRQ  Status Parity Offset
*/
#define PRUSS_CFG_ISP		(PRUSS_CFG + 0x18)
/**
* @def PRUSS_CFG_IESP
*      PRUSS CFG Register IRQ  Enable  set Parity Offset
*/
#define PRUSS_CFG_IESP		(PRUSS_CFG + 0x1C)
/**
* @def PRUSS_CFG_IECP
*      PRUSS CFG Register IRQ  Clear  set Parity Offset
*/
#define PRUSS_CFG_IECP		(PRUSS_CFG + 0x20)
/**
* @def PRUSS_CFG_SCRP
*      PRUSS CFG Register SCRP Offset
*/
#define PRUSS_CFG_SCRP		(PRUSS_CFG + 0x24)
/**
* @def PRUSS_CFG_PMAO
*      PRUSS CFG Register PRU Master OCP Address Offset
*/
#define PRUSS_CFG_PMAO		(PRUSS_CFG + 0x28)
/**
* @def PRUSS_CFG_MII_RT
*      PRUSS CFG Register MIIRT Event Enable Offset
*/
#define PRUSS_CFG_MII_RT	(PRUSS_CFG + 0x2C)
/**
* @def PRUSS_CFG_IEPCLK
*      PRUSS CFG Register IEP Clock Source Offset
*/
#define PRUSS_CFG_IEPCLK	(PRUSS_CFG + 0x30)
/**
* @def PRUSS_CFG_SPP
*      PRUSS CFG Register Scratchpad priority and config Offset
*/
#define PRUSS_CFG_SPP		(PRUSS_CFG + 0x34)
/**
* @def PRUSS_CFG_PIN_MX
*      PRUSS CFG Register SA Mux Select Offset
*/
#define PRUSS_CFG_PIN_MX	(PRUSS_CFG + 0x40)

/*
 * MII_RT_CFG
 */
/**
* @def PRUSS_MII_RT_CFG_RXCFG0
*      PRUSS PRU0 MII RT RXCFG
*/
#define PRUSS_MII_RT_CFG_RXCFG0		(PRUSS_MII_RT_CFG + 0x00)
/**
* @def PRUSS_MII_RT_CFG_RXCFG1
*      PRUSS PRU1 MII RT RXCFG
*/
#define PRUSS_MII_RT_CFG_RXCFG1		(PRUSS_MII_RT_CFG + 0x04)
/**
* @def PRUSS_MII_RT_CFG_TXCFG0
*      PRUSS PRU0 MII RT TXCFG
*/
#define PRUSS_MII_RT_CFG_TXCFG0		(PRUSS_MII_RT_CFG + 0x10)
/**
* @def PRUSS_MII_RT_CFG_TXCFG1
*      PRUSS PRU1 MII RT TXCFG
*/
#define PRUSS_MII_RT_CFG_TXCFG1		(PRUSS_MII_RT_CFG + 0x14)
/**
* @def PRUSS_MII_RT_CFG_TXCRC0
*      PRUSS PRU0 MII RT TXCRC
*/
#define PRUSS_MII_RT_CFG_TXCRC0		(PRUSS_MII_RT_CFG + 0x20)
/**
* @def PRUSS_MII_RT_CFG_TXCRC1
*      PRUSS PRU1 MII RT TXCRC
*/
#define PRUSS_MII_RT_CFG_TXCRC1		(PRUSS_MII_RT_CFG + 0x24)
/**
* @def PRUSS_MII_RT_CFG_TXIPG0
*      PRUSS PRU0 MII RT TXIPG
*/
#define PRUSS_MII_RT_CFG_TXIPG0		(PRUSS_MII_RT_CFG + 0x30)
/**
* @def PRUSS_MII_RT_CFG_TXIPG1
*      PRUSS PRU1 MII RT TXIPG
*/
#define PRUSS_MII_RT_CFG_TXIPG1		(PRUSS_MII_RT_CFG + 0x34)
/**
* @def PRUSS_MII_RT_CFG_PRS0
*      PRUSS PRU0 MII RT Port Raw Status
*/
#define PRUSS_MII_RT_CFG_PRS0		(PRUSS_MII_RT_CFG + 0x38)
/**
* @def PRUSS_MII_RT_CFG_PRS1
*      PRUSS PRU1 MII RT Port Raw Status
*/
#define PRUSS_MII_RT_CFG_PRS1		(PRUSS_MII_RT_CFG + 0x3C)
/**
* @def PRUSS_MII_RT_CFG_RXFRMS0
*      PRUSS PRU0 MII RT Rx Frame Size
*/
#define PRUSS_MII_RT_CFG_RXFRMS0	(PRUSS_MII_RT_CFG + 0x40)
/**
* @def PRUSS_MII_RT_CFG_RXFRMS1
*      PRUSS PRU1 MII RT Rx Frame Size
*/
#define PRUSS_MII_RT_CFG_RXFRMS1	(PRUSS_MII_RT_CFG + 0x44)
/**
* @def PRUSS_MII_RT_CFG_RXPCNT0
*     PRUSS PRU0 MII RT Rx Preamble Count
*/
#define PRUSS_MII_RT_CFG_RXPCNT0	(PRUSS_MII_RT_CFG + 0x48)
/**
* @def PRUSS_MII_RT_CFG_RXPCNT1
*      PRUSS PRU1 MII RT Rx Preamble Count
*/
#define PRUSS_MII_RT_CFG_RXPCNT1	(PRUSS_MII_RT_CFG + 0x4C)
/**
* @def PRUSS_MII_RT_CFG_RXERR0
*      PRUSS PRU0 MII RT Rx Error
*/
#define PRUSS_MII_RT_CFG_RXERR0		(PRUSS_MII_RT_CFG + 0x50)
/**
* @def PRUSS_MII_RT_CFG_RXERR1
*      PRUSS PRU1 MII RT Rx Error
*/
#define PRUSS_MII_RT_CFG_RXERR1		(PRUSS_MII_RT_CFG + 0x54)



/* SYSCFG */
#define PRUSS_SYSCFG_SUB_MWAIT_READY	0
#define PRUSS_SYSCFG_SUB_MWAIT_WAIT		1
#define PRUSS_SYSCFG_SUB_MWAIT_SHIFT	5

#define PRUSS_SYSCFG_STANDBY_INIT_STANDBY	1
#define PRUSS_SYSCFG_STANDBY_INIT_ENABLE	0
#define PRUSS_SYSCFG_STANDBY_INIT_SHIFT		4

#define PRUSS_SYSCFG_STANDBY_MODE_FORCE		0
#define PRUSS_SYSCFG_STANDBY_MODE_NO		1
#define PRUSS_SYSCFG_STANDBY_MODE_SMART		2
#define PRUSS_SYSCFG_STANDBY_MODE_SHIFT		2

#define PRUSS_SYSCFG_IDLE_MODE_FORCE		0
#define PRUSS_SYSCFG_IDLE_MODE_NO			1
#define PRUSS_SYSCFG_IDLE_MODE_SMART		2
#define PRUSS_SYSCFG_IDLE_MODE_SHIFT		0

/* GPCFG0 */
#define PRUSS_GPCFG0_PRU0_GPO_SH_SEL_SH0	0
#define PRUSS_GPCFG0_PRU0_GPO_SH_SEL_SH1	1
#define PRUSS_GPCFG0_PRU0_GPO_SH_SEL_SHIFT	25

#define PRUSS_GPCFG0_PRU0_DIV1_SHIFT		20

#define PRUSS_GPCFG0_PRU0_DIV0_SHIFT		15

#define PRUSS_GPCFG0_PRU0_GPO_MODE_DIRECT	0
#define PRUSS_GPCFG0_PRU0_GPO_MODE_SERIAL	1
#define PRUSS_GPCFG0_PRU0_GPO_MODE_SHIFT	14

#define PRUSS_GPCFG0_PRU0_GPI_SB_SHIFT		13

#define PRUSS_GPCFG0_PRU0_GPI_DIV1_SHIFT	8

#define PRUSS_GPCFG0_PRU0_GPI_DIV0_SHIFT	3

#define PRUSS_GPCFG0_PRU0_GPI_CLK_MODE_POSITIVE		0
#define PRUSS_GPCFG0_PRU0_GPI_CLK_MODE_NEGATIVE		1
#define PRUSS_GPCFG0_PRU0_GPI_CLK_MODE_SHIFT		2

#define PRUSS_GPCFG0_PRU0_GPI_MODE_DIRECTMODE		0
#define PRUSS_GPCFG0_PRU0_GPI_MODE_PARALLELMODE 	1
#define PRUSS_GPCFG0_PRU0_GPI_MODE_SHIFTMODE 		2
#define PRUSS_GPCFG0_PRU0_GPI_MODE_MIIMODE			3
#define PRUSS_GPCFG0_PRU0_GPI_MODE_SHIFT			0

/* GPCFG1 */
#define PRUSS_GPCFG1_PRU1_GPO_SH_SEL_SH0	0
#define PRUSS_GPCFG1_PRU1_GPO_SH_SEL_SH1	1
#define PRUSS_GPCFG1_PRU1_GPO_SH_SEL_SHIFT	25

#define PRUSS_GPCFG1_PRU1_DIV1_SHIFT		20

#define PRUSS_GPCFG1_PRU1_DIV0_SHIFT		15

#define PRUSS_GPCFG1_PRU1_GPO_MODE_DIRECT	0
#define PRUSS_GPCFG1_PRU1_GPO_MODE_SERIAL	1
#define PRUSS_GPCFG1_PRU1_GPO_MODE_SHIFT	14

#define PRUSS_GPCFG1_PRU1_GPI_SB_SHIFT		13

#define PRUSS_GPCFG1_PRU1_GPI_DIV1_SHIFT	8

#define PRUSS_GPCFG1_PRU1_GPI_DIV0_SHIFT	3

#define PRUSS_GPCFG1_PRU1_GPI_CLK_MODE_POSITIVE		0
#define PRUSS_GPCFG1_PRU1_GPI_CLK_MODE_NEGATIVE		1
#define PRUSS_GPCFG1_PRU1_GPI_CLK_MODE_SHIFT		2

#define PRUSS_GPCFG1_PRU1_GPI_MODE_DIRECTMODE		0
#define PRUSS_GPCFG1_PRU1_GPI_MODE_PARALLELMODE 	1
#define PRUSS_GPCFG1_PRU1_GPI_MODE_SHIFTMODE 		2
#define PRUSS_GPCFG1_PRU1_GPI_MODE_MIIMODE			3
#define PRUSS_GPCFG1_PRU1_GPI_MODE_SHIFT			0

/* CGR */
#define PRUSS_CGR_IEP_CLK_EN_DISABLE	0
#define PRUSS_CGR_IEP_CLK_EN_ENABLE		1
#define PRUSS_CGR_IEP_CLK_EN_SHIFT		17

#define PRUSS_CGR_IEP_CLK_STOP_ACK_NOTREADY		0
#define PRUSS_CGR_IEP_CLK_STOP_ACK_READY		1
#define PRUSS_CGR_IEP_CLK_STOP_ACK_SHIFT		16

#define PRUSS_CGR_IEP_CLK_STOP_REQ_NOTREQUEST	0
#define PRUSS_CGR_IEP_CLK_STOP_REQ_REQUEST		1
#define PRUSS_CGR_IEP_CLK_STOP_REQ_SHIFT		15

#define PRUSS_CGR_ECAP_CLK_EN_DISABLE	0
#define PRUSS_CGR_ECAP_CLK_EN_ENABLE	1
#define PRUSS_CGR_ECAP_CLK_EN_SHIFT		14

#define PRUSS_CGR_ECAP_CLK_STOP_ACK_NOTREADY	0
#define PRUSS_CGR_ECAP_CLK_STOP_ACK_READY		1
#define PRUSS_CGR_ECAP_CLK_STOP_ACK_SHIFT		13

#define PRUSS_CGR_ECAP_CLK_STOP_REQ_NOTREADY	0
#define PRUSS_CGR_ECAP_CLK_STOP_REQ_READY		1
#define PRUSS_CGR_ECAP_CLK_STOP_REQ_SHIFT		12

#define PRUSS_CGR_UART_CLK_EN_DISABLE	0
#define PRUSS_CGR_UART_CLK_EN_ENABLE	1
#define PRUSS_CGR_UART_CLK_EN_SHIFT		11

#define PRUSS_CGR_UART_CLK_STOP_ACK_NOTREADY	0
#define PRUSS_CGR_UART_CLK_STOP_ACK_READY		1
#define PRUSS_CGR_UART_CLK_STOP_ACK_SHIFT		10

#define PRUSS_CGR_UART_CLK_STOP_REQ_NOTREADY	0
#define PRUSS_CGR_UART_CLK_STOP_REQ_READY		1
#define PRUSS_CGR_UART_CLK_STOP_REQ_SHIFT		9

#define PRUSS_CGR_INTC_CLK_EN_DISABLE	0
#define PRUSS_CGR_INTC_CLK_EN_ENABLE	1
#define PRUSS_CGR_INTC_CLK_EN_SHIFT		8

#define PRUSS_CGR_INTC_CLK_STOP_ACK_NOTREADY	0
#define PRUSS_CGR_INTC_CLK_STOP_ACK_READY		1
#define PRUSS_CGR_INTC_CLK_STOP_ACK_SHIFT		7

#define PRUSS_CGR_INTC_CLK_STOP_REQ_NOTREADY	0
#define PRUSS_CGR_INTC_CLK_STOP_REQ_READY		1
#define PRUSS_CGR_INTC_CLK_STOP_REQ_SHIFT		6

#define PRUSS_CGR_PRU1_CLK_EN_DISABLE	0
#define PRUSS_CGR_PRU1_CLK_EN_ENABLE	1
#define PRUSS_CGR_PRU1_CLK_EN_SHIFT		5

#define PRUSS_CGR_PRU1_CLK_STOP_ACK_NOTREADY	0
#define PRUSS_CGR_PRU1_CLK_STOP_ACK_READY		1
#define PRUSS_CGR_PRU1_CLK_STOP_ACK_SHIFT		4

#define PRUSS_CGR_PRU1_CLK_STOP_REQ_NOTREADY	0
#define PRUSS_CGR_PRU1_CLK_STOP_REQ_READY		1
#define PRUSS_CGR_PRU1_CLK_STOP_REQ_SHIFT		3

#define PRUSS_CGR_PRU0_CLK_EN_DISABLE	0
#define PRUSS_CGR_PRU0_CLK_EN_ENABLE	1
#define PRUSS_CGR_PRU0_CLK_EN_SHIFT		2

#define PRUSS_CGR_PRU0_CLK_STOP_ACK_NOTREADY	0
#define PRUSS_CGR_PRU0_CLK_STOP_ACK_READY		1
#define PRUSS_CGR_PRU0_CLK_STOP_ACK_SHIFT		1

#define PRUSS_CGR_PRU0_CLK_STOP_REQ_NOTREADY	0
#define PRUSS_CGR_PRU0_CLK_STOP_REQ_READY		1
#define PRUSS_CGR_PRU0_CLK_STOP_REQ_SHIFT		0

/* ISRP */
#define PRUSS_ISRP_RAM_PE_RAW_SHIFT			16
#define PRUSS_ISRP_PRU1_DMEM_PE_RAW_SHIFT	12
#define PRUSS_ISRP_PRU1_IMEM_PE_RAW_SHIFT	8
#define PRUSS_ISRP_PRU0_DMAM_PE_RAW_SHIFT	4
#define PRUSS_ISRP_PRU0_IMEM_PE_RAW_SHIFT	0

/* ISP */
#define PRUSS_ISP_RAM_PE_SHIFT			16
#define PRUSS_ISP_PRU1_DRAM_PE_SHIFT	12
#define PRUSS_ISP_PRU1_IMEM_PE_SHIFT	8
#define PRUSS_ISP_PRU0_DMEM_PE_SHIFT	4
#define PRUSS_ISP_PRU0_IMEM_PE_SHIFT	0

/* IESP */
#define PRUSS_IESP_RAM_PE_SET_SHIFT			16
#define PRUSS_IESP_PRU1_DRAM_PE_SET_SHIFT	12
#define PRUSS_IESP_PRU1_IMEM_PE_SET_SHIFT	8
#define PRUSS_IESP_PRU0_DMEM_PE_SET_SHIFT	4
#define PRUSS_IESP_PRU0_IMEM_PE_SET_SHIFT	0

/* IECP */
#define PRUSS_IECP_RAM_PE_CLR_SHIFT			16
#define PRUSS_IECP_PRU1_DRAM_PE_CLR_SHIFT	12
#define PRUSS_IECP_PRU1_IMEM_PE_CLR_SHIFT	8
#define PRUSS_IECP_PRU0_DMEM_PE_CLR_SHIFT	4
#define PRUSS_IECP_PRU0_IMEM_PE_CLR_SHIFT	0

/* SCRP */
#define PRUSS_SCRP_18_SHIFT		21
#define PRUSS_SCRP_17_SHIFT		20
#define PRUSS_SCRP_16_SHIFT		19
#define PRUSS_SCRP_15_SHIFT		18
#define PRUSS_SCRP_14_SHIFT		17
#define PRUSS_SCRP_13_SHIFT		16
#define PRUSS_SCRP_12_SHIFT		15
#define PRUSS_SCRP_11_SHIFT		14
#define PRUSS_SCRP_10_SHIFT		13
#define PRUSS_SCRP_9_SHIFT		12
#define PRUSS_SCRP_8_SHIFT		11
#define PRUSS_SCRP_7_SHIFT		10
#define PRUSS_SCRP_6_SHIFT		9
#define PRUSS_SCRP_5_SHIFT		8
#define PRUSS_SCRP_4_SHIFT		6
#define PRUSS_SCRP_3_SHIFT		4
#define PRUSS_SCRP_2_SHIFT		2
#define PRUSS_SCRP_1_SHIFT		0

/* PMAO */
#define PRUSS_PMAO_PRU1_DISABLE	0
#define PRUSS_PMAO_PRU1_ENABLE		1
#define PRUSS_PMAO_PRU1_SHIFT		1

#define PRUSS_PMAO_PRU0_DISABLE	0
#define PRUSS_PMAO_PRU0_ENABLE		1
#define PRUSS_PMAO_PRU0_SHIFT		0

/* MII_RT */
#define PRUSS_MII_RT_EVENT_EN_DISABLE	0
#define PRUSS_MII_RT_EVENT_EN_ENABLE	1
#define PRUSS_MII_RT_EVENT_EN_SHIFT		0

/* IEPCLK */
#define PRUSS_IEPCLK_OCP_EN_IEPCLK		0
#define PRUSS_IEPCLK_OCP_EN_OCPCLK		1
#define PRUSS_IEPCLK_OCP_EN_SHIFT		0

/* SPP */
#define PRUSS_SPP_XFER_SHIFT_EN_DISABLE		0
#define PRUSS_SPP_XFER_SHIFT_EN_ENABLE		1
#define PRUSS_SPP_XFER_SHIFT_EN_SHIFT		1

#define PRUSS_SPP_PRU1_PAD_HP_EN_PRU0		0
#define PRUSS_SPP_PRU1_PAD_HP_EN_PRU1		1
#define PRUSS_SPP_PRU1_PAD_HP_EN_SHIFT		0

/* PIN_MX */
#define PRUSS_PIN_MUX_SEL0_SHIFT	0
#define PRUSS_PIN_MUX_SEL1_SHIFT	1


/* RXCFG0 */
#define PRUSS_RXCFG0_RX_AUTO_FWD_PRE_DISABLE	0
#define PRUSS_RXCFG0_RX_AUTO_FWD_PRE_ENABLE		1
#define PRUSS_RXCFG0_RX_AUTO_FWD_PRE_SHIFT		6

#define PRUSS_RXCFG0_RX_BYTE_SWAP_DISABLE		0
#define PRUSS_RXCFG0_RX_BYTE_SWAP_ENABLE		1
#define PRUSS_RXCFG0_RX_BYTE_SWAP_SHIFT			5

#define PRUSS_RXCFG0_RX_L2_DISABLE				0
#define PRUSS_RXCFG0_RX_L2_ENABLE				1
#define PRUSS_RXCFG0_RX_L2_SHIFT				4

#define PRUSS_RXCFG0_RX_MUX_SELECT_PORT0		0
#define PRUSS_RXCFG0_RX_MUX_SELECT_PORT1		1
#define PRUSS_RXCFG0_RX_MUX_SELECT_SHIFT		3

#define PRUSS_RXCFG0_RX_CUT_PREAMBLE_DISABLE	0
#define PRUSS_RXCFG0_RX_CUT_PREAMBLE_ENABLE		1
#define PRUSS_RXCFG0_RX_CUT_PREAMBLE_SHIFT		2

#define PRUSS_RXCFG0_RX_DISABLE			0
#define PRUSS_RXCFG0_RX_ENABLE			1
#define PRUSS_RXCFG0_RX_ENABLE_SHIFT			0

/* RXCFG1 */
#define PRUSS_RXCFG1_RX_AUTO_FWD_PRE_DISABLE	0
#define PRUSS_RXCFG1_RX_AUTO_FWD_PRE_ENABLE		1
#define PRUSS_RXCFG1_RX_AUTO_FWD_PRE_SHIFT		6

#define PRUSS_RXCFG1_RX_BYTE_SWAP_DISABLE		0
#define PRUSS_RXCFG1_RX_BYTE_SWAP_ENABLE		1
#define PRUSS_RXCFG1_RX_BYTE_SWAP_SHIFT			5

#define PRUSS_RXCFG1_RX_L2_DISABLE				0
#define PRUSS_RXCFG1_RX_L2_ENABLE				1
#define PRUSS_RXCFG1_RX_L2_SHIFT				4

#define PRUSS_RXCFG1_RX_MUX_SELECT_PORT0		0
#define PRUSS_RXCFG1_RX_MUX_SELECT_PORT1		1
#define PRUSS_RXCFG1_RX_MUX_SELECT_SHIFT		3

#define PRUSS_RXCFG1_RX_CUT_PREAMBLE_DISABLE	0
#define PRUSS_RXCFG1_RX_CUT_PREAMBLE_ENABLE		1
#define PRUSS_RXCFG1_RX_CUT_PREAMBLE_SHIFT		2

#define PRUSS_RXCFG1_RX_DISABLE			0
#define PRUSS_RXCFG1_RX_ENABLE			1
#define PRUSS_RXCFG1_RX_ENABLE_SHIFT			0


/* TXCFG0 */
#define PRUSS_TXCFG0_TX_CLK_DELAY_SHIFT			28

#define PRUSS_TXCFG0_TX_START_DELAY_SHIFT		16

#define PRUSS_TXCFG0_TX_AUTO_ESC_ERR_DISABLE	0
#define PRUSS_TXCFG0_TX_AUTO_ESC_ERR_ENABLE		1
#define PRUSS_TXCFG0_TX_AUTO_ESC_ERR_SHIFT		10

#define PRUSS_TXCFG0_TX_AUTO_SEQUENCE_DISABLE	0
#define PRUSS_TXCFG0_TX_AUTO_SEQUENCE_ENABLE	1
#define PRUSS_TXCFG0_TX_AUTO_SEQUENCE_SHIFT		9

#define PRUSS_TXCFG0_TX_MUX_SEL_PORT0			0
#define PRUSS_TXCFG0_TX_MUX_SEL_PORT1			1
#define PRUSS_TXCFG0_TX_MUX_SEL_SHIFT			8

#define PRUSS_TXCFG0_TX_BYTE_SWAP_DISABLE		0
#define PRUSS_TXCFG0_TX_BYTE_SWAP_ENABLE		1
#define PRUSS_TXCFG0_TX_BYTE_SWAP_SHIFT			3

#define PRUSS_TXCFG0_TX_EN_MODE_DISABLE			0
#define PRUSS_TXCFG0_TX_EN_MODE_ENABLE			1
#define PRUSS_TXCFG0_TX_EN_MODE_SHIFT			2

#define PRUSS_TXCFG0_TX_AUTO_PREAMBLE_DISABLE	0
#define PRUSS_TXCFG0_TX_AUTO_PREAMBLE_ENABLE	1
#define PRUSS_TXCFG0_TX_AUTO_PREAMBLE_SHIFT		1

#define PRUSS_TXCFG0_TX_DISABLE			0
#define PRUSS_TXCFG0_TX_ENABLE			1
#define PRUSS_TXCFG0_TX_ENABLE_SHIFT 	0

/* TXCFG1 */
#define PRUSS_TXCFG1_TX_CLK_DELAY_SHIFT			28

#define PRUSS_TXCFG1_TX_START_DELAY_SHIFT		16

#define PRUSS_TXCFG1_TX_AUTO_ESC_ERR_DISABLE	0
#define PRUSS_TXCFG1_TX_AUTO_ESC_ERR_ENABLE		1
#define PRUSS_TXCFG1_TX_AUTO_ESC_ERR_SHIFT		10

#define PRUSS_TXCFG1_TX_AUTO_SEQUENCE_DISABLE	0
#define PRUSS_TXCFG1_TX_AUTO_SEQUENCE_ENABLE	1
#define PRUSS_TXCFG1_TX_AUTO_SEQUENCE_SHIFT		9

#define PRUSS_TXCFG1_TX_MUX_SEL_PORT0			0
#define PRUSS_TXCFG1_TX_MUX_SEL_PORT1			1
#define PRUSS_TXCFG1_TX_MUX_SEL_SHIFT			8

#define PRUSS_TXCFG1_TX_BYTE_SWAP_DISABLE		0
#define PRUSS_TXCFG1_TX_BYTE_SWAP_ENABLE		1
#define PRUSS_TXCFG1_TX_BYTE_SWAP_SHIFT			3

#define PRUSS_TXCFG1_TX_EN_MODE_DISABLE			0
#define PRUSS_TXCFG1_TX_EN_MODE_ENABLE			1
#define PRUSS_TXCFG1_TX_EN_MODE_SHIFT			2

#define PRUSS_TXCFG1_TX_AUTO_PREAMBLE_DISABLE	0
#define PRUSS_TXCFG1_TX_AUTO_PREAMBLE_ENABLE	1
#define PRUSS_TXCFG1_TX_AUTO_PREAMBLE_SHIFT		1

#define PRUSS_TXCFG1_TX_DISABLE			0
#define PRUSS_TXCFG1_TX_ENABLE			1
#define PRUSS_TXCFG1_TX_ENABLE_SHIFT 	0

/* RXFRMS0 */
#define PRUSS_RXFRMS0_RX_MAX_FRM_CNT_SHIFT		16

#define PRUSS_RXFRMS0_RX_MIN_FRM_CNT_SHIFT		0

/* RXFRMS1 */
#define PRUSS_RXFRMS1_RX_MAX_FRM_CNT_SHIFT		16

#define PRUSS_RXFRMS1_RX_MIN_FRM_CNT_SHIFT		0

/* RXPCNT0 */
#define PRUSS_RXPCNT0_RX_MAX_PRE_CNT_SHIFT				4

#define PRUSS_RXPCNT0_RX_MIN_PRE_CNT_SHIFT				0

/* RXPCNT1 */
#define PRUSS_RXPCNT1_RX_MAX_PRE_CNT_SHIFT				4

#define PRUSS_RX_RXPCNT1_MIN_PRE_CNT_SHIFT				0

/* RXERR0 */
#define PRUSS_RXERR0_RX_MAX_FRM_CNT_ERR		0x08
#define PRUSS_RXERR0_RX_MIN_FRM_CNT_ERR		0x04
#define PRUSS_RXERR0_RX_MAX_PRE_CNT_ERR		0x02
#define PRUSS_RXERR0_RX_MIN_PRE_CNT_ERR		0x01

#endif /* PRUSS_REGISTER_H_ */
