/**
* @file icss_miimdio_regs.h
*
* @brief Contains MII MDIO Register offsets and definitions
*
* \par
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
* \par
*/

#ifndef _ICSS_MIIMDIO_REGS_H
#define _ICSS_MIIMDIO_REGS_H

#ifdef __cplusplus
extern "C" {
#endif

/**
* @def USE_STARTERWARE_MDIO_APIS
*      Use starterware APIs for MDIO register Access
*/
#define USE_STARTERWARE_MDIO_APIS

/***************************************************************************
**                                                                         
**         M D I O  M E M O R Y  M A P 
**                                                                         
***************************************************************************/


#ifndef USE_STARTERWARE_MDIO_APIS

#define pMDIO_VER(base)                 ((volatile Uint32 *)(base+0x00))
#define pMDIO_CONTROL(base)             ((volatile Uint32 *)(base+0x04))
#define pMDIO_ALIVE(base)               ((volatile Uint32 *)(base+0x08))
#define pMDIO_LINK(base)                ((volatile Uint32 *)(base+0x0C))
#define pMDIO_LINKINTRAW(base)          ((volatile Uint32 *)(base+0x10))
#define pMDIO_LINKINTMASKED(base)       ((volatile Uint32 *)(base+0x14))
#define pMDIO_USERINTRAW(base)          ((volatile Uint32 *)(base+0x20))
#define pMDIO_USERINTMASKED(base)       ((volatile Uint32 *)(base+0x24))
#define pMDIO_USERINTMASKED_SET(base)   ((volatile Uint32 *)(base+0x28))
#define pMDIO_USERINTMASKED_CLR(base)   ((volatile Uint32 *)(base+0x2C))
#define pMDIO_USERACCESS(base, channel) ((volatile Uint32 *)(base+(0x80+(channel*8))))
#define pMDIO_USERPHYSEL(base, channel) ((volatile Uint32 *)(base+(0x84+(channel*8))))


#define MDIO_ALIVE(base)                    (*(pMDIO_ALIVE(base)))
#define MDIO_CONTROL(base)                  (*(pMDIO_CONTROL(base)))
#define MDIO_CONTROL_IDLE	          		(1 << 31)
#define MDIO_CONTROL_ENABLE	          		(1 << 30)
#define MDIO_CONTROL_PREAMBLE             	(1 << 20)
#define MDIO_CONTROL_FAULT	          		(1 << 19)
#define MDIO_CONTROL_FAULT_DETECT_ENABLE  	(1 << 18)
#define MDIO_CONTROL_INT_TEST_ENABLE      	(1 << 17)
#define MDIO_CONTROL_HIGHEST_USER_CHANNEL 	(0x1F << 8)
#define MDIO_CONTROL_CLKDIV	          		(0xFF)
#define MDIO_LINK(base)                     (*(pMDIO_LINK(base)))
#define MDIO_LINKINTRAW(base)               (*(pMDIO_LINKINTRAW(base)))
#define MDIO_LINKINTMASKED(base)            (*(pMDIO_LINKINTMASKED(base)))
#define MDIO_USERINTRAW(base)               (*(pMDIO_USERINTRAW(base)))
#define MDIO_USERINTMASKED(base)            (*(pMDIO_USERINTMASKED(base)))
#define MDIO_USERINTMASKED_CLR(base)        (*(pMDIO_USERINTMASKED_CLR(base)))
#define MDIO_USERINTMASKED_SET(base)        (*(pMDIO_USERINTMASKED_SET(base)))
#define MDIO_USERINTRAW(base)               (*(pMDIO_USERINTRAW(base)))
#define MDIO_USERACCESS(base, channel)      (*(pMDIO_USERACCESS(base, channel)))
#define MDIO_USERACCESS_GO     				((Uint32)(1 << 31))
#define MDIO_USERACCESS_WRITE  				(1 << 30)
#define MDIO_USERACCESS_READ   				(0 << 30)
#define MDIO_USERACCESS_ACK    				(1 << 29)
#define MDIO_USERACCESS_REGADR 				(0x1F << 21)
#define MDIO_USERACCESS_PHYADR 				(0x1F << 16)
#define MDIO_USERACCESS_DATA   				(0xFFFF)
#define MDIO_USERPHYSEL(base, channel)      (*(pMDIO_USERPHYSEL(base, channel)))
#define MDIO_USERPHYSEL_LINKSEL         	(1 << 7)
#define MDIO_USERPHYSEL_LINKINT_ENABLE  	(1 << 6)
#define MDIO_USERPHYSEL_PHYADR_MON      	(0x1F)
#define MDIO_VER(base)                      (*(pMDIO_VER(base)))
#define MDIO_VER_MODID         				((Uint32)(0xFFFF << 16))
#define MDIO_VER_REVMAJ        				(0xFF   << 8)
#define MDIO_VER_REVMIN        				(0xFF)


#endif

/***************************************************************************
**
**         M D I O  R E G I S T E R  A C C E S S  M A C R O S
**
***************************************************************************/

/**
* @def MDIO_USERACCESS_DATA
*      MDIO User Accss Data
*/
#define MDIO_USERACCESS_DATA   				(0xFFFF)
/**
* @def MDIO_USERPHYSEL_LINKSEL
*      MDIO user PHYSEL_LINKSEL
*/
#define MDIO_USERPHYSEL_LINKSEL         	(1 << 7)
/**
* @def MDIO_VER_MODID
*      MDIO version modid
*/
#define MDIO_VER_MODID         				((Uint32)(0xFFFF << 16))
/**
* @def MDIO_VER_REVMAJ
*      MDIO Major revision
*/
#define MDIO_VER_REVMAJ        				(0xFF   << 8)
/**
* @def MDIO_VER_REVMIN
*      MDIO Minor revision
*/
#define MDIO_VER_REVMIN        				(0xFF)



/****************************************************************************/
/*                                                                          */
/*         P H Y   R E G I S T E R  D E F I N I T I O N S                   */
/*                                                                          */
/****************************************************************************/
/**
* @def PHY_CONTROL_REG
*      Phy Control register
*/
  #define PHY_CONTROL_REG       0
/**
* @def MII_PHY_RESET
*      Phy reset
*/
  #define MII_PHY_RESET           (1<<15)
/**
* @def MII_PHY_LOOP
*      Phy Loop
*/
  #define MII_PHY_LOOP            (1<<14)
/**
* @def MII_PHY_100
*      Phy 100 Mbps
*/
  #define MII_PHY_100             (1<<13)
/**
* @def MII_AUTO_NEGOTIATE_EN
*      Phy Autonegotiate enable
*/
  #define MII_AUTO_NEGOTIATE_EN   (1<<12)
/**
* @def MII_PHY_PDOWN
*      Phy PDown
*/
  #define MII_PHY_PDOWN           (1<<11)
/**
* @def MII_PHY_ISOLATE
*      Phy Isolate
*/
  #define MII_PHY_ISOLATE         (1<<10)
/**
* @def MII_RENEGOTIATE
*      Phy Renegotiate
*/
  #define MII_RENEGOTIATE         (1<<9)
/**
* @def MII_PHY_FD
*      Phy Full Duplex
*/
  #define MII_PHY_FD              (1<<8)
/**
* @def MII_PHY_1000
*      Phy 1 Gbps
*/
  #define MII_PHY_1000            (1<<6)

/**
* @def PHY_CNTRL_REG
*      Phy Control register
*/
#define PHY_CNTRL_REG        0x0019
/**
* @def PHY_SCR_REG
*      PHY Specific Control register
*/
#define PHY_SCR_REG        0x0011
/**
* @def PHY_STAT_REG
*      Phy Status register
*/
#define PHY_STAT_REG        0x0010
/**
* @def NLP_DET_REG
*      NLP Parallel Detect Configuration register
*/
#define NLP_DET_REG   0x0020
/**
* @def NLP_DET_CONFIG_REGVAL
*      NLP Parallel Detect Configuration Value
*/
#define NLP_DET_CONFIG_REGVAL  0x5668
/**
* @def PHY_REGCR_REG
*      Value reg for accessing extended registers
*/
#define PHY_REGCR_REG  0x000D
/**
* @def PHY_ADDR_REG
*      ADDR reg for accessing extended registers
*/
#define PHY_ADDR_REG   0x000E
/**
* @def EXT_REG_ADDRESS_ACCESS
*      Extended reg address access value
*/
#define EXT_REG_ADDRESS_ACCESS 0x001F
/**
* @def EXT_REG_DATA_NORMAL_ACCESS
*      Extended reg data access value
*/
#define EXT_REG_DATA_NORMAL_ACCESS 0x401F
/**
* @def PHY_SSCR1_REG
*      Software strap control register 1
*/
#define PHY_SSCR1_REG		0x9
/**
* @def MII_ROBUST_MDIX
*      Robust Auto MDIX
*/
#define MII_ROBUST_MDIX        (1<<5)
/**
* @def MII_PSMODE_ENABLE
*
*/
#define MII_PSMODE_ENABLE   (1<<14)
/**
* @def MII_PSMODE_BIT1
*
*/
#define MII_PSMODE_BIT1   (1<<12)
/**
* @def MII_PSMODE_BIT2
*
*/
#define MII_PSMODE_BIT2   (1<<13)


/**
* @def PHY_STATUS_REG
*      Phy Status register
*/
#define PHY_STATUS_REG        1
/**
* @def MII_NWAY_COMPLETE
*      Complete
*/
#define MII_NWAY_COMPLETE       (1<<5)
/**
* @def MII_NWAY_CAPABLE
*      Capable
*/
#define MII_NWAY_CAPABLE        (1<<3)
/**
* @def MII_PHY_LINKED
*      Phy Linked
*/
#define MII_PHY_LINKED          (1<<2)
/**
* @def PHY_IDENT_REG
*      Phy Ident register
*/
#define PHY_IDENT_REG         2
/**
* @def NWAY_ADVERTIZE_REG
*      Advertize register
*/
#define NWAY_ADVERTIZE_REG    4
/**
* @def NWAY_REMADVERTISE_REG
*      REM Advertize register
*/
#define NWAY_REMADVERTISE_REG 5
/**
* @def MII_NWAY_FD100
*     Full Duplex 100 Mbps
*/
#define MII_NWAY_FD100          (1<<8)
/**
* @def MII_NWAY_HD100
*      Half Duplex 100 Mbps
*/
#define MII_NWAY_HD100          (1<<7)
/**
* @def MII_NWAY_FD10
*      Full Duplex 10 Mbps
*/
#define MII_NWAY_FD10           (1<<6)
/**
* @def MII_NWAY_HD10
*      Half Duplex 10 Mbps
*/
#define MII_NWAY_HD10           (1<<5)
/**
* @def MII_NWAY_SEL
*      Select
*/
#define MII_NWAY_SEL            (1<<0)
/**
* @def NWAY_1000BT_ADVERTISE_REG
*      NWAY_1000BT_ADVERTISE_REG
*/
#define NWAY_1000BT_ADVERTISE_REG    9
/**
* @def MII_NWAY_MY_FD1000
*      MII_NWAY_MY_FD1000
*/
#define MII_NWAY_MY_FD1000         (1<<9)
/**
* @def MII_NWAY_MY_HD1000
*      MII_NWAY_MY_HD1000
*/
#define MII_NWAY_MY_HD1000         (1<<8)
/**
* @def NWAY_1000BT_REMADVERTISE_REG
*      NWAY_1000BT_REMADVERTISE_REG
*/
#define NWAY_1000BT_REMADVERTISE_REG 10
/**
* @def MII_NWAY_REM_FD1000
*      MII_NWAY_REM_FD1000
*/
#define MII_NWAY_REM_FD1000         (1<<11)
/**
* @def MII_NWAY_REM_HD1000
*      MII_NWAY_REM_HD1000
*/
#define MII_NWAY_REM_HD1000         (1<<10)
/**
* @def PHY_CONFIG_REG
*      Phy Config register
*/
#define PHY_CONFIG_REG	22
/**
* @def SYSTEM_CLOCK_ENABLE_125MHZ
*      System Clock Enable 125 Mhz
*/
#define SYSTEM_CLOCK_ENABLE_125MHZ		(1<<4)
/**
* @def TRANSMIT_CLOCK_ENABLE_1000BASET
*      Transmit  Clock Enable
*/
#define TRANSMIT_CLOCK_ENABLE_1000BASET	(1<<5)
/**
* @def GMII_CLOCKED_BY_GTX_CLK
*      GMII Clocked
*/
#define GMII_CLOCKED_BY_GTX_CLK			(1<<1)
/**
* @def PHY_LED_CONTROL_REG
*      Phy Led Control register
*/
#define PHY_LED_CONTROL_REG	28
#ifdef __cplusplus
}
#endif

#endif /*_ICSS_MIIMDIO_REGS_H_*/
