///**
// * icss_switch.h
// *
// *
// * Copyright (c) 2012 Texas Instruments Incorporated ALL RIGHTS RESERVED
// *
//*/
//*****************************************************************************/
// file:   icss_switch.h
//
// brief:  Definitions and mapping of Ethernet switch over PRU
//         Includes:
//         1. Buffer pools, queus, descriptors
//         2. Switch configutation parameter
//         3. Statistics
//         4. Events for switch interaction
//         5. Memory Map and Control Register definition
//
//
//  (C) Copyright 2012, Texas Instruments, Inc
//
//	Version		Description								Author
//
// 	0.1     	Created								Thomas Leyrer
//  0.2			updates for  broadcast send			tley
//  0.3 		added table for queue size			tley
//  0.4         cleanup for ARM include             Frank Walzer
//
//

#ifndef __ICSS_SWITCH_H__
#define __ICSS_SWITCH_H__

// Target switches: PRU / ARM
// Protocol switches: PROFINET / EIP / 61850 / AVB
//
// Port assignment:
// PORT 0: ARM or host port
// PORT 1: PHY Port 1 - PRU0 receive and PRU1 transmit
// PORT 2: PHY Port 2 - PRU1 receive and PRU0 transmit

// Basic Switch Parameters
// Queue size definitions – Ethernet Switch
#define SWITCH_BUFFER_SIZE		64*1024 // L3 buffer
#define BLOCK_SIZE				32		// bytes derived from ICSS architecture
#define BD_SIZE					4		// one buffer descriptor is 4 bytes
#define MAX_NUMBER_OF_QUEUES 	4   	// up to 4 queues supported
#define MIN_NUMBER_OF_QUEUES 	1		//
#define NUMBER_OF_PORTS			3		// two phy ports and one host port

//***************************************Half duplex values*********************************
//comment this flag to disable half duplex
#define HALF_DUPLEX_ENABLED

//uncomment to disable DLR
//#define DISABLE_DLR

#define PORT_IS_HD				t0
#define PORT_IS_HD_MASK			0x1

#define PORT0_LINK_UP           t1
#define PORT1_LINK_UP           t2
#define SWITCH_STAT_DISABLED    t3

// Queues on PHY PORT 1/2
#define NUMBER_OF_QUEUES	4			// different number of queues will have significant impact to memory map
#define MAX_ETH_SIZE_BYTES	1536
#define MAX_ETH_SIZE_BLOKS 	1536/32	 	// typically 48 blocks per Ethernet frame
// 48 blocks per max packet
// 2 full sized ETH packets: 96 blocks, 3 packets = 144, 4 packets = 192

// Physical Port queue size. Same for both ports
#define QUEUE_1_SIZE		97 	// Network Management high
#define QUEUE_2_SIZE		97	// Network Management low
#define	QUEUE_3_SIZE		97	// Protocol specific
#define QUEUE_4_SIZE		97	// NRT (IP,ARP, ICMP, …)

// HOST PORT QUEUES can buffer up to 4 full sized frames per queue
#define	HOST_QUEUE_1_SIZE		194	// Protocol and/or VLAN priority 7 and 6
#define HOST_QUEUE_2_SIZE		194	// Protocol mid
#define HOST_QUEUE_3_SIZE		194	// Protocol low
#define HOST_QUEUE_4_SIZE		194	// NRT (IP, ARP, ICMP …)

#define COLLISION_QUEUE_SIZE	48
#define P0_COL_TOP_MOST_BD_OFFSET	(4*COLLISION_QUEUE_SIZE) + P0_COL_BD_OFFSET - 4
#define P1_COL_TOP_MOST_BD_OFFSET	(4*COLLISION_QUEUE_SIZE) + P1_COL_BD_OFFSET - 4
#define P2_COL_TOP_MOST_BD_OFFSET	(4*COLLISION_QUEUE_SIZE) + P2_COL_BD_OFFSET - 4

#define TOTAL_BUFFER_POOL	2*(QUEUE_1_SIZE + QUEUE_2_SIZE + QUEUE_3_SIZE + QUEUE_4_SIZE) +	HOST_QUEUE_1_SIZE + HOST_QUEUE_2_SIZE + HOST_QUEUE_3_SIZE + HOST_QUEUE_4_SIZE

// NRT Buffer descriptor definition
// Each buffer descriptor points to a max 32 byte block and has 32 bit in size to have atomic operation.
// PRU can address bytewise into memory.
// Definition of 32 bit desriptor is as follows
//
// Bits		Name			Meaning
// ==================================================================================================
// 0..7 	Index			points to index in buffer queue, max 256 x 32 byte blocks can be addressed
// 8..12	Block_length    number of valid bytes in this specific block. Will be <=32 bytes on last block of packet
// 13		More			"More" bit indicating that there are more blocks for the
// 14 		Shadow			inidcates that "index" is pointing into shadow buffer
// 15		TimeStamp		indicates that this packet has time stamp in seperate buffer - only needed of PTCP runs on host
// 16..17	Port			different meaning for ingress and egress, ingress Port=0 inidcates phy port 1 and Port = 1
//							inidcates phy port 2. Egress: 0 sends on phy port 1 and 1 sends on phy port 2. Port = 2 goes
// 							over MAC table look-up
// 18..28   Length			11 bit of total packet length which is put into first BD only so that host access only one BD
// 29		VlanTag			indicates that packet has Length/Type field of 0x08100 with VLAN tag in following byte
// 30		Broadcast		inidcates that packet goes out on both physical ports,  there will be two bd but only one buffer
// 31		Error			indicates there was an error in the packet
//
#ifdef PRU
#define		Index			b0
#define		Block_length	b1
#define   	More			t13
#define     Shadow			t14
#define		TimeStamp		t16
#define 	Port			b2
#define		Length			w2
#define 	VlanTag			t29
#define 	Broadcat		t30
#define		Error			t31
#else
  // #defines for bd masks
#endif

// NRT Queue Defintion
// Each port has up to 4 queues with variable length. The queus is processed as ring buffer with read and write pointer.
// Both pointer are address pointers and increment by 4 for each buffer descriptor/position.
// Queue has a length defined in constants and a status. Status is defined as described below
//
// Bits		Name 			Meaning
// =====================================================================================================
// 0 		Busy_M			This queue is busy by the master port which is the PRU receiving packets from the master
// 1		Collision		Slave is/has written into shadow queue, both descriptors and data.
// 2		Overflow		there was not enough space to write to queue and packet was discarded
// 4..7    	Reserved		reserved
//
// There is busy slave flag in different byte address to grant access to queue to master in case
// of simultaneous access. Host will alwasys be slave in this case. The PRU which is sending the
// packet on phy port will be the master. When both PRUs wants to write to host queues PRU0
// is master and PRU1 is slave.
//
// Bits		Name 			Meaning
// =====================================================================================================
// 0 		Busy_S			This queue is busy by the master port which is the PRU receiving packets from the master
// 1..7		Reserved
//
// Length is the number of 32 byte blocks per queue. max_fill_level tells the minimum distance between write and read pointer.
// over_flow_cnt tells how many times the write pointer runs into the read_pointer.

#ifdef PRU
.struct struct_queue
    .u16 rd_ptr
    .u16 wr_ptr
    .u8 busy_s
    .u8 status
    .u8 max_fill_level
    .u8 overflow_cnt
.ends

#define	busy_m 		t0
#else
typedef struct _Queue {
	Uint16  rd_ptr;
	Uint16  wr_ptr;
	Uint8	busy_s;
	Uint8   status;
	Uint8   max_fill_level;
	Uint8   overflow_cnt;
} Queue;

#endif

#ifdef PRU
#define QUEUE_DESCRIPTOR_SIZE SIZE(struct_queue) 	// typically 8 bytes per register
#else
#define QUEUE_DESCRIPTOR_SIZE sizeof(Queue) 		// typically 8 bytes per register
#endif
#define TOTAL_QUEUE_DESCRIPTOR_SIZE NUMBER_OF_PORTS * NUMBER_OF_QUEUES

#define	Q_MAX_FILL_LEVEL_OFFSET		6
#define	Q_OVERFLOW_CNT_OFFSET		7
// Memory Map for buffer pool, buffer descriptor and queue descriptor
#define TX0_UNDERFLOW t7
#define TX0_OVERFLOW t8
#define TX1_UNDERFLOW t19
#define TX1_OVERFLOW t20

#define NUM_EXCESS_COLLISIONS       15

//****************************************************************************
//*                       General Purpose Statistics                         *
//*              These are present on both PRU0 and PRU1 DRAM                *
//****************************************************************************

// base statistics offset
#define STATISTICS_OFFSET		0x1f00

// MII port TX statistics flags
#define TX_BC_FRAMES_OFFSET              0x0
#define TX_MC_FRAMES_OFFSET              0x4
#define TX_UC_FRAMES_OFFSET              0x8

//Binning counters : disabled by default
#define TX_BYTE_CNT_OFFSET               0xc

// MII port RX statistics flags
#define RX_BC_FRAMES_OFFSET             0x10
#define RX_MC_FRAMES_OFFSET             0x14
#define RX_UC_FRAMES_OFFSET             0x18      //counted on ARM side, UC packets not meant for ARM are included in cut through count

//Binning counters : disabled by default
#define RX_BYTE_CNT_OFFSET              0x1c

//**********************************Collision Counters*******************************/
#define LATE_COLLISION_OFFSET           STATISTICS_OFFSET + 0x20      //set for a frame where collision took place after 512 bytes were sent on wire
#define SINGLE_COLLISION_OFFSET         STATISTICS_OFFSET + 0x24      //frame was sent after a single collision was reported
#define MULTIPLE_COLLISION_OFFSET       STATISTICS_OFFSET + 0x28      //frame was sent after more than one collision
#define EXCESS_COLLISION_OFFSET         STATISTICS_OFFSET + 0x2c      //more than 16 collisions
//***********************************************************************************/

//****************Debug Statistics***************************************************/
#define TX_OVERFLOW_OFFSET				STATISTICS_OFFSET + 0x30
//**********************************************************************************/

//********************Error packets****************
//Packed dropped on account of storm prevention
#define RX_MISALIGNMENT_COUNT_OFFSET  STATISTICS_OFFSET + 0x34 //frame size in bits is not a multiple of 8
#define STORM_PREVENTION_COUNTER  	  STATISTICS_OFFSET + 0x38
#define RX_ERROR_OFFSET               STATISTICS_OFFSET + 0x3c
#define SFD_ERROR_OFFSET		      STATISTICS_OFFSET + 0x40
#define TX_DEFERRED_OFFSET            STATISTICS_OFFSET + 0x44
#define TX_ERROR_OFFSET               STATISTICS_OFFSET + 0x48
#define RX_OVERSIZED_FRAME_OFFSET     STATISTICS_OFFSET + 0x4c  //count of frames with size greater than 1518 bytes
#define RX_UNDERSIZED_FRAME_OFFSET    STATISTICS_OFFSET + 0x50  //count of frames shorter than 64 bytes (including CRC)
#define RX_CRC_COUNT_OFFSET      	  STATISTICS_OFFSET + 0x54  //number of frames with CRC error
#define RX_DROPPED_FRAMES_OFFSET      STATISTICS_OFFSET + 0x58

#define TX_64_BYTE_FRAME_OFFSET			0x5c
#define TX_65_127_BYTE_FRAME_OFFSET		0x60
#define TX_128_255_BYTE_FRAME_OFFSET	0x64
#define TX_256_511_BYTE_FRAME_OFFSET	0x68
#define TX_512_1023_BYTE_FRAME_OFFSET	0x6c
#define TX_1024_MAX_BYTE_FRAME_OFFSET	0x70

#define RX_64_BYTE_FRAME_OFFSET			0x74
#define RX_65_127_BYTE_FRAME_OFFSET		0x78
#define RX_128_255_BYTE_FRAME_OFFSET	0x7c
#define RX_256_511_BYTE_FRAME_OFFSET	0x80
#define RX_512_1023_BYTE_FRAME_OFFSET	0x84
#define RX_1024_MAX_BYTE_FRAME_OFFSET	0x88

//#define CS_ERROR_OFFSET             0x7c  //HW Does not support at this Point of time
//#define SQE_TEST_ERROR_OFFSET       0x80  //HW Does not support at this Point of time

#define STAT_SIZE  RX_1024_MAX_BYTE_FRAME_OFFSET + 4    //always keep it's value same as the last stat offset
//------------------------------End of Statistics----------------------------------//
//****************************************************************************
//*              Offset for storing Storm Prevention Params                  *
//*              This is present on both PRU0 and PRU1                       *
//****************************************************************************
#define STORM_PREVENTION_OFFSET   	  STATISTICS_OFFSET + STAT_SIZE

//****************************************************************************
//*                       Offset for storing PHY SPeed                       *
//*              This is present only on PRU0 DRAM                           *
//****************************************************************************
#define PHY_SPEED_OFFSET		STORM_PREVENTION_OFFSET + 0x4

//****************************************************************************
//*                       ICSS PRU1 DRAM Mem Usage                           *
//* Please update all mem usage here to make it easier for other developers  *
//*       Not updating memory usage leads to difficult to fix errors         *
//****************************************************************************
#define ICSS_PRU1_DRAM_FREE_MEM_SIZE        ICSS_PRU1_DRAM_FREE_MEM_END - ICSS_PRU1_DRAM_FREE_MEM_START
#define ICSS_PRU1_DRAM_FREE_MEM_END         0x1D00
#define ICSS_PRU1_DRAM_FREE_MEM_START       PROTOCOL_SPECIFIC_DRAM_MEMORY_OFFSET + PROTOCOL_SPECIFIC_DRAM_MEMORY_SIZE


//Memory from 0 to 0x200 on PRU1 DRAM is reserved for protocol specific usage
//Do not use this memory
//#define PROTOCOL_SPECIFIC_DRAM_MEMORY_SIZE       0x200
//#define PROTOCOL_SPECIFIC_DRAM_MEMORY_OFFSET     0x0

//------------------------------Queue Descriptors--------------------------------//
#define P2_QUEUE_DESC_OFFSET	0x1EE0			// 4 queue descriptors for port 2 (PRU0 xmt)
#define P1_QUEUE_DESC_OFFSET	0x1EC0			// 4 queue descriptors for port 1 (PRU1 xmt)
#define P0_QUEUE_DESC_OFFSET	0x1EA0			// 4 queue descriptors for port 0 (host receive)
#define P2_COL_QUEUE_DESC_OFFSET 	0x1E98      // collision descriptor of port 2
#define P1_COL_QUEUE_DESC_OFFSET 	0x1E90      // collision descriptor of port 1
#define P0_COL_QUEUE_DESC_OFFSET 	0x1E88      // collision descriptor of port 0
//------------------------------End of queue descriptors---------------------------//

#define COLLISION_STATUS_ADDR 		0x1E84		// Collision Status Register, P0: bit 0 is pending flag, bit 1..2 inidicates which queue,
												// P1: bit 8 is pending flag, 9..10 is queue number
												// p2: bit 16 is pending flag, 17..18 is queue number, remaining bits are 0.
#define BROADCAST_SEND_STATUS_ADDR	0x1E80		// bit 0 flags broadcast packet sent on P1,
												// bit 8 flags broadcast packet sent on P2, remaining bits are reserved
#define BRIDGE_OPTION_ADDR			0x1E7C		// configures port rules for laerning, forwarding and aging
//#define SWITCH_CONTROL_ADDR			0x1E78		// Global enable of swtich, reset isolation, reset of queues and dynamic tables
#define SWITCH_STATUS_ADDR			0x1E78		// status flags per port: rcv_active, xmt_active, cut-through, forward, receive
#define INTERFACE_MAC_ADDR			0x1E70		// Interface MAC Address

#define SWITCH_CONTROL_ADDR			0x1E6C		// Global enable of swtich, reset isolation, reset of queues and dynamic tables

#define P2_MAC_ADDR					0x1E66		// Port 2 MAC Adress
#define P1_MAC_ADDR					0x1E60	 	// Port 1 MAC Address
#define INTERFACE_IP_ADDR			0x1E5C		// IP address of device

// todo: flag to add SA with to learning, type UC/MC/BC
// todo: port state: blocking, receiving, learninig, ... per port
// todo: global status: rcv_active flag, host_recv_flag, forward_flag, cut_through_flag

// With dynamic configuration of queue size the offsets are variablel. For PRU to find which queue and descriptor needs to be served there
// is a look-up table with index of port and queue number.
// table definition to access queue size, buffer descriptor and buffer

// table offset for queue size: 3 ports * 4 Queues * 1 byte offset = 12 bytes
#define QUEUE_SIZE_ADDR					0x1E30
// table offset for queue: 3 ports * 4 Queues * 2 byte offset = 24 bytes
#define QUEUE_OFFSET_ADDR				0x1E18
// table offset for queue descriptors: 3 ports * 4 Queues * 2 byte offset = 24 bytes
#define QUEUE_DESCRIPTOR_OFFSET_ADDR	0x1E00
// todo: remove this older definition
#define QUEUE_SIZE_TBL_ADDR		0x1E00          // table is filled by host before operation and structured in
                                                // 0x1E08: P0Q0 0x1E09: P0Q1 0x1E0A: P0Q2 0x1E0B: P0Q3
												// 0x1E04: P1Q0 0x1E05: P1Q1 0x1E06: P1Q2 0x1E07: P0Q3
												// 0x1E00: P0Q0 0x1E01: P0Q1 0x1E02: P0Q2 0x1E03: P0Q3

#define CONFIGURATION_OFFSET	0x1E00	        // 256 bytes of Configuratuin which also includes queue descriptors

// Port 2 Rx Collision context
#define COL_RX_CONTEXT_P2_OFFSET_ADDR	COL_RX_CONTEXT_P1_OFFSET_ADDR + 12   //10 bytes
// Port 1 Rx Collision context
#define COL_RX_CONTEXT_P1_OFFSET_ADDR	COL_RX_CONTEXT_P0_OFFSET_ADDR + 12   //10 bytes
// Host Port Collision Context
#define COL_RX_CONTEXT_P0_OFFSET_ADDR	P2_Q4_RX_CONTEXT_OFFSET + 8   //10 bytes

// Port 2 Rx Context
#define P2_Q4_RX_CONTEXT_OFFSET			P2_Q3_RX_CONTEXT_OFFSET + 8
#define P2_Q3_RX_CONTEXT_OFFSET			P2_Q2_RX_CONTEXT_OFFSET + 8
#define P2_Q2_RX_CONTEXT_OFFSET			P2_Q1_RX_CONTEXT_OFFSET + 8
#define P2_Q1_RX_CONTEXT_OFFSET			RX_CONTEXT_P2_Q1_OFFSET_ADDR
#define RX_CONTEXT_P2_Q1_OFFSET_ADDR	P1_Q4_RX_CONTEXT_OFFSET + 8

// Port 1 Rx Context
#define P1_Q4_RX_CONTEXT_OFFSET			P1_Q3_RX_CONTEXT_OFFSET + 8
#define P1_Q3_RX_CONTEXT_OFFSET			P1_Q2_RX_CONTEXT_OFFSET + 8
#define P1_Q2_RX_CONTEXT_OFFSET			P1_Q1_RX_CONTEXT_OFFSET + 8
#define P1_Q1_RX_CONTEXT_OFFSET			RX_CONTEXT_P1_Q1_OFFSET_ADDR
#define RX_CONTEXT_P1_Q1_OFFSET_ADDR	P0_Q4_RX_CONTEXT_OFFSET + 8

// Host Port Rx Context
#define P0_Q4_RX_CONTEXT_OFFSET			P0_Q3_RX_CONTEXT_OFFSET + 8
#define P0_Q3_RX_CONTEXT_OFFSET			P0_Q2_RX_CONTEXT_OFFSET + 8
#define P0_Q2_RX_CONTEXT_OFFSET			P0_Q1_RX_CONTEXT_OFFSET + 8
#define P0_Q1_RX_CONTEXT_OFFSET			RX_CONTEXT_P0_Q1_OFFSET_ADDR
#define RX_CONTEXT_P0_Q1_OFFSET_ADDR	COL_TX_CONTEXT_P2_Q1_OFFSET_ADDR + 8

// Port 2 Tx Collision Context
#define COL_TX_CONTEXT_P2_Q1_OFFSET_ADDR	COL_TX_CONTEXT_P1_Q1_OFFSET_ADDR + 8
// Port 1 Tx Collision Context
#define COL_TX_CONTEXT_P1_Q1_OFFSET_ADDR	P2_Q4_TX_CONTEXT_OFFSET + 8

// Port 2
#define P2_Q4_TX_CONTEXT_OFFSET			P2_Q3_TX_CONTEXT_OFFSET + 8
#define P2_Q3_TX_CONTEXT_OFFSET			P2_Q2_TX_CONTEXT_OFFSET + 8
#define P2_Q2_TX_CONTEXT_OFFSET			P2_Q1_TX_CONTEXT_OFFSET + 8
#define P2_Q1_TX_CONTEXT_OFFSET			TX_CONTEXT_P2_Q1_OFFSET_ADDR
#define TX_CONTEXT_P2_Q1_OFFSET_ADDR	P1_Q4_TX_CONTEXT_OFFSET + 8
// Port 1
#define P1_Q4_TX_CONTEXT_OFFSET			P1_Q3_TX_CONTEXT_OFFSET + 8
#define P1_Q3_TX_CONTEXT_OFFSET			P1_Q2_TX_CONTEXT_OFFSET + 8
#define P1_Q2_TX_CONTEXT_OFFSET			P1_Q1_TX_CONTEXT_OFFSET + 8
#define P1_Q1_TX_CONTEXT_OFFSET			TX_CONTEXT_P1_Q1_OFFSET_ADDR
#define TX_CONTEXT_P1_Q1_OFFSET_ADDR	0x1D00

// PRU0 Data Memory

//****************************************************************************
//*                       ICSS PRU0 DRAM Mem Usage                           *
//* Please update all mem usage here to make it easier for other developers  *
//*       Not updating memory usage leads to difficult to fix errors         *
//****************************************************************************
#define ICSS_PRU0_DRAM_FREE_MEM_SIZE        ICSS_PRU0_DRAM_FREE_MEM_END - ICSS_PRU0_DRAM_FREE_MEM_START
#define ICSS_PRU0_DRAM_FREE_MEM_END         0x1f00
#define ICSS_PRU0_DRAM_FREE_MEM_START       PROTOCOL_SPECIFIC_DRAM_MEMORY_OFFSET + PROTOCOL_SPECIFIC_DRAM_MEMORY_SIZE


//Memory from 0 to 0x200 on PRU0 DRAM is reserved for protocol specific usage
//Do not use this memory
#define PROTOCOL_SPECIFIC_DRAM_MEMORY_SIZE       0x200
#define PROTOCOL_SPECIFIC_DRAM_MEMORY_OFFSET     0x0

//****************************************************************************
//*                       ICSS Shared RAM Mem Usage                          *
//* Please update all mem usage here to make it easier for other developers  *
//*       Not updating memory usage leads to difficult to fix errors         *
//****************************************************************************

#define ICSS_SHARED_FREE_MEM_SIZE           ICSS_SHARED_FREE_MEM_END - ICSS_SHARED_FREE_MEM_START
#define ICSS_SHARED_FREE_MEM_END            0x1f00
#define ICSS_SHARED_FREE_MEM_START          PROTOCOL_SPECIFIC_SRAM_MEMORY_OFFSET + PROTOCOL_SPECIFIC_SRAM_MEMORY_SIZE + 4

//Memory from 0 to 0x200 on Shared DRAM is reserved for protocol specific usage
//Do not use this memory
#define PROTOCOL_SPECIFIC_SRAM_MEMORY_SIZE       0x100
#define PROTOCOL_SPECIFIC_SRAM_MEMORY_OFFSET     RX_INT_STATUS_OFFSET + 1 //word aligned
//****************************************************************************
#define RX_INT_STATUS_OFFSET				STAT_CTRL_OFFSET + 1	     //1 byte

#define STAT_CTRL_OFFSET                    COLLISION_COUNTER_PORT1 + 1
#define COLLISION_COUNTER_PORT1             COLLISION_COUNTER_PORT0 + 1  //1 byte
#define COLLISION_COUNTER_PORT0             PORT_STATUS_OFFSET + 4       //4 byte
#define PORT_STATUS_OFFSET					MULTICAST_LAST_VALID_ADDR_OFFSET + 12 

// ICSS Shared RAM 12kB
#define MULTICAST_FIRST_VALID_ADDR_OFFSET	0x1c40   //6 bytes
#define	MULTICAST_LAST_VALID_ADDR_OFFSET	0x1c48   //6 bytes

#define STATIC_MAC_TABLE_FWD_PORT2	STATIC_MAC_TABLE_RCV_PORT2  + 256
#define STATIC_MAC_TABLE_RCV_PORT2	STATIC_MAC_TABLE_FWD_PORT1 + 256  
#define STATIC_MAC_TABLE_FWD_PORT1	STATIC_MAC_TABLE_RCV_PORT1  + 256
#define STATIC_MAC_TABLE_RCV_PORT1	EOF_COL_BUFFER_BD

#define EOF_COL_BUFFER_BD       P0_COL_BD_OFFSET + 3* BD_SIZE * 48
#define P2_COL_BD_OFFSET		P1_COL_BD_OFFSET  + BD_SIZE * 48
#define P1_COL_BD_OFFSET		P0_COL_BD_OFFSET  + BD_SIZE * 48
#define P0_COL_BD_OFFSET		EOF_48K_BUFFER_BD						

// allow for max 48k switch buffer which spans the descriptors up to 0x1800 6kB
#define EOF_48K_BUFFER_BD       P0_BUFFER_DESC_OFFSET + 0x1800

#define P2_Q4_BD_OFFSET			P2_Q3_BD_OFFSET + QUEUE_3_SIZE * BD_SIZE
#define P2_Q3_BD_OFFSET			P2_Q2_BD_OFFSET + QUEUE_2_SIZE * BD_SIZE
#define P2_Q2_BD_OFFSET			P2_Q1_BD_OFFSET + QUEUE_1_SIZE * BD_SIZE
#define P2_Q1_BD_OFFSET			P1_Q4_BD_OFFSET + QUEUE_4_SIZE * BD_SIZE
#define P1_Q4_BD_OFFSET			P1_Q3_BD_OFFSET + QUEUE_3_SIZE * BD_SIZE
#define P1_Q3_BD_OFFSET			P1_Q2_BD_OFFSET + QUEUE_2_SIZE * BD_SIZE
#define P1_Q2_BD_OFFSET			P1_Q1_BD_OFFSET + QUEUE_1_SIZE * BD_SIZE
#define P1_Q1_BD_OFFSET			P0_Q4_BD_OFFSET + HOST_QUEUE_4_SIZE * BD_SIZE
#define P0_Q4_BD_OFFSET			P0_Q3_BD_OFFSET + HOST_QUEUE_3_SIZE * BD_SIZE
#define P0_Q3_BD_OFFSET			P0_Q2_BD_OFFSET + HOST_QUEUE_2_SIZE * BD_SIZE
#define P0_Q2_BD_OFFSET			P0_Q1_BD_OFFSET + HOST_QUEUE_1_SIZE * BD_SIZE
#define P0_Q1_BD_OFFSET			P0_BUFFER_DESC_OFFSET
#define	P0_BUFFER_DESC_OFFSET	0x400			// host port buffer descriptor offset


// L3 64KB Memory - mainly buffer Pool
// put collision buffer at end of L3 memory. Simplifies PRU coding to be on same memory as queue buffer
#define P2_COL_BUFFER_OFFSET    0xFA00	// 1536 byte collision buffer for port 2 send queue
#define P1_COL_BUFFER_OFFSET    0xF400	// 1536 byte collision buffer for port 1 send queue
#define P0_COL_BUFFER_OFFSET    0xEE00	// 1536 byte collision buffer for port 0 send queue

#define END_OF_BUFFER_POOL		P2_Q4_BUFFER_OFFSET + QUEUE_4_SIZE * BLOCK_SIZE
#define P2_Q4_BUFFER_OFFSET     P2_Q3_BUFFER_OFFSET + QUEUE_3_SIZE * BLOCK_SIZE
#define P2_Q3_BUFFER_OFFSET     P2_Q2_BUFFER_OFFSET + QUEUE_2_SIZE * BLOCK_SIZE
#define P2_Q2_BUFFER_OFFSET     P2_Q1_BUFFER_OFFSET + QUEUE_1_SIZE * BLOCK_SIZE
#define P2_Q1_BUFFER_OFFSET     P1_Q4_BUFFER_OFFSET + QUEUE_4_SIZE * BLOCK_SIZE
#define P1_Q4_BUFFER_OFFSET     P1_Q3_BUFFER_OFFSET + QUEUE_3_SIZE * BLOCK_SIZE
#define P1_Q3_BUFFER_OFFSET     P1_Q2_BUFFER_OFFSET + QUEUE_2_SIZE * BLOCK_SIZE
#define P1_Q2_BUFFER_OFFSET     P1_Q1_BUFFER_OFFSET + QUEUE_1_SIZE * BLOCK_SIZE
#define P1_Q1_BUFFER_OFFSET     P0_Q4_BUFFER_OFFSET + HOST_QUEUE_4_SIZE * BLOCK_SIZE
#define P0_Q4_BUFFER_OFFSET     P0_Q3_BUFFER_OFFSET + HOST_QUEUE_3_SIZE * BLOCK_SIZE
#define P0_Q3_BUFFER_OFFSET     P0_Q2_BUFFER_OFFSET + HOST_QUEUE_2_SIZE * BLOCK_SIZE
#define P0_Q2_BUFFER_OFFSET     P0_Q1_BUFFER_OFFSET + HOST_QUEUE_1_SIZE * BLOCK_SIZE
#define P0_Q1_BUFFER_OFFSET		0x0000

#ifdef PRU
// Collision Status Register
.struct struct_collision_status
    .u8		port0	   	// port 0 pending and queue number
    .u8		port1      	// port 1 pending and queue number
	.u8		port2		// port 2 pending and queue number
.ends

#define 	P0_COLLISION_PENDING 	t0
#define 	P1_COLLISION_PENDING 	t8
#define		P2_COLLISION_PENDING 	t16


#endif

// switch configuration
// enable ports : receive enable , transmit enable, block, learning, flush table, age out table (older are removed), tear
// rate limiting setup
// filter database setup for MC
// learn multicast option one for both ports
// learn broadcast option one for both ports
// statistics clear
#endif

