/**
* @file icss_common.h
*
* @brief Contains common macros and function definitions
*
* \par
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
* \par
*/
#ifndef _ICSS_COMMON_H_
#define _ICSS_COMMON_H_


/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
#include <xdc/std.h>
#include <xdc/cfg/global.h>
#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
#include <stdio.h>
#include "icss_switch_init_cfg.h"
#include <soc_AM335x.h>
#include "hw/hw_control_AM335x.h"
#include <hw/hw_types.h>
#include "osdrv_prussdefs.h"
#include "phy.h"
#include "plat_utils.h"
/*BIOS includes*/
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/knl/Semaphore.h>
#include <ti/sysbios/timers/dmtimer/Timer.h>
#include <ti/sysbios/knl/Clock.h>

/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */

/*Hardware dependent macros*/
/**
* @def ICSS_MDIO_BASEADDR
*      ICSS MDIO Base address
*/
#define ICSS_MDIO_BASEADDR				    (0x4A332400U)

/**
* @def ICSS_MDIO_ALIVE_OFFSET
*
*/
#define ICSS_MDIO_ALIVE_OFFSET	0x8
/**
* @def ICSS_MDIO_LINK_OFFSET
*
*/
#define ICSS_MDIO_LINK_OFFSET 0xC
/**
* @def ICSS_MDIO_LINKINT_RAW_MASK_OFFSET
*
*/
#define ICSS_MDIO_LINKINT_RAW_MASK_OFFSET	0x14
/**
* @def ICSS_MDIO_LINK0_STATUS_MASK
*
*/
#define ICSS_MDIO_LINK0_STATUS_MASK			0x2
/**
* @def ICSS_MDIO_LINK0_STATUS_SHIFT
*
*/
#define ICSS_MDIO_LINK0_STATUS_SHIFT  		0x1
/**
* @def ICSS_MDIO_ICEV2_LINK1_STATUS_MASK
*
*/
#define ICSS_MDIO_ICEV2_LINK1_STATUS_MASK   0x8
/**
* @def ICSS_MDIO_ICEV2_LINK1_STATUS_SHIFT
*
*/
#define ICSS_MDIO_ICEV2_LINK1_STATUS_SHIFT   0x3
/**
* @def ICSS_MDIO_ICEV1_LINK1_STATUS_MASK
*
*/
#define ICSS_MDIO_ICEV1_LINK1_STATUS_MASK	0x4
/**
* @def ICSS_MDIO_ICEV1_LINK1_STATUS_SHIFT
*
*/
#define ICSS_MDIO_ICEV1_LINK1_STATUS_SHIFT	0x2
/**
* @def ICSS_MDIO_ICEV2_BOTH_LINKS_UP_VAL
*
*/
#define ICSS_MDIO_ICEV2_BOTH_LINKS_UP_VAL	0xA
/**
* @def ICSS_MDIO_ICEV1_BOTH_LINKS_UP_VAL
*
*/
#define ICSS_MDIO_ICEV1_BOTH_LINKS_UP_VAL	0x6

/**
* @def ICSS_RX_PULSE_INTNUM
*      Interrupt number to the ARM CPU
*/
#define ICSS_RX_PULSE_INTNUM                 20
/**
* @def ICSS_LINK0_STAT_INTNUM
*      Link 0 Status Interrupt number from MDIO to ARM
*/
#define ICSS_LINK0_STAT_INTNUM                25
/**
* @def ICSS_LINK1_STAT_INTNUM
*      Link 1 Status Interrupt number from MDIO to ARM
*/
#define ICSS_LINK1_STAT_INTNUM                26

/**
* @def CLR_INT22
*      Clear Interrupt 22
*/
#define CLR_INT22  HWREG(0x4a320280) = 0x00400000;
/**
* @def CLR_INT23
*      Clear Interrupt  23
*/
#define CLR_INT23  HWREG(0x4a320280) = 0x00800000;
/**
* @def CLR_INT23
*      Clear Interrupt  24
*/
#define CLR_INT24  HWREG(0x4a320280) = 0x01000000;
/**
* @def DLR_MDIO_POLL_REG
*      MDIO Poll register for DLR implementation
*/
#define DLR_MDIO_POLL_REG 	0x4a33240C
/**
* @def DMTIMER_SRC_CLK_FREQ
*      DMtimer Clock Frequency
*/
#define DMTIMER_SRC_CLK_FREQ 	24000000
/**
* @def DMTIMER3_ID
*      DMTIMER3_ID
*/
#define DMTIMER3_ID			1
/**
* @def DMTIMER4_ID
*      DMTIMER4_ID
*/
#define DMTIMER4_ID 		2
/**
* @def DMTIMER5_ID
*      DMTIMER5_ID
*/
#define DMTIMER5_ID			3
/**
* @def PRU_SHARED_DRAM_BASE_ADDRESS
*      PRUSS shared ram base address
*/
#define PRU_SHARED_DRAM_BASE_ADDRESS    PRUSS_SHAREDRAM_BASE //PRUSS Shared mem
/**
* @def PRU0_DRAM_BASE_ADDRESS
*      Pru0 Dram base address
*/
#define PRU0_DRAM_BASE_ADDRESS 			DATARAM0_PHYS_BASE  // PRUSS PRU0 DMEM
/**
* @def PRU1_DRAM_BASE_ADDRESS
*      Pru1 Dram base address
*/
#define PRU1_DRAM_BASE_ADDRESS 			DATARAM1_PHYS_BASE  // PRUSS PRU1 DMEM
/**
* @def HWPORT0
*      H/w port 0(Physical port)
*/
#define HWPORT0     0
/**
* @def HWPORT1
*      H/w port 1(Physical port)
*/
#define HWPORT1     1
/**
* @def FALSE_VAL
*      Return value False
*/
#define FALSE_VAL  0
/**
* @def TRUE_VAL
*      Return value True
*/
#define TRUE_VAL   1

/** Enabling this allows one to view multiple system events based on chronology*/
//#define ENABLE_SYSTEM_LEVEL_DEBUGGING

/**Gives numbers to system events for debugging*/
#ifdef ENABLE_SYSTEM_LEVEL_DEBUGGING
#define LINK0_LOST  	0
#define LINK1_LOST  	1
#define LINK0_UP    	2
#define LINK1_UP    	3
#define TX_PKT			4
#define RX_PKT			5
#define USER_EVENT_1	6
#define USER_EVENT_2	7
#endif

//typedef void*       Handle; cancellato perchè da un warning;

#endif /* _ICSS_COMMON_H_ */
