#ifndef _PINMUX_H_
#define _PINMUX_H_

/*
 * MODE0 - Mux Mode 0
 * MODE1 - Mux Mode 1
 * MODE2 - Mux Mode 2
 * MODE3 - Mux Mode 3
 * MODE4 - Mux Mode 4
 * MODE5 - Mux Mode 5
 * MODE6 - Mux Mode 6
 * MODE7 - Mux Mode 7
 * IDIS - Receiver disabled
 * IEN - Receiver enabled
 * PD - Internal pull-down
 * PU - Internal pull-up
 * OFF - Internal pull disabled
 */

#define MUX_EVM() \

/* Design Status: NO ERRORS */

MUX_VAL(CONTROL_PADCONF_GPMC_AD0, (IEN | PD | MODE0 )) /* gpmc_ad0 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD1, (IEN | PD | MODE0 )) /* gpmc_ad1 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD2, (IEN | PD | MODE0 )) /* gpmc_ad2 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD3, (IEN | PD | MODE0 )) /* gpmc_ad3 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD4, (IEN | PD | MODE0 )) /* gpmc_ad4 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD5, (IEN | PD | MODE0 )) /* gpmc_ad5 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD6, (IEN | PD | MODE0 )) /* gpmc_ad6 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD7, (IEN | PD | MODE0 )) /* gpmc_ad7 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD8, (IEN | PD | MODE0 )) /* gpmc_ad8 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD9, (IEN | PD | MODE0 )) /* gpmc_ad9 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD10, (IEN | PD | MODE0 )) /* gpmc_ad10 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD11, (IEN | PD | MODE0 )) /* gpmc_ad11 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD12, (IEN | PD | MODE0 )) /* gpmc_ad12 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD13, (IEN | PD | MODE0 )) /* gpmc_ad13 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD14, (IEN | PD | MODE0 )) /* gpmc_ad14 */\
MUX_VAL(CONTROL_PADCONF_GPMC_AD15, (IEN | PD | MODE0 )) /* gpmc_ad15 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A0, (IEN | PD | MODE5 )) /* pr1_mii_mt1_clk */\
MUX_VAL(CONTROL_PADCONF_GPMC_A1, (IDIS | PD | MODE5 )) /* pr1_mii1_txd3 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A2, (IDIS | PD | MODE5 )) /* pr1_mii1_txd2 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A3, (IDIS | PD | MODE5 )) /* pr1_mii1_txd1 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A4, (IDIS | PD | MODE5 )) /* pr1_mii1_txd0 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A5, (IEN | PD | MODE5 )) /* pr1_mii1_rxd3 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A6, (IEN | PD | MODE5 )) /* pr1_mii1_rxd2 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A7, (IEN | PD | MODE5 )) /* pr1_mii1_rxd1 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A8, (IEN | PD | MODE5 )) /* pr1_mii1_rxd0 */\
MUX_VAL(CONTROL_PADCONF_GPMC_A9, (IEN | PD | MODE5 )) /* pr1_mii_mr1_clk */\
MUX_VAL(CONTROL_PADCONF_GPMC_A10, (IEN | PD | MODE5 )) /* pr1_mii1_rxdv */\
MUX_VAL(CONTROL_PADCONF_GPMC_A11, (IEN | PD | MODE5 )) /* pr1_mii1_rxer */\
MUX_VAL(CONTROL_PADCONF_GPMC_WAIT0, (IEN | PU | MODE0 )) /* gpmc_wait0 */\
MUX_VAL(CONTROL_PADCONF_GPMC_WPN, (IDIS | PU | MODE5 )) /* pr1_mii1_txen */\
MUX_VAL(CONTROL_PADCONF_GPMC_BEN1, (IEN | PU | MODE5 )) /* pr1_mii1_rxlink */\
MUX_VAL(CONTROL_PADCONF_GPMC_CSN0, (IDIS | PU | MODE0 )) /* gpmc_csn0 */\
MUX_VAL(CONTROL_PADCONF_GPMC_CSN1, (IEN | PU | MODE1 )) /* gpmc_clk_mux1 */\
MUX_VAL(CONTROL_PADCONF_GPMC_CSN2, (IDIS | PU | MODE0 )) /* gpmc_csn2 */\
MUX_VAL(CONTROL_PADCONF_GPMC_CSN3, (IEN | PU | MODE5 )) /* pr1_mdio_data */\
MUX_VAL(CONTROL_PADCONF_GPMC_CLK, (IDIS | PD | MODE5 )) /* pr1_mdio_mdclk */\
MUX_VAL(CONTROL_PADCONF_GPMC_ADVN_ALE, (IDIS | PU | MODE0 )) /* gpmc_advn_ale */\
MUX_VAL(CONTROL_PADCONF_GPMC_OEN_REN, (IDIS | PU | MODE0 )) /* gpmc_oen_ren */\
MUX_VAL(CONTROL_PADCONF_GPMC_WEN, (IDIS | PU | MODE0 )) /* gpmc_wen */\
MUX_VAL(CONTROL_PADCONF_GPMC_BEN0_CLE, (IDIS | PU | MODE0 )) /* gpmc_be0n_cle */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA0, (IEN | OFF | MODE2 )) /* pr1_mii_mt0_clk_mux1 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA1, (IDIS | OFF | MODE2 )) /* pr1_mii0_txen_mux1 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA2, (IDIS | OFF | MODE2 )) /* pr1_mii0_txd3_mux1 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA3, (IDIS | OFF | MODE2 )) /* pr1_mii0_txd2_mux1 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA4, (IDIS | OFF | MODE2 )) /* pr1_mii0_txd1_mux1 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA5, (IDIS | OFF | MODE2 )) /* pr1_mii0_txd0_mux1 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA6, (IEN | OFF | MODE7 )) /* gpio2[12] */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA7, (IEN | OFF | MODE7 )) /* gpio2[13] */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA8, (IEN | OFF | MODE2 )) /* ehrpwm1_tripzone_input_mux0 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA9, (IEN | OFF | MODE7 )) /* gpio2[15] */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA10, (IDIS | OFF | MODE2 )) /* ehrpwm1A_mux0 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA11, (IDIS | OFF | MODE2 )) /* ehrpwm1B_mux0 */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA12, (IEN | OFF | MODE5 )) /* pr1_mii0_rxlink */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA13, (IEN | OFF | MODE5 )) /* pr1_mii0_rxer */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA14, (IEN | OFF | MODE5 )) /* pr1_mii_mr0_clk */\
MUX_VAL(CONTROL_PADCONF_LCD_DATA15, (IEN | OFF | MODE5 )) /* pr1_mii0_rxdv */\
MUX_VAL(CONTROL_PADCONF_LCD_VSYNC, (IEN | OFF | MODE6 )) /* pr1_pru1_pru_r31[8] */\
MUX_VAL(CONTROL_PADCONF_LCD_HSYNC, (IEN | OFF | MODE6 )) /* pr1_pru1_pru_r31[9] */\
MUX_VAL(CONTROL_PADCONF_LCD_PCLK, (IEN | OFF | MODE6 )) /* pr1_pru1_pru_r31[10] */\
MUX_VAL(CONTROL_PADCONF_LCD_AC_BIAS_EN, (IEN | OFF | MODE6 )) /* pr1_pru1_pru_r31[11] */\
MUX_VAL(CONTROL_PADCONF_MMC0_DAT3, (IEN | PU | MODE0 )) /* mmc0_dat3 */\
MUX_VAL(CONTROL_PADCONF_MMC0_DAT2, (IEN | PU | MODE0 )) /* mmc0_dat2 */\
MUX_VAL(CONTROL_PADCONF_MMC0_DAT1, (IEN | PU | MODE0 )) /* mmc0_dat1 */\
MUX_VAL(CONTROL_PADCONF_MMC0_DAT0, (IEN | PU | MODE0 )) /* mmc0_dat0 */\
MUX_VAL(CONTROL_PADCONF_MMC0_CLK, (IEN | PU | MODE0 )) /* mmc0_clk */\
MUX_VAL(CONTROL_PADCONF_MMC0_CMD, (IEN | PU | MODE0 )) /* mmc0_cmd */\
MUX_VAL(CONTROL_PADCONF_MII1_COL, (IEN | PD | MODE7 )) /* gpio3[0] */\
MUX_VAL(CONTROL_PADCONF_MII1_CRS, (IEN | PD | MODE7 )) /* gpio3[1] */\
MUX_VAL(CONTROL_PADCONF_MII1_RX_ER, (IEN | PD | MODE0 )) /* gmii1_rxer */\
MUX_VAL(CONTROL_PADCONF_MII1_TX_EN, (IDIS | PD | MODE0 )) /* gmii1_txen */\
MUX_VAL(CONTROL_PADCONF_MII1_RX_DV, (IEN | PD | MODE0 )) /* gmii1_rxdv */\
MUX_VAL(CONTROL_PADCONF_MII1_TXD3, (IDIS | PD | MODE0 )) /* gmii1_txd3 */\
MUX_VAL(CONTROL_PADCONF_MII1_TXD2, (IDIS | PD | MODE0 )) /* gmii1_txd2 */\
MUX_VAL(CONTROL_PADCONF_MII1_TXD1, (IDIS | PD | MODE0 )) /* gmii1_txd1 */\
MUX_VAL(CONTROL_PADCONF_MII1_TXD0, (IDIS | PD | MODE0 )) /* gmii1_txd0 */\
MUX_VAL(CONTROL_PADCONF_MII1_TX_CLK, (IEN | PD | MODE0 )) /* gmii1_txclk */\
MUX_VAL(CONTROL_PADCONF_MII1_RX_CLK, (IEN | PD | MODE0 )) /* gmii1_rxclk */\
MUX_VAL(CONTROL_PADCONF_MII1_RXD3, (IEN | PD | MODE0 )) /* gmii1_rxd3 */\
MUX_VAL(CONTROL_PADCONF_MII1_RXD2, (IEN | PD | MODE0 )) /* gmii1_rxd2 */\
MUX_VAL(CONTROL_PADCONF_MII1_RXD1, (IEN | PD | MODE0 )) /* gmii1_rxd1 */\
MUX_VAL(CONTROL_PADCONF_MII1_RXD0, (IEN | PD | MODE0 )) /* gmii1_rxd0 */\
MUX_VAL(CONTROL_PADCONF_RMII1_REF_CLK, (IEN | PU | MODE7 )) /* gpio0[29] */\
MUX_VAL(CONTROL_PADCONF_MDIO, (IEN | PU | MODE0 )) /* mdio_data */\
MUX_VAL(CONTROL_PADCONF_MDC, (IDIS | PU | MODE0 )) /* mdio_clk */\
MUX_VAL(CONTROL_PADCONF_SPI0_SCLK, (IEN | OFF | MODE0 )) /* spi0_sclk */\
MUX_VAL(CONTROL_PADCONF_SPI0_D0, (IEN | OFF | MODE0 )) /* spi0_d0 */\
MUX_VAL(CONTROL_PADCONF_SPI0_D1, (IEN | OFF | MODE0 )) /* spi0_d1 */\
MUX_VAL(CONTROL_PADCONF_SPI0_CS0, (IEN | OFF | MODE0 )) /* spi0_cs0 */\
MUX_VAL(CONTROL_PADCONF_SPI0_CS1, (IEN | OFF | MODE1 )) /* uart3_rxd_mux1 */\
MUX_VAL(CONTROL_PADCONF_ECAP0_IN_PWM0_OUT, (IDIS | OFF | MODE1 )) /* uart3_txd_mux1 */\
MUX_VAL(CONTROL_PADCONF_UART0_CTSN, (IEN | OFF | MODE7 )) /* gpio1[8] */\
MUX_VAL(CONTROL_PADCONF_UART0_RTSN, (IEN | OFF | MODE7 )) /* gpio1[9] */\
MUX_VAL(CONTROL_PADCONF_UART0_RXD, (IEN | OFF | MODE7 )) /* gpio1[10] */\
MUX_VAL(CONTROL_PADCONF_UART0_TXD, (IEN | OFF | MODE7 )) /* gpio1[11] */\
MUX_VAL(CONTROL_PADCONF_UART1_CTSN, (IEN | OFF | MODE7 )) /* gpio0[12] */\
MUX_VAL(CONTROL_PADCONF_UART1_RTSN, (IEN | OFF | MODE7 )) /* gpio0[13] */\
MUX_VAL(CONTROL_PADCONF_UART1_RXD, (IDIS | OFF | MODE2 )) /* dcan1_tx_mux1 */\
MUX_VAL(CONTROL_PADCONF_UART1_TXD, (IEN | OFF | MODE2 )) /* dcan1_rx_mux1 */\
MUX_VAL(CONTROL_PADCONF_I2C0_SDA, (IEN | OFF | MODE0 )) /* I2C0_SDA */\
MUX_VAL(CONTROL_PADCONF_I2C0_SCL, (IEN | OFF | MODE0 )) /* I2C0_SCL */\
MUX_VAL(CONTROL_PADCONF_MCASP0_ACLKX, (IEN | PD | MODE7 )) /* gpio3[14] */\
MUX_VAL(CONTROL_PADCONF_MCASP0_FSX, (IEN | PD | MODE7 )) /* gpio3[15] */\
MUX_VAL(CONTROL_PADCONF_MCASP0_AXR0, (IEN | PD | MODE7 )) /* gpio3[16] */\
MUX_VAL(CONTROL_PADCONF_MCASP0_AHCLKR, (IEN | PD | MODE7 )) /* gpio3[17] */\
MUX_VAL(CONTROL_PADCONF_MCASP0_ACLKR, (IEN | PD | MODE1 )) /* eQEP0A_in_mux0 */\
MUX_VAL(CONTROL_PADCONF_MCASP0_FSR, (IEN | PD | MODE1 )) /* eQEP0B_in_mux0 */\
MUX_VAL(CONTROL_PADCONF_MCASP0_AXR1, (IEN | PD | MODE1 )) /* eQEP0_index_mux0 */\
MUX_VAL(CONTROL_PADCONF_MCASP0_AHCLKX, (IEN | PD | MODE1 )) /* eQEP0_strobe_mux0 */\
MUX_VAL(CONTROL_PADCONF_XDMA_EVENT_INTR0, (IDIS | OFF | MODE3 )) /* clkout1 */\
MUX_VAL(CONTROL_PADCONF_XDMA_EVENT_INTR1, (IDIS | OFF | MODE3 )) /* clkout2 */\
MUX_VAL(CONTROL_PADCONF_WARMRSTN, (IEN | OFF | MODE0 )) /* nRESETIN_OUT */\
MUX_VAL(CONTROL_PADCONF_EXTINTN, (IEN | OFF | MODE0 )) /* nNMI */\
MUX_VAL(CONTROL_PADCONF_TMS, (IEN | PU | MODE0 )) /* TMS */\
MUX_VAL(CONTROL_PADCONF_TDI, (IEN | PU | MODE0 )) /* TDI */\
MUX_VAL(CONTROL_PADCONF_TDO, (IDIS | PU | MODE0 )) /* TDO */\
MUX_VAL(CONTROL_PADCONF_TCK, (IEN | PU | MODE0 )) /* TCK */\
MUX_VAL(CONTROL_PADCONF_TRSTN, (IEN | PD | MODE0 )) /* nTRST */\
MUX_VAL(CONTROL_PADCONF_EMU0, (IEN | PU | MODE0 )) /* EMU0 */\
MUX_VAL(CONTROL_PADCONF_EMU1, (IEN | PU | MODE0 )) /* EMU1 */\
MUX_VAL(CONTROL_PADCONF_RTC_PWRONRSTN, (IEN | OFF | MODE0 )) /* RTC_porz */\
MUX_VAL(CONTROL_PADCONF_PMIC_POWER_EN, (IDIS | PU | MODE0 )) /* PMIC_POWER_EN */\
MUX_VAL(CONTROL_PADCONF_EXT_WAKEUP, (IEN | PD | MODE0 )) /* EXT_WAKEUP */\
MUX_VAL(CONTROL_PADCONF_RTC_KALDO_ENN, (IEN | OFF | MODE0 )) /* ENZ_KALDO_1P8V */\
MUX_VAL(CONTROL_PADCONF_USB0_DRVVBUS, (IDIS | PD | MODE0 )) /* USB0_DRVVBUS */\
MUX_VAL(CONTROL_PADCONF_USB1_DRVVBUS, (IEN | PD | MODE7 )) /* gpio3[13] */\

#endif
