/*
 * \file   drivers.c
 *
 * \brief
 *
*/
#include "drivers.h"
#include "plat_mux.h"
#include "hw_control_AM335x.h"
#include "plat_utils.h"
#include "edma.h"
#include "evmskAM335x.h"
#include "sys_utils.h"

MUX_CONFIG iard_mux[] = {

	// PROFIBUS
	{ CONTROL_CONF_UART_RXD(1), 5, AM335X_PIN_INPUT },	// pr1_uart0_rxd
    { CONTROL_CONF_UART_TXD(1), 5, AM335X_PIN_OUTPUT },	// pr1_uart0_txd
	{ CONTROL_CONF_MCASP0_FSR, 	5, AM335X_PIN_OUTPUT },	// pr1_pru0_pru_r30[5]

	// I2C
    { CONTROL_CONF_I2C0_SDA, 0, AM335X_PIN_INPUT },	// i2c0_sda
    { CONTROL_CONF_I2C0_SCL, 0, AM335X_PIN_INPUT },	// i2c0_scl

    // GPMC (General Purpouse Memory Controller)
    { CONTROL_CONF_GPMC_ADVN_ALE, 	0, AM335X_PIN_OUTPUT_PULLUP },	// gpmc_advn_ale
    { CONTROL_CONF_GPMC_OEN_REN,	0, AM335X_PIN_OUTPUT_PULLUP },	// gpmc_oen_ren
    { CONTROL_CONF_GPMC_WEN, 		0, AM335X_PIN_OUTPUT_PULLUP },	// gpmc_wen
    { CONTROL_CONF_GPMC_BE0N_CLE,	0, AM335X_PIN_OUTPUT_PULLUP },	// gpmc_be0n_cle
    { CONTROL_CONF_GPMC_AD(0), 		0, AM335X_PIN_INPUT_PULLDOWN }, // GPMC_AD0
    { CONTROL_CONF_GPMC_AD(1), 		0, AM335X_PIN_INPUT_PULLDOWN }, // GPMC_AD1
    { CONTROL_CONF_GPMC_AD(2), 		0, AM335X_PIN_INPUT_PULLDOWN }, // GPMC_AD2
    { CONTROL_CONF_GPMC_AD(3), 		0, AM335X_PIN_INPUT_PULLDOWN }, // GPMC_AD3
    { CONTROL_CONF_GPMC_AD(4), 		0, AM335X_PIN_INPUT_PULLDOWN }, // GPMC_AD4
    { CONTROL_CONF_GPMC_AD(5), 		0, AM335X_PIN_INPUT_PULLDOWN }, // GPMC_AD5
    { CONTROL_CONF_GPMC_AD(6), 		0, AM335X_PIN_INPUT_PULLDOWN }, // GPMC_AD6
    { CONTROL_CONF_GPMC_AD(7), 		0, AM335X_PIN_INPUT_PULLDOWN }, // GPMC_AD7
    { CONTROL_CONF_GPMC_AD(8), 		0, AM335X_PIN_INPUT_PULLDOWN }, // GPMC_AD8
    { CONTROL_CONF_GPMC_AD(9), 		0, AM335X_PIN_INPUT_PULLDOWN }, // GPMC_AD9
    { CONTROL_CONF_GPMC_AD(10), 	0, AM335X_PIN_INPUT_PULLDOWN }, // GPMC_AD10
    { CONTROL_CONF_GPMC_AD(11), 	0, AM335X_PIN_INPUT_PULLDOWN }, // GPMC_AD11
    { CONTROL_CONF_GPMC_AD(12), 	0, AM335X_PIN_INPUT_PULLDOWN }, // GPMC_AD12
    { CONTROL_CONF_GPMC_AD(13), 	0, AM335X_PIN_INPUT_PULLDOWN }, // GPMC_AD13
    { CONTROL_CONF_GPMC_AD(14), 	0, AM335X_PIN_INPUT_PULLDOWN }, // GPMC_AD14
    { CONTROL_CONF_GPMC_AD(15), 	0, AM335X_PIN_INPUT_PULLDOWN }, // GPMC_AD15
    { CONTROL_CONF_GPMC_WAIT0, 		0, AM335X_PIN_INPUT_PULLUP }, 	// GPMC_WAIT0
    { CONTROL_CONF_GPMC_CSN(0), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// GPMC_CSN0
    { CONTROL_CONF_GPMC_CSN(1), 	1, AM335X_PIN_INPUT_PULLUP }, 	// GPMC_CSN1
    { CONTROL_CONF_GPMC_CSN(2), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// GPMC_CSN2
    { CONTROL_CONF_GPMC_ADVN_ALE, 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// GPMC_ADVN_ALE
    { CONTROL_CONF_GPMC_OEN_REN, 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// GPMC_OEN_REN
    { CONTROL_CONF_GPMC_WEN, 		0, AM335X_PIN_OUTPUT_PULLUP }, 	// GPMC_WEN
    { CONTROL_CONF_GPMC_BE0N_CLE, 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// GPMC_BEN0_CLE
    { CONTROL_CONF_USB_DRVVBUS(1), 	7, AM335X_PIN_INPUT_PULLDOWN }, // GPMC_WPN

    // ETHERCAT
    { CONTROL_CONF_GPMC_A(0), 	5, AM335X_PIN_INPUT_PULLDOWN },		// pr1_mii_mt1_clk	gpmc_a0
    { CONTROL_CONF_GPMC_A(1), 	5, AM335X_PIN_OUTPUT },				// pr1_mii1_txd3
    { CONTROL_CONF_GPMC_A(2), 	5, AM335X_PIN_OUTPUT },				// pr1_mii1_txd2
    { CONTROL_CONF_GPMC_A(3), 	5, AM335X_PIN_OUTPUT },				// pr1_mii1_txd1
    { CONTROL_CONF_GPMC_A(4), 	5, AM335X_PIN_OUTPUT },				// pr1_mii1_txd0
    { CONTROL_CONF_GPMC_A(5), 	5, AM335X_PIN_INPUT_PULLDOWN },		// pr1_mii1_rxd3
    { CONTROL_CONF_GPMC_A(6), 	5, AM335X_PIN_INPUT_PULLDOWN },		// pr1_mii1_rxd2
    { CONTROL_CONF_GPMC_A(7), 	5, AM335X_PIN_INPUT_PULLDOWN },		// pr1_mii1_rxd1
    { CONTROL_CONF_GPMC_A(8), 	5, AM335X_PIN_INPUT_PULLDOWN },		// pr1_mii1_rxd0
    { CONTROL_CONF_GPMC_A(9), 	5, AM335X_PIN_INPUT_PULLDOWN },		// pr1_mii_mr1_clk	gpmc_a9
    { CONTROL_CONF_GPMC_A(10), 	5, AM335X_PIN_INPUT_PULLDOWN },		// pr1_mii1_rxdv
    { CONTROL_CONF_GPMC_A(11), 	5, AM335X_PIN_INPUT_PULLDOWN },		// pr1_mii1_rxer
    { CONTROL_CONF_GPMC_WPN, 	5, AM335X_PIN_OUTPUT_PULLUP },		// pr1_mii1_txen
    { CONTROL_CONF_GPMC_BE1N, 	5, AM335X_PIN_INPUT_PULLUP },	    // pr1_mii1_rxlink	gpmc_be1n
	{ CONTROL_CONF_GPMC_CSN(3), 5, AM335X_PIN_INPUT_PULLUP },		// pr1_mdio_data
	{ CONTROL_CONF_GPMC_CLK, 	5, AM335X_PIN_OUTPUT_PULLUP },		// pr1_mdio_mdclk
    { CONTROL_CONF_LCD_DATA(0), 2, AM335X_PIN_INPUT },				// pr1_mii_mt0_clk_mux1
    { CONTROL_CONF_LCD_DATA(1), 2, AM335X_PIN_OUTPUT },				// pr1_mii0_txen_mux1
    { CONTROL_CONF_LCD_DATA(2), 2, AM335X_PIN_OUTPUT },				// pr1_mii0_txd3_mux1
    { CONTROL_CONF_LCD_DATA(3), 2, AM335X_PIN_OUTPUT },				// pr1_mii0_txd2_mux1
    { CONTROL_CONF_LCD_DATA(4), 2, AM335X_PIN_OUTPUT },				// pr1_mii0_txd1_mux1
    { CONTROL_CONF_LCD_DATA(5), 2, AM335X_PIN_OUTPUT },				// pr1_mii0_txd0_mux1
    { CONTROL_CONF_LCD_DATA(6) ,7, (AM335X_PIN_OUTPUT | AM335X_PIN_INPUT) }, //	gpio2[12] prueth0_resetn
    { CONTROL_CONF_LCD_DATA(7) ,7, (AM335X_PIN_OUTPUT | AM335X_PIN_INPUT) }, //	gpio2[13] prueth1_resetn
    { CONTROL_CONF_LCD_DATA(12),5, AM335X_PIN_INPUT },				// PR1_MII0_RXLINK
    { CONTROL_CONF_LCD_DATA(13),5, AM335X_PIN_INPUT },				// PR1_MII0_RXER
    { CONTROL_CONF_LCD_DATA(14),5, AM335X_PIN_INPUT },				// PR1_MII_MR0_CLK
    { CONTROL_CONF_LCD_DATA(15),5, AM335X_PIN_INPUT },				// PR1_MII0_RXDV
    { CONTROL_CONF_LCD_VSYNC, 	6, AM335X_PIN_INPUT },				// PR1_PRU1_PRU_R31[8]
    { CONTROL_CONF_LCD_HSYNC, 	6, AM335X_PIN_INPUT },				// PR1_PRU1_PRU_R31[9]
    { CONTROL_CONF_LCD_PCLK, 	6, AM335X_PIN_INPUT },				// PR1_PRU1_PRU_R31[10]
    { CONTROL_CONF_LCD_AC_BIAS_EN, 6, AM335X_PIN_INPUT },			// PR1_PRU1_PRU_R31[11]
	{ CONTROL_CONF_UART_CTSN(1),7, AM335X_PIN_INPUT },				// FET_nOE

    // GPIO
    { CONTROL_CONF_LCD_DATA(8),  2, AM335X_PIN_INPUT },				// EHRPWM1_TRIPZONE_INPUT_MUX0
    { CONTROL_CONF_LCD_DATA(9),  7, AM335X_PIN_INPUT },				// GPIO2[15] (synch0)
    { CONTROL_CONF_LCD_DATA(10), 2, AM335X_PIN_OUTPUT },			// PWM1A
    { CONTROL_CONF_LCD_DATA(11), 2, AM335X_PIN_OUTPUT },			// PWM1B
	{ CONTROL_CONF_MCASP0_ACLKX, 7, AM335X_PIN_INPUT_PULLDOWN },	// PWM0A
	{ CONTROL_CONF_MCASP0_FSX, 	 7, AM335X_PIN_INPUT_PULLDOWN },	// PWM0B
	{ CONTROL_CONF_MCASP0_AXR0,	 7, AM335X_PIN_INPUT_PULLDOWN },	// PWM0TRIP
	{ CONTROL_CONF_MCASP0_ACLKR, 7, AM335X_PIN_INPUT_PULLDOWN }, 	// GPIO3[18] // QENC0A
	{ CONTROL_CONF_MCASP0_AXR1,  7, AM335X_PIN_INPUT_PULLDOWN }, 	// GPIO3[20] // QENC0_INDEX
	{ CONTROL_CONF_MCASP0_AHCLKX,7, AM335X_PIN_INPUT_PULLDOWN }, 	// GPIO3[21] // QENC0_STROBE

    // FPGA
    { CONTROL_CONF_MII1_COL,  	 7, (AM335X_PIN_OUTPUT | AM335X_PIN_INPUT) },	// fpga_dclk
    { CONTROL_CONF_MII1_CRS,  	 7, (AM335X_PIN_OUTPUT | AM335X_PIN_INPUT) },	// fpga_data0
    { CONTROL_CONF_UART_CTSN(0), 7, AM335X_PIN_OUTPUT },						// FPGA_CONFIGn
    { CONTROL_CONF_UART_RTSN(1), 7, AM335X_PIN_OUTPUT },						// FPGA_PROG_EN#
    { CONTROL_CONF_MCASP0_AHCLKR,7, AM335X_PIN_INPUT_PULLDOWN },				// FPGA_STATUSn
    { CONTROL_CONF_UART_RXD(0),  7, AM335X_PIN_INPUT },							// FPGA_CONF_DONE
	{ CONTROL_CONF_UART_TXD(0),	 7, AM335X_PIN_INPUT },							// FPGA_RESETn
	{ CONTROL_CONF_NNMI, 		 0, AM335X_PIN_INPUT }, 						// NNMI

    // SERIALE (UART3)
    { CONTROL_CONF_SPI0_CS1, 		  1, AM335X_PIN_INPUT },	// UART3_RXD
    { CONTROL_CONF_ECAP0_IN_PWM0_OUT, 1, AM335X_PIN_OUTPUT },	// UART3_TXD_MUX1

    // ANALOG INPUTS
    { CONTROL_CONF_AIN7, 0, AM335X_PIN_INPUT },	// AIN7
    { CONTROL_CONF_AIN6, 0, AM335X_PIN_INPUT },	// AIN6
    { CONTROL_CONF_AIN5, 0, AM335X_PIN_INPUT },	// AIN5
    { CONTROL_CONF_AIN4, 0, AM335X_PIN_INPUT },	// AIN4
    { CONTROL_CONF_AIN3, 0, AM335X_PIN_INPUT },	// AIN3
    { CONTROL_CONF_AIN2, 0, AM335X_PIN_INPUT },	// AIN2
    { CONTROL_CONF_AIN1, 0, AM335X_PIN_INPUT },	// AIN1
    { CONTROL_CONF_AIN0, 0, AM335X_PIN_INPUT },	// AIN0
    { CONTROL_CONF_VREFP,0, AM335X_PIN_INPUT },	// VREFP
    { CONTROL_CONF_VREFN,0, AM335X_PIN_INPUT },	// VREFN

    // SPI
    { CONTROL_CONF_SPI0_SCLK,0, AM335X_PIN_INPUT },	// spi0_sclk
    { CONTROL_CONF_SPI0_D0,	 0, AM335X_PIN_INPUT },	// spi0_do
    { CONTROL_CONF_SPI0_D1,  0, AM335X_PIN_INPUT },	// spi0_di
    { CONTROL_CONF_SPI0_CS0, 0, AM335X_PIN_INPUT },	// spi0_cs0

    // MMC
    { CONTROL_CONF_MMC0_DAT3, 0, AM335X_PIN_INPUT_PULLUP },	    // MMC0_DAT3
    { CONTROL_CONF_MMC0_DAT2, 0, AM335X_PIN_INPUT_PULLUP },	    // MMC0_DAT2
    { CONTROL_CONF_MMC0_DAT1, 0, AM335X_PIN_INPUT_PULLUP },	    // MMC0_DAT1
    { CONTROL_CONF_MMC0_DAT0, 0, AM335X_PIN_INPUT_PULLUP },	    // MMC0_DAT0
    { CONTROL_CONF_MMC0_CLK,  0, AM335X_PIN_INPUT_PULLUP },	    // MMC0_CLK
    { CONTROL_CONF_MMC0_CMD,  0, AM335X_PIN_INPUT_PULLUP },	    // MMC0_CMD

    // ETHERNET
    { CONTROL_CONF_MII1_RXERR,	0, AM335X_PIN_INPUT_PULLDOWN },	//	GMII1_RXER
    { CONTROL_CONF_MII1_TXEN, 	0, AM335X_PIN_OUTPUT },			//	GMII1_TXEN
    { CONTROL_CONF_MII1_RXDV, 	0, AM335X_PIN_INPUT_PULLDOWN },	//	GMII1_RXDV
    { CONTROL_CONF_MII1_TXD3,  	0, AM335X_PIN_OUTPUT },			//	GMII1_TXD3
    { CONTROL_CONF_MII1_TXD2,  	0, AM335X_PIN_OUTPUT },			//	GMII1_TXD2
    { CONTROL_CONF_MII1_TXD1,  	0, AM335X_PIN_OUTPUT },			//	GMII1_TXD1
    { CONTROL_CONF_MII1_TXD0,  	0, AM335X_PIN_OUTPUT },			//	GMII1_TXD0
    { CONTROL_CONF_MII1_TXCLK, 	0, AM335X_PIN_INPUT_PULLDOWN },	//	GMII1_TXCLK
    { CONTROL_CONF_MII1_RXCLK,	0, AM335X_PIN_INPUT_PULLDOWN },	//	GMII1_RXCLK
    { CONTROL_CONF_MII1_RXD3, 	0, AM335X_PIN_INPUT_PULLDOWN },	//	GMII1_RXD3
    { CONTROL_CONF_MII1_RXD2, 	0, AM335X_PIN_INPUT_PULLDOWN },	//	GMII1_RXD2
    { CONTROL_CONF_MII1_RXD1,	0, AM335X_PIN_INPUT_PULLDOWN },	//	GMII1_RXD1
    { CONTROL_CONF_MII1_RXD0, 	0, AM335X_PIN_INPUT_PULLDOWN },	//	GMII1_RXD0
    { CONTROL_CONF_RMII1_REFCLK,7, AM335X_PIN_OUTPUT },			//	GPIO0[29]
    { CONTROL_CONF_MDIO_DATA, 	0, AM335X_PIN_INPUT },			//	MDIO_DATA
    { CONTROL_CONF_MDIO_CLK, 	0, AM335X_PIN_OUTPUT },			//	MDIO_CLK

	// USB
	{ CONTROL_CONF_USB_DM(0), 	0, AM335X_PIN_INPUT }, 	// USB0_DM
	{ CONTROL_CONF_USB_DP(0), 	0, AM335X_PIN_INPUT }, 	// USB0_DP
	{ CONTROL_CONF_USB_CE(0), 	0, AM335X_PIN_INPUT }, 	// USB0_CE
	{ CONTROL_CONF_USB_ID(0), 	0, AM335X_PIN_INPUT }, 	// USB0_ID
	{ CONTROL_CONF_USB_VBUS(0), 0, AM335X_PIN_INPUT }, 	// USB0_VBUS
	{ CONTROL_CONF_USB_DRVVBUS(0),	0, AM335X_PIN_OUTPUT }, // USB0_DRVVBUS

	// VARIE ED EVENTUALI
//	{ CONTROL_CONF_XDMA_EVENT_INTR(0), 3, AM335X_PULL_DISA }, 	// CLKOUT1	// potrebbe diventare l'intr da fpga a dma
	{ CONTROL_CONF_XDMA_EVENT_INTR(0), 0, AM335X_PIN_INPUT }, 	// CLKOUT1	// usato come trigger da fpga a dma
	{ CONTROL_CONF_XDMA_EVENT_INTR(1), 3, AM335X_PULL_DISA }, 	// CLKOUT2
	{ CONTROL_CONF_NRESETIN_OUT,0, AM335X_PIN_INPUT }, 			// NRESETIN_OUT
	{ CONTROL_CONF_PORZ,		0, AM335X_PIN_INPUT }, 			// PORZ
	{ CONTROL_CONF_OSC_IN(0), 	0, AM335X_PIN_INPUT }, 			// OSC0_IN
	{ CONTROL_CONF_OSC_OUT(0), 	0, AM335X_PULL_DISA },			// OSC0_OUT
	{ CONTROL_CONF_TMS, 		0, AM335X_PIN_INPUT_PULLUP }, 	// TMS
	{ CONTROL_CONF_TDI, 		0, AM335X_PIN_INPUT_PULLUP }, 	// TDI
	{ CONTROL_CONF_TDO, 		0, AM335X_PIN_OUTPUT_PULLUP }, 	// TDO
	{ CONTROL_CONF_TCK, 		0, AM335X_PIN_INPUT_PULLUP }, 	// TCK
	{ CONTROL_CONF_NTRST, 		0, AM335X_PIN_INPUT_PULLDOWN }, // NTRST
	{ CONTROL_CONF_EMU(0), 		0, AM335X_PIN_INPUT_PULLUP }, 	// EMU0
	{ CONTROL_CONF_EMU(1), 		0, AM335X_PIN_INPUT_PULLUP }, 	// EMU1
//	{ CONTROL_CONF_OSC_IN(1), 	0, AM335X_PIN_INPUT }, 			// OSC1_IN
//	{ CONTROL_CONF_OSC_OUT(1), 	0, AM335X_PULL_DISA }, 			// OSC1_OUT
	{ CONTROL_CONF_RTC_PORZ,	0, AM335X_PIN_INPUT }, 			// RTC_PORZ
	{ CONTROL_CONF_PMIC_POWER_EN,	0, AM335X_PIN_OUTPUT_PULLUP }, 	// PMIC_POWER_EN
	{ CONTROL_CONF_EXT_WAKEUP,		0, AM335X_PIN_INPUT_PULLDOWN }, // EXT_WAKEUP
	{ CONTROL_CONF_ENZ_KALDO_1P8V,	0, AM335X_PIN_INPUT }, 			// ENZ_KALDO_1P8V

	// DDR3
    // Fatto da bootloader: se l'applicazione gira, significa che
    // il bootloader ha impostato correttamente i pin della ddr
    // e ribadire significherebbe solo rischiare di introdurre errori
//  { CONTROL_CONF_DDR_RESETN, 	0, AM335X_PIN_OUTPUT }, 		// DDR_RESETN
//	{ CONTROL_CONF_DDR_CSN0,	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_CSN0
//	{ CONTROL_CONF_DDR_CKE, 	0, AM335X_PIN_OUTPUT }, 		// DDR_CKE
//	{ CONTROL_CONF_DDR_CK, 		0, AM335X_PIN_OUTPUT }, 		// DDR_CK
//	{ CONTROL_CONF_DDR_NCK, 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_NCK
//	{ CONTROL_CONF_DDR_CASN, 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_CASN
//	{ CONTROL_CONF_DDR_RASN, 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_RASN
//	{ CONTROL_CONF_DDR_WEN, 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_WEN
//	{ CONTROL_CONF_DDR_BA(0), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_BA0
//	{ CONTROL_CONF_DDR_BA(1), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_BA1
//	{ CONTROL_CONF_DDR_BA(2), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_BA2
//	{ CONTROL_CONF_DDR_A(0), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_A0
//	{ CONTROL_CONF_DDR_A(1), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_A1
//	{ CONTROL_CONF_DDR_A(2), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_A2
//	{ CONTROL_CONF_DDR_A(3), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_A3
//	{ CONTROL_CONF_DDR_A(4), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_A4
//	{ CONTROL_CONF_DDR_A(5), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_A5
//	{ CONTROL_CONF_DDR_A(6), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_A6
//	{ CONTROL_CONF_DDR_A(7), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_A7
//	{ CONTROL_CONF_DDR_A(8), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_A8
//	{ CONTROL_CONF_DDR_A(9), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_A9
//	{ CONTROL_CONF_DDR_A(10), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_A10
//	{ CONTROL_CONF_DDR_A(11), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_A11
//	{ CONTROL_CONF_DDR_A(12), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_A12
//	{ CONTROL_CONF_DDR_A(13), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_A13
//	{ CONTROL_CONF_DDR_A(14), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_A14
//	{ CONTROL_CONF_DDR_A(15), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_A15
//	{ CONTROL_CONF_DDR_ODT, 	0, AM335X_PIN_OUTPUT }, 		// DDR_ODT
//	{ CONTROL_CONF_DDR_D(0), 	0, AM335X_PIN_INPUT_PULLDOWN }, // DDR_D0
//	{ CONTROL_CONF_DDR_D(1), 	0, AM335X_PIN_INPUT_PULLDOWN }, // DDR_D1
//	{ CONTROL_CONF_DDR_D(2), 	0, AM335X_PIN_INPUT_PULLDOWN }, // DDR_D2
//	{ CONTROL_CONF_DDR_D(3), 	0, AM335X_PIN_INPUT_PULLDOWN }, // DDR_D3
//	{ CONTROL_CONF_DDR_D(4), 	0, AM335X_PIN_INPUT_PULLDOWN }, // DDR_D4
//	{ CONTROL_CONF_DDR_D(5), 	0, AM335X_PIN_INPUT_PULLDOWN }, // DDR_D5
//	{ CONTROL_CONF_DDR_D(6), 	0, AM335X_PIN_INPUT_PULLDOWN }, // DDR_D6
//	{ CONTROL_CONF_DDR_D(7), 	0, AM335X_PIN_INPUT_PULLDOWN }, // DDR_D7
//	{ CONTROL_CONF_DDR_D(8), 	0, AM335X_PIN_INPUT_PULLDOWN }, // DDR_D8
//	{ CONTROL_CONF_DDR_D(9), 	0, AM335X_PIN_INPUT_PULLDOWN }, // DDR_D9
//	{ CONTROL_CONF_DDR_D(10), 	0, AM335X_PIN_INPUT_PULLDOWN }, // DDR_D10
//	{ CONTROL_CONF_DDR_D(11), 	0, AM335X_PIN_INPUT_PULLDOWN }, // DDR_D11
//	{ CONTROL_CONF_DDR_D(12), 	0, AM335X_PIN_INPUT_PULLDOWN }, // DDR_D12
//	{ CONTROL_CONF_DDR_D(13), 	0, AM335X_PIN_INPUT_PULLDOWN }, // DDR_D13
//	{ CONTROL_CONF_DDR_D(14), 	0, AM335X_PIN_INPUT_PULLDOWN }, // DDR_D14
//	{ CONTROL_CONF_DDR_D(15), 	0, AM335X_PIN_INPUT_PULLDOWN }, // DDR_D15
//	{ CONTROL_CONF_DDR_DQM(0), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_DQM0
//	{ CONTROL_CONF_DDR_DQM(1), 	0, AM335X_PIN_OUTPUT_PULLUP }, 	// DDR_DQM1
//	{ CONTROL_CONF_DDR_DQS(0), 	0, AM335X_PIN_INPUT_PULLDOWN }, // DDR_DQS0
//	{ CONTROL_CONF_DDR_DQSN(0),	0, AM335X_PIN_INPUT_PULLUP }, 	// DDR_DQSN0
//	{ CONTROL_CONF_DDR_DQS(1), 	0, AM335X_PIN_INPUT_PULLDOWN }, // DDR_DQS1
//	{ CONTROL_CONF_DDR_DQSN(1),	0, AM335X_PIN_INPUT_PULLUP }, 	// DDR_DQSN1
//	{ CONTROL_CONF_DDR_VREF, 	0, AM335X_PIN_INPUT }, 			// DDR_VREF
//	{ CONTROL_CONF_DDR_VTP, 	0, AM335X_PIN_INPUT }, 			// DDR_VTP

    {0xFFFFFFFF,0,0}
};

void driver_init ( void )
{
	// Lo IARD ha una configurazione di PIN MUX nota e costante (indipendente dall'applicazione).
	// Per questo motivo l'inizializzazione per tutti i pin è stata fatta qui una volta per tutte.
	// Si è poi avuto cura di modificare le init nella sdk, in caso di IARD,
	// per evitare che altre init possano sovrascrivere la configurazione desiderata.
	if(AM335X_BOARD_TYPE_IARD == UTILsGetBoardType())
    {
		PinMuxConfig(iard_mux);
    }

	/* Configure the EDMA clocks. */
	EDMAModuleClkConfig();
    /* Configurazione degli interrupt di trasferimento e di errore */
    EDMA3IntConfigure();

    dmtimer_init();
    led_init();

    return;
}


