/**
 * cpsw_miimdio_regs.h
 * 
 *
 * Copyright (c) 2012 Texas Instruments Incorporated ALL RIGHTS RESERVED
 *
*/
#ifndef _CPSW_MIIMDIO_REGS_H
#define _CPSW_MIIMDIO_REGS_H

#ifdef __cplusplus
extern "C" {
#endif


/***************************************************************************
**
**         M D I O  R E G I S T E R  A C C E S S  M A C R O S
**
***************************************************************************/

#define         MDIO_USERACCESS_DATA   (0xFFFF)
#define         MDIO_USERPHYSEL_LINKSEL         (1 << 7)

/****************************************************************************/
/*                                                                          */
/*         P H Y   R E G I S T E R  D E F I N I T I O N S                   */
/*                                                                          */
/****************************************************************************/


#define PHY_CONTROL_REG       0
  #define MII_PHY_RESET           (1<<15)
  #define MII_PHY_LOOP            (1<<14)
  #define MII_PHY_100             (1<<13)
  #define MII_AUTO_NEGOTIATE_EN   (1<<12)
  #define MII_PHY_PDOWN           (1<<11)
  #define MII_PHY_ISOLATE         (1<<10)
  #define MII_RENEGOTIATE         (1<<9)
  #define MII_PHY_FD              (1<<8)
  #define MII_PHY_1000            (1<<6)

#define PHY_STATUS_REG        1
  #define MII_NWAY_COMPLETE       (1<<5)
  #define MII_NWAY_CAPABLE        (1<<3)
  #define MII_PHY_LINKED          (1<<2)

#define PHY_IDENT_REG         2
#define NWAY_ADVERTIZE_REG    4
#define NWAY_REMADVERTISE_REG 5
  #define MII_NWAY_FD100          (1<<8)
  #define MII_NWAY_HD100          (1<<7)
  #define MII_NWAY_FD10           (1<<6)
  #define MII_NWAY_HD10           (1<<5)
  #define MII_NWAY_SEL            (1<<0)

#define NWAY_1000BT_ADVERTISE_REG    9
  #define MII_NWAY_MY_FD1000         (1<<9)
  #define MII_NWAY_MY_HD1000         (1<<8)
#define NWAY_1000BT_REMADVERTISE_REG 10
  #define MII_NWAY_REM_FD1000         (1<<11)
  #define MII_NWAY_REM_HD1000         (1<<10)

#define PHY_CNTRL_REG        0x0019

#define PHY_CONFIG_REG	22
  #define SYSTEM_CLOCK_ENABLE_125MHZ	(1<<4)
  #define TRANSMIT_CLOCK_ENABLE_1000BASET	(1<<5)
  #define GMII_CLOCKED_BY_GTX_CLK	(1<<1)
  
#define PHY_LED_CONTROL_REG	28
#ifdef __cplusplus
}
#endif

#endif /*_CPSW_MIIMDIO_REGS_H_*/
