tidl_tools_path = /home/deepanshu/EdgeAI/edgeai-tidl-tools/tidl_tools artifacts_folder = ../../../model-artifacts//fnc_safety_fp32/ tidl_tensor_bits = 16 debug_level = 4 num_tidl_subgraphs = 16 tidl_denylist = tidl_denylist_layer_name = tidl_denylist_layer_type = tidl_allowlist_layer_name = model_type = tidl_calibration_accuracy_level = 7 tidl_calibration_options:num_frames_calibration = 3 tidl_calibration_options:bias_calibration_iterations = 3 mixed_precision_factor = -1.000000 model_group_id = 0 power_of_2_quantization = 2 ONNX QDQ Enabled = 0 enable_high_resolution_optimization = 0 pre_batchnorm_fold = 1 add_data_convert_ops = 3 output_feature_16bit_names_list = m_params_16bit_names_list = m_single_core_layers_names_list = reserved_compile_constraints_flag = 1601 ti_internal_reserved_1 = WARNING : 'meta_layers_names_list' is not provided - running OD post processing in ARM mode Number of OD backbone nodes = 0 Size of odBackboneNodeIds = 0 Layer 0 -- layer name -- Conv_0 Input dims size = 4 dims --- 1 3 320 800 Supported TIDL layer type --- Conv -- Conv_0 Layer 1 -- layer name -- Relu_1 Input dims size = 4 dims --- 1 64 160 400 Supported TIDL layer type --- Relu -- Relu_1 Layer 2 -- layer name -- MaxPool_2 Input dims size = 4 dims --- 1 64 160 400 Supported TIDL layer type --- MaxPool -- MaxPool_2 Layer 3 -- layer name -- Conv_3 Input dims size = 4 dims --- 1 64 80 200 Supported TIDL layer type --- Conv -- Conv_3 Layer 4 -- layer name -- Relu_4 Input dims size = 4 dims --- 1 64 80 200 Supported TIDL layer type --- Relu -- Relu_4 Layer 5 -- layer name -- Conv_5 Input dims size = 4 dims --- 1 64 80 200 Supported TIDL layer type --- Conv -- Conv_5 Layer 6 -- layer name -- Add_6 Input dims size = 4 dims --- 1 64 80 200 Supported TIDL layer type --- Add -- Add_6 Layer 7 -- layer name -- Relu_7 Input dims size = 4 dims --- 1 64 80 200 Supported TIDL layer type --- Relu -- Relu_7 Layer 8 -- layer name -- Conv_8 Input dims size = 4 dims --- 1 64 80 200 Supported TIDL layer type --- Conv -- Conv_8 Layer 9 -- layer name -- Relu_9 Input dims size = 4 dims --- 1 64 80 200 Supported TIDL layer type --- Relu -- Relu_9 Layer 10 -- layer name -- Conv_10 Input dims size = 4 dims --- 1 64 80 200 Supported TIDL layer type --- Conv -- Conv_10 Layer 11 -- layer name -- Add_11 Input dims size = 4 dims --- 1 64 80 200 Supported TIDL layer type --- Add -- Add_11 Layer 12 -- layer name -- Relu_12 Input dims size = 4 dims --- 1 64 80 200 Supported TIDL layer type --- Relu -- Relu_12 Layer 13 -- layer name -- Conv_13 Input dims size = 4 dims --- 1 64 80 200 Supported TIDL layer type --- Conv -- Conv_13 Layer 14 -- layer name -- Relu_14 Input dims size = 4 dims --- 1 128 40 100 Supported TIDL layer type --- Relu -- Relu_14 Layer 15 -- layer name -- Conv_15 Input dims size = 4 dims --- 1 128 40 100 Supported TIDL layer type --- Conv -- Conv_15 Layer 16 -- layer name -- Conv_16 Input dims size = 4 dims --- 1 64 80 200 Supported TIDL layer type --- Conv -- Conv_16 Layer 17 -- layer name -- Add_17 Input dims size = 4 dims --- 1 128 40 100 Supported TIDL layer type --- Add -- Add_17 Layer 18 -- layer name -- Relu_18 Input dims size = 4 dims --- 1 128 40 100 Supported TIDL layer type --- Relu -- Relu_18 Layer 19 -- layer name -- Conv_19 Input dims size = 4 dims --- 1 128 40 100 Supported TIDL layer type --- Conv -- Conv_19 Layer 20 -- layer name -- Relu_20 Input dims size = 4 dims --- 1 128 40 100 Supported TIDL layer type --- Relu -- Relu_20 Layer 21 -- layer name -- Conv_21 Input dims size = 4 dims --- 1 128 40 100 Supported TIDL layer type --- Conv -- Conv_21 Layer 22 -- layer name -- Add_22 Input dims size = 4 dims --- 1 128 40 100 Supported TIDL layer type --- Add -- Add_22 Layer 23 -- layer name -- Relu_23 Input dims size = 4 dims --- 1 128 40 100 Supported TIDL layer type --- Relu -- Relu_23 Layer 24 -- layer name -- Conv_24 Input dims size = 4 dims --- 1 128 40 100 Supported TIDL layer type --- Conv -- Conv_24 Layer 25 -- layer name -- Relu_25 Input dims size = 4 dims --- 1 256 20 50 Supported TIDL layer type --- Relu -- Relu_25 Layer 26 -- layer name -- Conv_26 Input dims size = 4 dims --- 1 256 20 50 Supported TIDL layer type --- Conv -- Conv_26 Layer 27 -- layer name -- Conv_27 Input dims size = 4 dims --- 1 128 40 100 Supported TIDL layer type --- Conv -- Conv_27 Layer 28 -- layer name -- Add_28 Input dims size = 4 dims --- 1 256 20 50 Supported TIDL layer type --- Add -- Add_28 Layer 29 -- layer name -- Relu_29 Input dims size = 4 dims --- 1 256 20 50 Supported TIDL layer type --- Relu -- Relu_29 Layer 30 -- layer name -- Conv_30 Input dims size = 4 dims --- 1 256 20 50 Supported TIDL layer type --- Conv -- Conv_30 Layer 31 -- layer name -- Relu_31 Input dims size = 4 dims --- 1 256 20 50 Supported TIDL layer type --- Relu -- Relu_31 Layer 32 -- layer name -- Conv_32 Input dims size = 4 dims --- 1 256 20 50 Supported TIDL layer type --- Conv -- Conv_32 Layer 33 -- layer name -- Add_33 Input dims size = 4 dims --- 1 256 20 50 Supported TIDL layer type --- Add -- Add_33 Layer 34 -- layer name -- Relu_34 Input dims size = 4 dims --- 1 256 20 50 Supported TIDL layer type --- Relu -- Relu_34 Layer 35 -- layer name -- Conv_35 Input dims size = 4 dims --- 1 256 20 50 Supported TIDL layer type --- Conv -- Conv_35 Layer 36 -- layer name -- Relu_36 Input dims size = 4 dims --- 1 512 10 25 Supported TIDL layer type --- Relu -- Relu_36 Layer 37 -- layer name -- Conv_37 Input dims size = 4 dims --- 1 512 10 25 Supported TIDL layer type --- Conv -- Conv_37 Layer 38 -- layer name -- Conv_38 Input dims size = 4 dims --- 1 256 20 50 Supported TIDL layer type --- Conv -- Conv_38 Layer 39 -- layer name -- Add_39 Input dims size = 4 dims --- 1 512 10 25 Supported TIDL layer type --- Add -- Add_39 Layer 40 -- layer name -- Relu_40 Input dims size = 4 dims --- 1 512 10 25 Supported TIDL layer type --- Relu -- Relu_40 Layer 41 -- layer name -- Conv_41 Input dims size = 4 dims --- 1 512 10 25 Supported TIDL layer type --- Conv -- Conv_41 Layer 42 -- layer name -- Relu_42 Input dims size = 4 dims --- 1 512 10 25 Supported TIDL layer type --- Relu -- Relu_42 Layer 43 -- layer name -- Conv_43 Input dims size = 4 dims --- 1 512 10 25 Supported TIDL layer type --- Conv -- Conv_43 Layer 44 -- layer name -- Add_44 Input dims size = 4 dims --- 1 512 10 25 Supported TIDL layer type --- Add -- Add_44 Layer 45 -- layer name -- Relu_45 Input dims size = 4 dims --- 1 512 10 25 Supported TIDL layer type --- Relu -- Relu_45 Layer 46 -- layer name -- Conv_46 Input dims size = 4 dims --- 1 512 10 25 Supported TIDL layer type --- Conv -- Conv_46 Layer 47 -- layer name -- Relu_47 Input dims size = 4 dims --- 1 64 10 25 Supported TIDL layer type --- Relu -- Relu_47 Layer 48 -- layer name -- Add_58 Input dims size = 4 dims --- 1 64 10 25 Supported TIDL layer type --- Add -- Add_58 Layer 49 -- layer name -- Conv_59 Input dims size = 4 dims --- 1 64 10 25 Supported TIDL layer type --- Conv -- Conv_59 Layer 50 -- layer name -- Reshape_64 Input dims size = 4 dims --- 1 16 10 25 Supported TIDL layer type --- Reshape -- Reshape_64 Layer 51 -- layer name -- Transpose_65 Input dims size = 3 dims --- 1 16 250 Supported TIDL layer type --- Transpose -- Transpose_65 Layer 52 -- layer name -- Conv_66 Input dims size = 4 dims --- 1 64 10 25 Supported TIDL layer type --- Conv -- Conv_66 Layer 53 -- layer name -- Reshape_71 Input dims size = 4 dims --- 1 16 10 25 Supported TIDL layer type --- Reshape -- Reshape_71 Layer 54 -- layer name -- MatMul_72 Input dims size = 3 dims --- 1 250 16 Supported TIDL layer type --- MatMul -- MatMul_72 Layer 55 -- layer name -- reshape_Unsqueeze_73 Input dims size = 3 dims --- 1 250 250 Supported TIDL layer type --- Reshape -- reshape_Unsqueeze_73 Layer 56 -- layer name -- Softmax_74 Input dims size = 4 dims --- 1 1 250 250 Supported TIDL layer type --- Softmax -- Softmax_74 Layer 57 -- layer name -- Squeeze_75 Input dims size = 4 dims --- 1 1 250 250 debug_TIDL_onnxMapSqueezeBaseParams: lIdx-57 axisIdx-0 squeeze axis[0] - 0 squeeze indim - 1 squeeze indim - 1 squeeze indim - 250 squeeze indim - 250 debug_TIDL_onnxMapSqueezeBaseParams: numDim-4 axes-2 Supported TIDL layer type --- Squeeze -- Squeeze_75 Layer 58 -- layer name -- Transpose_76 Input dims size = 3 dims --- 1 250 250 Supported TIDL layer type --- Transpose -- Transpose_76 Layer 59 -- layer name -- Conv_77 Input dims size = 4 dims --- 1 64 10 25 Supported TIDL layer type --- Conv -- Conv_77 Layer 60 -- layer name -- Reshape_82 Input dims size = 4 dims --- 1 64 10 25 Supported TIDL layer type --- Reshape -- Reshape_82 Layer 61 -- layer name -- MatMul_83 Input dims size = 3 dims --- 1 64 250 Supported TIDL layer type --- MatMul -- MatMul_83 Layer 62 -- layer name -- Reshape_88 Input dims size = 3 dims --- 1 64 250 Supported TIDL layer type --- Reshape -- Reshape_88 Layer 63 -- layer name -- Mul_89 Input dims size = 0 dims --- Supported TIDL layer type --- Mul -- Mul_89 Layer 64 -- layer name -- Add_90 Input dims size = 4 dims --- 1 64 10 25 Supported TIDL layer type --- Add -- Add_90 Layer 65 -- layer name -- Conv_91 Input dims size = 4 dims --- 1 64 10 25 Supported TIDL layer type --- Conv -- Conv_91 Layer 66 -- layer name -- Relu_92 Input dims size = 4 dims --- 1 64 10 25 Supported TIDL layer type --- Relu -- Relu_92 Layer 67 -- layer name -- Conv_93 Input dims size = 4 dims --- 1 64 10 25 Supported TIDL layer type --- Conv -- Conv_93 Layer 68 -- layer name -- Relu_94 Input dims size = 4 dims --- 1 64 10 25 Supported TIDL layer type --- Relu -- Relu_94 Layer 69 -- layer name -- Add_105 Input dims size = 4 dims --- 1 64 10 25 Supported TIDL layer type --- Add -- Add_105 Layer 70 -- layer name -- Conv_106 Input dims size = 4 dims --- 1 64 10 25 Supported TIDL layer type --- Conv -- Conv_106 Layer 71 -- layer name -- Reshape_111 Input dims size = 4 dims --- 1 16 10 25 Supported TIDL layer type --- Reshape -- Reshape_111 Layer 72 -- layer name -- Transpose_112 Input dims size = 3 dims --- 1 16 250 Supported TIDL layer type --- Transpose -- Transpose_112 Layer 73 -- layer name -- Conv_113 Input dims size = 4 dims --- 1 64 10 25 Supported TIDL layer type --- Conv -- Conv_113 Layer 74 -- layer name -- Reshape_118 Input dims size = 4 dims --- 1 16 10 25 Supported TIDL layer type --- Reshape -- Reshape_118 Layer 75 -- layer name -- MatMul_119 Input dims size = 3 dims --- 1 250 16 Supported TIDL layer type --- MatMul -- MatMul_119 Layer 76 -- layer name -- reshape_Unsqueeze_120 Input dims size = 3 dims --- 1 250 250 Supported TIDL layer type --- Reshape -- reshape_Unsqueeze_120 Layer 77 -- layer name -- Softmax_121 Input dims size = 4 dims --- 1 1 250 250 Supported TIDL layer type --- Softmax -- Softmax_121 Layer 78 -- layer name -- Squeeze_122 Input dims size = 4 dims --- 1 1 250 250 debug_TIDL_onnxMapSqueezeBaseParams: lIdx-78 axisIdx-0 squeeze axis[0] - 0 squeeze indim - 1 squeeze indim - 1 squeeze indim - 250 squeeze indim - 250 debug_TIDL_onnxMapSqueezeBaseParams: numDim-4 axes-2 Supported TIDL layer type --- Squeeze -- Squeeze_122 Layer 79 -- layer name -- Transpose_123 Input dims size = 3 dims --- 1 250 250 Supported TIDL layer type --- Transpose -- Transpose_123 Layer 80 -- layer name -- Conv_124 Input dims size = 4 dims --- 1 64 10 25 Supported TIDL layer type --- Conv -- Conv_124 Layer 81 -- layer name -- Reshape_129 Input dims size = 4 dims --- 1 64 10 25 Supported TIDL layer type --- Reshape -- Reshape_129 Layer 82 -- layer name -- MatMul_130 Input dims size = 3 dims --- 1 64 250 Supported TIDL layer type --- MatMul -- MatMul_130 Layer 83 -- layer name -- Reshape_135 Input dims size = 3 dims --- 1 64 250 Supported TIDL layer type --- Reshape -- Reshape_135 Layer 84 -- layer name -- Mul_136 Input dims size = 0 dims --- Supported TIDL layer type --- Mul -- Mul_136 Layer 85 -- layer name -- Add_137 Input dims size = 4 dims --- 1 64 10 25 Supported TIDL layer type --- Add -- Add_137 Layer 86 -- layer name -- Conv_138 Input dims size = 4 dims --- 1 64 10 25 Supported TIDL layer type --- Conv -- Conv_138 Layer 87 -- layer name -- Relu_139 Input dims size = 4 dims --- 1 64 10 25 Supported TIDL layer type --- Relu -- Relu_139 Layer 88 -- layer name -- Conv_142 Input dims size = 4 dims --- 1 64 10 25 Supported TIDL layer type --- Conv -- Conv_142 Layer 89 -- layer name -- Upsample_143 Input dims size = 4 dims --- 1 64 10 25 Supported TIDL layer type --- Upsample -- Upsample_143 Layer 90 -- layer name -- Conv_141 Input dims size = 4 dims --- 1 256 20 50 Supported TIDL layer type --- Conv -- Conv_141 Layer 91 -- layer name -- Add_144 Input dims size = 4 dims --- 1 64 20 50 Supported TIDL layer type --- Add -- Add_144 Layer 92 -- layer name -- Conv_148 Input dims size = 4 dims --- 1 64 20 50 Supported TIDL layer type --- Conv -- Conv_148 Layer 93 -- layer name -- Conv_152 Input dims size = 4 dims --- 1 64 20 50 Supported TIDL layer type --- Conv -- Conv_152 Layer 94 -- layer name -- Relu_153 Input dims size = 4 dims --- 1 64 20 50 Supported TIDL layer type --- Relu -- Relu_153 Layer 95 -- layer name -- Conv_154 Input dims size = 4 dims --- 1 64 20 50 Supported TIDL layer type --- Conv -- Conv_154 Layer 96 -- layer name -- Sigmoid_170 Input dims size = 4 dims --- 1 1 20 50 Supported TIDL layer type --- Sigmoid -- Sigmoid_170 Layer 97 -- layer name -- Add_172 Input dims size = 4 dims --- 1 1 20 50 Supported TIDL layer type --- Add -- Add_172 Layer 98 -- layer name -- Relu_173 Input dims size = 4 dims --- 1 1 20 50 Supported TIDL layer type --- Relu -- Relu_173 Layer 99 -- layer name -- Add_175 Input dims size = 4 dims --- 1 1 20 50 Supported TIDL layer type --- Add -- Add_175 Layer 100 -- layer name -- Mul_177 Input dims size = 0 dims --- Supported TIDL layer type --- Mul -- Mul_177 Layer 101 -- layer name -- Add_179 Input dims size = 0 dims --- Supported TIDL layer type --- Add -- Add_179 Layer 102 -- layer name -- Relu_180 Input dims size = 4 dims --- 1 1 20 50 Supported TIDL layer type --- Relu -- Relu_180 Layer 103 -- layer name -- Mul_182 Input dims size = 0 dims --- Supported TIDL layer type --- Mul -- Mul_182 Layer 104 -- layer name -- Add_184 Input dims size = 0 dims --- Supported TIDL layer type --- Add -- Add_184 Layer 105 -- layer name -- MaxPool_204 Input dims size = 4 dims --- 1 1 20 50 Supported TIDL layer type --- MaxPool -- MaxPool_204 Layer 106 -- layer name -- Mul_206 Input dims size = 4 dims --- 1 1 20 50 Supported TIDL layer type --- Mul -- Mul_206 Layer 107 -- layer name -- Add_207 Input dims size = 4 dims --- 1 1 20 50 Supported TIDL layer type --- Add -- Add_207 Layer 108 -- layer name -- Mul_209 Input dims size = 4 dims --- 1 1 20 50 Supported TIDL layer type --- Mul -- Mul_209 Layer 109 -- layer name -- Add_211 Input dims size = 4 dims --- 1 1 20 50 Supported TIDL layer type --- Add -- Add_211 Layer 110 -- layer name -- Relu_212 Input dims size = 4 dims --- 1 1 20 50 Supported TIDL layer type --- Relu -- Relu_212 Layer 111 -- layer name -- Mul_214 Input dims size = 4 dims --- 1 1 20 50 Supported TIDL layer type --- Mul -- Mul_214 Layer 112 -- layer name -- Mul_215 Input dims size = 4 dims --- 1 1 20 50 Supported TIDL layer type --- Mul -- Mul_215 Layer 113 -- layer name -- Squeeze_216 Input dims size = 4 dims --- 1 1 20 50 debug_TIDL_onnxMapSqueezeBaseParams: lIdx-113 axisIdx-0 squeeze axis[0] - 0 squeeze indim - 1 squeeze indim - 1 squeeze indim - 20 squeeze indim - 50 debug_TIDL_onnxMapSqueezeBaseParams: numDim-4 axes-2 Supported TIDL layer type --- Squeeze -- Squeeze_216 Layer 114 -- layer name -- Reshape_218 Input dims size = 3 dims --- 1 20 50 Supported TIDL layer type --- Reshape -- Reshape_218 Layer 115 -- layer name -- TopK_219 Input dims size = 1 dims --- 1000 debug_TIDL_onnxMapTopKBaseParams: in-1 out-2 Supported TIDL layer type --- TopK -- TopK_219 Layer 116 -- layer name -- Reshape_221 Input dims size = 1 dims --- 6 Supported TIDL layer type --- Reshape -- Reshape_221 Layer 117 -- layer name -- Squeeze_224 Input dims size = 2 dims --- 6 1 debug_TIDL_onnxMapSqueezeBaseParams: lIdx-117 axisIdx-0 squeeze axis[0] - 1 squeeze indim - 6 squeeze indim - 1 debug_TIDL_onnxMapSqueezeBaseParams: numDim-2 axes-5 Supported TIDL layer type --- Squeeze -- Squeeze_224 Layer 118 -- layer name -- Conv_155 Input dims size = 4 dims --- 1 64 20 50 Supported TIDL layer type --- Conv -- Conv_155 Layer 119 -- layer name -- Relu_156 Input dims size = 4 dims --- 1 64 20 50 Supported TIDL layer type --- Relu -- Relu_156 Layer 120 -- layer name -- Conv_157 Input dims size = 4 dims --- 1 64 20 50 Supported TIDL layer type --- Conv -- Conv_157 Layer 121 -- layer name -- Reshape_195 Input dims size = 4 dims --- 1 134 20 50 Supported TIDL layer type --- Reshape -- Reshape_195 Layer 122 -- layer name -- Transpose_196 Input dims size = 5 dims --- 1 1 134 20 50 Supported TIDL layer type --- Transpose -- Transpose_196 Layer 123 -- layer name -- Reshape_203 Input dims size = 5 dims --- 1 134 1 20 50 Supported TIDL layer type --- Reshape -- Reshape_203 Layer 124 -- layer name -- Conv_289 Input dims size = 4 dims --- 1 134 1 1000 Supported TIDL layer type --- Conv -- Conv_289 Layer 125 -- layer name -- Transpose_290 Input dims size = 4 dims --- 1 67 1 1000 Supported TIDL layer type --- Transpose -- Transpose_290 Layer 126 -- layer name -- Reshape_292 Input dims size = 4 dims --- 1 1000 1 67 Supported TIDL layer type --- Reshape -- Reshape_292 Layer 127 -- layer name -- Conv_228 Input dims size = 4 dims --- 1 134 1 1000 Supported TIDL layer type --- Conv -- Conv_228 Layer 128 -- layer name -- Transpose_229 Input dims size = 4 dims --- 1 67 1 1000 Supported TIDL layer type --- Transpose -- Transpose_229 Layer 129 -- layer name -- Reshape_231 Input dims size = 4 dims --- 1 1000 1 67 Supported TIDL layer type --- Reshape -- Reshape_231 Layer 130 -- layer name -- Upsample_145 Input dims size = 4 dims --- 1 64 20 50 Supported TIDL layer type --- Upsample -- Upsample_145 Layer 131 -- layer name -- Conv_140 Input dims size = 4 dims --- 1 128 40 100 Supported TIDL layer type --- Conv -- Conv_140 Layer 132 -- layer name -- Add_146 Input dims size = 4 dims --- 1 64 40 100 Supported TIDL layer type --- Add -- Add_146 Layer 133 -- layer name -- Conv_147 Input dims size = 4 dims --- 1 64 40 100 Supported TIDL layer type --- Conv -- Conv_147 Layer 134 -- layer name -- Conv_185 Input dims size = 4 dims --- 1 64 40 100 Supported TIDL layer type --- Conv -- Conv_185 Layer 135 -- layer name -- Relu_186 Input dims size = 4 dims --- 1 64 40 100 Supported TIDL layer type --- Relu -- Relu_186 Layer 136 -- layer name -- Conv_187 Input dims size = 4 dims --- 1 64 40 100 Supported TIDL layer type --- Conv -- Conv_187 Layer 137 -- layer name -- Relu_188 Input dims size = 4 dims --- 1 64 40 100 Supported TIDL layer type --- Relu -- Relu_188 Layer 138 -- layer name -- Conv_189 Input dims size = 4 dims --- 1 64 40 100 Supported TIDL layer type --- Conv -- Conv_189 Preliminary subgraphs created = 1 Final number of subgraphs created are : 1, - Offloaded Nodes - 139, Total Nodes - 139 INFORMATION -- [TIDL_ResizeLayer] Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. INFORMATION -- [TIDL_ResizeLayer] Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. Running runtimes graphviz - /home/deepanshu/EdgeAI/edgeai-tidl-tools/tidl_tools/tidl_graphVisualiser_runtimes.out ../../../model-artifacts//fnc_safety_fp32//allowedNode.txt ../../../model-artifacts//fnc_safety_fp32//tempDir/graphvizInfo.txt ../../../model-artifacts//fnc_safety_fp32//tempDir/runtimes_visualization.svg *** In TIDL_createStateImportFunc *** Supported TIDL layer type --- Conv -- Conv_0 Supported TIDL layer type --- Relu -- Relu_1 Supported TIDL layer type --- MaxPool -- MaxPool_2 Supported TIDL layer type --- Conv -- Conv_3 Supported TIDL layer type --- Relu -- Relu_4 Supported TIDL layer type --- Conv -- Conv_5 Supported TIDL layer type --- Add -- Add_6 Supported TIDL layer type --- Relu -- Relu_7 Supported TIDL layer type --- Conv -- Conv_8 Supported TIDL layer type --- Relu -- Relu_9 Supported TIDL layer type --- Conv -- Conv_10 Supported TIDL layer type --- Add -- Add_11 Supported TIDL layer type --- Relu -- Relu_12 Supported TIDL layer type --- Conv -- Conv_16 Supported TIDL layer type --- Conv -- Conv_13 Supported TIDL layer type --- Relu -- Relu_14 Supported TIDL layer type --- Conv -- Conv_15 Supported TIDL layer type --- Add -- Add_17 Supported TIDL layer type --- Relu -- Relu_18 Supported TIDL layer type --- Conv -- Conv_19 Supported TIDL layer type --- Relu -- Relu_20 Supported TIDL layer type --- Conv -- Conv_21 Supported TIDL layer type --- Add -- Add_22 Supported TIDL layer type --- Relu -- Relu_23 Supported TIDL layer type --- Conv -- Conv_140 Supported TIDL layer type --- Conv -- Conv_27 Supported TIDL layer type --- Conv -- Conv_24 Supported TIDL layer type --- Relu -- Relu_25 Supported TIDL layer type --- Conv -- Conv_26 Supported TIDL layer type --- Add -- Add_28 Supported TIDL layer type --- Relu -- Relu_29 Supported TIDL layer type --- Conv -- Conv_30 Supported TIDL layer type --- Relu -- Relu_31 Supported TIDL layer type --- Conv -- Conv_32 Supported TIDL layer type --- Add -- Add_33 Supported TIDL layer type --- Relu -- Relu_34 Supported TIDL layer type --- Conv -- Conv_141 Supported TIDL layer type --- Conv -- Conv_38 Supported TIDL layer type --- Conv -- Conv_35 Supported TIDL layer type --- Relu -- Relu_36 Supported TIDL layer type --- Conv -- Conv_37 Supported TIDL layer type --- Add -- Add_39 Supported TIDL layer type --- Relu -- Relu_40 Supported TIDL layer type --- Conv -- Conv_41 Supported TIDL layer type --- Relu -- Relu_42 Supported TIDL layer type --- Conv -- Conv_43 Supported TIDL layer type --- Add -- Add_44 Supported TIDL layer type --- Relu -- Relu_45 Supported TIDL layer type --- Conv -- Conv_46 Supported TIDL layer type --- Relu -- Relu_47 Supported TIDL layer type --- Add -- Add_58 Supported TIDL layer type --- Conv -- Conv_77 Supported TIDL layer type --- Reshape -- Reshape_82 Supported TIDL layer type --- Conv -- Conv_66 Supported TIDL layer type --- Reshape -- Reshape_71 Supported TIDL layer type --- Conv -- Conv_59 Supported TIDL layer type --- Reshape -- Reshape_64 Supported TIDL layer type --- Transpose -- Transpose_65 Supported TIDL layer type --- MatMul -- MatMul_72 Supported TIDL layer type --- Reshape -- reshape_Unsqueeze_73 Supported TIDL layer type --- Softmax -- Softmax_74 debug_TIDL_onnxMapSqueezeBaseParams: lIdx-61 axisIdx-0 squeeze axis[0] - 0 squeeze indim - 1 squeeze indim - 1 squeeze indim - 250 squeeze indim - 250 debug_TIDL_onnxMapSqueezeBaseParams: numDim-4 axes-2 Supported TIDL layer type --- Squeeze -- Squeeze_75 Supported TIDL layer type --- Transpose -- Transpose_76 Supported TIDL layer type --- MatMul -- MatMul_83 Supported TIDL layer type --- Reshape -- Reshape_88 Supported TIDL layer type --- Mul -- Mul_89 Supported TIDL layer type --- Add -- Add_90 Supported TIDL layer type --- Conv -- Conv_91 Supported TIDL layer type --- Relu -- Relu_92 Supported TIDL layer type --- Conv -- Conv_93 Supported TIDL layer type --- Relu -- Relu_94 Supported TIDL layer type --- Add -- Add_105 Supported TIDL layer type --- Conv -- Conv_124 Supported TIDL layer type --- Reshape -- Reshape_129 Supported TIDL layer type --- Conv -- Conv_113 Supported TIDL layer type --- Reshape -- Reshape_118 Supported TIDL layer type --- Conv -- Conv_106 Supported TIDL layer type --- Reshape -- Reshape_111 Supported TIDL layer type --- Transpose -- Transpose_112 Supported TIDL layer type --- MatMul -- MatMul_119 Supported TIDL layer type --- Reshape -- reshape_Unsqueeze_120 Supported TIDL layer type --- Softmax -- Softmax_121 debug_TIDL_onnxMapSqueezeBaseParams: lIdx-82 axisIdx-0 squeeze axis[0] - 0 squeeze indim - 1 squeeze indim - 1 squeeze indim - 250 squeeze indim - 250 debug_TIDL_onnxMapSqueezeBaseParams: numDim-4 axes-2 Supported TIDL layer type --- Squeeze -- Squeeze_122 Supported TIDL layer type --- Transpose -- Transpose_123 Supported TIDL layer type --- MatMul -- MatMul_130 Supported TIDL layer type --- Reshape -- Reshape_135 Supported TIDL layer type --- Mul -- Mul_136 Supported TIDL layer type --- Add -- Add_137 Supported TIDL layer type --- Conv -- Conv_138 Supported TIDL layer type --- Relu -- Relu_139 Supported TIDL layer type --- Conv -- Conv_142 Supported TIDL layer type --- Upsample -- Upsample_143 Supported TIDL layer type --- Add -- Add_144 Supported TIDL layer type --- Upsample -- Upsample_145 Supported TIDL layer type --- Add -- Add_146 Supported TIDL layer type --- Conv -- Conv_147 Supported TIDL layer type --- Conv -- Conv_185 Supported TIDL layer type --- Relu -- Relu_186 Supported TIDL layer type --- Conv -- Conv_187 Supported TIDL layer type --- Relu -- Relu_188 Supported TIDL layer type --- Conv -- Conv_189 Supported TIDL layer type --- Conv -- Conv_148 Supported TIDL layer type --- Conv -- Conv_155 Supported TIDL layer type --- Relu -- Relu_156 Supported TIDL layer type --- Conv -- Conv_157 Supported TIDL layer type --- Reshape -- Reshape_195 Supported TIDL layer type --- Transpose -- Transpose_196 Supported TIDL layer type --- Reshape -- Reshape_203 Supported TIDL layer type --- Conv -- Conv_228 Supported TIDL layer type --- Transpose -- Transpose_229 Supported TIDL layer type --- Reshape -- Reshape_231 Supported TIDL layer type --- Conv -- Conv_289 Supported TIDL layer type --- Transpose -- Transpose_290 Supported TIDL layer type --- Reshape -- Reshape_292 Supported TIDL layer type --- Conv -- Conv_152 Supported TIDL layer type --- Relu -- Relu_153 Supported TIDL layer type --- Conv -- Conv_154 Supported TIDL layer type --- Sigmoid -- Sigmoid_170 Supported TIDL layer type --- Add -- Add_172 Supported TIDL layer type --- Relu -- Relu_173 Supported TIDL layer type --- Add -- Add_175 Supported TIDL layer type --- Mul -- Mul_177 Supported TIDL layer type --- Add -- Add_179 Supported TIDL layer type --- Relu -- Relu_180 Supported TIDL layer type --- Mul -- Mul_182 Supported TIDL layer type --- Add -- Add_184 Supported TIDL layer type --- MaxPool -- MaxPool_204 Supported TIDL layer type --- Mul -- Mul_206 Supported TIDL layer type --- Add -- Add_207 Supported TIDL layer type --- Mul -- Mul_209 Supported TIDL layer type --- Add -- Add_211 Supported TIDL layer type --- Relu -- Relu_212 Supported TIDL layer type --- Mul -- Mul_214 Supported TIDL layer type --- Mul -- Mul_215 debug_TIDL_onnxMapSqueezeBaseParams: lIdx-134 axisIdx-0 squeeze axis[0] - 0 squeeze indim - 1 squeeze indim - 1 squeeze indim - 20 squeeze indim - 50 debug_TIDL_onnxMapSqueezeBaseParams: numDim-4 axes-2 Supported TIDL layer type --- Squeeze -- Squeeze_216 Supported TIDL layer type --- Reshape -- Reshape_218 debug_TIDL_onnxMapTopKBaseParams: in-1 out-2 Supported TIDL layer type --- TopK -- TopK_219 Supported TIDL layer type --- Reshape -- Reshape_221 debug_TIDL_onnxMapSqueezeBaseParams: lIdx-138 axisIdx-0 squeeze axis[0] - 1 squeeze indim - 6 squeeze indim - 1 debug_TIDL_onnxMapSqueezeBaseParams: numDim-2 axes-5 Supported TIDL layer type --- Squeeze -- Squeeze_224 Compute on node : TIDLExecutionProvider_TIDL_0_0 0, Conv, 3, 1, image, 717 1, Relu, 1, 1, 717, 227 2, MaxPool, 1, 1, 227, 228 3, Conv, 3, 1, 228, 720 4, Relu, 1, 1, 720, 231 5, Conv, 3, 1, 231, 723 6, Add, 2, 1, 723, 234 7, Relu, 1, 1, 234, 235 8, Conv, 3, 1, 235, 726 9, Relu, 1, 1, 726, 238 10, Conv, 3, 1, 238, 729 11, Add, 2, 1, 729, 241 12, Relu, 1, 1, 241, 242 13, Conv, 3, 1, 242, 738 14, Conv, 3, 1, 242, 732 15, Relu, 1, 1, 732, 245 16, Conv, 3, 1, 245, 735 17, Add, 2, 1, 735, 250 18, Relu, 1, 1, 250, 251 19, Conv, 3, 1, 251, 741 20, Relu, 1, 1, 741, 254 21, Conv, 3, 1, 254, 744 22, Add, 2, 1, 744, 257 23, Relu, 1, 1, 257, 258 24, Conv, 3, 1, 258, 405 25, Conv, 3, 1, 258, 753 26, Conv, 3, 1, 258, 747 27, Relu, 1, 1, 747, 261 28, Conv, 3, 1, 261, 750 29, Add, 2, 1, 750, 266 30, Relu, 1, 1, 266, 267 31, Conv, 3, 1, 267, 756 32, Relu, 1, 1, 756, 270 33, Conv, 3, 1, 270, 759 34, Add, 2, 1, 759, 273 35, Relu, 1, 1, 273, 274 36, Conv, 3, 1, 274, 406 37, Conv, 3, 1, 274, 768 38, Conv, 3, 1, 274, 762 39, Relu, 1, 1, 762, 277 40, Conv, 3, 1, 277, 765 41, Add, 2, 1, 765, 282 42, Relu, 1, 1, 282, 283 43, Conv, 3, 1, 283, 771 44, Relu, 1, 1, 771, 286 45, Conv, 3, 1, 286, 774 46, Add, 2, 1, 774, 289 47, Relu, 1, 1, 289, 290 48, Conv, 3, 1, 290, 777 49, Relu, 1, 1, 777, 293 50, Add, 2, 1, 293, 304 51, Conv, 3, 1, 304, 327 52, Reshape, 2, 1, 327, 334 53, Conv, 3, 1, 304, 314 54, Reshape, 2, 1, 314, 321 55, Conv, 3, 1, 304, 305 56, Reshape, 2, 1, 305, 312 57, Transpose, 1, 1, 312, 313 58, MatMul, 2, 1, 313, 322 59, Reshape, 2, 1, 322, 323 60, Softmax, 1, 1, 323, 324 61, Squeeze, 1, 1, 324, 325 62, Transpose, 1, 1, 325, 326 63, MatMul, 2, 1, 334, 335 64, Reshape, 2, 1, 335, 342 65, Mul, 2, 1, ortshared_6_1_1, 343 66, Add, 2, 1, 343, 344 67, Conv, 3, 1, 344, 780 68, Relu, 1, 1, 780, 347 69, Conv, 3, 1, 347, 783 70, Relu, 1, 1, 783, 350 71, Add, 2, 1, 350, 361 72, Conv, 3, 1, 361, 384 73, Reshape, 2, 1, 384, 391 74, Conv, 3, 1, 361, 371 75, Reshape, 2, 1, 371, 378 76, Conv, 3, 1, 361, 362 77, Reshape, 2, 1, 362, 369 78, Transpose, 1, 1, 369, 370 79, MatMul, 2, 1, 370, 379 80, Reshape, 2, 1, 379, 380 81, Softmax, 1, 1, 380, 381 82, Squeeze, 1, 1, 381, 382 83, Transpose, 1, 1, 382, 383 84, MatMul, 2, 1, 391, 392 85, Reshape, 2, 1, 392, 399 86, Mul, 2, 1, ortshared_5_1_1, 400 87, Add, 2, 1, 400, 401 88, Conv, 3, 1, 401, 786 89, Relu, 1, 1, 786, 404 90, Conv, 3, 1, 404, 407 91, Upsample, 2, 1, 407, 411 92, Add, 2, 1, 406, 412 93, Upsample, 2, 1, 412, 416 94, Add, 2, 1, 405, 417 95, Conv, 3, 1, 417, 418 96, Conv, 3, 1, 418, 789 97, Relu, 1, 1, 789, 458 98, Conv, 3, 1, 458, 792 99, Relu, 1, 1, 792, 461 100, Conv, 3, 1, 461, 795 101, Conv, 3, 1, 412, 419 102, Conv, 3, 1, 419, 426 103, Relu, 1, 1, 426, 427 104, Conv, 3, 1, 427, 428 105, Reshape, 2, 1, 428, 473 106, Transpose, 1, 1, 473, 474 107, Reshape, 2, 1, 474, 485 108, Conv, 2, 1, 485, 511 109, Transpose, 1, 1, 511, 512 110, Reshape, 2, 1, 512, 514 111, Conv, 2, 1, 485, 604 112, Transpose, 1, 1, 604, 605 113, Reshape, 2, 1, 605, 607 114, Conv, 3, 1, 419, 423 115, Relu, 1, 1, 423, 424 116, Conv, 3, 1, 424, 425 117, Sigmoid, 1, 1, 425, 441 118, Add, 2, 1, 441, 443 119, Relu, 1, 1, 443, 444 120, Add, 2, 1, 444, 446 121, Mul, 2, 1, 447, 448 122, Add, 2, 1, 449, 450 123, Relu, 1, 1, 450, 451 124, Mul, 2, 1, 447, 453 125, Add, 2, 1, 449, 455 126, MaxPool, 1, 1, 455, 486 127, Mul, 2, 1, 486, 488 128, Add, 2, 1, 455, 489 129, Mul, 2, 1, 489, 491 130, Add, 2, 1, 491, 493 131, Relu, 1, 1, 493, 494 132, Mul, 2, 1, 494, 496 133, Mul, 2, 1, 455, 497 134, Squeeze, 1, 1, 497, 498 135, Reshape, 2, 1, 498, 500 136, TopK, 1, 2, 500, 501 137, Reshape, 2, 1, 502, seeds 138, Squeeze, 1, 1, seeds, 507 Input tensor name - image Output tensor name - seeds Output tensor name - 507 Output tensor name - 607 Output tensor name - 514 Output tensor name - 795 Graph Domain TO version : 9In TIDL_onnxRtImportInit subgraph_name=795514607501507 Layer 0, subgraph id 795514607501507, name=seeds Layer 1, subgraph id 795514607501507, name=507 Layer 2, subgraph id 795514607501507, name=607 Layer 3, subgraph id 795514607501507, name=514 Layer 4, subgraph id 795514607501507, name=795 Layer 5, subgraph id 795514607501507, name=image debug_TIDL_onnxMapSqueezeBaseParams: lIdx-61 axisIdx-0 squeeze axis[0] - 0 squeeze indim - 1 squeeze indim - 1 squeeze indim - 250 squeeze indim - 250 debug_TIDL_onnxMapSqueezeBaseParams: numDim-4 axes-2 debug_TIDL_onnxMapSqueezeBaseParams: lIdx-82 axisIdx-0 squeeze axis[0] - 0 squeeze indim - 1 squeeze indim - 1 squeeze indim - 250 squeeze indim - 250 debug_TIDL_onnxMapSqueezeBaseParams: numDim-4 axes-2 debug_TIDL_onnxMapSqueezeBaseParams: lIdx-134 axisIdx-0 squeeze axis[0] - 0 squeeze indim - 1 squeeze indim - 1 squeeze indim - 20 squeeze indim - 50 debug_TIDL_onnxMapSqueezeBaseParams: numDim-4 axes-2 debug_TIDL_onnxMapTopKBaseParams: in-1 out-2 debug_TIDL_onnxMapSqueezeBaseParams: lIdx-138 axisIdx-0 squeeze axis[0] - 1 squeeze indim - 6 squeeze indim - 1 debug_TIDL_onnxMapSqueezeBaseParams: numDim-2 axes-5 In TIDL_runtimesOptimizeNet: LayerIndex = 145, dataIndex = 141 debug_tidl_optimizeNet0: numLayers-153 0 0 printing Current net 0|TIDL_DataLayer | |image | 0| 0| 0| 6| 1|TIDL_ConvolutionLayer |image |717 | 0| 1| 0| 3| 2|TIDL_ReLULayer |717 |227 | 1| 2| 0| 0| 3|TIDL_PoolingLayer |227 |228 | 2| 3| 0| 0| 4|TIDL_ConvolutionLayer |228 |720 | 3| 4| 0| 3| 5|TIDL_ReLULayer |720 |231 | 4| 5| 0| 0| 6|TIDL_ConvolutionLayer |231 |723 | 5| 6| 0| 3| 7|TIDL_EltWiseLayer |723 |234 | 6| 7| 0| 0| 8|TIDL_ReLULayer |234 |235 | 7| 8| 0| 0| 9|TIDL_ConvolutionLayer |235 |726 | 8| 9| 0| 3| 10|TIDL_ReLULayer |726 |238 | 9| 10| 0| 0| 11|TIDL_ConvolutionLayer |238 |729 | 10| 11| 0| 3| 12|TIDL_EltWiseLayer |729 |241 | 11| 12| 0| 0| 13|TIDL_ReLULayer |241 |242 | 12| 13| 0| 0| 14|TIDL_ConvolutionLayer |242 |738 | 13| 14| 0| 3| 15|TIDL_ConvolutionLayer |242 |732 | 13| 15| 0| 3| 16|TIDL_ReLULayer |732 |245 | 15| 16| 0| 0| 17|TIDL_ConvolutionLayer |245 |735 | 16| 17| 0| 3| 18|TIDL_EltWiseLayer |735 |250 | 17| 18| 0| 0| 19|TIDL_ReLULayer |250 |251 | 18| 19| 0| 0| 20|TIDL_ConvolutionLayer |251 |741 | 19| 20| 0| 3| 21|TIDL_ReLULayer |741 |254 | 20| 21| 0| 0| 22|TIDL_ConvolutionLayer |254 |744 | 21| 22| 0| 3| 23|TIDL_EltWiseLayer |744 |257 | 22| 23| 0| 0| 24|TIDL_ReLULayer |257 |258 | 23| 24| 0| 0| 25|TIDL_ConvolutionLayer |258 |405 | 24| 25| 0| 3| 26|TIDL_ConvolutionLayer |258 |753 | 24| 26| 0| 3| 27|TIDL_ConvolutionLayer |258 |747 | 24| 27| 0| 3| 28|TIDL_ReLULayer |747 |261 | 27| 28| 0| 0| 29|TIDL_ConvolutionLayer |261 |750 | 28| 29| 0| 3| 30|TIDL_EltWiseLayer |750 |266 | 29| 30| 0| 0| 31|TIDL_ReLULayer |266 |267 | 30| 31| 0| 0| 32|TIDL_ConvolutionLayer |267 |756 | 31| 32| 0| 3| 33|TIDL_ReLULayer |756 |270 | 32| 33| 0| 0| 34|TIDL_ConvolutionLayer |270 |759 | 33| 34| 0| 3| 35|TIDL_EltWiseLayer |759 |273 | 34| 35| 0| 0| 36|TIDL_ReLULayer |273 |274 | 35| 36| 0| 0| 37|TIDL_ConvolutionLayer |274 |406 | 36| 37| 0| 3| 38|TIDL_ConvolutionLayer |274 |768 | 36| 38| 0| 3| 39|TIDL_ConvolutionLayer |274 |762 | 36| 39| 0| 3| 40|TIDL_ReLULayer |762 |277 | 39| 40| 0| 0| 41|TIDL_ConvolutionLayer |277 |765 | 40| 41| 0| 3| 42|TIDL_EltWiseLayer |765 |282 | 41| 42| 0| 0| 43|TIDL_ReLULayer |282 |283 | 42| 43| 0| 0| 44|TIDL_ConvolutionLayer |283 |771 | 43| 44| 0| 3| 45|TIDL_ReLULayer |771 |286 | 44| 45| 0| 0| 46|TIDL_ConvolutionLayer |286 |774 | 45| 46| 0| 3| 47|TIDL_EltWiseLayer |774 |289 | 46| 47| 0| 0| 48|TIDL_ReLULayer |289 |290 | 47| 48| 0| 0| 49|TIDL_ConvolutionLayer |290 |777 | 48| 49| 0| 3| 50|TIDL_ReLULayer |777 |293 | 49| 50| 0| 0| 51|TIDL_ConstDataLayer | |303_145 | 0| 51| 0| 3| 52|TIDL_ConstDataLayer | |303_146 | 0| 52| 0| 3| 53|TIDL_ConstDataLayer | |442_147 | 0| 53| 0| 3| 54|TIDL_ConstDataLayer | |445_148 | 0| 54| 0| 3| 55|TIDL_ConstDataLayer | |447_149 | 0| 55| 0| 3| 56|TIDL_ConstDataLayer | |449_150 | 0| 56| 0| 3| 57|TIDL_ConstDataLayer | |447_151 | 0| 57| 0| 3| 58|TIDL_ConstDataLayer | |449_152 | 0| 58| 0| 3| 59|TIDL_EltWiseLayer |293 |304 | 50| 59| 0| 0| 60|TIDL_ConvolutionLayer |304 |327 | 59| 60| 0| 3| 61|TIDL_ReshapeLayer |327 |334 | 60| 61| 0| 0| 62|TIDL_ConvolutionLayer |304 |314 | 59| 62| 0| 3| 63|TIDL_ReshapeLayer |314 |321 | 62| 63| 0| 0| 64|TIDL_ConvolutionLayer |304 |305 | 59| 64| 0| 3| 65|TIDL_ReshapeLayer |305 |312 | 64| 65| 0| 0| 66|TIDL_TransposeLayer |312 |313 | 65| 66| 0| 0| 67|TIDL_InnerProductLayer |313 |322 | 66| 67| 0| 3| 68|TIDL_ReshapeLayer |322 |323 | 67| 68| 0| 0| 69|TIDL_SoftMaxLayer |323 |324 | 68| 69| 0| 0| 70|TIDL_SqueezeLayer |324 |325 | 69| 70| 0| 0| 71|TIDL_TransposeLayer |325 |326 | 70| 71| 0| 0| 72|TIDL_InnerProductLayer |334 |335 | 61| 72| 0| 3| 73|TIDL_ReshapeLayer |335 |342 | 72| 73| 0| 0| 74|TIDL_BatchNormLayer |342 |343 | 73| 74| 0| 0| 75|TIDL_EltWiseLayer |343 |344 | 74| 75| 0| 0| 76|TIDL_ConvolutionLayer |344 |780 | 75| 76| 0| 3| 77|TIDL_ReLULayer |780 |347 | 76| 77| 0| 0| 78|TIDL_ConvolutionLayer |347 |783 | 77| 78| 0| 3| 79|TIDL_ReLULayer |783 |350 | 78| 79| 0| 0| 80|TIDL_EltWiseLayer |350 |361 | 79| 80| 0| 0| 81|TIDL_ConvolutionLayer |361 |384 | 80| 81| 0| 3| 82|TIDL_ReshapeLayer |384 |391 | 81| 82| 0| 0| 83|TIDL_ConvolutionLayer |361 |371 | 80| 83| 0| 3| 84|TIDL_ReshapeLayer |371 |378 | 83| 84| 0| 0| 85|TIDL_ConvolutionLayer |361 |362 | 80| 85| 0| 3| 86|TIDL_ReshapeLayer |362 |369 | 85| 86| 0| 0| 87|TIDL_TransposeLayer |369 |370 | 86| 87| 0| 0| 88|TIDL_InnerProductLayer |370 |379 | 87| 88| 0| 3| 89|TIDL_ReshapeLayer |379 |380 | 88| 89| 0| 0| 90|TIDL_SoftMaxLayer |380 |381 | 89| 90| 0| 0| 91|TIDL_SqueezeLayer |381 |382 | 90| 91| 0| 0| 92|TIDL_TransposeLayer |382 |383 | 91| 92| 0| 0| 93|TIDL_InnerProductLayer |391 |392 | 82| 93| 0| 3| 94|TIDL_ReshapeLayer |392 |399 | 93| 94| 0| 0| 95|TIDL_BatchNormLayer |399 |400 | 94| 95| 0| 0| 96|TIDL_EltWiseLayer |400 |401 | 95| 96| 0| 0| 97|TIDL_ConvolutionLayer |401 |786 | 96| 97| 0| 3| 98|TIDL_ReLULayer |786 |404 | 97| 98| 0| 0| 99|TIDL_ConvolutionLayer |404 |407 | 98| 99| 0| 3| 100|TIDL_ResizeLayer |407 |411 | 99| 100| 0| 0| 101|TIDL_EltWiseLayer |406 |412 | 37| 101| 0| 0| 102|TIDL_ResizeLayer |412 |416 | 101| 102| 0| 0| 103|TIDL_EltWiseLayer |405 |417 | 25| 103| 0| 0| 104|TIDL_ConvolutionLayer |417 |418 | 103| 104| 0| 3| 105|TIDL_ConvolutionLayer |418 |789 | 104| 105| 0| 3| 106|TIDL_ReLULayer |789 |458 | 105| 106| 0| 0| 107|TIDL_ConvolutionLayer |458 |792 | 106| 107| 0| 3| 108|TIDL_ReLULayer |792 |461 | 107| 108| 0| 0| 109|TIDL_ConvolutionLayer |461 |795 | 108| 109| 0| 3| 110|TIDL_ConvolutionLayer |412 |419 | 101| 110| 0| 3| 111|TIDL_ConvolutionLayer |419 |426 | 110| 111| 0| 3| 112|TIDL_ReLULayer |426 |427 | 111| 112| 0| 0| 113|TIDL_ConvolutionLayer |427 |428 | 112| 113| 0| 3| 114|TIDL_ReshapeLayer |428 |473 | 113| 114| 0| 0| 115|TIDL_TransposeLayer |473 |474 | 114| 115| 0| 0| 116|TIDL_ReshapeLayer |474 |485 | 115| 116| 0| 0| 117|TIDL_ConvolutionLayer |485 |511 | 116| 117| 0| 3| 118|TIDL_TransposeLayer |511 |512 | 117| 118| 0| 0| 119|TIDL_ReshapeLayer |512 |514 | 118| 119| 0| 0| 120|TIDL_ConvolutionLayer |485 |604 | 116| 120| 0| 3| 121|TIDL_TransposeLayer |604 |605 | 120| 121| 0| 0| 122|TIDL_ReshapeLayer |605 |607 | 121| 122| 0| 0| 123|TIDL_ConvolutionLayer |419 |423 | 110| 123| 0| 3| 124|TIDL_ReLULayer |423 |424 | 123| 124| 0| 0| 125|TIDL_ConvolutionLayer |424 |425 | 124| 125| 0| 3| 126|TIDL_SigmoidLayer |425 |441 | 125| 126| 0| 2| 127|TIDL_EltWiseLayer |441 |443 | 126| 127| 0| 0| 128|TIDL_ReLULayer |443 |444 | 127| 128| 0| 0| 129|TIDL_EltWiseLayer |444 |446 | 128| 129| 0| 0| 130|TIDL_EltWiseLayer |447_149 |448 | 55| 130| 0| 0| 131|TIDL_EltWiseLayer |449_150 |450 | 56| 131| 0| 0| 132|TIDL_ReLULayer |450 |451 | 131| 132| 0| 0| 133|TIDL_EltWiseLayer |447_151 |453 | 57| 133| 0| 0| 134|TIDL_EltWiseLayer |449_152 |455 | 58| 134| 0| 0| 135|TIDL_PoolingLayer |455 |486 | 134| 135| 0| 0| 136|TIDL_BatchNormLayer |486 |488 | 135| 136| 0| 0| 137|TIDL_EltWiseLayer |455 |489 | 134| 137| 0| 0| 138|TIDL_BatchNormLayer |489 |491 | 137| 138| 0| 0| 139|TIDL_BatchNormLayer |491 |493 | 138| 139| 0| 0| 140|TIDL_ReLULayer |493 |494 | 139| 140| 0| 0| 141|TIDL_BatchNormLayer |494 |496 | 140| 141| 0| 0| 142|TIDL_EltWiseLayer |455 |497 | 134| 142| 0| 0| 143|TIDL_SqueezeLayer |497 |498 | 142| 143| 0| 0| 144|TIDL_ReshapeLayer |498 |500 | 143| 144| 0| 0| 145|TIDL_TopKLayer |500 |501 | 144| 145| 0| 0| 146|TIDL_ReshapeLayer |502 |seeds | 146| 147| 0| 0| 147|TIDL_SqueezeLayer |seeds |507 | 147| 148| 0| 0| 148|TIDL_DataLayer |seeds |seeds | 147| 0| 0| 0| 149|TIDL_DataLayer |507 |507 | 148| 0| 0| 0| 150|TIDL_DataLayer |607 |607 | 122| 0| 0| 0| 151|TIDL_DataLayer |514 |514 | 119| 0| 0| 0| 152|TIDL_DataLayer |795 |795 | 109| 0| 0| 0| debug_TIDL_tfOutReshapeReshapeLayer: lInd - 61, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 63, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 65, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 68, eltType - 3 debug_TIDL_tfOutReshapeSqueeze: axis[5] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[4] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[3] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[2] - 1 debug_TIDL_tfOutReshapeSqueeze: axis[1] - 0 debug_TIDL_tfOutReshapeSqueeze: lInd-70 type-2 1 1 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 73, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 82, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 84, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 86, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 89, eltType - 3 debug_TIDL_tfOutReshapeSqueeze: axis[5] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[4] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[3] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[2] - 1 debug_TIDL_tfOutReshapeSqueeze: axis[1] - 0 debug_TIDL_tfOutReshapeSqueeze: lInd-91 type-2 1 1 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 94, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 114, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 116, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 119, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 122, eltType - 3 debug_TIDL_tfOutReshapeSqueeze: axis[5] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[4] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[3] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[2] - 1 debug_TIDL_tfOutReshapeSqueeze: axis[1] - 0 debug_TIDL_tfOutReshapeSqueeze: lInd-143 type-3 1 1 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 144, eltType - 3 debug_TIDL_tfOutReshapeTopK: numOutBufs-2 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 146, eltType - 3 debug_TIDL_tfOutReshapeSqueeze: axis[5] - 1 debug_TIDL_tfOutReshapeSqueeze: axis[4] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[3] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[2] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[1] - 0 debug_TIDL_tfOutReshapeSqueeze: lInd-147 type-3 1 1 debug_tidl_optimizeNet1: numLayers-153 0 0 debug_tidl_optimizeNet2: numLayers-124 0 0 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 43, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 45, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 47, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 50, eltType - 3 debug_TIDL_tfOutReshapeSqueeze: axis[5] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[4] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[3] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[2] - 1 debug_TIDL_tfOutReshapeSqueeze: axis[1] - 0 debug_TIDL_tfOutReshapeSqueeze: lInd-52 type-2 1 1 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 55, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 62, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 64, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 66, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 69, eltType - 3 debug_TIDL_tfOutReshapeSqueeze: axis[5] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[4] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[3] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[2] - 1 debug_TIDL_tfOutReshapeSqueeze: axis[1] - 0 debug_TIDL_tfOutReshapeSqueeze: lInd-71 type-2 1 1 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 74, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 90, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 92, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 95, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 98, eltType - 3 debug_TIDL_tfOutReshapeSqueeze: axis[5] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[4] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[3] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[2] - 1 debug_TIDL_tfOutReshapeSqueeze: axis[1] - 0 debug_TIDL_tfOutReshapeSqueeze: lInd-114 type-3 1 1 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 115, eltType - 3 debug_TIDL_tfOutReshapeTopK: numOutBufs-2 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 117, eltType - 3 debug_TIDL_tfOutReshapeSqueeze: axis[5] - 1 debug_TIDL_tfOutReshapeSqueeze: axis[4] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[3] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[2] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[1] - 0 debug_TIDL_tfOutReshapeSqueeze: lInd-118 type-3 1 1 debug_tidl_optimizeNet3: numLayers-122 0 0 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 44, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 46, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 48, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 51, eltType - 3 debug_TIDL_tfOutReshapeSqueeze: axis[5] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[4] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[3] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[2] - 1 debug_TIDL_tfOutReshapeSqueeze: axis[1] - 0 debug_TIDL_tfOutReshapeSqueeze: lInd-53 type-2 1 1 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 55, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 62, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 64, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 66, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 69, eltType - 3 debug_TIDL_tfOutReshapeSqueeze: axis[5] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[4] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[3] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[2] - 1 debug_TIDL_tfOutReshapeSqueeze: axis[1] - 0 debug_TIDL_tfOutReshapeSqueeze: lInd-71 type-2 1 1 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 73, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 89, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 91, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 94, eltType - 3 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 97, eltType - 3 debug_TIDL_tfOutReshapeSqueeze: axis[5] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[4] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[3] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[2] - 1 debug_TIDL_tfOutReshapeSqueeze: axis[1] - 0 debug_TIDL_tfOutReshapeSqueeze: lInd-113 type-3 1 1 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 114, eltType - 3 debug_TIDL_tfOutReshapeTopK: numOutBufs-2 debug_TIDL_tfOutReshapeReshapeLayer: lInd - 116, eltType - 3 debug_TIDL_tfOutReshapeSqueeze: axis[5] - 1 debug_TIDL_tfOutReshapeSqueeze: axis[4] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[3] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[2] - 0 debug_TIDL_tfOutReshapeSqueeze: axis[1] - 0 debug_TIDL_tfOutReshapeSqueeze: lInd-117 type-3 1 1 debug_tidl_optimizeNet4: numLayers-128 0 0 debug_tidl_optimizeNet4.2: numLayers-128 debug_tidl_optimizeNet5: numLayers-184 debug_tidl_optimizeNet6: numLayers-184 debug_tidl_optimizeNet7: numLayers-184 printing Current net 0|TIDL_DataLayer | |image | 0| 0| 0| 6| 1|TIDL_ConstDataLayer | |303_145 | 0| 1| 0| 3| 2|TIDL_ConstDataLayer | |303_146 | 0| 2| 0| 3| 3|TIDL_ConstDataLayer | |442_147 | 0| 3| 0| 3| 4|TIDL_ConstDataLayer | |445_148 | 0| 4| 0| 3| 5|TIDL_ConstDataLayer | |447_149 | 0| 5| 0| 3| 6|TIDL_ConstDataLayer | |449_150 | 0| 6| 0| 3| 7|TIDL_ConstDataLayer | |447_151 | 0| 7| 0| 3| 8|TIDL_ConstDataLayer | |449_152 | 0| 8| 0| 3| 9|TIDL_DataConvertLayer |image |image_netFormat | 0| 9| 6| 3| 10|TIDL_ConvolutionLayer |image_netFormat |227 | 9| 10| 3| 2| 11|TIDL_PoolingLayer |227 |228 | 10| 11| 2| 2| 12|TIDL_ConvolutionLayer |228 |231 | 11| 12| 2| 2| 13|TIDL_ConvolutionLayer |231 |723 | 12| 13| 2| 3| 14|TIDL_EltWiseLayer |723 |235 | 13| 14| 3| 2| 15|TIDL_ConvolutionLayer |235 |238 | 14| 15| 2| 2| 16|TIDL_ConvolutionLayer |238 |729 | 15| 16| 2| 3| 17|TIDL_EltWiseLayer |729 |242 | 16| 17| 3| 2| 18|TIDL_ConvolutionLayer |242 |738 | 17| 18| 2| 3| 19|TIDL_ConvolutionLayer |242 |245 | 17| 19| 2| 2| 20|TIDL_ConvolutionLayer |245 |735 | 19| 20| 2| 3| 21|TIDL_EltWiseLayer |735 |251 | 20| 21| 3| 2| 22|TIDL_ConvolutionLayer |251 |254 | 21| 22| 2| 2| 23|TIDL_ConvolutionLayer |254 |744 | 22| 23| 2| 3| 24|TIDL_EltWiseLayer |744 |258 | 23| 24| 3| 2| 25|TIDL_ConvolutionLayer |258 |405 | 24| 25| 2| 3| 26|TIDL_ConvolutionLayer |258 |753 | 24| 26| 2| 3| 27|TIDL_ConvolutionLayer |258 |261 | 24| 27| 2| 2| 28|TIDL_ConvolutionLayer |261 |750 | 27| 28| 2| 3| 29|TIDL_EltWiseLayer |750 |267 | 28| 29| 3| 2| 30|TIDL_ConvolutionLayer |267 |270 | 29| 30| 2| 2| 31|TIDL_ConvolutionLayer |270 |759 | 30| 31| 2| 3| 32|TIDL_EltWiseLayer |759 |274 | 31| 32| 3| 2| 33|TIDL_ConvolutionLayer |274 |406 | 32| 33| 2| 3| 34|TIDL_ConvolutionLayer |274 |768 | 32| 34| 2| 3| 35|TIDL_ConvolutionLayer |274 |277 | 32| 35| 2| 2| 36|TIDL_ConvolutionLayer |277 |765 | 35| 36| 2| 3| 37|TIDL_EltWiseLayer |765 |283 | 36| 37| 3| 2| 38|TIDL_ConvolutionLayer |283 |286 | 37| 38| 2| 2| 39|TIDL_ConvolutionLayer |286 |774 | 38| 39| 2| 3| 40|TIDL_EltWiseLayer |774 |290 | 39| 40| 3| 2| 41|TIDL_ConvolutionLayer |290 |293 | 40| 41| 2| 2| 42|TIDL_EltWiseLayer |293 |304 | 41| 42| 2| 3| 43|TIDL_ConvolutionLayer |304 |327 | 42| 43| 3| 3| 44|TIDL_ConvolutionLayer |304 |314 | 42| 45| 3| 3| 45|TIDL_ConvolutionLayer |304 |305 | 42| 47| 3| 3| 46|TIDL_DataConvertLayer |327 |327_netFormatB | 43| 184| 3| 3| 47|TIDL_DataConvertLayer |314 |314_netFormatB | 45| 186| 3| 3| 48|TIDL_DataConvertLayer |305 |305_netFormatB | 47| 188| 3| 3| 49|TIDL_ReshapeLayer |327_netFormatB |334_netFormatA | 184| 183| 3| 3| 50|TIDL_ReshapeLayer |314_netFormatB |321_netFormatA | 186| 185| 3| 3| 51|TIDL_ReshapeLayer |305_netFormatB |312_netFormatA | 188| 187| 3| 3| 52|TIDL_DataConvertLayer |334_netFormatA |334 | 183| 44| 3| 3| 53|TIDL_DataConvertLayer |321_netFormatA |321 | 185| 46| 3| 3| 54|TIDL_DataConvertLayer |312_netFormatA |312 | 187| 48| 3| 3| 55|TIDL_DataConvertLayer |312 |312_2 | 48| 157| 3| 3| 56|TIDL_DataConvertLayer |312_2 |312_2_netFormatB | 157| 190| 3| 3| 57|TIDL_ReshapeLayer |312_2_netFormatB |312_2_22_netFormatA | 190| 189| 3| 3| 58|TIDL_DataConvertLayer |312_2_22_netFormatA |312_2_22 | 189| 177| 3| 3| 59|TIDL_DataConvertLayer |312_2_22 |312_2_16 | 177| 171| 3| 3| 60|TIDL_DataConvertLayer |312_2_16 |312_2_16_netFormatB | 171| 192| 3| 3| 61|TIDL_ReshapeLayer |312_2_16_netFormatB |313_3_netFormatA | 192| 191| 3| 3| 62|TIDL_DataConvertLayer |313_3_netFormatA |313_3 | 191| 158| 3| 3| 63|TIDL_DataConvertLayer |313_3 |313 | 158| 49| 3| 3| 64|TIDL_InnerProductLayer |313 |323 | 49| 50| 3| 3| 65|TIDL_DataConvertLayer |323 |323_4 | 50| 159| 3| 3| 66|TIDL_DataConvertLayer |323_4 |323_4_netFormatB | 159| 194| 3| 3| 67|TIDL_ReshapeLayer |323_4_netFormatB |323_4_23_netFormatA | 194| 193| 3| 3| 68|TIDL_DataConvertLayer |323_4_23_netFormatA |323_4_23 | 193| 178| 3| 3| 69|TIDL_DataConvertLayer |323_4_23 |323_4_17 | 178| 172| 3| 3| 70|TIDL_DataConvertLayer |323_4_17 |323_4_17_netFormatB | 172| 196| 3| 3| 71|TIDL_ReshapeLayer |323_4_17_netFormatB |323_0_5_netFormatA | 196| 195| 3| 3| 72|TIDL_DataConvertLayer |323_0_5_netFormatA |323_0_5 | 195| 160| 3| 3| 73|TIDL_DataConvertLayer |323_0_5 |323_0 | 160| 51| 3| 3| 74|TIDL_SoftMaxLayer |323_0 |324 | 51| 52| 3| 2| 75|TIDL_InnerProductLayer |334 |335 | 44| 53| 3| 3| 76|TIDL_DataConvertLayer |335 |335_netFormatB | 53| 198| 3| 3| 77|TIDL_ReshapeLayer |335_netFormatB |342_netFormatA | 198| 197| 3| 3| 78|TIDL_DataConvertLayer |342_netFormatA |342 | 197| 54| 3| 3| 79|TIDL_BatchNormLayer |342 |343 | 54| 55| 3| 3| 80|TIDL_EltWiseLayer |343 |344 | 55| 56| 3| 3| 81|TIDL_ConvolutionLayer |344 |347 | 56| 57| 3| 2| 82|TIDL_ConvolutionLayer |347 |350 | 57| 58| 2| 2| 83|TIDL_EltWiseLayer |350 |361 | 58| 59| 2| 3| 84|TIDL_ConvolutionLayer |361 |384 | 59| 60| 3| 3| 85|TIDL_ConvolutionLayer |361 |371 | 59| 62| 3| 3| 86|TIDL_ConvolutionLayer |361 |362 | 59| 64| 3| 3| 87|TIDL_DataConvertLayer |384 |384_netFormatB | 60| 200| 3| 3| 88|TIDL_DataConvertLayer |371 |371_netFormatB | 62| 202| 3| 3| 89|TIDL_DataConvertLayer |362 |362_netFormatB | 64| 204| 3| 3| 90|TIDL_ReshapeLayer |384_netFormatB |391_netFormatA | 200| 199| 3| 3| 91|TIDL_ReshapeLayer |371_netFormatB |378_netFormatA | 202| 201| 3| 3| 92|TIDL_ReshapeLayer |362_netFormatB |369_netFormatA | 204| 203| 3| 3| 93|TIDL_DataConvertLayer |391_netFormatA |391 | 199| 61| 3| 3| 94|TIDL_DataConvertLayer |378_netFormatA |378 | 201| 63| 3| 3| 95|TIDL_DataConvertLayer |369_netFormatA |369 | 203| 65| 3| 3| 96|TIDL_DataConvertLayer |369 |369_6 | 65| 161| 3| 3| 97|TIDL_DataConvertLayer |369_6 |369_6_netFormatB | 161| 206| 3| 3| 98|TIDL_ReshapeLayer |369_6_netFormatB |369_6_24_netFormatA | 206| 205| 3| 3| 99|TIDL_DataConvertLayer |369_6_24_netFormatA |369_6_24 | 205| 179| 3| 3| 100|TIDL_DataConvertLayer |369_6_24 |369_6_18 | 179| 173| 3| 3| 101|TIDL_DataConvertLayer |369_6_18 |369_6_18_netFormatB | 173| 208| 3| 3| 102|TIDL_ReshapeLayer |369_6_18_netFormatB |370_7_netFormatA | 208| 207| 3| 3| 103|TIDL_DataConvertLayer |370_7_netFormatA |370_7 | 207| 162| 3| 3| 104|TIDL_DataConvertLayer |370_7 |370 | 162| 66| 3| 3| 105|TIDL_InnerProductLayer |370 |380 | 66| 67| 3| 3| 106|TIDL_DataConvertLayer |380 |380_8 | 67| 163| 3| 3| 107|TIDL_DataConvertLayer |380_8 |380_8_netFormatB | 163| 210| 3| 3| 108|TIDL_ReshapeLayer |380_8_netFormatB |380_8_25_netFormatA | 210| 209| 3| 3| 109|TIDL_DataConvertLayer |380_8_25_netFormatA |380_8_25 | 209| 180| 3| 3| 110|TIDL_DataConvertLayer |380_8_25 |380_8_19 | 180| 174| 3| 3| 111|TIDL_DataConvertLayer |380_8_19 |380_8_19_netFormatB | 174| 212| 3| 3| 112|TIDL_ReshapeLayer |380_8_19_netFormatB |380_1_9_netFormatA | 212| 211| 3| 3| 113|TIDL_DataConvertLayer |380_1_9_netFormatA |380_1_9 | 211| 164| 3| 3| 114|TIDL_DataConvertLayer |380_1_9 |380_1 | 164| 68| 3| 3| 115|TIDL_SoftMaxLayer |380_1 |381 | 68| 69| 3| 2| 116|TIDL_InnerProductLayer |391 |392 | 61| 70| 3| 3| 117|TIDL_DataConvertLayer |392 |392_netFormatB | 70| 214| 3| 3| 118|TIDL_ReshapeLayer |392_netFormatB |399_netFormatA | 214| 213| 3| 3| 119|TIDL_DataConvertLayer |399_netFormatA |399 | 213| 71| 3| 3| 120|TIDL_BatchNormLayer |399 |400 | 71| 72| 3| 3| 121|TIDL_EltWiseLayer |400 |401 | 72| 73| 3| 3| 122|TIDL_ConvolutionLayer |401 |404 | 73| 74| 3| 2| 123|TIDL_ConvolutionLayer |404 |407 | 74| 75| 2| 3| 124|TIDL_ResizeLayer |407 |411 | 75| 76| 3| 3| 125|TIDL_EltWiseLayer |406 |412 | 33| 77| 3| 3| 126|TIDL_ResizeLayer |412 |416 | 77| 78| 3| 3| 127|TIDL_EltWiseLayer |405 |417 | 25| 79| 3| 3| 128|TIDL_ConvolutionLayer |417 |418 | 79| 80| 3| 3| 129|TIDL_ConvolutionLayer |418 |458 | 80| 81| 3| 2| 130|TIDL_ConvolutionLayer |458 |461 | 81| 82| 2| 2| 131|TIDL_ConvolutionLayer |461 |795 | 82| 83| 2| 3| 132|TIDL_ConvolutionLayer |412 |419 | 77| 84| 3| 3| 133|TIDL_ConvolutionLayer |419 |427 | 84| 85| 3| 2| 134|TIDL_ConvolutionLayer |427 |473 | 85| 86| 2| 3| 135|TIDL_ConvolutionLayer |419 |424 | 84| 95| 3| 2| 136|TIDL_ConvolutionLayer |424 |425 | 95| 96| 2| 3| 137|TIDL_BatchNormLayer |425 |441 | 96| 97| 3| 2| 138|TIDL_EltWiseLayer |441 |444 | 97| 98| 2| 2| 139|TIDL_EltWiseLayer |444 |446 | 98| 99| 2| 3| 140|TIDL_EltWiseLayer |447_149 |448 | 5| 100| 3| 3| 141|TIDL_EltWiseLayer |449_150 |451 | 6| 101| 3| 2| 142|TIDL_EltWiseLayer |447_151 |453 | 7| 102| 3| 3| 143|TIDL_EltWiseLayer |449_152 |455 | 8| 103| 3| 3| 144|TIDL_PoolingLayer |455 |486 | 103| 104| 3| 3| 145|TIDL_BatchNormLayer |486 |488 | 104| 105| 3| 3| 146|TIDL_EltWiseLayer |455 |489 | 103| 106| 3| 3| 147|TIDL_BatchNormLayer |489 |494 | 106| 107| 3| 2| 148|TIDL_BatchNormLayer |494 |496 | 107| 108| 2| 3| 149|TIDL_EltWiseLayer |455 |497 | 103| 109| 3| 3| 150|TIDL_DataLayer |795 |795 | 119| 0| 6| 0| 151|TIDL_DataConvertLayer |795 |795 | 83| 119| 3| 6| 152|TIDL_DataConvertLayer |473 |473_10 | 86| 165| 3| 3| 153|TIDL_TransposeLayer |473_10 |474_11 | 165| 166| 3| 3| 154|TIDL_DataConvertLayer |474_11 |474 | 166| 87| 3| 3| 155|TIDL_ReshapeLayer |474 |485 | 87| 88| 3| 3| 156|TIDL_ConvolutionLayer |485 |511 | 88| 89| 3| 3| 157|TIDL_ConvolutionLayer |485 |604 | 88| 92| 3| 3| 158|TIDL_DataConvertLayer |511 |511_12 | 89| 167| 3| 3| 159|TIDL_DataConvertLayer |604 |604_14 | 92| 169| 3| 3| 160|TIDL_DataConvertLayer |511_12 |511_12_20_26 | 167| 181| 3| 3| 161|TIDL_DataConvertLayer |604_14 |604_14_21_27 | 169| 182| 3| 3| 162|TIDL_ReshapeLayer |511_12_20_26 |511_12_20 | 181| 175| 3| 3| 163|TIDL_ReshapeLayer |604_14_21_27 |604_14_21 | 182| 176| 3| 3| 164|TIDL_ReshapeLayer |511_12_20 |512_13 | 175| 168| 3| 3| 165|TIDL_ReshapeLayer |604_14_21 |605_15 | 176| 170| 3| 3| 166|TIDL_DataConvertLayer |512_13 |512 | 168| 90| 3| 3| 167|TIDL_DataConvertLayer |605_15 |605 | 170| 93| 3| 3| 168|TIDL_ReshapeLayer |512 |514 | 90| 91| 3| 3| 169|TIDL_ReshapeLayer |605 |607 | 93| 94| 3| 3| 170|TIDL_DataLayer |607 |607 | 117| 0| 6| 0| 171|TIDL_DataLayer |514 |514 | 118| 0| 6| 0| 172|TIDL_DataConvertLayer |607 |607 | 94| 117| 3| 6| 173|TIDL_DataConvertLayer |514 |514 | 91| 118| 3| 6| 174|TIDL_DataConvertLayer |497 |497_netFormatB | 109| 216| 3| 3| 175|TIDL_ReshapeLayer |497_netFormatB |500_netFormatA | 216| 215| 3| 3| 176|TIDL_DataConvertLayer |500_netFormatA |500 | 215| 110| 3| 3| 177|TIDL_TopKLayer |500 |501 | 110| 111| 3| 3| 178|TIDL_ReshapeLayer |502 |seeds | 112| 113| 3| 3| 179|TIDL_ReshapeLayer |seeds |507 | 113| 114| 3| 3| 180|TIDL_DataLayer |seeds |seeds | 115| 0| 8| 0| 181|TIDL_DataLayer |507 |507 | 116| 0| 8| 0| 182|TIDL_DataConvertLayer |seeds |seeds | 113| 115| 3| 8| 183|TIDL_DataConvertLayer |507 |507 | 114| 116| 3| 8| debug_tidl_optimizeNet8: final ops list:- printing Current net 0|TIDL_DataLayer | |image | 0| 0| 0| 6| 1|TIDL_ConstDataLayer | |303_145 | 0| 1| 0| 3| 2|TIDL_ConstDataLayer | |303_146 | 0| 2| 0| 3| 3|TIDL_ConstDataLayer | |442_147 | 0| 3| 0| 3| 4|TIDL_ConstDataLayer | |445_148 | 0| 4| 0| 3| 5|TIDL_ConstDataLayer | |447_149 | 0| 5| 0| 3| 6|TIDL_ConstDataLayer | |449_150 | 0| 6| 0| 3| 7|TIDL_ConstDataLayer | |447_151 | 0| 7| 0| 3| 8|TIDL_ConstDataLayer | |449_152 | 0| 8| 0| 3| 9|TIDL_DataConvertLayer |image |image_netFormat | 0| 9| 6| 3| 10|TIDL_ConvolutionLayer |image_netFormat |227 | 9| 10| 3| 2| 11|TIDL_PoolingLayer |227 |228 | 10| 11| 2| 2| 12|TIDL_ConvolutionLayer |228 |231 | 11| 12| 2| 2| 13|TIDL_ConvolutionLayer |231 |723 | 12| 13| 2| 3| 14|TIDL_EltWiseLayer |723 |235 | 13| 14| 3| 2| 15|TIDL_ConvolutionLayer |235 |238 | 14| 15| 2| 2| 16|TIDL_ConvolutionLayer |238 |729 | 15| 16| 2| 3| 17|TIDL_EltWiseLayer |729 |242 | 16| 17| 3| 2| 18|TIDL_ConvolutionLayer |242 |738 | 17| 18| 2| 3| 19|TIDL_ConvolutionLayer |242 |245 | 17| 19| 2| 2| 20|TIDL_ConvolutionLayer |245 |735 | 19| 20| 2| 3| 21|TIDL_EltWiseLayer |735 |251 | 20| 21| 3| 2| 22|TIDL_ConvolutionLayer |251 |254 | 21| 22| 2| 2| 23|TIDL_ConvolutionLayer |254 |744 | 22| 23| 2| 3| 24|TIDL_EltWiseLayer |744 |258 | 23| 24| 3| 2| 25|TIDL_ConvolutionLayer |258 |405 | 24| 25| 2| 3| 26|TIDL_ConvolutionLayer |258 |753 | 24| 26| 2| 3| 27|TIDL_ConvolutionLayer |258 |261 | 24| 27| 2| 2| 28|TIDL_ConvolutionLayer |261 |750 | 27| 28| 2| 3| 29|TIDL_EltWiseLayer |750 |267 | 28| 29| 3| 2| 30|TIDL_ConvolutionLayer |267 |270 | 29| 30| 2| 2| 31|TIDL_ConvolutionLayer |270 |759 | 30| 31| 2| 3| 32|TIDL_EltWiseLayer |759 |274 | 31| 32| 3| 2| 33|TIDL_ConvolutionLayer |274 |406 | 32| 33| 2| 3| 34|TIDL_ConvolutionLayer |274 |768 | 32| 34| 2| 3| 35|TIDL_ConvolutionLayer |274 |277 | 32| 35| 2| 2| 36|TIDL_ConvolutionLayer |277 |765 | 35| 36| 2| 3| 37|TIDL_EltWiseLayer |765 |283 | 36| 37| 3| 2| 38|TIDL_ConvolutionLayer |283 |286 | 37| 38| 2| 2| 39|TIDL_ConvolutionLayer |286 |774 | 38| 39| 2| 3| 40|TIDL_EltWiseLayer |774 |290 | 39| 40| 3| 2| 41|TIDL_ConvolutionLayer |290 |293 | 40| 41| 2| 2| 42|TIDL_EltWiseLayer |293 |304 | 41| 42| 2| 3| 43|TIDL_ConvolutionLayer |304 |327 | 42| 43| 3| 3| 44|TIDL_ConvolutionLayer |304 |314 | 42| 44| 3| 3| 45|TIDL_ConvolutionLayer |304 |305 | 42| 45| 3| 3| 46|TIDL_DataConvertLayer |327 |327_netFormatB | 43| 46| 3| 3| 47|TIDL_DataConvertLayer |314 |314_netFormatB | 44| 47| 3| 3| 48|TIDL_DataConvertLayer |305 |305_netFormatB | 45| 48| 3| 3| 49|TIDL_ReshapeLayer |327_netFormatB |334_netFormatA | 46| 49| 3| 3| 50|TIDL_ReshapeLayer |314_netFormatB |321_netFormatA | 47| 50| 3| 3| 51|TIDL_ReshapeLayer |305_netFormatB |312_netFormatA | 48| 51| 3| 3| 52|TIDL_DataConvertLayer |334_netFormatA |334 | 49| 52| 3| 3| 53|TIDL_DataConvertLayer |321_netFormatA |321 | 50| 53| 3| 3| 54|TIDL_DataConvertLayer |312_netFormatA |312 | 51| 54| 3| 3| 55|TIDL_DataConvertLayer |312 |312_2 | 54| 55| 3| 3| 56|TIDL_DataConvertLayer |312_2 |312_2_netFormatB | 55| 56| 3| 3| 57|TIDL_ReshapeLayer |312_2_netFormatB |312_2_22_netFormatA | 56| 57| 3| 3| 58|TIDL_DataConvertLayer |312_2_22_netFormatA |312_2_22 | 57| 58| 3| 3| 59|TIDL_DataConvertLayer |312_2_22 |312_2_16 | 58| 59| 3| 3| 60|TIDL_DataConvertLayer |312_2_16 |312_2_16_netFormatB | 59| 60| 3| 3| 61|TIDL_ReshapeLayer |312_2_16_netFormatB |313_3_netFormatA | 60| 61| 3| 3| 62|TIDL_DataConvertLayer |313_3_netFormatA |313_3 | 61| 62| 3| 3| 63|TIDL_DataConvertLayer |313_3 |313 | 62| 63| 3| 3| 64|TIDL_InnerProductLayer |313 |323 | 63| 64| 3| 3| 65|TIDL_DataConvertLayer |323 |323_4 | 64| 65| 3| 3| 66|TIDL_DataConvertLayer |323_4 |323_4_netFormatB | 65| 66| 3| 3| 67|TIDL_ReshapeLayer |323_4_netFormatB |323_4_23_netFormatA | 66| 67| 3| 3| 68|TIDL_DataConvertLayer |323_4_23_netFormatA |323_4_23 | 67| 68| 3| 3| 69|TIDL_DataConvertLayer |323_4_23 |323_4_17 | 68| 69| 3| 3| 70|TIDL_DataConvertLayer |323_4_17 |323_4_17_netFormatB | 69| 70| 3| 3| 71|TIDL_ReshapeLayer |323_4_17_netFormatB |323_0_5_netFormatA | 70| 71| 3| 3| 72|TIDL_DataConvertLayer |323_0_5_netFormatA |323_0_5 | 71| 72| 3| 3| 73|TIDL_DataConvertLayer |323_0_5 |323_0 | 72| 73| 3| 3| 74|TIDL_SoftMaxLayer |323_0 |324 | 73| 74| 3| 2| 75|TIDL_InnerProductLayer |334 |335 | 52| 75| 3| 3| 76|TIDL_DataConvertLayer |335 |335_netFormatB | 75| 76| 3| 3| 77|TIDL_ReshapeLayer |335_netFormatB |342_netFormatA | 76| 77| 3| 3| 78|TIDL_DataConvertLayer |342_netFormatA |342 | 77| 78| 3| 3| 79|TIDL_BatchNormLayer |342 |343 | 78| 79| 3| 3| 80|TIDL_EltWiseLayer |343 |344 | 79| 80| 3| 3| 81|TIDL_ConvolutionLayer |344 |347 | 80| 81| 3| 2| 82|TIDL_ConvolutionLayer |347 |350 | 81| 82| 2| 2| 83|TIDL_EltWiseLayer |350 |361 | 82| 83| 2| 3| 84|TIDL_ConvolutionLayer |361 |384 | 83| 84| 3| 3| 85|TIDL_ConvolutionLayer |361 |371 | 83| 85| 3| 3| 86|TIDL_ConvolutionLayer |361 |362 | 83| 86| 3| 3| 87|TIDL_DataConvertLayer |384 |384_netFormatB | 84| 87| 3| 3| 88|TIDL_DataConvertLayer |371 |371_netFormatB | 85| 88| 3| 3| 89|TIDL_DataConvertLayer |362 |362_netFormatB | 86| 89| 3| 3| 90|TIDL_ReshapeLayer |384_netFormatB |391_netFormatA | 87| 90| 3| 3| 91|TIDL_ReshapeLayer |371_netFormatB |378_netFormatA | 88| 91| 3| 3| 92|TIDL_ReshapeLayer |362_netFormatB |369_netFormatA | 89| 92| 3| 3| 93|TIDL_DataConvertLayer |391_netFormatA |391 | 90| 93| 3| 3| 94|TIDL_DataConvertLayer |378_netFormatA |378 | 91| 94| 3| 3| 95|TIDL_DataConvertLayer |369_netFormatA |369 | 92| 95| 3| 3| 96|TIDL_DataConvertLayer |369 |369_6 | 95| 96| 3| 3| 97|TIDL_DataConvertLayer |369_6 |369_6_netFormatB | 96| 97| 3| 3| 98|TIDL_ReshapeLayer |369_6_netFormatB |369_6_24_netFormatA | 97| 98| 3| 3| 99|TIDL_DataConvertLayer |369_6_24_netFormatA |369_6_24 | 98| 99| 3| 3| 100|TIDL_DataConvertLayer |369_6_24 |369_6_18 | 99| 100| 3| 3| 101|TIDL_DataConvertLayer |369_6_18 |369_6_18_netFormatB | 100| 101| 3| 3| 102|TIDL_ReshapeLayer |369_6_18_netFormatB |370_7_netFormatA | 101| 102| 3| 3| 103|TIDL_DataConvertLayer |370_7_netFormatA |370_7 | 102| 103| 3| 3| 104|TIDL_DataConvertLayer |370_7 |370 | 103| 104| 3| 3| 105|TIDL_InnerProductLayer |370 |380 | 104| 105| 3| 3| 106|TIDL_DataConvertLayer |380 |380_8 | 105| 106| 3| 3| 107|TIDL_DataConvertLayer |380_8 |380_8_netFormatB | 106| 107| 3| 3| 108|TIDL_ReshapeLayer |380_8_netFormatB |380_8_25_netFormatA | 107| 108| 3| 3| 109|TIDL_DataConvertLayer |380_8_25_netFormatA |380_8_25 | 108| 109| 3| 3| 110|TIDL_DataConvertLayer |380_8_25 |380_8_19 | 109| 110| 3| 3| 111|TIDL_DataConvertLayer |380_8_19 |380_8_19_netFormatB | 110| 111| 3| 3| 112|TIDL_ReshapeLayer |380_8_19_netFormatB |380_1_9_netFormatA | 111| 112| 3| 3| 113|TIDL_DataConvertLayer |380_1_9_netFormatA |380_1_9 | 112| 113| 3| 3| 114|TIDL_DataConvertLayer |380_1_9 |380_1 | 113| 114| 3| 3| 115|TIDL_SoftMaxLayer |380_1 |381 | 114| 115| 3| 2| 116|TIDL_InnerProductLayer |391 |392 | 93| 116| 3| 3| 117|TIDL_DataConvertLayer |392 |392_netFormatB | 116| 117| 3| 3| 118|TIDL_ReshapeLayer |392_netFormatB |399_netFormatA | 117| 118| 3| 3| 119|TIDL_DataConvertLayer |399_netFormatA |399 | 118| 119| 3| 3| 120|TIDL_BatchNormLayer |399 |400 | 119| 120| 3| 3| 121|TIDL_EltWiseLayer |400 |401 | 120| 121| 3| 3| 122|TIDL_ConvolutionLayer |401 |404 | 121| 122| 3| 2| 123|TIDL_ConvolutionLayer |404 |407 | 122| 123| 2| 3| 124|TIDL_ResizeLayer |407 |411 | 123| 124| 3| 3| 125|TIDL_EltWiseLayer |406 |412 | 33| 125| 3| 3| 126|TIDL_ResizeLayer |412 |416 | 125| 126| 3| 3| 127|TIDL_EltWiseLayer |405 |417 | 25| 127| 3| 3| 128|TIDL_ConvolutionLayer |417 |418 | 127| 128| 3| 3| 129|TIDL_ConvolutionLayer |418 |458 | 128| 129| 3| 2| 130|TIDL_ConvolutionLayer |458 |461 | 129| 130| 2| 2| 131|TIDL_ConvolutionLayer |461 |795 | 130| 131| 2| 3| 132|TIDL_ConvolutionLayer |412 |419 | 125| 132| 3| 3| 133|TIDL_ConvolutionLayer |419 |427 | 132| 133| 3| 2| 134|TIDL_ConvolutionLayer |427 |473 | 133| 134| 2| 3| 135|TIDL_ConvolutionLayer |419 |424 | 132| 135| 3| 2| 136|TIDL_ConvolutionLayer |424 |425 | 135| 136| 2| 3| 137|TIDL_BatchNormLayer |425 |441 | 136| 137| 3| 2| 138|TIDL_EltWiseLayer |441 |444 | 137| 138| 2| 2| 139|TIDL_EltWiseLayer |444 |446 | 138| 139| 2| 3| 140|TIDL_EltWiseLayer |447_149 |448 | 5| 140| 3| 3| 141|TIDL_EltWiseLayer |449_150 |451 | 6| 141| 3| 2| 142|TIDL_EltWiseLayer |447_151 |453 | 7| 142| 3| 3| 143|TIDL_EltWiseLayer |449_152 |455 | 8| 143| 3| 3| 144|TIDL_PoolingLayer |455 |486 | 143| 144| 3| 3| 145|TIDL_BatchNormLayer |486 |488 | 144| 145| 3| 3| 146|TIDL_EltWiseLayer |455 |489 | 143| 146| 3| 3| 147|TIDL_BatchNormLayer |489 |494 | 146| 147| 3| 2| 148|TIDL_BatchNormLayer |494 |496 | 147| 148| 2| 3| 149|TIDL_EltWiseLayer |455 |497 | 143| 149| 3| 3| 150|TIDL_DataLayer |795 |795 | 151| 0| 6| 0| 151|TIDL_DataConvertLayer |795 |795 | 131| 151| 3| 6| 152|TIDL_DataConvertLayer |473 |473_10 | 134| 152| 3| 3| 153|TIDL_TransposeLayer |473_10 |474_11 | 152| 153| 3| 3| 154|TIDL_DataConvertLayer |474_11 |474 | 153| 154| 3| 3| 155|TIDL_ReshapeLayer |474 |485 | 154| 155| 3| 3| 156|TIDL_ConvolutionLayer |485 |511 | 155| 156| 3| 3| 157|TIDL_ConvolutionLayer |485 |604 | 155| 157| 3| 3| 158|TIDL_DataConvertLayer |511 |511_12 | 156| 158| 3| 3| 159|TIDL_DataConvertLayer |604 |604_14 | 157| 159| 3| 3| 160|TIDL_DataConvertLayer |511_12 |511_12_20_26 | 158| 160| 3| 3| 161|TIDL_DataConvertLayer |604_14 |604_14_21_27 | 159| 161| 3| 3| 162|TIDL_ReshapeLayer |511_12_20_26 |511_12_20 | 160| 162| 3| 3| 163|TIDL_ReshapeLayer |604_14_21_27 |604_14_21 | 161| 163| 3| 3| 164|TIDL_ReshapeLayer |511_12_20 |512_13 | 162| 164| 3| 3| 165|TIDL_ReshapeLayer |604_14_21 |605_15 | 163| 165| 3| 3| 166|TIDL_DataConvertLayer |512_13 |512 | 164| 166| 3| 3| 167|TIDL_DataConvertLayer |605_15 |605 | 165| 167| 3| 3| 168|TIDL_ReshapeLayer |512 |514 | 166| 168| 3| 3| 169|TIDL_ReshapeLayer |605 |607 | 167| 169| 3| 3| 170|TIDL_DataLayer |607 |607 | 172| 0| 6| 0| 171|TIDL_DataLayer |514 |514 | 173| 0| 6| 0| 172|TIDL_DataConvertLayer |607 |607 | 169| 172| 3| 6| 173|TIDL_DataConvertLayer |514 |514 | 168| 173| 3| 6| 174|TIDL_DataConvertLayer |497 |497_netFormatB | 149| 174| 3| 3| 175|TIDL_ReshapeLayer |497_netFormatB |500_netFormatA | 174| 175| 3| 3| 176|TIDL_DataConvertLayer |500_netFormatA |500 | 175| 176| 3| 3| 177|TIDL_TopKLayer |500 |501 | 176| 177| 3| 3| 178|TIDL_ReshapeLayer |502 |seeds | 177| 178| 3| 3| 179|TIDL_ReshapeLayer |seeds |507 | 178| 179| 3| 3| 180|TIDL_DataLayer |seeds |seeds | 182| 0| 8| 0| 181|TIDL_DataLayer |507 |507 | 183| 0| 8| 0| 182|TIDL_DataConvertLayer |seeds |seeds | 178| 182| 3| 8| 183|TIDL_DataConvertLayer |507 |507 | 179| 183| 3| 8| debug_tidl_optimizeNetLast: numLayers-184 ************** Frame index 1 : Running float import ************* In TIDL_runtimesPostProcessNet In TIDL_runtimesPostProcessNet 1 In TIDL_runtimesPostProcessNet 2 In TIDL_runtimesPostProcessNet 3 0 image : 1x3x320x800 1 : 1x64x10x25 2 : 1x64x10x25 3 : 1x1x20x50 4 : 1x1x20x50 5 : 1x1x20x50 6 : 1x1x20x50 7 : 1x1x20x50 8 : 1x1x20x50 9 : 1x3x320x800 10 Conv_0 : 1x64x160x400 11 MaxPool_2 : 1x64x80x200 12 Conv_3 : 1x64x80x200 13 Conv_5 : 1x64x80x200 14 Add_6 : 1x64x80x200 15 Conv_8 : 1x64x80x200 16 Conv_10 : 1x64x80x200 17 Add_11 : 1x64x80x200 18 Conv_16 : 1x128x40x100 19 Conv_13 : 1x128x40x100 20 Conv_15 : 1x128x40x100 21 Add_17 : 1x128x40x100 22 Conv_19 : 1x128x40x100 23 Conv_21 : 1x128x40x100 24 Add_22 : 1x128x40x100 25 Conv_140 : 1x64x40x100 26 Conv_27 : 1x256x20x50 27 Conv_24 : 1x256x20x50 28 Conv_26 : 1x256x20x50 29 Add_28 : 1x256x20x50 30 Conv_30 : 1x256x20x50 31 Conv_32 : 1x256x20x50 32 Add_33 : 1x256x20x50 33 Conv_141 : 1x64x20x50 34 Conv_38 : 1x512x10x25 35 Conv_35 : 1x512x10x25 36 Conv_37 : 1x512x10x25 37 Add_39 : 1x512x10x25 38 Conv_41 : 1x512x10x25 39 Conv_43 : 1x512x10x25 40 Add_44 : 1x512x10x25 41 Conv_46 : 1x64x10x25 42 Add_58 : 1x64x10x25 43 Conv_77 : 1x64x10x25 44 Conv_66 : 1x16x10x25 45 Conv_59 : 1x16x10x25 46 : 1x64x10x25 47 : 1x16x10x25 48 : 1x16x10x25 49 Reshape_82 : 1x1x64x250 50 Reshape_71 : 1x1x16x250 51 Reshape_64 : 1x1x16x250 52 : 1x1x64x250 53 : 1x1x16x250 54 : 1x1x16x250 55 : 1x1x16x250 56 : 1x1x16x250 57 : 1x250x1x16 58 : 1x250x1x16 59 : 1x250x1x16 60 : 1x250x1x16 61 Transpose_65 : 1x1x250x16 62 : 1x1x250x16 63 : 1x1x250x16 64 MatMul_72 : 1x1x250x250 65 : 1x1x250x250 66 : 1x1x250x250 67 : 1x250x1x250 68 : 1x250x1x250 69 : 1x250x1x250 70 : 1x250x1x250 71 : 1x1x250x250 72 : 1x1x250x250 73 : 1x1x250x250 74 Softmax_74 : 1x1x250x250 75 MatMul_83 : 1x1x64x250 76 : 1x1x64x250 77 Reshape_88 : 1x64x10x25 78 : 1x64x10x25 79 Mul_89 : 1x64x10x25 80 Add_90 : 1x64x10x25 81 Conv_91 : 1x64x10x25 82 Conv_93 : 1x64x10x25 83 Add_105 : 1x64x10x25 84 Conv_124 : 1x64x10x25 85 Conv_113 : 1x16x10x25 86 Conv_106 : 1x16x10x25 87 : 1x64x10x25 88 : 1x16x10x25 89 : 1x16x10x25 90 Reshape_129 : 1x1x64x250 91 Reshape_118 : 1x1x16x250 92 Reshape_111 : 1x1x16x250 93 : 1x1x64x250 94 : 1x1x16x250 95 : 1x1x16x250 96 : 1x1x16x250 97 : 1x1x16x250 98 : 1x250x1x16 99 : 1x250x1x16 100 : 1x250x1x16 101 : 1x250x1x16 102 Transpose_112 : 1x1x250x16 103 : 1x1x250x16 104 : 1x1x250x16 105 MatMul_119 : 1x1x250x250 106 : 1x1x250x250 107 : 1x1x250x250 108 : 1x250x1x250 109 : 1x250x1x250 110 : 1x250x1x250 111 : 1x250x1x250 112 : 1x1x250x250 113 : 1x1x250x250 114 : 1x1x250x250 115 Softmax_121 : 1x1x250x250 116 MatMul_130 : 1x1x64x250 117 : 1x1x64x250 118 Reshape_135 : 1x64x10x25 119 : 1x64x10x25 120 Mul_136 : 1x64x10x25 121 Add_137 : 1x64x10x25 122 Conv_138 : 1x64x10x25 123 Conv_142 : 1x64x10x25 124 Upsample_143 : 1x64x20x50 125 Add_144 : 1x64x20x50 126 Upsample_145 : 1x64x40x100 127 Add_146 : 1x64x40x100 128 Conv_147 : 1x64x40x100 129 Conv_185 : 1x64x40x100 130 Conv_187 : 1x64x40x100 131 Conv_189 : 1x64x40x100 132 Conv_148 : 1x64x20x50 133 Conv_155 : 1x64x20x50 134 Conv_157 : 1x134x20x50 135 Conv_152 : 1x64x20x50 136 Conv_154 : 1x1x20x50 137 Sigmoid_170 : 1x1x20x50 138 Add_172 : 1x1x20x50 139 Add_175 : 1x1x20x50 140 Mul_177 : 1x1x20x50 141 Add_179 : 1x1x20x50 142 Mul_182 : 1x1x20x50 143 Add_184 : 1x1x20x50 144 MaxPool_204 : 1x1x20x50 145 Mul_206 : 1x1x20x50 146 Add_207 : 1x1x20x50 147 Add_211 : 1x1x20x50 148 Mul_214 : 1x1x20x50 149 Mul_215 : 1x1x20x50 151 : 1x64x40x100 152 : 1x134x20x50 153 Transpose_196 : 1x1x20x50 154 : 1x1x20x50 155 Reshape_203 : 1x134x1x1000 156 Conv_228 : 1x67x1x1000 157 Conv_289 : 1x67x1x1000 158 : 1x67x1x1000 159 : 1x67x1x1000 160 : 1x67x1x1000 161 : 1x67x1x1000 162 : 1x1x1000x67 163 : 1x1x1000x67 164 Transpose_229 : 1x1000x1x67 165 Transpose_290 : 1x1000x1x67 166 : 1x1000x1x67 167 : 1x1000x1x67 168 Reshape_231 : 1x1x1000x67 169 Reshape_292 : 1x1x1000x67 172 : 1x1x1000x67 173 : 1x1x1000x67 174 : 1x1x20x50 175 Reshape_218 : 1x1x1x1000 176 : 1x1x1x1000 177 TopK_219 : 1x1x1x6 177 TopK_219 : 1x1x1x6 178 Reshape_221 : 1x1x6x1 179 Squeeze_224 : 1x1x1x6 182 : 1x1x6x1 183 : 1x1x1x6 INFORMATION: [TIDL_ResizeLayer] Upsample_143 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. INFORMATION: [TIDL_ResizeLayer] Upsample_145 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. **************************************************** ** 2 WARNINGS 0 ERRORS ** **************************************************** In TIDL_runtimesPostProcessNet 4 ************ in TIDL_subgraphRtCreate ************ The soft limit is 2048 The hard limit is 2048 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INIT:Enabled 0.7s: VX_ZONE_ERROR:Enabled 0.8s: VX_ZONE_WARNING:Enabled 0.1622s: VX_ZONE_INIT:[tivxInit:190] Initialization Done !!! debug_TIDL_alloc: inside TIDL_alloc debug_TIDL_alloc0: status-0, ok-0 fail--1 debug_TIDL_alloc0: lIdx-1 mem-0 64128 0 lT-39 debug_TIDL_alloc0: lIdx-2 mem-0 64128 0 lT-39 debug_TIDL_alloc0: lIdx-3 mem-0 4128 0 lT-39 debug_TIDL_alloc0: lIdx-4 mem-0 4128 0 lT-39 debug_TIDL_alloc0: lIdx-5 mem-0 4128 0 lT-39 debug_TIDL_alloc0: lIdx-6 mem-0 4128 0 lT-39 debug_TIDL_alloc0: lIdx-7 mem-0 4128 0 lT-39 debug_TIDL_alloc0: lIdx-8 mem-0 4128 0 lT-39 debug_TIDL_alloc0: lIdx-9 mem-128 128 3151100 lT-29 debug_TIDL_alloc0: lIdx-10 mem-25099520 768 16733056 lT-1 debug_TIDL_alloc0: lIdx-11 mem-6406400 128 4270976 lT-2 debug_TIDL_alloc0: lIdx-12 mem-6406400 768 4270976 lT-1 debug_TIDL_alloc0: lIdx-13 mem-6144128 768 4096128 lT-1 debug_TIDL_alloc0: lIdx-14 mem-6406400 128 128 lT-5 debug_TIDL_alloc0: lIdx-15 mem-6406400 768 128 lT-1 debug_TIDL_alloc0: lIdx-16 mem-6144128 768 128 lT-1 debug_TIDL_alloc0: lIdx-17 mem-6406400 128 128 lT-5 debug_TIDL_alloc0: lIdx-18 mem-3072128 1280 2048128 lT-1 debug_TIDL_alloc0: lIdx-19 mem-3335552 1280 2223744 lT-1 debug_TIDL_alloc0: lIdx-20 mem-3072128 1280 2048128 lT-1 debug_TIDL_alloc0: lIdx-21 mem-3335552 128 128 lT-5 debug_TIDL_alloc0: lIdx-22 mem-3335552 1280 2223744 lT-1 debug_TIDL_alloc0: lIdx-23 mem-3072128 1280 128 lT-1 debug_TIDL_alloc0: lIdx-24 mem-3335552 128 128 lT-5 debug_TIDL_alloc0: lIdx-25 mem-1536128 768 128 lT-1 debug_TIDL_alloc0: lIdx-26 mem-1536128 2304 1024128 lT-1 debug_TIDL_alloc0: lIdx-27 mem-1801856 2304 1201280 lT-1 debug_TIDL_alloc0: lIdx-28 mem-1536128 2304 1024128 lT-1 debug_TIDL_alloc0: lIdx-29 mem-1801856 128 128 lT-5 debug_TIDL_alloc0: lIdx-30 mem-1801856 2304 1201280 lT-1 debug_TIDL_alloc0: lIdx-31 mem-1536128 2304 128 lT-1 debug_TIDL_alloc0: lIdx-32 mem-1801856 128 128 lT-5 debug_TIDL_alloc0: lIdx-33 mem-384128 768 128 lT-1 debug_TIDL_alloc0: lIdx-34 mem-768128 4352 512128 lT-1 debug_TIDL_alloc0: lIdx-35 mem-1038464 4352 692352 lT-1 debug_TIDL_alloc0: lIdx-36 mem-768128 4352 512128 lT-1 debug_TIDL_alloc0: lIdx-37 mem-1038464 128 128 lT-5 debug_TIDL_alloc0: lIdx-38 mem-1038464 4352 692352 lT-1 debug_TIDL_alloc0: lIdx-39 mem-768128 4352 128 lT-1 debug_TIDL_alloc0: lIdx-40 mem-1038464 128 128 lT-5 debug_TIDL_alloc0: lIdx-41 mem-96128 768 128 lT-1 debug_TIDL_alloc0: lIdx-42 mem-96128 128 128 lT-5 debug_TIDL_alloc0: lIdx-43 mem-96128 768 128 lT-1 debug_TIDL_alloc0: lIdx-44 mem-24128 384 16128 lT-1 debug_TIDL_alloc0: lIdx-45 mem-24128 384 16128 lT-1 debug_TIDL_alloc0: lIdx-46 mem-128 128 64128 lT-29 debug_TIDL_alloc0: lIdx-47 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-48 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-49 mem-128 128 64128 lT-38 debug_TIDL_alloc0: lIdx-50 mem-128 128 16128 lT-38 debug_TIDL_alloc0: lIdx-51 mem-128 128 16128 lT-38 debug_TIDL_alloc0: lIdx-52 mem-128 128 64128 lT-29 debug_TIDL_alloc0: lIdx-53 mem-128 128 16128 lT-29 debug_TIDL_alloc0: lIdx-54 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-55 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-56 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-57 mem-128 128 16128 lT-38 debug_TIDL_alloc0: lIdx-58 mem-128 128 16128 lT-29 debug_TIDL_alloc0: lIdx-59 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-60 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-61 mem-128 128 16128 lT-38 debug_TIDL_alloc0: lIdx-62 mem-128 128 16128 lT-29 debug_TIDL_alloc0: lIdx-63 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-64 mem-375128 256 250128 lT-6 debug_TIDL_alloc0: lIdx-65 mem-128 128 250128 lT-29 debug_TIDL_alloc0: lIdx-66 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-67 mem-128 128 250128 lT-38 debug_TIDL_alloc0: lIdx-68 mem-128 128 250128 lT-29 debug_TIDL_alloc0: lIdx-69 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-70 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-71 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-72 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-73 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-74 mem-128 128 128 lT-7 debug_TIDL_alloc0: lIdx-75 mem-96128 256 128 lT-6 debug_TIDL_alloc0: lIdx-76 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-77 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-78 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-79 mem-96128 1280 128 lT-8 debug_TIDL_alloc0: lIdx-80 mem-129920 128 128 lT-5 debug_TIDL_alloc0: lIdx-81 mem-129920 768 128 lT-1 debug_TIDL_alloc0: lIdx-82 mem-96128 768 128 lT-1 debug_TIDL_alloc0: lIdx-83 mem-96128 128 128 lT-5 debug_TIDL_alloc0: lIdx-84 mem-96128 768 128 lT-1 debug_TIDL_alloc0: lIdx-85 mem-24128 384 128 lT-1 debug_TIDL_alloc0: lIdx-86 mem-24128 384 128 lT-1 debug_TIDL_alloc0: lIdx-87 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-88 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-89 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-90 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-91 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-92 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-93 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-94 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-95 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-96 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-97 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-98 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-99 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-100 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-101 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-102 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-103 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-104 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-105 mem-375128 256 128 lT-6 debug_TIDL_alloc0: lIdx-106 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-107 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-108 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-109 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-110 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-111 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-112 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-113 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-114 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-115 mem-128 128 128 lT-7 debug_TIDL_alloc0: lIdx-116 mem-96128 256 128 lT-6 debug_TIDL_alloc0: lIdx-117 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-118 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-119 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-120 mem-96128 1280 128 lT-8 debug_TIDL_alloc0: lIdx-121 mem-129920 128 128 lT-5 debug_TIDL_alloc0: lIdx-122 mem-96128 768 128 lT-1 debug_TIDL_alloc0: lIdx-123 mem-129920 768 128 lT-1 debug_TIDL_alloc0: lIdx-124 mem-128 128 128 lT-21 debug_TIDL_alloc0: lIdx-125 mem-450560 128 128 lT-5 debug_TIDL_alloc0: lIdx-126 mem-128 128 128 lT-21 debug_TIDL_alloc0: lIdx-127 mem-1667840 128 128 lT-5 debug_TIDL_alloc0: lIdx-128 mem-1667840 768 128 lT-1 debug_TIDL_alloc0: lIdx-129 mem-1667840 768 128 lT-1 debug_TIDL_alloc0: lIdx-130 mem-1667840 768 128 lT-1 debug_TIDL_alloc0: lIdx-131 mem-1536128 768 128 lT-1 debug_TIDL_alloc0: lIdx-132 mem-450560 768 128 lT-1 debug_TIDL_alloc0: lIdx-133 mem-384128 768 128 lT-1 debug_TIDL_alloc0: lIdx-134 mem-804128 1328 128 lT-1 debug_TIDL_alloc0: lIdx-135 mem-384128 768 128 lT-1 debug_TIDL_alloc0: lIdx-136 mem-6128 264 4128 lT-1 debug_TIDL_alloc0: lIdx-137 mem-6128 524 128 lT-8 debug_TIDL_alloc0: lIdx-138 mem-6128 128 128 lT-5 debug_TIDL_alloc0: lIdx-139 mem-6128 128 128 lT-5 debug_TIDL_alloc0: lIdx-140 mem-6128 128 128 lT-5 debug_TIDL_alloc0: lIdx-141 mem-6128 128 128 lT-5 debug_TIDL_alloc0: lIdx-142 mem-6128 128 128 lT-5 debug_TIDL_alloc0: lIdx-143 mem-7166 128 128 lT-5 debug_TIDL_alloc0: lIdx-144 mem-6128 128 128 lT-2 debug_TIDL_alloc0: lIdx-145 mem-6128 524 128 lT-8 debug_TIDL_alloc0: lIdx-146 mem-6128 128 128 lT-5 debug_TIDL_alloc0: lIdx-147 mem-6128 524 128 lT-8 debug_TIDL_alloc0: lIdx-148 mem-6128 524 128 lT-8 debug_TIDL_alloc0: lIdx-149 mem-6128 128 128 lT-5 debug_TIDL_alloc0: lIdx-151 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-152 mem-128 128 536128 lT-29 debug_TIDL_alloc0: lIdx-153 mem-128 128 128 lT-41 debug_TIDL_alloc0: lIdx-154 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-155 mem-128 128 536128 lT-38 debug_TIDL_alloc0: lIdx-156 mem-402128 792 268128 lT-1 debug_TIDL_alloc0: lIdx-157 mem-402128 792 268128 lT-1 debug_TIDL_alloc0: lIdx-158 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-159 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-160 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-161 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-162 mem-128 128 268128 lT-38 debug_TIDL_alloc0: lIdx-163 mem-128 128 268128 lT-38 debug_TIDL_alloc0: lIdx-164 mem-128 128 268128 lT-38 debug_TIDL_alloc0: lIdx-165 mem-128 128 268128 lT-38 debug_TIDL_alloc0: lIdx-166 mem-128 128 268128 lT-29 debug_TIDL_alloc0: lIdx-167 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-168 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-169 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-172 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-173 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-174 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-175 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-176 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-177 mem-128 65920 152 lT-43 debug_TIDL_alloc0: lIdx-178 mem-128 128 152 lT-38 debug_TIDL_alloc0: lIdx-179 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-182 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-183 mem-128 128 128 lT-29 debug_TIDL_init0: lIdx-1 0 64128 0 debug_TIDL_init0: lIdx-2 0 64128 0 debug_TIDL_init0: lIdx-3 0 4128 0 debug_TIDL_init0: lIdx-4 0 4128 0 debug_TIDL_init0: lIdx-5 0 4128 0 debug_TIDL_init0: lIdx-6 0 4128 0 debug_TIDL_init0: lIdx-7 0 4128 0 debug_TIDL_init0: lIdx-8 0 4128 0 debug_TIDL_init0: lIdx-9 128 128 3151100 debug_TIDL_init0: lIdx-10 25099520 768 16733056 debug_TIDL_init0: lIdx-11 6406400 128 4270976 debug_TIDL_init0: lIdx-12 6406400 768 4270976 debug_TIDL_init0: lIdx-13 6144128 768 4096128 debug_TIDL_init0: lIdx-14 6406400 128 128 debug_TIDL_init0: lIdx-15 6406400 768 128 debug_TIDL_init0: lIdx-16 6144128 768 128 debug_TIDL_init0: lIdx-17 6406400 128 128 debug_TIDL_init0: lIdx-18 3072128 1280 2048128 debug_TIDL_init0: lIdx-19 3335552 1280 2223744 debug_TIDL_init0: lIdx-20 3072128 1280 2048128 debug_TIDL_init0: lIdx-21 3335552 128 128 debug_TIDL_init0: lIdx-22 3335552 1280 2223744 debug_TIDL_init0: lIdx-23 3072128 1280 128 debug_TIDL_init0: lIdx-24 3335552 128 128 debug_TIDL_init0: lIdx-25 1536128 768 128 debug_TIDL_init0: lIdx-26 1536128 2304 1024128 debug_TIDL_init0: lIdx-27 1801856 2304 1201280 debug_TIDL_init0: lIdx-28 1536128 2304 1024128 debug_TIDL_init0: lIdx-29 1801856 128 128 debug_TIDL_init0: lIdx-30 1801856 2304 1201280 debug_TIDL_init0: lIdx-31 1536128 2304 128 debug_TIDL_init0: lIdx-32 1801856 128 128 debug_TIDL_init0: lIdx-33 384128 768 128 debug_TIDL_init0: lIdx-34 768128 4352 512128 debug_TIDL_init0: lIdx-35 1038464 4352 692352 debug_TIDL_init0: lIdx-36 768128 4352 512128 debug_TIDL_init0: lIdx-37 1038464 128 128 debug_TIDL_init0: lIdx-38 1038464 4352 692352 debug_TIDL_init0: lIdx-39 768128 4352 128 debug_TIDL_init0: lIdx-40 1038464 128 128 debug_TIDL_init0: lIdx-41 96128 768 128 debug_TIDL_init0: lIdx-42 96128 128 128 debug_TIDL_init0: lIdx-43 96128 768 128 debug_TIDL_init0: lIdx-44 24128 384 16128 debug_TIDL_init0: lIdx-45 24128 384 16128 debug_TIDL_init0: lIdx-46 128 128 64128 debug_TIDL_init0: lIdx-47 128 128 128 debug_TIDL_init0: lIdx-48 128 128 128 debug_TIDL_init0: lIdx-49 128 128 64128 debug_TIDL_init0: lIdx-50 128 128 16128 debug_TIDL_init0: lIdx-51 128 128 16128 debug_TIDL_init0: lIdx-52 128 128 64128 debug_TIDL_init0: lIdx-53 128 128 16128 debug_TIDL_init0: lIdx-54 128 128 128 debug_TIDL_init0: lIdx-55 128 128 128 debug_TIDL_init0: lIdx-56 128 128 128 debug_TIDL_init0: lIdx-57 128 128 16128 debug_TIDL_init0: lIdx-58 128 128 16128 debug_TIDL_init0: lIdx-59 128 128 128 debug_TIDL_init0: lIdx-60 128 128 128 debug_TIDL_init0: lIdx-61 128 128 16128 debug_TIDL_init0: lIdx-62 128 128 16128 debug_TIDL_init0: lIdx-63 128 128 128 debug_TIDL_init0: lIdx-64 375128 128 250128 debug_TIDL_init0: lIdx-65 128 128 250128 debug_TIDL_init0: lIdx-66 128 128 128 debug_TIDL_init0: lIdx-67 128 128 250128 debug_TIDL_init0: lIdx-68 128 128 250128 debug_TIDL_init0: lIdx-69 128 128 128 debug_TIDL_init0: lIdx-70 128 128 128 debug_TIDL_init0: lIdx-71 128 128 128 debug_TIDL_init0: lIdx-72 128 128 128 debug_TIDL_init0: lIdx-73 128 128 128 debug_TIDL_init0: lIdx-74 128 128 128 debug_TIDL_init0: lIdx-75 96128 128 128 debug_TIDL_init0: lIdx-76 128 128 128 debug_TIDL_init0: lIdx-77 128 128 128 debug_TIDL_init0: lIdx-78 128 128 128 debug_TIDL_init0: lIdx-79 96128 896 128 debug_TIDL_init0: lIdx-80 129920 128 128 debug_TIDL_init0: lIdx-81 129920 768 128 debug_TIDL_init0: lIdx-82 96128 768 128 debug_TIDL_init0: lIdx-83 96128 128 128 debug_TIDL_init0: lIdx-84 96128 768 128 debug_TIDL_init0: lIdx-85 24128 384 128 debug_TIDL_init0: lIdx-86 24128 384 128 debug_TIDL_init0: lIdx-87 128 128 128 debug_TIDL_init0: lIdx-88 128 128 128 debug_TIDL_init0: lIdx-89 128 128 128 debug_TIDL_init0: lIdx-90 128 128 128 debug_TIDL_init0: lIdx-91 128 128 128 debug_TIDL_init0: lIdx-92 128 128 128 debug_TIDL_init0: lIdx-93 128 128 128 debug_TIDL_init0: lIdx-94 128 128 128 debug_TIDL_init0: lIdx-95 128 128 128 debug_TIDL_init0: lIdx-96 128 128 128 debug_TIDL_init0: lIdx-97 128 128 128 debug_TIDL_init0: lIdx-98 128 128 128 debug_TIDL_init0: lIdx-99 128 128 128 debug_TIDL_init0: lIdx-100 128 128 128 debug_TIDL_init0: lIdx-101 128 128 128 debug_TIDL_init0: lIdx-102 128 128 128 debug_TIDL_init0: lIdx-103 128 128 128 debug_TIDL_init0: lIdx-104 128 128 128 debug_TIDL_init0: lIdx-105 375128 128 128 debug_TIDL_init0: lIdx-106 128 128 128 debug_TIDL_init0: lIdx-107 128 128 128 debug_TIDL_init0: lIdx-108 128 128 128 debug_TIDL_init0: lIdx-109 128 128 128 debug_TIDL_init0: lIdx-110 128 128 128 debug_TIDL_init0: lIdx-111 128 128 128 debug_TIDL_init0: lIdx-112 128 128 128 debug_TIDL_init0: lIdx-113 128 128 128 debug_TIDL_init0: lIdx-114 128 128 128 debug_TIDL_init0: lIdx-115 128 128 128 debug_TIDL_init0: lIdx-116 96128 128 128 debug_TIDL_init0: lIdx-117 128 128 128 debug_TIDL_init0: lIdx-118 128 128 128 debug_TIDL_init0: lIdx-119 128 128 128 debug_TIDL_init0: lIdx-120 96128 896 128 debug_TIDL_init0: lIdx-121 129920 128 128 debug_TIDL_init0: lIdx-122 96128 768 128 debug_TIDL_init0: lIdx-123 129920 768 128 debug_TIDL_init0: lIdx-124 128 128 128 debug_TIDL_init0: lIdx-125 450560 128 128 debug_TIDL_init0: lIdx-126 128 128 128 debug_TIDL_init0: lIdx-127 1667840 128 128 debug_TIDL_init0: lIdx-128 1667840 768 128 debug_TIDL_init0: lIdx-129 1667840 768 128 debug_TIDL_init0: lIdx-130 1667840 768 128 debug_TIDL_init0: lIdx-131 1536128 768 128 debug_TIDL_init0: lIdx-132 450560 768 128 debug_TIDL_init0: lIdx-133 384128 768 128 debug_TIDL_init0: lIdx-134 804128 1328 128 debug_TIDL_init0: lIdx-135 384128 768 128 debug_TIDL_init0: lIdx-136 6128 264 4128 debug_TIDL_init0: lIdx-137 6128 512 128 debug_TIDL_init0: lIdx-138 6128 128 128 debug_TIDL_init0: lIdx-139 6128 128 128 debug_TIDL_init0: lIdx-140 6128 128 128 debug_TIDL_init0: lIdx-141 6128 128 128 debug_TIDL_init0: lIdx-142 6128 128 128 debug_TIDL_init0: lIdx-143 7166 128 128 debug_TIDL_init0: lIdx-144 6128 128 128 debug_TIDL_init0: lIdx-145 6128 512 128 debug_TIDL_init0: lIdx-146 6128 128 128 debug_TIDL_init0: lIdx-147 6128 512 128 debug_TIDL_init0: lIdx-148 6128 512 128 debug_TIDL_init0: lIdx-149 6128 128 128 debug_TIDL_init0: lIdx-151 128 128 128 debug_TIDL_init0: lIdx-152 128 128 536128 debug_TIDL_init0: lIdx-153 128 128 128 debug_TIDL_init0: lIdx-154 128 128 128 debug_TIDL_init0: lIdx-155 128 128 536128 debug_TIDL_init0: lIdx-156 402128 792 268128 debug_TIDL_init0: lIdx-157 402128 792 268128 debug_TIDL_init0: lIdx-158 128 128 128 debug_TIDL_init0: lIdx-159 128 128 128 debug_TIDL_init0: lIdx-160 128 128 128 debug_TIDL_init0: lIdx-161 128 128 128 debug_TIDL_init0: lIdx-162 128 128 268128 debug_TIDL_init0: lIdx-163 128 128 268128 debug_TIDL_init0: lIdx-164 128 128 268128 debug_TIDL_init0: lIdx-165 128 128 268128 debug_TIDL_init0: lIdx-166 128 128 268128 debug_TIDL_init0: lIdx-167 128 128 128 debug_TIDL_init0: lIdx-168 128 128 128 debug_TIDL_init0: lIdx-169 128 128 128 debug_TIDL_init0: lIdx-172 128 128 128 debug_TIDL_init0: lIdx-173 128 128 128 debug_TIDL_init0: lIdx-174 128 128 128 debug_TIDL_init0: lIdx-175 128 128 128 debug_TIDL_init0: lIdx-176 128 128 128 debug_TIDL_init0: lIdx-177 128 65792 152 debug_TIDL_init0: lIdx-178 128 128 152 debug_TIDL_init0: lIdx-179 128 128 128 debug_TIDL_init0: lIdx-182 128 128 128 debug_TIDL_init0: lIdx-183 128 128 128 ************ TIDL_subgraphRtCreate done ************ ******* In TIDL_subgraphRtInvoke ******** 0 1.00000 0.00000 1.00000 6 9 1.00000 0.00000 1.00000 6 10 1.00000 0.00000 0.93819 6 11 1.00000 0.00000 0.93819 6 12 1.00000 0.00000 0.67219 6 13 1.00000 -1.61719 1.96721 6 14 1.00000 0.00000 2.42432 6 15 1.00000 0.00000 1.22122 6 16 1.00000 -1.78311 2.00622 6 17 1.00000 0.00000 3.07801 6 18 1.00000 -1.83924 1.41457 6 19 1.00000 0.00000 1.73494 6 20 1.00000 -6.37549 3.42187 6 21 1.00000 0.00000 3.73146 6 22 1.00000 0.00000 2.54082 6 23 1.00000 -6.50051 5.31858 6 24 1.00000 0.00000 6.24390 6 25 1.00000 -3.19425 3.24052 6 26 1.00000 -2.07672 1.56626 6 27 1.00000 0.00000 3.87898 6 28 1.00000 -11.20481 5.76467 6 29 1.00000 0.00000 6.04468 6 30 1.00000 0.00000 5.43123 6 31 1.00000 -12.11593 9.83501 6 32 1.00000 0.00000 10.24289 6 33 1.00000 -2.35908 2.18817 6 34 1.00000 -9.77310 8.93708 6 35 1.00000 0.00000 7.95309 6 36 1.00000 -74.65942 31.18906 6 37 1.00000 0.00000 31.93826 6 38 1.00000 0.00000 62.41200 6 39 1.00000 -1328.83594 946.17719 6 40 1.00000 0.00000 946.17719 6 41 1.00000 0.00000 5.81276 6 1 1.00000 -0.99999 1.00000 6 42 1.00000 -0.99996 5.83927 6 43 1.00000 -3.29916 7.31220 6 44 1.00000 -4.78091 6.76474 6 45 1.00000 -4.35799 3.23186 6 46 1.00000 -3.29916 7.31220 6 47 1.00000 -4.78091 6.76474 6 48 1.00000 -4.35799 3.23186 6 49 1.00000 -3.29916 7.31220 6 50 1.00000 -4.78091 6.76474 6 51 1.00000 -4.35799 3.23186 6 52 1.00000 -3.29916 7.31220 6 53 1.00000 -4.78091 6.76474 6 54 1.00000 -4.35799 3.23186 6 55 1.00000 -4.35799 3.23186 6 56 1.00000 -4.35799 3.23186 6 57 1.00000 -4.35799 3.23186 6 58 1.00000 -4.35799 3.23186 6 59 1.00000 -4.35799 3.23186 6 60 1.00000 -4.35799 3.23186 6 61 1.00000 -4.35799 3.23186 6 62 1.00000 -4.35799 3.23186 6 63 1.00000 -4.35799 3.23186 6 64 1.00000 -38.93083 7.39591 6 65 1.00000 -38.93083 7.39591 6 66 1.00000 -38.93083 7.39591 6 67 1.00000 -38.93083 7.39591 6 68 1.00000 -38.93083 7.39591 6 69 1.00000 -38.93083 7.39591 6 70 1.00000 -38.93083 7.39591 6 71 1.00000 -38.93083 7.39591 6 72 1.00000 -38.93083 7.39591 6 73 1.00000 -38.93083 7.39591 6 74 1.00000 0.00000 0.82678 6 75 1.00000 -2.11647 4.05829 6 76 1.00000 -2.11647 4.05829 6 77 1.00000 -2.11647 4.05829 6 78 1.00000 -2.11647 4.05829 6 79 1.00000 -1.63037 0.85026 6 80 1.00000 -2.15262 5.81791 6 81 1.00000 0.00000 5.84620 6 82 1.00000 0.00000 4.47276 6 2 1.00000 -0.99999 1.00000 6 83 1.00000 -0.99999 5.34740 6 84 1.00000 -5.08273 7.34845 6 85 1.00000 -5.13670 3.50328 6 86 1.00000 -3.51702 4.58296 6 87 1.00000 -5.08273 7.34845 6 88 1.00000 -5.13670 3.50328 6 89 1.00000 -3.51702 4.58296 6 90 1.00000 -5.08273 7.34845 6 91 1.00000 -5.13670 3.50328 6 92 1.00000 -3.51702 4.58296 6 93 1.00000 -5.08273 7.34845 6 94 1.00000 -5.13670 3.50328 6 95 1.00000 -3.51702 4.58296 6 96 1.00000 -3.51702 4.58296 6 97 1.00000 -3.51702 4.58296 6 98 1.00000 -3.51702 4.58296 6 99 1.00000 -3.51702 4.58296 6 100 1.00000 -3.51702 4.58296 6 101 1.00000 -3.51702 4.58296 6 102 1.00000 -3.51702 4.58296 6 103 1.00000 -3.51702 4.58296 6 104 1.00000 -3.51702 4.58296 6 105 1.00000 -32.74919 17.62335 6 106 1.00000 -32.74919 17.62335 6 107 1.00000 -32.74919 17.62335 6 108 1.00000 -32.74919 17.62335 6 109 1.00000 -32.74919 17.62335 6 110 1.00000 -32.74919 17.62335 6 111 1.00000 -32.74919 17.62335 6 112 1.00000 -32.74919 17.62335 6 113 1.00000 -32.74919 17.62335 6 114 1.00000 -32.74919 17.62335 6 115 1.00000 0.00000 0.98720 6 116 1.00000 -3.83237 6.88803 6 117 1.00000 -3.83237 6.88803 6 118 1.00000 -3.83237 6.88803 6 119 1.00000 -3.83237 6.88803 6 120 1.00000 -1.76397 0.98144 6 121 1.00000 -2.36006 4.78521 6 122 1.00000 0.00000 4.48227 6 123 1.00000 -3.06431 2.87235 6 124 1.00000 -3.06431 2.87235 6 125 1.00000 -3.87164 3.42716 6 126 1.00000 -3.87164 3.42716 6 127 1.00000 -6.47238 4.85163 6 128 1.00000 -12.21945 11.04519 6 129 1.00000 0.00000 4.71314 6 130 1.00000 0.00000 4.42627 6 131 1.00000 -4.62150 4.53446 6 132 1.00000 -4.98266 4.85966 6 133 1.00000 0.00000 8.22535 6 134 1.00000 -4.33975 4.30877 6 135 1.00000 0.00000 17.84409 6 136 1.00000 -13.87507 4.07825 6 137 1.00000 0.00000 0.98335 6 3 1.00000 -0.00010 -0.00010 6 138 1.00000 0.00000 0.98325 6 4 1.00000 0.00010 0.00010 6 139 1.00000 0.00010 0.98335 6 5 1.00000 -1.00000 -1.00000 6 140 1.00000 -0.98335 -0.00010 6 6 1.00000 0.99990 0.99990 6 141 1.00000 0.01655 0.99980 6 7 1.00000 -1.00000 -1.00000 6 142 1.00000 -0.99980 -0.01655 6 8 1.00000 0.99990 0.99990 6 143 1.00000 0.00010 0.98335 6 144 1.00000 0.00010 0.98335 6 145 1.00000 -0.98335 -0.00010 6 146 1.00000 -0.98042 0.00000 6 147 1.00000 0.00000 0.10000 6 148 1.00000 0.00000 1.00000 6 149 1.00000 0.00000 0.98335 6 151 1.00000 -4.62150 4.53446 6 152 1.00000 -4.33975 4.30877 6 In Transpose: perm - 0 1 3 2 4 5, pp - 1 In Transpose: indata width-50 height-20 #ch-134 dim2-1 dim1-1 batch-1 In Transpose: outdata width-50 height-20 #ch-1 dim2-134 dim1-1 batch-1 153 1.00000 -4.33975 4.30877 6 154 1.00000 -4.33975 4.30877 6 155 1.00000 -4.33975 4.30877 6 156 1.00000 -4.33975 4.30877 6 157 1.00000 -3.97490 4.16372 6 158 1.00000 -4.33975 4.30877 6 159 1.00000 -3.97490 4.16372 6 160 1.00000 -4.33975 4.30877 6 161 1.00000 -3.97490 4.16372 6 162 1.00000 -4.33975 4.30877 6 163 1.00000 -3.97490 4.16372 6 164 1.00000 -4.33975 4.30877 6 165 1.00000 -3.97490 4.16372 6 166 1.00000 -4.33975 4.30877 6 167 1.00000 -3.97490 4.16372 6 168 1.00000 -4.33975 4.30877 6 169 1.00000 -3.97490 4.16372 6 172 1.00000 -3.97490 4.16372 6 173 1.00000 -4.33975 4.30877 6 174 1.00000 0.00000 0.98335 6 175 1.00000 0.00000 0.98335 6 176 1.00000 0.00000 0.98335 6 ****** in TOPK *********** Inside TopK: index-0, value-0.000780582 Inside TopK: index-1, value-0 Inside TopK: index-2, value-0.000100017 Inside TopK: index-3, value-0.000100017 Inside TopK: index-4, value-0.000100017 Inside TopK: index-5, value-0.000100017 Inside TopK: index-12, value-0.000537395 Inside TopK: index-20, value-0.00699091 Inside TopK: index-49, value-0.00222981 Inside TopK: index-149, value-0.0103909 Inside TopK: index-162, value-0.00292653 Inside TopK: index-225, value-0.00093168 Inside TopK: index-249, value-0.0143731 Inside TopK: index-250, value-0.00128621 Inside TopK: index-259, value-0.00204778 Inside TopK: index-500, value-0.983345 Inside TopK: index-659, value-0.00717902 Inside TopK: index-749, value-0.00603288 Inside TopK: index-953, value-0.981534 Inside TopK: index-984, value-0.925356 debug_TopK_output: k-6, eltType-6 indexes - 500.000000 953.000000 984.000000 249.000000 149.000000 659.000000 values - 0.983345 0.981534 0.925356 0.014373 0.010391 0.007179 177 1.00000 149.00000 984.00000 6 178 1.00000 149.00000 984.00000 6 179 1.00000 149.00000 984.00000 6 182 1.00000 149.00000 984.00000 6 183 1.00000 149.00000 984.00000 6 Layer, Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger, paddingWait,LayerWithoutPad,LayerHandleCopy, BackupCycles, RestoreCycles,Multic7xContextCopyCycles, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 18, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 22, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 23, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 24, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 26, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 27, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 28, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 29, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 33, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 34, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 35, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 36, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 37, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 38, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 39, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 40, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 41, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 43, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 44, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 45, 0, 0, 0, 0, 0, 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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 175, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 176, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 177, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 178, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 179, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 182, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 183, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Sum of Layer Cycles 0 Sub Graph Stats 390.000000 9622176.000000 1422.000000 ******* TIDL_subgraphRtInvoke done ******** ********** Frame Index 1 : Running float inference ********** Graph Domain TO version : 9******* In TIDL_subgraphRtInvoke ******** 0 1.00000 0.00000 1.00000 6 9 1.00000 0.00000 1.00000 6 10 1.00000 0.00000 1.08594 6 11 1.00000 0.00000 1.08594 6 12 1.00000 0.00000 0.67964 6 13 1.00000 -1.70915 2.02182 6 14 1.00000 0.00000 2.47414 6 15 1.00000 0.00000 1.23282 6 16 1.00000 -1.91853 2.15057 6 17 1.00000 0.00000 3.19284 6 18 1.00000 -1.92042 1.67323 6 19 1.00000 0.00000 2.22063 6 20 1.00000 -6.91496 3.52516 6 21 1.00000 0.00000 3.99788 6 22 1.00000 0.00000 3.54521 6 23 1.00000 -6.67245 5.28764 6 24 1.00000 0.00000 5.79163 6 25 1.00000 -3.24408 3.01604 6 26 1.00000 -2.12311 1.57813 6 27 1.00000 0.00000 4.80337 6 28 1.00000 -13.99006 6.41007 6 29 1.00000 0.00000 6.78098 6 30 1.00000 0.00000 7.37690 6 31 1.00000 -13.86282 7.19759 6 32 1.00000 0.00000 8.60674 6 33 1.00000 -3.07554 2.95196 6 34 1.00000 -13.49907 14.83215 6 35 1.00000 0.00000 9.74216 6 36 1.00000 -88.49768 34.65625 6 37 1.00000 0.00000 35.15793 6 38 1.00000 0.00000 51.02837 6 39 1.00000 -1370.92639 800.81555 6 40 1.00000 0.00000 800.81555 6 41 1.00000 0.00000 4.44155 6 1 1.00000 -0.99999 1.00000 6 42 1.00000 -0.99999 5.11838 6 43 1.00000 -2.99190 6.04647 6 44 1.00000 -2.98903 4.52081 6 45 1.00000 -2.59054 3.06313 6 46 1.00000 -2.99190 6.04647 6 47 1.00000 -2.98903 4.52081 6 48 1.00000 -2.59054 3.06313 6 49 1.00000 -2.99190 6.04647 6 50 1.00000 -2.98903 4.52081 6 51 1.00000 -2.59054 3.06313 6 52 1.00000 -2.99190 6.04647 6 53 1.00000 -2.98903 4.52081 6 54 1.00000 -2.59054 3.06313 6 55 1.00000 -2.59054 3.06313 6 56 1.00000 -2.59054 3.06313 6 57 1.00000 -2.59054 3.06313 6 58 1.00000 -2.59054 3.06313 6 59 1.00000 -2.59054 3.06313 6 60 1.00000 -2.59054 3.06313 6 61 1.00000 -2.59054 3.06313 6 62 1.00000 -2.59054 3.06313 6 63 1.00000 -2.59054 3.06313 6 64 1.00000 -21.05310 3.76214 6 65 1.00000 -21.05310 3.76214 6 66 1.00000 -21.05310 3.76214 6 67 1.00000 -21.05310 3.76214 6 68 1.00000 -21.05310 3.76214 6 69 1.00000 -21.05310 3.76214 6 70 1.00000 -21.05310 3.76214 6 71 1.00000 -21.05310 3.76214 6 72 1.00000 -21.05310 3.76214 6 73 1.00000 -21.05310 3.76214 6 74 1.00000 0.00000 0.57111 6 75 1.00000 -1.70444 3.93050 6 76 1.00000 -1.70444 3.93050 6 77 1.00000 -1.70444 3.93050 6 78 1.00000 -1.70444 3.93050 6 79 1.00000 -1.57903 0.68474 6 80 1.00000 -1.91534 4.43610 6 81 1.00000 0.00000 4.42732 6 82 1.00000 0.00000 5.57974 6 2 1.00000 -0.99999 1.00000 6 83 1.00000 -0.99999 6.57974 6 84 1.00000 -5.09362 6.96877 6 85 1.00000 -4.76182 3.55382 6 86 1.00000 -3.42732 4.23100 6 87 1.00000 -5.09362 6.96877 6 88 1.00000 -4.76182 3.55382 6 89 1.00000 -3.42732 4.23100 6 90 1.00000 -5.09362 6.96877 6 91 1.00000 -4.76182 3.55382 6 92 1.00000 -3.42732 4.23100 6 93 1.00000 -5.09362 6.96877 6 94 1.00000 -4.76182 3.55382 6 95 1.00000 -3.42732 4.23100 6 96 1.00000 -3.42732 4.23100 6 97 1.00000 -3.42732 4.23100 6 98 1.00000 -3.42732 4.23100 6 99 1.00000 -3.42732 4.23100 6 100 1.00000 -3.42732 4.23100 6 101 1.00000 -3.42732 4.23100 6 102 1.00000 -3.42732 4.23100 6 103 1.00000 -3.42732 4.23100 6 104 1.00000 -3.42732 4.23100 6 105 1.00000 -27.50623 12.02152 6 106 1.00000 -27.50623 12.02152 6 107 1.00000 -27.50623 12.02152 6 108 1.00000 -27.50623 12.02152 6 109 1.00000 -27.50623 12.02152 6 110 1.00000 -27.50623 12.02152 6 111 1.00000 -27.50623 12.02152 6 112 1.00000 -27.50623 12.02152 6 113 1.00000 -27.50623 12.02152 6 114 1.00000 -27.50623 12.02152 6 115 1.00000 0.00000 0.77902 6 116 1.00000 -3.35688 5.67781 6 117 1.00000 -3.35688 5.67781 6 118 1.00000 -3.35688 5.67781 6 119 1.00000 -3.35688 5.67781 6 120 1.00000 -1.45405 0.85967 6 121 1.00000 -1.91086 5.75523 6 122 1.00000 0.00000 3.57153 6 123 1.00000 -2.68470 2.68152 6 124 1.00000 -2.68470 2.68152 6 125 1.00000 -4.59629 3.98501 6 126 1.00000 -4.59629 3.98501 6 127 1.00000 -6.87889 4.53765 6 128 1.00000 -12.51527 10.49797 6 129 1.00000 0.00000 4.77872 6 130 1.00000 0.00000 4.64514 6 131 1.00000 -4.14286 4.31413 6 132 1.00000 -5.35005 4.82424 6 133 1.00000 0.00000 8.24390 6 134 1.00000 -4.58772 4.65713 6 135 1.00000 0.00000 16.90320 6 136 1.00000 -12.42661 3.47063 6 137 1.00000 0.00000 0.96984 6 3 1.00000 -0.00010 -0.00010 6 138 1.00000 0.00000 0.96974 6 4 1.00000 0.00010 0.00010 6 139 1.00000 0.00010 0.96984 6 5 1.00000 -1.00000 -1.00000 6 140 1.00000 -0.96984 -0.00010 6 6 1.00000 0.99990 0.99990 6 141 1.00000 0.03006 0.99980 6 7 1.00000 -1.00000 -1.00000 6 142 1.00000 -0.99980 -0.03006 6 8 1.00000 0.99990 0.99990 6 143 1.00000 0.00010 0.96984 6 144 1.00000 0.00010 0.96984 6 145 1.00000 -0.96984 -0.00010 6 146 1.00000 -0.96631 0.00000 6 147 1.00000 0.00000 0.10000 6 148 1.00000 0.00000 1.00000 6 149 1.00000 0.00000 0.96984 6 151 1.00000 -4.14286 4.31413 6 152 1.00000 -4.58772 4.65713 6 In Transpose: perm - 0 1 3 2 4 5, pp - 1 In Transpose: indata width-50 height-20 #ch-134 dim2-1 dim1-1 batch-1 In Transpose: outdata width-50 height-20 #ch-1 dim2-134 dim1-1 batch-1 153 1.00000 -4.58772 4.65713 6 154 1.00000 -4.58772 4.65713 6 155 1.00000 -4.58772 4.65713 6 156 1.00000 -4.58772 4.65713 6 157 1.00000 -4.22531 4.19750 6 158 1.00000 -4.58772 4.65713 6 159 1.00000 -4.22531 4.19750 6 160 1.00000 -4.58772 4.65713 6 161 1.00000 -4.22531 4.19750 6 162 1.00000 -4.58772 4.65713 6 163 1.00000 -4.22531 4.19750 6 164 1.00000 -4.58772 4.65713 6 165 1.00000 -4.22531 4.19750 6 166 1.00000 -4.58772 4.65713 6 167 1.00000 -4.22531 4.19750 6 168 1.00000 -4.58772 4.65713 6 169 1.00000 -4.22531 4.19750 6 172 1.00000 -4.22531 4.19750 6 173 1.00000 -4.58772 4.65713 6 174 1.00000 0.00000 0.96984 6 175 1.00000 0.00000 0.96984 6 176 1.00000 0.00000 0.96984 6 ****** in TOPK *********** Inside TopK: index-0, value-0 Inside TopK: index-1, value-0 Inside TopK: index-2, value-0 Inside TopK: index-3, value-0 Inside TopK: index-4, value-0 Inside TopK: index-5, value-3.97472e-05 Inside TopK: index-6, value-8.63052e-05 Inside TopK: index-7, value-0.000100017 Inside TopK: index-8, value-0.000100017 Inside TopK: index-9, value-0.000100017 Inside TopK: index-10, value-0.000100017 Inside TopK: index-11, value-0.000100017 Inside TopK: index-12, value-0.000100017 Inside TopK: index-31, value-0.000605762 Inside TopK: index-43, value-0.00941783 Inside TopK: index-49, value-0.00148731 Inside TopK: index-50, value-0.00305021 Inside TopK: index-88, value-0.00357342 Inside TopK: index-129, value-0.00136298 Inside TopK: index-133, value-0.000960767 Inside TopK: index-177, value-0.00273073 Inside TopK: index-222, value-0.00223464 Inside TopK: index-269, value-0.00184536 Inside TopK: index-373, value-0.00252593 Inside TopK: index-402, value-0.00618088 Inside TopK: index-550, value-0.909768 Inside TopK: index-699, value-0.00313967 Inside TopK: index-764, value-0.00785643 Inside TopK: index-961, value-0.969841 Inside TopK: index-993, value-0.957735 debug_TopK_output: k-6, eltType-6 indexes - 961.000000 993.000000 550.000000 43.000000 764.000000 402.000000 values - 0.969841 0.957735 0.909768 0.009418 0.007856 0.006181 177 1.00000 43.00000 993.00000 6 178 1.00000 43.00000 993.00000 6 179 1.00000 43.00000 993.00000 6 182 1.00000 43.00000 993.00000 6 183 1.00000 43.00000 993.00000 6 Layer, Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger, paddingWait,LayerWithoutPad,LayerHandleCopy, BackupCycles, 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0, 0, 0, 164, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 165, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 166, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 167, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 168, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 169, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 172, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 173, 0, 0, 0, Skipping import of model optimizer Available execution providers : ['TIDLExecutionProvider', 'TIDLCompilationProvider', 'CPUExecutionProvider'] Running 1 Models - ['fnc_safety_fp32'] Running_Model : fnc_safety_fp32 Running shape inference on model ../../../lucid/model_onnx/4_FNC_segv2b_1.onnx ***************Running_Inference Section ********** This is Lucid Model for image ../../../lucid/data_onnx/test_images/img0221.png [array([[[[[[ 0.511462 , 0.41680342, 0.43828052, ..., 0.7086981 , 0.6772027 , 0.8240755 ], [ 0.44560736, 0.63672996, 0.72779065, ..., 0.91080624, 0.76169664, 0.7300023 ], [ 0.57133067, 1.0649538 , 1.1465257 , ..., 1.203231 , 0.9644641 , 0.82434 ], ..., [-1.2045385 , -2.2349632 , -2.433329 , ..., 0.27026686, 0.42285463, 0.2905605 ], [-0.92067355, -1.763102 , -1.8720196 , ..., 0.3520038 , 0.53917825, 0.36092928], [-0.15355474, -0.73811895, -0.83222 , ..., 0.4825024 , 0.5897818 , 0.53294533]], [[ 2.3841689 , 1.4062831 , 2.1977563 , ..., 1.5596943 , 1.139936 , 0.9861106 ], [ 3.7244954 , 2.3186052 , 3.3090394 , ..., 2.1389172 , 1.5474398 , 1.630906 ], [ 2.424337 , -0.22847734, -0.12934232, ..., -0.7007511 , -0.44983777, 0.8992278 ], ..., [ 3.1530886 , 1.3939265 , 1.1020697 , ..., -0.13184476, 0.4716928 , 1.2162737 ], [ 2.928351 , 1.2248297 , 0.9520055 , ..., -0.044136 , 0.3155792 , 1.0919745 ], [ 2.2480333 , 1.0698355 , 0.7804826 , ..., -0.2915687 , 0.02010241, 0.8158504 ]], [[ 0.6618193 , 0.75634074, 0.8223851 , ..., 0.56460905, 0.2918093 , 0.17694342], [ 0.30635574, 0.4048044 , 0.26282194, ..., 0.04415524, -0.06930671, -0.08647949], [ 0.05835931, -0.01026255, -0.26276216, ..., -0.488038 , -0.56132495, -0.4551766 ], ..., [ 0.9862292 , 0.47808993, 0.93043375, ..., -0.98591965, -1.1231134 , -0.72337264], [ 1.113683 , 0.57825166, 1.1035222 , ..., -0.9532932 , -1.0548035 , -0.6583646 ], [ 0.9092247 , 0.54730076, 0.99107957, ..., -0.64531755, -0.5419298 , -0.2003365 ]], ..., [[ 1.4820056 , 1.1283653 , 1.5384485 , ..., 1.313376 , 1.208936 , 1.3080407 ], [ 1.068837 , 0.6277739 , 0.9584801 , ..., 1.0439694 , 1.2075676 , 1.5530211 ], [ 0.9803109 , 0.00696067, 0.317604 , ..., 0.6675898 , 0.8646536 , 1.5470409 ], ..., [ 0.7283539 , -0.19180292, -0.52068245, ..., 0.941422 , 0.657021 , 1.9825711 ], [ 0.7204142 , -0.16031516, -0.41056836, ..., 0.6227242 , 0.43768483, 1.7174236 ], [ 0.685763 , -0.05837438, -0.31247008, ..., 0.92192817, 0.67356336, 1.4909666 ]], [[-0.11445669, -0.10193413, -0.14813626, ..., 0.16301394, 0.3555874 , -0.14734118], [-0.24861805, -0.2140084 , -0.28421617, ..., 0.21316232, 0.527504 , -0.40682337], [-0.3268138 , -0.30877453, -0.29717854, ..., 0.24429561, 0.69015086, -0.24867557], ..., [-1.2280847 , -1.7917873 , -1.6336652 , ..., 0.87687296, 1.3487198 , -0.04492792], [-1.0070736 , -1.5138723 , -1.4477255 , ..., 0.83013815, 1.2523803 , 0.027419 ], [-0.8004235 , -1.0705858 , -1.0499563 , ..., 0.5819657 , 0.85660535, 0.10644702]], [[ 0.47283155, 0.8211557 , 0.28327703, ..., 0.12849069, -0.06892616, 0.7846182 ], [ 0.31851798, 1.082738 , 0.7232499 , ..., 0.57434535, 0.42841008, 0.895289 ], [ 0.29006937, 0.97329336, 0.42737636, ..., 0.26101035, 0.06185104, 0.6204602 ], ..., [-0.57476753, -0.02512613, -0.4345483 , ..., 0.04023543, 0.15519994, 1.1900432 ], [-0.51010644, -0.28359646, -0.5799791 , ..., 0.24837033, 0.29065323, 1.2170067 ], [ 0.09451364, -0.12823 , -0.31821746, ..., 0.45109993, 0.8010767 , 1.1840268 ]]]]]], dtype=float32), array([[[[[[500], [953], [984], [249], [149], [659]]]]]], dtype=int64), array([[[[[[-0.03189182, 0.04785951, 1.4390036 , ..., -1.2859398 , 0.15582752, 1.6347104 ], [-0.05510483, 0.01119827, 1.7420107 , ..., -1.2208266 , 0.3081583 , 1.8542352 ], [-0.08553713, 0.0251184 , 1.8451748 , ..., -1.1139983 , 0.36310807, 1.8959929 ], ..., [-0.06448374, 0.06929123, 0.27610952, ..., -0.27408406, -0.27173454, 1.5156449 ], [-0.05269045, 0.06625804, 0.26288772, ..., -0.27773437, -0.2666724 , 1.475576 ], [-0.04474444, 0.05044444, 0.33272624, ..., -0.19810446, -0.28652173, 1.4088204 ]]]]]], dtype=float32), array([[[[[[-0.0116068 , 0.0917424 , -0.9190511 , ..., 0.8704735 , 1.762514 , -0.9922944 ], [-0.01411797, 0.08845685, -0.93355775, ..., 1.5997343 , 1.7429008 , -0.7332344 ], [-0.0130433 , 0.16310924, -0.7437568 , ..., 1.8849945 , 1.6774775 , -0.55390996], ..., [-0.03662303, 0.05907633, -0.40749156, ..., 1.6502976 , 1.8500556 , -0.39089516], [-0.0221734 , 0.05225439, -0.38777417, ..., 1.6431766 , 1.781872 , -0.2700711 ], [-0.02571772, 0.06609517, -0.3706054 , ..., 1.7820725 , 1.7778959 , -0.2979802 ]]]]]], dtype=float32), array([[[[[[500, 953, 984, 249, 149, 659]]]]]], dtype=int64)] ***************Running_Benchmark_Section ********** ***************Running_Inference Section ********** This is Lucid Model for image ../../../lucid/data_onnx/test_images/img0002.png 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 174, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 175, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 176, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 177, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 178, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 179, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 182, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 183, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Sum of Layer Cycles 0 Sub Graph Stats 345.000000 9615806.000000 1045.000000 ******* TIDL_subgraphRtInvoke done ******** ********** Frame Index 2 : Running float inference ********** Graph Domain TO version : 9******* In TIDL_subgraphRtInvoke ******** 0 1.00000 0.00000 1.00000 6 9 1.00000 0.00000 1.00000 6 10 1.00000 0.00000 0.92256 6 11 1.00000 0.00000 0.92256 6 12 1.00000 0.00000 0.68258 6 13 1.00000 -1.61600 2.02735 6 14 1.00000 0.00000 2.47907 6 15 1.00000 0.00000 1.21477 6 16 1.00000 -1.99066 2.15828 6 17 1.00000 0.00000 2.93869 6 18 1.00000 -1.61467 1.35443 6 19 1.00000 0.00000 1.88040 6 20 1.00000 -6.38037 3.98819 6 21 1.00000 0.00000 4.11070 6 22 1.00000 0.00000 3.28966 6 23 1.00000 -7.13017 6.50971 6 24 1.00000 0.00000 6.84784 6 25 1.00000 -3.34509 3.14964 6 26 1.00000 -2.74268 1.56674 6 27 1.00000 0.00000 5.81895 6 28 1.00000 -14.70219 7.08142 6 29 1.00000 0.00000 7.10297 6 30 1.00000 0.00000 6.99753 6 31 1.00000 -16.44808 8.89491 6 32 1.00000 0.00000 8.89491 6 33 1.00000 -2.76994 2.69272 6 34 1.00000 -13.83402 8.03743 6 35 1.00000 0.00000 9.77327 6 36 1.00000 -88.05355 40.92447 6 37 1.00000 0.00000 41.54440 6 38 1.00000 0.00000 53.69049 6 39 1.00000 -1369.93921 866.18268 6 40 1.00000 0.00000 866.18268 6 41 1.00000 0.00000 5.90778 6 1 1.00000 -0.99999 1.00000 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107 1.00000 -33.51022 15.77821 6 108 1.00000 -33.51022 15.77821 6 109 1.00000 -33.51022 15.77821 6 110 1.00000 -33.51022 15.77821 6 111 1.00000 -33.51022 15.77821 6 112 1.00000 -33.51022 15.77821 6 113 1.00000 -33.51022 15.77821 6 114 1.00000 -33.51022 15.77821 6 115 1.00000 0.00000 0.91256 6 116 1.00000 -3.56255 7.00344 6 117 1.00000 -3.56255 7.00344 6 118 1.00000 -3.56255 7.00344 6 119 1.00000 -3.56255 7.00344 6 120 1.00000 -1.79353 0.91234 6 121 1.00000 -2.21732 5.48413 6 122 1.00000 0.00000 4.66173 6 123 1.00000 -2.87255 3.36746 6 124 1.00000 -2.87255 3.36746 6 125 1.00000 -4.24654 4.30048 6 126 1.00000 -4.24654 4.30048 6 127 1.00000 -5.82096 5.56081 6 128 1.00000 -14.12290 12.05998 6 129 1.00000 0.00000 4.66805 6 130 1.00000 0.00000 4.93386 6 131 1.00000 -4.41856 5.15351 6 132 1.00000 -5.39507 4.72790 6 133 1.00000 0.00000 9.20933 6 134 1.00000 -4.68395 4.88042 6 135 1.00000 0.00000 19.10133 6 136 1.00000 -15.47406 5.03881 6 137 1.00000 0.00000 0.99356 6 3 1.00000 -0.00010 -0.00010 6 138 1.00000 0.00000 0.99346 6 4 1.00000 0.00010 0.00010 6 139 1.00000 0.00010 0.99356 6 5 1.00000 -1.00000 -1.00000 6 140 1.00000 -0.99356 -0.00010 6 6 1.00000 0.99990 0.99990 6 141 1.00000 0.00634 0.99980 6 7 1.00000 -1.00000 -1.00000 6 142 1.00000 -0.99980 -0.00634 6 8 1.00000 0.99990 0.99990 6 143 1.00000 0.00010 0.99356 6 144 1.00000 0.00010 0.99356 6 145 1.00000 -0.99356 -0.00010 6 146 1.00000 -0.98092 0.00000 6 147 1.00000 0.00000 0.10000 6 148 1.00000 0.00000 1.00000 6 149 1.00000 0.00000 0.99356 6 151 1.00000 -4.41856 5.15351 6 152 1.00000 -4.68395 4.88042 6 In Transpose: perm - 0 1 3 2 4 5, pp - 1 In Transpose: indata width-50 height-20 #ch-134 dim2-1 dim1-1 batch-1 In Transpose: outdata width-50 height-20 #ch-1 dim2-134 dim1-1 batch-1 153 1.00000 -4.68395 4.88042 6 154 1.00000 -4.68395 4.88042 6 155 1.00000 -4.68395 4.88042 6 156 1.00000 -4.68395 4.88042 6 157 1.00000 -4.02118 4.60765 6 158 1.00000 -4.68395 4.88042 6 159 1.00000 -4.02118 4.60765 6 160 1.00000 -4.68395 4.88042 6 161 1.00000 -4.02118 4.60765 6 162 1.00000 -4.68395 4.88042 6 163 1.00000 -4.02118 4.60765 6 164 1.00000 -4.68395 4.88042 6 165 1.00000 -4.02118 4.60765 6 166 1.00000 -4.68395 4.88042 6 167 1.00000 -4.02118 4.60765 6 168 1.00000 -4.68395 4.88042 6 169 1.00000 -4.02118 4.60765 6 172 1.00000 -4.02118 4.60765 6 173 1.00000 -4.68395 4.88042 6 174 1.00000 0.00000 0.99356 6 175 1.00000 0.00000 0.99356 6 176 1.00000 0.00000 0.99356 6 ****** in TOPK *********** Inside TopK: index-0, value-0.00195462 Inside TopK: index-1, value-0 Inside TopK: index-2, value-0 Inside TopK: index-3, value-0 Inside TopK: index-4, value-0 Inside TopK: index-5, value-0 Inside TopK: index-16, value-0.00864631 Inside TopK: index-18, value-0.0094437 Inside TopK: index-24, value-0.018661 Inside TopK: index-34, value-0.000100017 Inside TopK: index-35, value-0.000100017 Inside TopK: index-49, value-0.000478446 Inside TopK: index-100, value-0.00232929 Inside TopK: index-126, value-0.00187123 Inside TopK: index-178, value-0.00236243 Inside TopK: index-549, value-0.00389844 Inside TopK: index-550, value-0.99356 Inside TopK: index-649, value-0.00307077 Inside TopK: index-664, value-0.00649941 Inside TopK: index-960, value-0.979808 Inside TopK: index-992, value-0.967558 debug_TopK_output: k-6, eltType-6 indexes - 550.000000 960.000000 992.000000 24.000000 18.000000 16.000000 values - 0.993560 0.979808 0.967558 0.018661 0.009444 0.008646 177 1.00000 16.00000 992.00000 6 178 1.00000 16.00000 992.00000 6 179 1.00000 16.00000 992.00000 6 182 1.00000 16.00000 992.00000 6 183 1.00000 16.00000 992.00000 6 Layer, Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger, paddingWait,LayerWithoutPad,LayerHandleCopy, BackupCycles, RestoreCycles,Multic7xContextCopyCycles, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 167, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 168, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 169, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 172, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 173, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 174, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 175, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 176, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 177, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 178, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 179, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 182, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 183, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Sum of Layer Cycles 0 Sub Graph Stats 339.000000 9978569.000000 1664.000000 ******* TIDL_subgraphRtInvoke done ******** ********** Frame Index 3 : Running fixed point mode for calibration ********** In TIDL_runtimesPostProcessNet In TIDL_runtimesPostProcessNet 1 In TIDL_runtimesPostProcessNet 2 In TIDL_runtimesPostProcessNet 3 Empty prototxt path, running calibration ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ tidl_import_core.cpp 654 cd /home/deepanshu/EdgeAI/edgeai-tidl-tools/tidl_tools && ./PC_dsp_test_dl_algo.out s:/home/deepanshu/EdgeAI/edgeai-tidl-tools/model-artifacts/fnc_safety_fp32/tempDir/795514607501507_tidl_io_.qunat_stats_config.txt Processing config file #0 : /home/deepanshu/EdgeAI/edgeai-tidl-tools/model-artifacts/fnc_safety_fp32/tempDir/795514607501507_tidl_io_.qunat_stats_config.txt debug_TIDL_alloc: inside TIDL_alloc debug_TIDL_alloc0: status-0, ok-0 fail--1 debug_TIDL_alloc0: lIdx-1 mem-0 64128 0 lT-39 debug_TIDL_alloc0: lIdx-2 mem-0 64128 0 lT-39 debug_TIDL_alloc0: lIdx-3 mem-0 4128 0 lT-39 debug_TIDL_alloc0: lIdx-4 mem-0 4128 0 lT-39 debug_TIDL_alloc0: lIdx-5 mem-0 4128 0 lT-39 debug_TIDL_alloc0: lIdx-6 mem-0 4128 0 lT-39 debug_TIDL_alloc0: lIdx-7 mem-0 4128 0 lT-39 debug_TIDL_alloc0: lIdx-8 mem-0 4128 0 lT-39 debug_TIDL_alloc0: lIdx-9 mem-128 128 3151100 lT-29 debug_TIDL_alloc0: lIdx-10 mem-25099520 768 16733056 lT-1 debug_TIDL_alloc0: lIdx-11 mem-6406400 128 4270976 lT-2 debug_TIDL_alloc0: lIdx-12 mem-6406400 768 4270976 lT-1 debug_TIDL_alloc0: lIdx-13 mem-6144128 768 4096128 lT-1 debug_TIDL_alloc0: lIdx-14 mem-6406400 128 128 lT-5 debug_TIDL_alloc0: lIdx-15 mem-6406400 768 128 lT-1 debug_TIDL_alloc0: lIdx-16 mem-6144128 768 128 lT-1 debug_TIDL_alloc0: lIdx-17 mem-6406400 128 128 lT-5 debug_TIDL_alloc0: lIdx-18 mem-3072128 1280 2048128 lT-1 debug_TIDL_alloc0: lIdx-19 mem-3335552 1280 2223744 lT-1 debug_TIDL_alloc0: lIdx-20 mem-3072128 1280 2048128 lT-1 debug_TIDL_alloc0: lIdx-21 mem-3335552 128 128 lT-5 debug_TIDL_alloc0: lIdx-22 mem-3335552 1280 2223744 lT-1 debug_TIDL_alloc0: lIdx-23 mem-3072128 1280 128 lT-1 debug_TIDL_alloc0: lIdx-24 mem-3335552 128 128 lT-5 debug_TIDL_alloc0: lIdx-25 mem-1536128 768 128 lT-1 debug_TIDL_alloc0: lIdx-26 mem-1536128 2304 1024128 lT-1 debug_TIDL_alloc0: lIdx-27 mem-1801856 2304 1201280 lT-1 debug_TIDL_alloc0: lIdx-28 mem-1536128 2304 1024128 lT-1 debug_TIDL_alloc0: lIdx-29 mem-1801856 128 128 lT-5 debug_TIDL_alloc0: lIdx-30 mem-1801856 2304 1201280 lT-1 debug_TIDL_alloc0: lIdx-31 mem-1536128 2304 128 lT-1 debug_TIDL_alloc0: lIdx-32 mem-1801856 128 128 lT-5 debug_TIDL_alloc0: lIdx-33 mem-384128 768 128 lT-1 debug_TIDL_alloc0: lIdx-34 mem-768128 4352 512128 lT-1 debug_TIDL_alloc0: lIdx-35 mem-1038464 4352 692352 lT-1 debug_TIDL_alloc0: lIdx-36 mem-768128 4352 512128 lT-1 debug_TIDL_alloc0: lIdx-37 mem-1038464 128 128 lT-5 debug_TIDL_alloc0: lIdx-38 mem-1038464 4352 692352 lT-1 debug_TIDL_alloc0: lIdx-39 mem-768128 4352 128 lT-1 debug_TIDL_alloc0: lIdx-40 mem-1038464 128 128 lT-5 debug_TIDL_alloc0: lIdx-41 mem-96128 768 128 lT-1 debug_TIDL_alloc0: lIdx-42 mem-96128 128 128 lT-5 debug_TIDL_alloc0: lIdx-43 mem-96128 768 128 lT-1 debug_TIDL_alloc0: lIdx-44 mem-24128 384 16128 lT-1 debug_TIDL_alloc0: lIdx-45 mem-24128 384 16128 lT-1 debug_TIDL_alloc0: lIdx-46 mem-128 128 64128 lT-29 debug_TIDL_alloc0: lIdx-47 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-48 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-49 mem-128 128 64128 lT-38 debug_TIDL_alloc0: lIdx-50 mem-128 128 16128 lT-38 debug_TIDL_alloc0: lIdx-51 mem-128 128 16128 lT-38 debug_TIDL_alloc0: lIdx-52 mem-128 128 64128 lT-29 debug_TIDL_alloc0: lIdx-53 mem-128 128 16128 lT-29 debug_TIDL_alloc0: lIdx-54 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-55 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-56 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-57 mem-128 128 16128 lT-38 debug_TIDL_alloc0: lIdx-58 mem-128 128 16128 lT-29 debug_TIDL_alloc0: lIdx-59 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-60 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-61 mem-128 128 16128 lT-38 debug_TIDL_alloc0: lIdx-62 mem-128 128 16128 lT-29 debug_TIDL_alloc0: lIdx-63 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-64 mem-375128 256 250128 lT-6 debug_TIDL_alloc0: lIdx-65 mem-128 128 250128 lT-29 debug_TIDL_alloc0: lIdx-66 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-67 mem-128 128 250128 lT-38 debug_TIDL_alloc0: lIdx-68 mem-128 128 250128 lT-29 debug_TIDL_alloc0: lIdx-69 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-70 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-71 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-72 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-73 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-74 mem-128 128 128 lT-7 debug_TIDL_alloc0: lIdx-75 mem-96128 256 128 lT-6 debug_TIDL_alloc0: lIdx-76 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-77 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-78 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-79 mem-96128 1280 128 lT-8 debug_TIDL_alloc0: lIdx-80 mem-129920 128 128 lT-5 debug_TIDL_alloc0: lIdx-81 mem-129920 768 128 lT-1 debug_TIDL_alloc0: lIdx-82 mem-96128 768 128 lT-1 debug_TIDL_alloc0: lIdx-83 mem-96128 128 128 lT-5 debug_TIDL_alloc0: lIdx-84 mem-96128 768 128 lT-1 debug_TIDL_alloc0: lIdx-85 mem-24128 384 128 lT-1 debug_TIDL_alloc0: lIdx-86 mem-24128 384 128 lT-1 debug_TIDL_alloc0: lIdx-87 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-88 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-89 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-90 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-91 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-92 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-93 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-94 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-95 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-96 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-97 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-98 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-99 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-100 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-101 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-102 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-103 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-104 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-105 mem-375128 256 128 lT-6 debug_TIDL_alloc0: lIdx-106 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-107 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-108 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-109 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-110 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-111 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-112 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-113 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-114 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-115 mem-128 128 128 lT-7 debug_TIDL_alloc0: lIdx-116 mem-96128 256 128 lT-6 debug_TIDL_alloc0: lIdx-117 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-118 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-119 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-120 mem-96128 1280 128 lT-8 debug_TIDL_alloc0: lIdx-121 mem-129920 128 128 lT-5 debug_TIDL_alloc0: lIdx-122 mem-96128 768 128 lT-1 debug_TIDL_alloc0: lIdx-123 mem-129920 768 128 lT-1 debug_TIDL_alloc0: lIdx-124 mem-128 128 128 lT-21 debug_TIDL_alloc0: lIdx-125 mem-450560 128 128 lT-5 debug_TIDL_alloc0: lIdx-126 mem-128 128 128 lT-21 debug_TIDL_alloc0: lIdx-127 mem-1667840 128 128 lT-5 debug_TIDL_alloc0: lIdx-128 mem-1667840 768 128 lT-1 debug_TIDL_alloc0: lIdx-129 mem-1667840 768 128 lT-1 debug_TIDL_alloc0: lIdx-130 mem-1667840 768 128 lT-1 debug_TIDL_alloc0: lIdx-131 mem-1536128 768 128 lT-1 debug_TIDL_alloc0: lIdx-132 mem-450560 768 128 lT-1 debug_TIDL_alloc0: lIdx-133 mem-384128 768 128 lT-1 debug_TIDL_alloc0: lIdx-134 mem-804128 1328 128 lT-1 debug_TIDL_alloc0: lIdx-135 mem-384128 768 128 lT-1 debug_TIDL_alloc0: lIdx-136 mem-6128 264 4128 lT-1 debug_TIDL_alloc0: lIdx-137 mem-6128 524 128 lT-8 debug_TIDL_alloc0: lIdx-138 mem-6128 128 128 lT-5 debug_TIDL_alloc0: lIdx-139 mem-6128 128 128 lT-5 debug_TIDL_alloc0: lIdx-140 mem-6128 128 128 lT-5 debug_TIDL_alloc0: lIdx-141 mem-6128 128 128 lT-5 debug_TIDL_alloc0: lIdx-142 mem-6128 128 128 lT-5 debug_TIDL_alloc0: lIdx-143 mem-7166 128 128 lT-5 debug_TIDL_alloc0: lIdx-144 mem-6128 128 128 lT-2 debug_TIDL_alloc0: lIdx-145 mem-6128 524 128 lT-8 debug_TIDL_alloc0: lIdx-146 mem-6128 128 128 lT-5 debug_TIDL_alloc0: lIdx-147 mem-6128 524 128 lT-8 debug_TIDL_alloc0: lIdx-148 mem-6128 524 128 lT-8 debug_TIDL_alloc0: lIdx-149 mem-6128 128 128 lT-5 debug_TIDL_alloc0: lIdx-151 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-152 mem-128 128 536128 lT-29 debug_TIDL_alloc0: lIdx-153 mem-128 128 128 lT-41 debug_TIDL_alloc0: lIdx-154 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-155 mem-128 128 536128 lT-38 debug_TIDL_alloc0: lIdx-156 mem-402128 792 268128 lT-1 debug_TIDL_alloc0: lIdx-157 mem-402128 792 268128 lT-1 debug_TIDL_alloc0: lIdx-158 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-159 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-160 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-161 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-162 mem-128 128 268128 lT-38 debug_TIDL_alloc0: lIdx-163 mem-128 128 268128 lT-38 debug_TIDL_alloc0: lIdx-164 mem-128 128 268128 lT-38 debug_TIDL_alloc0: lIdx-165 mem-128 128 268128 lT-38 debug_TIDL_alloc0: lIdx-166 mem-128 128 268128 lT-29 debug_TIDL_alloc0: lIdx-167 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-168 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-169 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-172 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-173 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-174 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-175 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-176 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-177 mem-128 65920 152 lT-43 debug_TIDL_alloc0: lIdx-178 mem-128 128 152 lT-38 debug_TIDL_alloc0: lIdx-179 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-182 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-183 mem-128 128 128 lT-29 debug_TIDL_init0: lIdx-1 0 64128 0 debug_TIDL_init0: lIdx-2 0 64128 0 debug_TIDL_init0: lIdx-3 0 4128 0 debug_TIDL_init0: lIdx-4 0 4128 0 debug_TIDL_init0: lIdx-5 0 4128 0 debug_TIDL_init0: lIdx-6 0 4128 0 debug_TIDL_init0: lIdx-7 0 4128 0 debug_TIDL_init0: lIdx-8 0 4128 0 debug_TIDL_init0: lIdx-9 128 128 3151100 debug_TIDL_init0: lIdx-10 25099520 768 16733056 debug_TIDL_init0: lIdx-11 6406400 128 4270976 debug_TIDL_init0: lIdx-12 6406400 768 4270976 debug_TIDL_init0: lIdx-13 6144128 768 4096128 debug_TIDL_init0: lIdx-14 6406400 128 128 debug_TIDL_init0: lIdx-15 6406400 768 128 debug_TIDL_init0: lIdx-16 6144128 768 128 debug_TIDL_init0: lIdx-17 6406400 128 128 debug_TIDL_init0: lIdx-18 3072128 1280 2048128 debug_TIDL_init0: lIdx-19 3335552 1280 2223744 debug_TIDL_init0: lIdx-20 3072128 1280 2048128 debug_TIDL_init0: lIdx-21 3335552 128 128 debug_TIDL_init0: lIdx-22 3335552 1280 2223744 debug_TIDL_init0: lIdx-23 3072128 1280 128 debug_TIDL_init0: lIdx-24 3335552 128 128 debug_TIDL_init0: lIdx-25 1536128 768 128 debug_TIDL_init0: lIdx-26 1536128 2304 1024128 debug_TIDL_init0: lIdx-27 1801856 2304 1201280 debug_TIDL_init0: lIdx-28 1536128 2304 1024128 debug_TIDL_init0: lIdx-29 1801856 128 128 debug_TIDL_init0: lIdx-30 1801856 2304 1201280 debug_TIDL_init0: lIdx-31 1536128 2304 128 debug_TIDL_init0: lIdx-32 1801856 128 128 debug_TIDL_init0: lIdx-33 384128 768 128 debug_TIDL_init0: lIdx-34 768128 4352 512128 debug_TIDL_init0: lIdx-35 1038464 4352 692352 debug_TIDL_init0: lIdx-36 768128 4352 512128 debug_TIDL_init0: lIdx-37 1038464 128 128 debug_TIDL_init0: lIdx-38 1038464 4352 692352 debug_TIDL_init0: lIdx-39 768128 4352 128 debug_TIDL_init0: lIdx-40 1038464 128 128 debug_TIDL_init0: lIdx-41 96128 768 128 debug_TIDL_init0: lIdx-42 96128 128 128 debug_TIDL_init0: lIdx-43 96128 768 128 debug_TIDL_init0: lIdx-44 24128 384 16128 debug_TIDL_init0: lIdx-45 24128 384 16128 debug_TIDL_init0: lIdx-46 128 128 64128 debug_TIDL_init0: lIdx-47 128 128 128 debug_TIDL_init0: lIdx-48 128 128 128 debug_TIDL_init0: lIdx-49 128 128 64128 debug_TIDL_init0: lIdx-50 128 128 16128 debug_TIDL_init0: lIdx-51 128 128 16128 debug_TIDL_init0: lIdx-52 128 128 64128 debug_TIDL_init0: lIdx-53 128 128 16128 debug_TIDL_init0: lIdx-54 128 128 128 debug_TIDL_init0: lIdx-55 128 128 128 debug_TIDL_init0: lIdx-56 128 128 128 debug_TIDL_init0: lIdx-57 128 128 16128 debug_TIDL_init0: lIdx-58 128 128 16128 debug_TIDL_init0: lIdx-59 128 128 128 debug_TIDL_init0: lIdx-60 128 128 128 debug_TIDL_init0: lIdx-61 128 128 16128 debug_TIDL_init0: lIdx-62 128 128 16128 debug_TIDL_init0: lIdx-63 128 128 128 debug_TIDL_init0: lIdx-64 375128 128 250128 debug_TIDL_init0: lIdx-65 128 128 250128 debug_TIDL_init0: lIdx-66 128 128 128 debug_TIDL_init0: lIdx-67 128 128 250128 debug_TIDL_init0: lIdx-68 128 128 250128 debug_TIDL_init0: lIdx-69 128 128 128 debug_TIDL_init0: lIdx-70 128 128 128 debug_TIDL_init0: lIdx-71 128 128 128 debug_TIDL_init0: lIdx-72 128 128 128 debug_TIDL_init0: lIdx-73 128 128 128 debug_TIDL_init0: lIdx-74 128 128 128 debug_TIDL_init0: lIdx-75 96128 128 128 debug_TIDL_init0: lIdx-76 128 128 128 debug_TIDL_init0: lIdx-77 128 128 128 debug_TIDL_init0: lIdx-78 128 128 128 debug_TIDL_init0: lIdx-79 96128 896 128 debug_TIDL_init0: lIdx-80 129920 128 128 debug_TIDL_init0: lIdx-81 129920 768 128 debug_TIDL_init0: lIdx-82 96128 768 128 debug_TIDL_init0: lIdx-83 96128 128 128 debug_TIDL_init0: lIdx-84 96128 768 128 debug_TIDL_init0: lIdx-85 24128 384 128 debug_TIDL_init0: lIdx-86 24128 384 128 debug_TIDL_init0: lIdx-87 128 128 128 debug_TIDL_init0: lIdx-88 128 128 128 debug_TIDL_init0: lIdx-89 128 128 128 debug_TIDL_init0: lIdx-90 128 128 128 debug_TIDL_init0: lIdx-91 128 128 128 debug_TIDL_init0: lIdx-92 128 128 128 debug_TIDL_init0: lIdx-93 128 128 128 debug_TIDL_init0: lIdx-94 128 128 128 debug_TIDL_init0: lIdx-95 128 128 128 debug_TIDL_init0: lIdx-96 128 128 128 debug_TIDL_init0: lIdx-97 128 128 128 debug_TIDL_init0: lIdx-98 128 128 128 debug_TIDL_init0: lIdx-99 128 128 128 debug_TIDL_init0: lIdx-100 128 128 128 debug_TIDL_init0: lIdx-101 128 128 128 debug_TIDL_init0: lIdx-102 128 128 128 debug_TIDL_init0: lIdx-103 128 128 128 debug_TIDL_init0: lIdx-104 128 128 128 debug_TIDL_init0: lIdx-105 375128 128 128 debug_TIDL_init0: lIdx-106 128 128 128 debug_TIDL_init0: lIdx-107 128 128 128 debug_TIDL_init0: lIdx-108 128 128 128 debug_TIDL_init0: lIdx-109 128 128 128 debug_TIDL_init0: lIdx-110 128 128 128 debug_TIDL_init0: lIdx-111 128 128 128 debug_TIDL_init0: lIdx-112 128 128 128 debug_TIDL_init0: lIdx-113 128 128 128 debug_TIDL_init0: lIdx-114 128 128 128 debug_TIDL_init0: lIdx-115 128 128 128 debug_TIDL_init0: lIdx-116 96128 128 128 debug_TIDL_init0: lIdx-117 128 128 128 debug_TIDL_init0: lIdx-118 128 128 128 debug_TIDL_init0: lIdx-119 128 128 128 debug_TIDL_init0: lIdx-120 96128 896 128 debug_TIDL_init0: lIdx-121 129920 128 128 debug_TIDL_init0: lIdx-122 96128 768 128 debug_TIDL_init0: lIdx-123 129920 768 128 debug_TIDL_init0: lIdx-124 128 128 128 debug_TIDL_init0: lIdx-125 450560 128 128 debug_TIDL_init0: lIdx-126 128 128 128 debug_TIDL_init0: lIdx-127 1667840 128 128 debug_TIDL_init0: lIdx-128 1667840 768 128 debug_TIDL_init0: lIdx-129 1667840 768 128 debug_TIDL_init0: lIdx-130 1667840 768 128 debug_TIDL_init0: lIdx-131 1536128 768 128 debug_TIDL_init0: lIdx-132 450560 768 128 debug_TIDL_init0: lIdx-133 384128 768 128 debug_TIDL_init0: lIdx-134 804128 1328 128 debug_TIDL_init0: lIdx-135 384128 768 128 debug_TIDL_init0: lIdx-136 6128 264 4128 debug_TIDL_init0: lIdx-137 6128 512 128 debug_TIDL_init0: lIdx-138 6128 128 128 debug_TIDL_init0: lIdx-139 6128 128 128 debug_TIDL_init0: lIdx-140 6128 128 128 debug_TIDL_init0: lIdx-141 6128 128 128 debug_TIDL_init0: lIdx-142 6128 128 128 debug_TIDL_init0: lIdx-143 7166 128 128 debug_TIDL_init0: lIdx-144 6128 128 128 debug_TIDL_init0: lIdx-145 6128 512 128 debug_TIDL_init0: lIdx-146 6128 128 128 debug_TIDL_init0: lIdx-147 6128 512 128 debug_TIDL_init0: lIdx-148 6128 512 128 debug_TIDL_init0: lIdx-149 6128 128 128 debug_TIDL_init0: lIdx-151 128 128 128 debug_TIDL_init0: lIdx-152 128 128 536128 debug_TIDL_init0: lIdx-153 128 128 128 debug_TIDL_init0: lIdx-154 128 128 128 debug_TIDL_init0: lIdx-155 128 128 536128 debug_TIDL_init0: lIdx-156 402128 792 268128 debug_TIDL_init0: lIdx-157 402128 792 268128 debug_TIDL_init0: lIdx-158 128 128 128 debug_TIDL_init0: lIdx-159 128 128 128 debug_TIDL_init0: lIdx-160 128 128 128 debug_TIDL_init0: lIdx-161 128 128 128 debug_TIDL_init0: lIdx-162 128 128 268128 debug_TIDL_init0: lIdx-163 128 128 268128 debug_TIDL_init0: lIdx-164 128 128 268128 debug_TIDL_init0: lIdx-165 128 128 268128 debug_TIDL_init0: lIdx-166 128 128 268128 debug_TIDL_init0: lIdx-167 128 128 128 debug_TIDL_init0: lIdx-168 128 128 128 debug_TIDL_init0: lIdx-169 128 128 128 debug_TIDL_init0: lIdx-172 128 128 128 debug_TIDL_init0: lIdx-173 128 128 128 debug_TIDL_init0: lIdx-174 128 128 128 debug_TIDL_init0: lIdx-175 128 128 128 debug_TIDL_init0: lIdx-176 128 128 128 debug_TIDL_init0: lIdx-177 128 65792 152 debug_TIDL_init0: lIdx-178 128 128 152 debug_TIDL_init0: lIdx-179 128 128 128 debug_TIDL_init0: lIdx-182 128 128 128 debug_TIDL_init0: lIdx-183 128 128 128 Freeing memory for user provided Net ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . ..In Transpose: perm - 0 1 3 2 4 5, pp - 1 In Transpose: indata width-50 height-20 #ch-134 dim2-1 dim1-1 batch-1 In Transpose: outdata width-50 height-20 #ch-1 dim2-134 dim1-1 batch-1 ****** in TOPK *********** Inside TopK: index-0, value-0.000780582 Inside TopK: index-1, value-0 Inside TopK: index-2, value-0.000100017 Inside TopK: index-3, value-0.000100017 Inside TopK: index-4, value-0.000100017 Inside TopK: index-5, value-0.000100017 Inside TopK: index-12, value-0.000537395 Inside TopK: index-20, value-0.00699091 Inside TopK: index-49, value-0.00222981 Inside TopK: index-149, value-0.0103909 Inside TopK: index-162, value-0.00292653 Inside TopK: index-225, value-0.00093168 Inside TopK: index-249, value-0.0143731 Inside TopK: index-250, value-0.00128621 Inside TopK: index-259, value-0.00204778 Inside TopK: index-500, value-0.983345 Inside TopK: index-659, value-0.00717902 Inside TopK: index-749, value-0.00603288 Inside TopK: index-953, value-0.981534 Inside TopK: index-984, value-0.925356 debug_TopK_output: k-6, eltType-6 indexes - 500.000000 953.000000 984.000000 249.000000 149.000000 659.000000 values - 0.983345 0.981534 0.925356 0.014373 0.010391 0.007179 T 10005.95 .... ..... ... dumping outputs 795 1x64x40x100 ele_size_in_bytes 4 607 1x1x1000x67 ele_size_in_bytes 4 514 1x1x1000x67 ele_size_in_bytes 4 seeds 1x1x6x1 ele_size_in_bytes 4 507 1x1x1x6 ele_size_in_bytes 4 .... ..... # 1 . ..In Transpose: perm - 0 1 3 2 4 5, pp - 1 In Transpose: indata width-50 height-20 #ch-134 dim2-1 dim1-1 batch-1 In Transpose: outdata width-50 height-20 #ch-1 dim2-134 dim1-1 batch-1 ****** in TOPK *********** Inside TopK: index-0, value-0 Inside TopK: index-1, value-0 Inside TopK: index-2, value-0 Inside TopK: index-3, value-0 Inside TopK: index-4, value-0 Inside TopK: index-5, value-3.97472e-05 Inside TopK: index-6, value-8.63052e-05 Inside TopK: index-7, value-0.000100017 Inside TopK: index-8, value-0.000100017 Inside TopK: index-9, value-0.000100017 Inside TopK: index-10, value-0.000100017 Inside TopK: index-11, value-0.000100017 Inside TopK: index-12, value-0.000100017 Inside TopK: index-31, value-0.000605762 Inside TopK: index-43, value-0.00941783 Inside TopK: index-49, value-0.00148731 Inside TopK: index-50, value-0.00305021 Inside TopK: index-88, value-0.00357342 Inside TopK: index-129, value-0.00136298 Inside TopK: index-133, value-0.000960767 Inside TopK: index-177, value-0.00273073 Inside TopK: index-222, value-0.00223464 Inside TopK: index-269, value-0.00184536 Inside TopK: index-373, value-0.00252593 Inside TopK: index-402, value-0.00618088 Inside TopK: index-550, value-0.909768 Inside TopK: index-699, value-0.00313967 Inside TopK: index-764, value-0.00785643 Inside TopK: index-961, value-0.969841 Inside TopK: index-993, value-0.957735 debug_TopK_output: k-6, eltType-6 indexes - 961.000000 993.000000 550.000000 43.000000 764.000000 402.000000 values - 0.969841 0.957735 0.909768 0.009418 0.007856 0.006181 T 9964.43 .... ..... ... dumping outputs 795 1x64x40x100 ele_size_in_bytes 4 607 1x1x1000x67 ele_size_in_bytes 4 514 1x1x1000x67 ele_size_in_bytes 4 seeds 1x1x6x1 ele_size_in_bytes 4 507 1x1x1x6 ele_size_in_bytes 4 .... ..... # 2 . ..In Transpose: perm - 0 1 3 2 4 5, pp - 1 In Transpose: indata width-50 height-20 #ch-134 dim2-1 dim1-1 batch-1 In Transpose: outdata width-50 height-20 #ch-1 dim2-134 dim1-1 batch-1 ****** in TOPK *********** Inside TopK: index-0, value-0.00195462 Inside TopK: index-1, value-0 Inside TopK: index-2, value-0 Inside TopK: index-3, value-0 Inside TopK: index-4, value-0 Inside TopK: index-5, value-0 Inside TopK: index-16, value-0.00864631 Inside TopK: index-18, value-0.0094437 Inside TopK: index-24, value-0.018661 Inside TopK: index-34, value-0.000100017 Inside TopK: index-35, value-0.000100017 Inside TopK: index-49, value-0.000478446 Inside TopK: index-100, value-0.00232929 Inside TopK: index-126, value-0.00187123 Inside TopK: index-178, value-0.00236243 Inside TopK: index-549, value-0.00389844 Inside TopK: index-550, value-0.99356 Inside TopK: index-649, value-0.00307077 Inside TopK: index-664, value-0.00649941 Inside TopK: index-960, value-0.979808 Inside TopK: index-992, value-0.967558 debug_TopK_output: k-6, eltType-6 indexes - 550.000000 960.000000 992.000000 24.000000 18.000000 16.000000 values - 0.993560 0.979808 0.967558 0.018661 0.009444 0.008646 T 9922.12 .... ..... ... dumping outputs 795 1x64x40x100 ele_size_in_bytes 4 607 1x1x1000x67 ele_size_in_bytes 4 514 1x1x1000x67 ele_size_in_bytes 4 seeds 1x1x6x1 ele_size_in_bytes 4 507 1x1x1x6 ele_size_in_bytes 4 .... ..... ***************** Calibration iteration number 0 started ************************ Empty prototxt path, running calibration ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ tidl_import_core.cpp 654 cd /home/deepanshu/EdgeAI/edgeai-tidl-tools/tidl_tools && ./PC_dsp_test_dl_algo.out s:/home/deepanshu/EdgeAI/edgeai-tidl-tools/model-artifacts/fnc_safety_fp32/tempDir/795514607501507_tidl_io_.qunat_stats_config.txt Processing config file #0 : /home/deepanshu/EdgeAI/edgeai-tidl-tools/model-artifacts/fnc_safety_fp32/tempDir/795514607501507_tidl_io_.qunat_stats_config.txt debug_TIDL_alloc: inside TIDL_alloc debug_TIDL_alloc0: status-0, ok-0 fail--1 debug_TIDL_alloc0: lIdx-1 mem-0 32128 0 lT-39 debug_TIDL_alloc0: lIdx-2 mem-0 32128 0 lT-39 debug_TIDL_alloc0: lIdx-3 mem-0 2128 0 lT-39 debug_TIDL_alloc0: lIdx-4 mem-0 2128 0 lT-39 debug_TIDL_alloc0: lIdx-5 mem-0 2128 0 lT-39 debug_TIDL_alloc0: lIdx-6 mem-0 2128 0 lT-39 debug_TIDL_alloc0: lIdx-7 mem-0 2128 0 lT-39 debug_TIDL_alloc0: lIdx-8 mem-0 2128 0 lT-39 debug_TIDL_alloc0: lIdx-9 mem-128 128 1575614 lT-29 debug_TIDL_alloc0: lIdx-10 mem-100397696 1024 8366592 lT-1 debug_TIDL_alloc0: lIdx-11 mem-25625216 128 2135552 lT-2 debug_TIDL_alloc0: lIdx-12 mem-25625216 1024 2135552 lT-1 debug_TIDL_alloc0: lIdx-13 mem-24576128 1024 2048128 lT-1 debug_TIDL_alloc0: lIdx-14 mem-25625216 128 128 lT-5 debug_TIDL_alloc0: lIdx-15 mem-25625216 1024 128 lT-1 debug_TIDL_alloc0: lIdx-16 mem-24576128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-17 mem-25625216 128 128 lT-5 debug_TIDL_alloc0: lIdx-18 mem-12288128 1792 1024128 lT-1 debug_TIDL_alloc0: lIdx-19 mem-13341824 1792 1111936 lT-1 debug_TIDL_alloc0: lIdx-20 mem-12288128 1792 1024128 lT-1 debug_TIDL_alloc0: lIdx-21 mem-13341824 128 128 lT-5 debug_TIDL_alloc0: lIdx-22 mem-13341824 1792 1111936 lT-1 debug_TIDL_alloc0: lIdx-23 mem-12288128 1792 128 lT-1 debug_TIDL_alloc0: lIdx-24 mem-13341824 128 128 lT-5 debug_TIDL_alloc0: lIdx-25 mem-6144128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-26 mem-6144128 3328 512128 lT-1 debug_TIDL_alloc0: lIdx-27 mem-7207040 3328 600704 lT-1 debug_TIDL_alloc0: lIdx-28 mem-6144128 3328 512128 lT-1 debug_TIDL_alloc0: lIdx-29 mem-7207040 128 128 lT-5 debug_TIDL_alloc0: lIdx-30 mem-7207040 3328 600704 lT-1 debug_TIDL_alloc0: lIdx-31 mem-6144128 3328 128 lT-1 debug_TIDL_alloc0: lIdx-32 mem-7207040 128 128 lT-5 debug_TIDL_alloc0: lIdx-33 mem-1536128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-34 mem-3072128 6400 256128 lT-1 debug_TIDL_alloc0: lIdx-35 mem-4153472 6400 346240 lT-1 debug_TIDL_alloc0: lIdx-36 mem-3072128 6400 256128 lT-1 debug_TIDL_alloc0: lIdx-37 mem-4153472 128 128 lT-5 debug_TIDL_alloc0: lIdx-38 mem-4153472 6400 346240 lT-1 debug_TIDL_alloc0: lIdx-39 mem-3072128 6400 128 lT-1 debug_TIDL_alloc0: lIdx-40 mem-4153472 128 128 lT-5 debug_TIDL_alloc0: lIdx-41 mem-384128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-42 mem-384128 128 128 lT-5 debug_TIDL_alloc0: lIdx-43 mem-384128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-44 mem-96128 448 8128 lT-1 debug_TIDL_alloc0: lIdx-45 mem-96128 448 8128 lT-1 debug_TIDL_alloc0: lIdx-46 mem-128 128 32128 lT-29 debug_TIDL_alloc0: lIdx-47 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-48 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-49 mem-128 128 32128 lT-38 debug_TIDL_alloc0: lIdx-50 mem-128 128 8128 lT-38 debug_TIDL_alloc0: lIdx-51 mem-128 128 8128 lT-38 debug_TIDL_alloc0: lIdx-52 mem-128 128 32128 lT-29 debug_TIDL_alloc0: lIdx-53 mem-128 128 8128 lT-29 debug_TIDL_alloc0: lIdx-54 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-55 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-56 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-57 mem-128 128 8128 lT-38 debug_TIDL_alloc0: lIdx-58 mem-128 128 8128 lT-29 debug_TIDL_alloc0: lIdx-59 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-60 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-61 mem-128 128 8128 lT-38 debug_TIDL_alloc0: lIdx-62 mem-128 128 8128 lT-29 debug_TIDL_alloc0: lIdx-63 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-64 mem-1500128 256 125128 lT-6 debug_TIDL_alloc0: lIdx-65 mem-128 128 125128 lT-29 debug_TIDL_alloc0: lIdx-66 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-67 mem-128 128 125128 lT-38 debug_TIDL_alloc0: lIdx-68 mem-128 128 125128 lT-29 debug_TIDL_alloc0: lIdx-69 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-70 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-71 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-72 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-73 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-74 mem-128 128 128 lT-7 debug_TIDL_alloc0: lIdx-75 mem-384128 256 128 lT-6 debug_TIDL_alloc0: lIdx-76 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-77 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-78 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-79 mem-384128 1152 128 lT-8 debug_TIDL_alloc0: lIdx-80 mem-519296 128 128 lT-5 debug_TIDL_alloc0: lIdx-81 mem-519296 1024 128 lT-1 debug_TIDL_alloc0: lIdx-82 mem-384128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-83 mem-384128 128 128 lT-5 debug_TIDL_alloc0: lIdx-84 mem-384128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-85 mem-96128 448 128 lT-1 debug_TIDL_alloc0: lIdx-86 mem-96128 448 128 lT-1 debug_TIDL_alloc0: lIdx-87 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-88 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-89 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-90 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-91 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-92 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-93 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-94 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-95 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-96 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-97 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-98 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-99 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-100 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-101 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-102 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-103 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-104 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-105 mem-1500128 256 128 lT-6 debug_TIDL_alloc0: lIdx-106 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-107 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-108 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-109 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-110 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-111 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-112 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-113 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-114 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-115 mem-128 128 128 lT-7 debug_TIDL_alloc0: lIdx-116 mem-384128 256 128 lT-6 debug_TIDL_alloc0: lIdx-117 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-118 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-119 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-120 mem-384128 1152 128 lT-8 debug_TIDL_alloc0: lIdx-121 mem-519296 128 128 lT-5 debug_TIDL_alloc0: lIdx-122 mem-384128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-123 mem-519296 1024 128 lT-1 debug_TIDL_alloc0: lIdx-124 mem-128 128 128 lT-21 debug_TIDL_alloc0: lIdx-125 mem-1801856 128 128 lT-5 debug_TIDL_alloc0: lIdx-126 mem-128 128 128 lT-21 debug_TIDL_alloc0: lIdx-127 mem-6670976 128 128 lT-5 debug_TIDL_alloc0: lIdx-128 mem-6670976 1024 128 lT-1 debug_TIDL_alloc0: lIdx-129 mem-6670976 1024 128 lT-1 debug_TIDL_alloc0: lIdx-130 mem-6670976 1024 128 lT-1 debug_TIDL_alloc0: lIdx-131 mem-6144128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-132 mem-1801856 1024 128 lT-1 debug_TIDL_alloc0: lIdx-133 mem-1536128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-134 mem-3216128 1864 128 lT-1 debug_TIDL_alloc0: lIdx-135 mem-1536128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-136 mem-24128 268 2128 lT-1 debug_TIDL_alloc0: lIdx-137 mem-24128 522 128 lT-8 debug_TIDL_alloc0: lIdx-138 mem-24128 128 128 lT-5 debug_TIDL_alloc0: lIdx-139 mem-24128 128 128 lT-5 debug_TIDL_alloc0: lIdx-140 mem-24128 128 128 lT-5 debug_TIDL_alloc0: lIdx-141 mem-24128 128 128 lT-5 debug_TIDL_alloc0: lIdx-142 mem-24128 128 128 lT-5 debug_TIDL_alloc0: lIdx-143 mem-28280 128 128 lT-5 debug_TIDL_alloc0: lIdx-144 mem-24128 128 128 lT-2 debug_TIDL_alloc0: lIdx-145 mem-24128 522 128 lT-8 debug_TIDL_alloc0: lIdx-146 mem-24128 128 128 lT-5 debug_TIDL_alloc0: lIdx-147 mem-24128 522 128 lT-8 debug_TIDL_alloc0: lIdx-148 mem-24128 522 128 lT-8 debug_TIDL_alloc0: lIdx-149 mem-24128 128 128 lT-5 debug_TIDL_alloc0: lIdx-151 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-152 mem-128 128 268128 lT-29 debug_TIDL_alloc0: lIdx-153 mem-128 128 128 lT-41 debug_TIDL_alloc0: lIdx-154 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-155 mem-128 128 268128 lT-38 debug_TIDL_alloc0: lIdx-156 mem-1608128 1060 134128 lT-1 debug_TIDL_alloc0: lIdx-157 mem-1608128 1060 134128 lT-1 debug_TIDL_alloc0: lIdx-158 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-159 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-160 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-161 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-162 mem-128 128 134128 lT-38 debug_TIDL_alloc0: lIdx-163 mem-128 128 134128 lT-38 debug_TIDL_alloc0: lIdx-164 mem-128 128 134128 lT-38 debug_TIDL_alloc0: lIdx-165 mem-128 128 134128 lT-38 debug_TIDL_alloc0: lIdx-166 mem-128 128 134128 lT-29 debug_TIDL_alloc0: lIdx-167 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-168 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-169 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-172 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-173 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-174 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-175 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-176 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-177 mem-128 65920 140 lT-43 debug_TIDL_alloc0: lIdx-178 mem-128 128 140 lT-38 debug_TIDL_alloc0: lIdx-179 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-182 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-183 mem-128 128 128 lT-29 debug_TIDL_init0: lIdx-1 0 32128 0 debug_TIDL_init0: lIdx-2 0 32128 0 debug_TIDL_init0: lIdx-3 0 2128 0 debug_TIDL_init0: lIdx-4 0 2128 0 debug_TIDL_init0: lIdx-5 0 2128 0 debug_TIDL_init0: lIdx-6 0 2128 0 debug_TIDL_init0: lIdx-7 0 2128 0 debug_TIDL_init0: lIdx-8 0 2128 0 debug_TIDL_init0: lIdx-9 128 128 1575614 debug_TIDL_init0: lIdx-10 100397696 1024 8366592 debug_TIDL_init0: lIdx-11 25625216 128 2135552 debug_TIDL_init0: lIdx-12 25625216 1024 2135552 debug_TIDL_init0: lIdx-13 24576128 1024 2048128 debug_TIDL_init0: lIdx-14 25625216 128 128 debug_TIDL_init0: lIdx-15 25625216 1024 128 debug_TIDL_init0: lIdx-16 24576128 1024 128 debug_TIDL_init0: lIdx-17 25625216 128 128 debug_TIDL_init0: lIdx-18 12288128 1792 1024128 debug_TIDL_init0: lIdx-19 13341824 1792 1111936 debug_TIDL_init0: lIdx-20 12288128 1792 1024128 debug_TIDL_init0: lIdx-21 13341824 128 128 debug_TIDL_init0: lIdx-22 13341824 1792 1111936 debug_TIDL_init0: lIdx-23 12288128 1792 128 debug_TIDL_init0: lIdx-24 13341824 128 128 debug_TIDL_init0: lIdx-25 6144128 1024 128 debug_TIDL_init0: lIdx-26 6144128 3328 512128 debug_TIDL_init0: lIdx-27 7207040 3328 600704 debug_TIDL_init0: lIdx-28 6144128 3328 512128 debug_TIDL_init0: lIdx-29 7207040 128 128 debug_TIDL_init0: lIdx-30 7207040 3328 600704 debug_TIDL_init0: lIdx-31 6144128 3328 128 debug_TIDL_init0: lIdx-32 7207040 128 128 debug_TIDL_init0: lIdx-33 1536128 1024 128 debug_TIDL_init0: lIdx-34 3072128 6400 256128 debug_TIDL_init0: lIdx-35 4153472 6400 346240 debug_TIDL_init0: lIdx-36 3072128 6400 256128 debug_TIDL_init0: lIdx-37 4153472 128 128 debug_TIDL_init0: lIdx-38 4153472 6400 346240 debug_TIDL_init0: lIdx-39 3072128 6400 128 debug_TIDL_init0: lIdx-40 4153472 128 128 debug_TIDL_init0: lIdx-41 384128 1024 128 debug_TIDL_init0: lIdx-42 384128 128 128 debug_TIDL_init0: lIdx-43 384128 1024 128 debug_TIDL_init0: lIdx-44 96128 448 8128 debug_TIDL_init0: lIdx-45 96128 448 8128 debug_TIDL_init0: lIdx-46 128 128 32128 debug_TIDL_init0: lIdx-47 128 128 128 debug_TIDL_init0: lIdx-48 128 128 128 debug_TIDL_init0: lIdx-49 128 128 32128 debug_TIDL_init0: lIdx-50 128 128 8128 debug_TIDL_init0: lIdx-51 128 128 8128 debug_TIDL_init0: lIdx-52 128 128 32128 debug_TIDL_init0: lIdx-53 128 128 8128 debug_TIDL_init0: lIdx-54 128 128 128 debug_TIDL_init0: lIdx-55 128 128 128 debug_TIDL_init0: lIdx-56 128 128 128 debug_TIDL_init0: lIdx-57 128 128 8128 debug_TIDL_init0: lIdx-58 128 128 8128 debug_TIDL_init0: lIdx-59 128 128 128 debug_TIDL_init0: lIdx-60 128 128 128 debug_TIDL_init0: lIdx-61 128 128 8128 debug_TIDL_init0: lIdx-62 128 128 8128 debug_TIDL_init0: lIdx-63 128 128 128 debug_TIDL_init0: lIdx-64 1500128 128 125128 debug_TIDL_init0: lIdx-65 128 128 125128 debug_TIDL_init0: lIdx-66 128 128 128 debug_TIDL_init0: lIdx-67 128 128 125128 debug_TIDL_init0: lIdx-68 128 128 125128 debug_TIDL_init0: lIdx-69 128 128 128 debug_TIDL_init0: lIdx-70 128 128 128 debug_TIDL_init0: lIdx-71 128 128 128 debug_TIDL_init0: lIdx-72 128 128 128 debug_TIDL_init0: lIdx-73 128 128 128 debug_TIDL_init0: lIdx-74 128 128 128 debug_TIDL_init0: lIdx-75 384128 128 128 debug_TIDL_init0: lIdx-76 128 128 128 debug_TIDL_init0: lIdx-77 128 128 128 debug_TIDL_init0: lIdx-78 128 128 128 debug_TIDL_init0: lIdx-79 384128 768 128 debug_TIDL_init0: lIdx-80 519296 128 128 debug_TIDL_init0: lIdx-81 519296 1024 128 debug_TIDL_init0: lIdx-82 384128 1024 128 debug_TIDL_init0: lIdx-83 384128 128 128 debug_TIDL_init0: lIdx-84 384128 1024 128 debug_TIDL_init0: lIdx-85 96128 448 128 debug_TIDL_init0: lIdx-86 96128 448 128 debug_TIDL_init0: lIdx-87 128 128 128 debug_TIDL_init0: lIdx-88 128 128 128 debug_TIDL_init0: lIdx-89 128 128 128 debug_TIDL_init0: lIdx-90 128 128 128 debug_TIDL_init0: lIdx-91 128 128 128 debug_TIDL_init0: lIdx-92 128 128 128 debug_TIDL_init0: lIdx-93 128 128 128 debug_TIDL_init0: lIdx-94 128 128 128 debug_TIDL_init0: lIdx-95 128 128 128 debug_TIDL_init0: lIdx-96 128 128 128 debug_TIDL_init0: lIdx-97 128 128 128 debug_TIDL_init0: lIdx-98 128 128 128 debug_TIDL_init0: lIdx-99 128 128 128 debug_TIDL_init0: lIdx-100 128 128 128 debug_TIDL_init0: lIdx-101 128 128 128 debug_TIDL_init0: lIdx-102 128 128 128 debug_TIDL_init0: lIdx-103 128 128 128 debug_TIDL_init0: lIdx-104 128 128 128 debug_TIDL_init0: lIdx-105 1500128 128 128 debug_TIDL_init0: lIdx-106 128 128 128 debug_TIDL_init0: lIdx-107 128 128 128 debug_TIDL_init0: lIdx-108 128 128 128 debug_TIDL_init0: lIdx-109 128 128 128 debug_TIDL_init0: lIdx-110 128 128 128 debug_TIDL_init0: lIdx-111 128 128 128 debug_TIDL_init0: lIdx-112 128 128 128 debug_TIDL_init0: lIdx-113 128 128 128 debug_TIDL_init0: lIdx-114 128 128 128 debug_TIDL_init0: lIdx-115 128 128 128 debug_TIDL_init0: lIdx-116 384128 128 128 debug_TIDL_init0: lIdx-117 128 128 128 debug_TIDL_init0: lIdx-118 128 128 128 debug_TIDL_init0: lIdx-119 128 128 128 debug_TIDL_init0: lIdx-120 384128 768 128 debug_TIDL_init0: lIdx-121 519296 128 128 debug_TIDL_init0: lIdx-122 384128 1024 128 debug_TIDL_init0: lIdx-123 519296 1024 128 debug_TIDL_init0: lIdx-124 128 128 128 debug_TIDL_init0: lIdx-125 1801856 128 128 debug_TIDL_init0: lIdx-126 128 128 128 debug_TIDL_init0: lIdx-127 6670976 128 128 debug_TIDL_init0: lIdx-128 6670976 1024 128 debug_TIDL_init0: lIdx-129 6670976 1024 128 debug_TIDL_init0: lIdx-130 6670976 1024 128 debug_TIDL_init0: lIdx-131 6144128 1024 128 debug_TIDL_init0: lIdx-132 1801856 1024 128 debug_TIDL_init0: lIdx-133 1536128 1024 128 debug_TIDL_init0: lIdx-134 3216128 1864 128 debug_TIDL_init0: lIdx-135 1536128 1024 128 debug_TIDL_init0: lIdx-136 24128 268 2128 debug_TIDL_init0: lIdx-137 24128 512 128 debug_TIDL_init0: lIdx-138 24128 128 128 debug_TIDL_init0: lIdx-139 24128 128 128 debug_TIDL_init0: lIdx-140 24128 128 128 debug_TIDL_init0: lIdx-141 24128 128 128 debug_TIDL_init0: lIdx-142 24128 128 128 debug_TIDL_init0: lIdx-143 28280 128 128 debug_TIDL_init0: lIdx-144 24128 128 128 debug_TIDL_init0: lIdx-145 24128 512 128 debug_TIDL_init0: lIdx-146 24128 128 128 debug_TIDL_init0: lIdx-147 24128 512 128 debug_TIDL_init0: lIdx-148 24128 512 128 debug_TIDL_init0: lIdx-149 24128 128 128 debug_TIDL_init0: lIdx-151 128 128 128 debug_TIDL_init0: lIdx-152 128 128 268128 debug_TIDL_init0: lIdx-153 128 128 128 debug_TIDL_init0: lIdx-154 128 128 128 debug_TIDL_init0: lIdx-155 128 128 268128 debug_TIDL_init0: lIdx-156 1608128 1060 134128 debug_TIDL_init0: lIdx-157 1608128 1060 134128 debug_TIDL_init0: lIdx-158 128 128 128 debug_TIDL_init0: lIdx-159 128 128 128 debug_TIDL_init0: lIdx-160 128 128 128 debug_TIDL_init0: lIdx-161 128 128 128 debug_TIDL_init0: lIdx-162 128 128 134128 debug_TIDL_init0: lIdx-163 128 128 134128 debug_TIDL_init0: lIdx-164 128 128 134128 debug_TIDL_init0: lIdx-165 128 128 134128 debug_TIDL_init0: lIdx-166 128 128 134128 debug_TIDL_init0: lIdx-167 128 128 128 debug_TIDL_init0: lIdx-168 128 128 128 debug_TIDL_init0: lIdx-169 128 128 128 debug_TIDL_init0: lIdx-172 128 128 128 debug_TIDL_init0: lIdx-173 128 128 128 debug_TIDL_init0: lIdx-174 128 128 128 debug_TIDL_init0: lIdx-175 128 128 128 debug_TIDL_init0: lIdx-176 128 128 128 debug_TIDL_init0: lIdx-177 128 65792 140 debug_TIDL_init0: lIdx-178 128 128 140 debug_TIDL_init0: lIdx-179 128 128 128 debug_TIDL_init0: lIdx-182 128 128 128 debug_TIDL_init0: lIdx-183 128 128 128 Freeing memory for user provided Net ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . ..In Transpose: perm - 0 1 3 2 4 5, pp - 1 In Transpose: indata width-50 height-20 #ch-134 dim2-1 dim1-1 batch-1 In Transpose: outdata width-50 height-20 #ch-1 dim2-134 dim1-1 batch-1 ****** in TOPK *********** Inside TopK: index-0, value-2 Inside TopK: index-1, value-2 Inside TopK: index-2, value-2 Inside TopK: index-3, value-2 Inside TopK: index-4, value-2 Inside TopK: index-5, value-2 Inside TopK: index-20, value-32 Inside TopK: index-149, value-288 Inside TopK: index-249, value-454 Inside TopK: index-500, value-18667 Inside TopK: index-659, value-52 Inside TopK: index-953, value-18603 Inside TopK: index-984, value-17725 debug_TopK_output: k-6, eltType-3 indexes - 500 953 984 249 149 659 values - 18667 18603 17725 454 288 52 debug_TIDL_refDataConvertVarOutType: will convert to long integer debug_TIDL_refDataConvertVarOutType: will convert to long integer T 5430.53 .... ..... ... dumping outputs 795 1x64x40x100 ele_size_in_bytes 4 607 1x1x1000x67 ele_size_in_bytes 4 514 1x1x1000x67 ele_size_in_bytes 4 seeds 1x1x6x1 ele_size_in_bytes 8 507 1x1x1x6 ele_size_in_bytes 8 .... ..... # 1 . ..In Transpose: perm - 0 1 3 2 4 5, pp - 1 In Transpose: indata width-50 height-20 #ch-134 dim2-1 dim1-1 batch-1 In Transpose: outdata width-50 height-20 #ch-1 dim2-134 dim1-1 batch-1 ****** in TOPK *********** Inside TopK: index-0, value-2 Inside TopK: index-1, value-2 Inside TopK: index-2, value-2 Inside TopK: index-3, value-2 Inside TopK: index-4, value-2 Inside TopK: index-5, value-2 Inside TopK: index-43, value-210 Inside TopK: index-550, value-17583 Inside TopK: index-764, value-91 Inside TopK: index-961, value-18295 Inside TopK: index-993, value-18089 debug_TopK_output: k-6, eltType-3 indexes - 961 993 550 43 764 0 values - 18295 18089 17583 210 91 2 debug_TIDL_refDataConvertVarOutType: will convert to long integer debug_TIDL_refDataConvertVarOutType: will convert to long integer T 5425.25 .... ..... ... dumping outputs 795 1x64x40x100 ele_size_in_bytes 4 607 1x1x1000x67 ele_size_in_bytes 4 514 1x1x1000x67 ele_size_in_bytes 4 seeds 1x1x6x1 ele_size_in_bytes 8 507 1x1x1x6 ele_size_in_bytes 8 .... ..... # 2 . ..In Transpose: perm - 0 1 3 2 4 5, pp - 1 In Transpose: indata width-50 height-20 #ch-134 dim2-1 dim1-1 batch-1 In Transpose: outdata width-50 height-20 #ch-1 dim2-134 dim1-1 batch-1 ****** in TOPK *********** Inside TopK: index-0, value-2 Inside TopK: index-1, value-2 Inside TopK: index-2, value-2 Inside TopK: index-3, value-2 Inside TopK: index-4, value-2 Inside TopK: index-5, value-2 Inside TopK: index-16, value-136 Inside TopK: index-18, value-200 Inside TopK: index-24, value-621 Inside TopK: index-550, value-19218 Inside TopK: index-960, value-18549 Inside TopK: index-992, value-18251 debug_TopK_output: k-6, eltType-3 indexes - 550 960 992 24 18 16 values - 19218 18549 18251 621 200 136 debug_TIDL_refDataConvertVarOutType: will convert to long integer debug_TIDL_refDataConvertVarOutType: will convert to long integer T 5426.52 .... ..... ... dumping outputs 795 1x64x40x100 ele_size_in_bytes 4 607 1x1x1000x67 ele_size_in_bytes 4 514 1x1x1000x67 ele_size_in_bytes 4 seeds 1x1x6x1 ele_size_in_bytes 8 507 1x1x1x6 ele_size_in_bytes 8 .... ..... ***************** Calibration iteration number 0 completed ************************ ***************** Calibration iteration number 1 started ************************ Empty prototxt path, running calibration ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ tidl_import_core.cpp 654 cd /home/deepanshu/EdgeAI/edgeai-tidl-tools/tidl_tools && ./PC_dsp_test_dl_algo.out s:/home/deepanshu/EdgeAI/edgeai-tidl-tools/model-artifacts/fnc_safety_fp32/tempDir/795514607501507_tidl_io_.qunat_stats_config.txt Processing config file #0 : /home/deepanshu/EdgeAI/edgeai-tidl-tools/model-artifacts/fnc_safety_fp32/tempDir/795514607501507_tidl_io_.qunat_stats_config.txt debug_TIDL_alloc: inside TIDL_alloc debug_TIDL_alloc0: status-0, ok-0 fail--1 debug_TIDL_alloc0: lIdx-1 mem-0 32128 0 lT-39 debug_TIDL_alloc0: lIdx-2 mem-0 32128 0 lT-39 debug_TIDL_alloc0: lIdx-3 mem-0 2128 0 lT-39 debug_TIDL_alloc0: lIdx-4 mem-0 2128 0 lT-39 debug_TIDL_alloc0: lIdx-5 mem-0 2128 0 lT-39 debug_TIDL_alloc0: lIdx-6 mem-0 2128 0 lT-39 debug_TIDL_alloc0: lIdx-7 mem-0 2128 0 lT-39 debug_TIDL_alloc0: lIdx-8 mem-0 2128 0 lT-39 debug_TIDL_alloc0: lIdx-9 mem-128 128 1575614 lT-29 debug_TIDL_alloc0: lIdx-10 mem-100397696 1024 8366592 lT-1 debug_TIDL_alloc0: lIdx-11 mem-25625216 128 2135552 lT-2 debug_TIDL_alloc0: lIdx-12 mem-25625216 1024 2135552 lT-1 debug_TIDL_alloc0: lIdx-13 mem-24576128 1024 2048128 lT-1 debug_TIDL_alloc0: lIdx-14 mem-25625216 128 128 lT-5 debug_TIDL_alloc0: lIdx-15 mem-25625216 1024 128 lT-1 debug_TIDL_alloc0: lIdx-16 mem-24576128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-17 mem-25625216 128 128 lT-5 debug_TIDL_alloc0: lIdx-18 mem-12288128 1792 1024128 lT-1 debug_TIDL_alloc0: lIdx-19 mem-13341824 1792 1111936 lT-1 debug_TIDL_alloc0: lIdx-20 mem-12288128 1792 1024128 lT-1 debug_TIDL_alloc0: lIdx-21 mem-13341824 128 128 lT-5 debug_TIDL_alloc0: lIdx-22 mem-13341824 1792 1111936 lT-1 debug_TIDL_alloc0: lIdx-23 mem-12288128 1792 128 lT-1 debug_TIDL_alloc0: lIdx-24 mem-13341824 128 128 lT-5 debug_TIDL_alloc0: lIdx-25 mem-6144128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-26 mem-6144128 3328 512128 lT-1 debug_TIDL_alloc0: lIdx-27 mem-7207040 3328 600704 lT-1 debug_TIDL_alloc0: lIdx-28 mem-6144128 3328 512128 lT-1 debug_TIDL_alloc0: lIdx-29 mem-7207040 128 128 lT-5 debug_TIDL_alloc0: lIdx-30 mem-7207040 3328 600704 lT-1 debug_TIDL_alloc0: lIdx-31 mem-6144128 3328 128 lT-1 debug_TIDL_alloc0: lIdx-32 mem-7207040 128 128 lT-5 debug_TIDL_alloc0: lIdx-33 mem-1536128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-34 mem-3072128 6400 256128 lT-1 debug_TIDL_alloc0: lIdx-35 mem-4153472 6400 346240 lT-1 debug_TIDL_alloc0: lIdx-36 mem-3072128 6400 256128 lT-1 debug_TIDL_alloc0: lIdx-37 mem-4153472 128 128 lT-5 debug_TIDL_alloc0: lIdx-38 mem-4153472 6400 346240 lT-1 debug_TIDL_alloc0: lIdx-39 mem-3072128 6400 128 lT-1 debug_TIDL_alloc0: lIdx-40 mem-4153472 128 128 lT-5 debug_TIDL_alloc0: lIdx-41 mem-384128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-42 mem-384128 128 128 lT-5 debug_TIDL_alloc0: lIdx-43 mem-384128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-44 mem-96128 448 8128 lT-1 debug_TIDL_alloc0: lIdx-45 mem-96128 448 8128 lT-1 debug_TIDL_alloc0: lIdx-46 mem-128 128 32128 lT-29 debug_TIDL_alloc0: lIdx-47 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-48 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-49 mem-128 128 32128 lT-38 debug_TIDL_alloc0: lIdx-50 mem-128 128 8128 lT-38 debug_TIDL_alloc0: lIdx-51 mem-128 128 8128 lT-38 debug_TIDL_alloc0: lIdx-52 mem-128 128 32128 lT-29 debug_TIDL_alloc0: lIdx-53 mem-128 128 8128 lT-29 debug_TIDL_alloc0: lIdx-54 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-55 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-56 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-57 mem-128 128 8128 lT-38 debug_TIDL_alloc0: lIdx-58 mem-128 128 8128 lT-29 debug_TIDL_alloc0: lIdx-59 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-60 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-61 mem-128 128 8128 lT-38 debug_TIDL_alloc0: lIdx-62 mem-128 128 8128 lT-29 debug_TIDL_alloc0: lIdx-63 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-64 mem-1500128 256 125128 lT-6 debug_TIDL_alloc0: lIdx-65 mem-128 128 125128 lT-29 debug_TIDL_alloc0: lIdx-66 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-67 mem-128 128 125128 lT-38 debug_TIDL_alloc0: lIdx-68 mem-128 128 125128 lT-29 debug_TIDL_alloc0: lIdx-69 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-70 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-71 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-72 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-73 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-74 mem-128 128 128 lT-7 debug_TIDL_alloc0: lIdx-75 mem-384128 256 128 lT-6 debug_TIDL_alloc0: lIdx-76 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-77 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-78 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-79 mem-384128 1152 128 lT-8 debug_TIDL_alloc0: lIdx-80 mem-519296 128 128 lT-5 debug_TIDL_alloc0: lIdx-81 mem-519296 1024 128 lT-1 debug_TIDL_alloc0: lIdx-82 mem-384128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-83 mem-384128 128 128 lT-5 debug_TIDL_alloc0: lIdx-84 mem-384128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-85 mem-96128 448 128 lT-1 debug_TIDL_alloc0: lIdx-86 mem-96128 448 128 lT-1 debug_TIDL_alloc0: lIdx-87 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-88 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-89 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-90 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-91 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-92 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-93 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-94 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-95 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-96 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-97 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-98 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-99 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-100 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-101 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-102 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-103 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-104 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-105 mem-1500128 256 128 lT-6 debug_TIDL_alloc0: lIdx-106 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-107 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-108 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-109 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-110 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-111 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-112 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-113 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-114 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-115 mem-128 128 128 lT-7 debug_TIDL_alloc0: lIdx-116 mem-384128 256 128 lT-6 debug_TIDL_alloc0: lIdx-117 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-118 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-119 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-120 mem-384128 1152 128 lT-8 debug_TIDL_alloc0: lIdx-121 mem-519296 128 128 lT-5 debug_TIDL_alloc0: lIdx-122 mem-384128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-123 mem-519296 1024 128 lT-1 debug_TIDL_alloc0: lIdx-124 mem-128 128 128 lT-21 debug_TIDL_alloc0: lIdx-125 mem-1801856 128 128 lT-5 debug_TIDL_alloc0: lIdx-126 mem-128 128 128 lT-21 debug_TIDL_alloc0: lIdx-127 mem-6670976 128 128 lT-5 debug_TIDL_alloc0: lIdx-128 mem-6670976 1024 128 lT-1 debug_TIDL_alloc0: lIdx-129 mem-6670976 1024 128 lT-1 debug_TIDL_alloc0: lIdx-130 mem-6670976 1024 128 lT-1 debug_TIDL_alloc0: lIdx-131 mem-6144128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-132 mem-1801856 1024 128 lT-1 debug_TIDL_alloc0: lIdx-133 mem-1536128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-134 mem-3216128 1864 128 lT-1 debug_TIDL_alloc0: lIdx-135 mem-1536128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-136 mem-24128 268 2128 lT-1 debug_TIDL_alloc0: lIdx-137 mem-24128 522 128 lT-8 debug_TIDL_alloc0: lIdx-138 mem-24128 128 128 lT-5 debug_TIDL_alloc0: lIdx-139 mem-24128 128 128 lT-5 debug_TIDL_alloc0: lIdx-140 mem-24128 128 128 lT-5 debug_TIDL_alloc0: lIdx-141 mem-24128 128 128 lT-5 debug_TIDL_alloc0: lIdx-142 mem-24128 128 128 lT-5 debug_TIDL_alloc0: lIdx-143 mem-28280 128 128 lT-5 debug_TIDL_alloc0: lIdx-144 mem-24128 128 128 lT-2 debug_TIDL_alloc0: lIdx-145 mem-24128 522 128 lT-8 debug_TIDL_alloc0: lIdx-146 mem-24128 128 128 lT-5 debug_TIDL_alloc0: lIdx-147 mem-24128 522 128 lT-8 debug_TIDL_alloc0: lIdx-148 mem-24128 522 128 lT-8 debug_TIDL_alloc0: lIdx-149 mem-24128 128 128 lT-5 debug_TIDL_alloc0: lIdx-151 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-152 mem-128 128 268128 lT-29 debug_TIDL_alloc0: lIdx-153 mem-128 128 128 lT-41 debug_TIDL_alloc0: lIdx-154 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-155 mem-128 128 268128 lT-38 debug_TIDL_alloc0: lIdx-156 mem-1608128 1060 134128 lT-1 debug_TIDL_alloc0: lIdx-157 mem-1608128 1060 134128 lT-1 debug_TIDL_alloc0: lIdx-158 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-159 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-160 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-161 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-162 mem-128 128 134128 lT-38 debug_TIDL_alloc0: lIdx-163 mem-128 128 134128 lT-38 debug_TIDL_alloc0: lIdx-164 mem-128 128 134128 lT-38 debug_TIDL_alloc0: lIdx-165 mem-128 128 134128 lT-38 debug_TIDL_alloc0: lIdx-166 mem-128 128 134128 lT-29 debug_TIDL_alloc0: lIdx-167 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-168 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-169 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-172 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-173 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-174 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-175 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-176 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-177 mem-128 65920 140 lT-43 debug_TIDL_alloc0: lIdx-178 mem-128 128 140 lT-38 debug_TIDL_alloc0: lIdx-179 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-182 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-183 mem-128 128 128 lT-29 debug_TIDL_init0: lIdx-1 0 32128 0 debug_TIDL_init0: lIdx-2 0 32128 0 debug_TIDL_init0: lIdx-3 0 2128 0 debug_TIDL_init0: lIdx-4 0 2128 0 debug_TIDL_init0: lIdx-5 0 2128 0 debug_TIDL_init0: lIdx-6 0 2128 0 debug_TIDL_init0: lIdx-7 0 2128 0 debug_TIDL_init0: lIdx-8 0 2128 0 debug_TIDL_init0: lIdx-9 128 128 1575614 debug_TIDL_init0: lIdx-10 100397696 1024 8366592 debug_TIDL_init0: lIdx-11 25625216 128 2135552 debug_TIDL_init0: lIdx-12 25625216 1024 2135552 debug_TIDL_init0: lIdx-13 24576128 1024 2048128 debug_TIDL_init0: lIdx-14 25625216 128 128 debug_TIDL_init0: lIdx-15 25625216 1024 128 debug_TIDL_init0: lIdx-16 24576128 1024 128 debug_TIDL_init0: lIdx-17 25625216 128 128 debug_TIDL_init0: lIdx-18 12288128 1792 1024128 debug_TIDL_init0: lIdx-19 13341824 1792 1111936 debug_TIDL_init0: lIdx-20 12288128 1792 1024128 debug_TIDL_init0: lIdx-21 13341824 128 128 debug_TIDL_init0: lIdx-22 13341824 1792 1111936 debug_TIDL_init0: lIdx-23 12288128 1792 128 debug_TIDL_init0: lIdx-24 13341824 128 128 debug_TIDL_init0: lIdx-25 6144128 1024 128 debug_TIDL_init0: lIdx-26 6144128 3328 512128 debug_TIDL_init0: lIdx-27 7207040 3328 600704 debug_TIDL_init0: lIdx-28 6144128 3328 512128 debug_TIDL_init0: lIdx-29 7207040 128 128 debug_TIDL_init0: lIdx-30 7207040 3328 600704 debug_TIDL_init0: lIdx-31 6144128 3328 128 debug_TIDL_init0: lIdx-32 7207040 128 128 debug_TIDL_init0: lIdx-33 1536128 1024 128 debug_TIDL_init0: lIdx-34 3072128 6400 256128 debug_TIDL_init0: lIdx-35 4153472 6400 346240 debug_TIDL_init0: lIdx-36 3072128 6400 256128 debug_TIDL_init0: lIdx-37 4153472 128 128 debug_TIDL_init0: lIdx-38 4153472 6400 346240 debug_TIDL_init0: lIdx-39 3072128 6400 128 debug_TIDL_init0: lIdx-40 4153472 128 128 debug_TIDL_init0: lIdx-41 384128 1024 128 debug_TIDL_init0: lIdx-42 384128 128 128 debug_TIDL_init0: lIdx-43 384128 1024 128 debug_TIDL_init0: lIdx-44 96128 448 8128 debug_TIDL_init0: lIdx-45 96128 448 8128 debug_TIDL_init0: lIdx-46 128 128 32128 debug_TIDL_init0: lIdx-47 128 128 128 debug_TIDL_init0: lIdx-48 128 128 128 debug_TIDL_init0: lIdx-49 128 128 32128 debug_TIDL_init0: lIdx-50 128 128 8128 debug_TIDL_init0: lIdx-51 128 128 8128 debug_TIDL_init0: lIdx-52 128 128 32128 debug_TIDL_init0: lIdx-53 128 128 8128 debug_TIDL_init0: lIdx-54 128 128 128 debug_TIDL_init0: lIdx-55 128 128 128 debug_TIDL_init0: lIdx-56 128 128 128 debug_TIDL_init0: lIdx-57 128 128 8128 debug_TIDL_init0: lIdx-58 128 128 8128 debug_TIDL_init0: lIdx-59 128 128 128 debug_TIDL_init0: lIdx-60 128 128 128 debug_TIDL_init0: lIdx-61 128 128 8128 debug_TIDL_init0: lIdx-62 128 128 8128 debug_TIDL_init0: lIdx-63 128 128 128 debug_TIDL_init0: lIdx-64 1500128 128 125128 debug_TIDL_init0: lIdx-65 128 128 125128 debug_TIDL_init0: lIdx-66 128 128 128 debug_TIDL_init0: lIdx-67 128 128 125128 debug_TIDL_init0: lIdx-68 128 128 125128 debug_TIDL_init0: lIdx-69 128 128 128 debug_TIDL_init0: lIdx-70 128 128 128 debug_TIDL_init0: lIdx-71 128 128 128 debug_TIDL_init0: lIdx-72 128 128 128 debug_TIDL_init0: lIdx-73 128 128 128 debug_TIDL_init0: lIdx-74 128 128 128 debug_TIDL_init0: lIdx-75 384128 128 128 debug_TIDL_init0: lIdx-76 128 128 128 debug_TIDL_init0: lIdx-77 128 128 128 debug_TIDL_init0: lIdx-78 128 128 128 debug_TIDL_init0: lIdx-79 384128 768 128 debug_TIDL_init0: lIdx-80 519296 128 128 debug_TIDL_init0: lIdx-81 519296 1024 128 debug_TIDL_init0: lIdx-82 384128 1024 128 debug_TIDL_init0: lIdx-83 384128 128 128 debug_TIDL_init0: lIdx-84 384128 1024 128 debug_TIDL_init0: lIdx-85 96128 448 128 debug_TIDL_init0: lIdx-86 96128 448 128 debug_TIDL_init0: lIdx-87 128 128 128 debug_TIDL_init0: lIdx-88 128 128 128 debug_TIDL_init0: lIdx-89 128 128 128 debug_TIDL_init0: lIdx-90 128 128 128 debug_TIDL_init0: lIdx-91 128 128 128 debug_TIDL_init0: lIdx-92 128 128 128 debug_TIDL_init0: lIdx-93 128 128 128 debug_TIDL_init0: lIdx-94 128 128 128 debug_TIDL_init0: lIdx-95 128 128 128 debug_TIDL_init0: lIdx-96 128 128 128 debug_TIDL_init0: lIdx-97 128 128 128 debug_TIDL_init0: lIdx-98 128 128 128 debug_TIDL_init0: lIdx-99 128 128 128 debug_TIDL_init0: lIdx-100 128 128 128 debug_TIDL_init0: lIdx-101 128 128 128 debug_TIDL_init0: lIdx-102 128 128 128 debug_TIDL_init0: lIdx-103 128 128 128 debug_TIDL_init0: lIdx-104 128 128 128 debug_TIDL_init0: lIdx-105 1500128 128 128 debug_TIDL_init0: lIdx-106 128 128 128 debug_TIDL_init0: lIdx-107 128 128 128 debug_TIDL_init0: lIdx-108 128 128 128 debug_TIDL_init0: lIdx-109 128 128 128 debug_TIDL_init0: lIdx-110 128 128 128 debug_TIDL_init0: lIdx-111 128 128 128 debug_TIDL_init0: lIdx-112 128 128 128 debug_TIDL_init0: lIdx-113 128 128 128 debug_TIDL_init0: lIdx-114 128 128 128 debug_TIDL_init0: lIdx-115 128 128 128 debug_TIDL_init0: lIdx-116 384128 128 128 debug_TIDL_init0: lIdx-117 128 128 128 debug_TIDL_init0: lIdx-118 128 128 128 debug_TIDL_init0: lIdx-119 128 128 128 debug_TIDL_init0: lIdx-120 384128 768 128 debug_TIDL_init0: lIdx-121 519296 128 128 debug_TIDL_init0: lIdx-122 384128 1024 128 debug_TIDL_init0: lIdx-123 519296 1024 128 debug_TIDL_init0: lIdx-124 128 128 128 debug_TIDL_init0: lIdx-125 1801856 128 128 debug_TIDL_init0: lIdx-126 128 128 128 debug_TIDL_init0: lIdx-127 6670976 128 128 debug_TIDL_init0: lIdx-128 6670976 1024 128 debug_TIDL_init0: lIdx-129 6670976 1024 128 debug_TIDL_init0: lIdx-130 6670976 1024 128 debug_TIDL_init0: lIdx-131 6144128 1024 128 debug_TIDL_init0: lIdx-132 1801856 1024 128 debug_TIDL_init0: lIdx-133 1536128 1024 128 debug_TIDL_init0: lIdx-134 3216128 1864 128 debug_TIDL_init0: lIdx-135 1536128 1024 128 debug_TIDL_init0: lIdx-136 24128 268 2128 debug_TIDL_init0: lIdx-137 24128 512 128 debug_TIDL_init0: lIdx-138 24128 128 128 debug_TIDL_init0: lIdx-139 24128 128 128 debug_TIDL_init0: lIdx-140 24128 128 128 debug_TIDL_init0: lIdx-141 24128 128 128 debug_TIDL_init0: lIdx-142 24128 128 128 debug_TIDL_init0: lIdx-143 28280 128 128 debug_TIDL_init0: lIdx-144 24128 128 128 debug_TIDL_init0: lIdx-145 24128 512 128 debug_TIDL_init0: lIdx-146 24128 128 128 debug_TIDL_init0: lIdx-147 24128 512 128 debug_TIDL_init0: lIdx-148 24128 512 128 debug_TIDL_init0: lIdx-149 24128 128 128 debug_TIDL_init0: lIdx-151 128 128 128 debug_TIDL_init0: lIdx-152 128 128 268128 debug_TIDL_init0: lIdx-153 128 128 128 debug_TIDL_init0: lIdx-154 128 128 128 debug_TIDL_init0: lIdx-155 128 128 268128 debug_TIDL_init0: lIdx-156 1608128 1060 134128 debug_TIDL_init0: lIdx-157 1608128 1060 134128 debug_TIDL_init0: lIdx-158 128 128 128 debug_TIDL_init0: lIdx-159 128 128 128 debug_TIDL_init0: lIdx-160 128 128 128 debug_TIDL_init0: lIdx-161 128 128 128 debug_TIDL_init0: lIdx-162 128 128 134128 debug_TIDL_init0: lIdx-163 128 128 134128 debug_TIDL_init0: lIdx-164 128 128 134128 debug_TIDL_init0: lIdx-165 128 128 134128 debug_TIDL_init0: lIdx-166 128 128 134128 debug_TIDL_init0: lIdx-167 128 128 128 debug_TIDL_init0: lIdx-168 128 128 128 debug_TIDL_init0: lIdx-169 128 128 128 debug_TIDL_init0: lIdx-172 128 128 128 debug_TIDL_init0: lIdx-173 128 128 128 debug_TIDL_init0: lIdx-174 128 128 128 debug_TIDL_init0: lIdx-175 128 128 128 debug_TIDL_init0: lIdx-176 128 128 128 debug_TIDL_init0: lIdx-177 128 65792 140 debug_TIDL_init0: lIdx-178 128 128 140 debug_TIDL_init0: lIdx-179 128 128 128 debug_TIDL_init0: lIdx-182 128 128 128 debug_TIDL_init0: lIdx-183 128 128 128 Freeing memory for user provided Net ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . ..In Transpose: perm - 0 1 3 2 4 5, pp - 1 In Transpose: indata width-50 height-20 #ch-134 dim2-1 dim1-1 batch-1 In Transpose: outdata width-50 height-20 #ch-1 dim2-134 dim1-1 batch-1 ****** in TOPK *********** Inside TopK: index-0, value-0 Inside TopK: index-1, value-0 Inside TopK: index-2, value-0 Inside TopK: index-3, value-0 Inside TopK: index-4, value-0 Inside TopK: index-5, value-0 debug_TopK_output: k-6, eltType-3 indexes - 0 1 2 3 4 5 values - 0 0 0 0 0 0 debug_TIDL_refDataConvertVarOutType: will convert to long integer debug_TIDL_refDataConvertVarOutType: will convert to long integer T 5462.09 .... ..... ... dumping outputs 795 1x64x40x100 ele_size_in_bytes 4 607 1x1x1000x67 ele_size_in_bytes 4 514 1x1x1000x67 ele_size_in_bytes 4 seeds 1x1x6x1 ele_size_in_bytes 8 507 1x1x1x6 ele_size_in_bytes 8 .... ..... # 1 . ..In Transpose: perm - 0 1 3 2 4 5, pp - 1 In Transpose: indata width-50 height-20 #ch-134 dim2-1 dim1-1 batch-1 In Transpose: outdata width-50 height-20 #ch-1 dim2-134 dim1-1 batch-1 ****** in TOPK *********** Inside TopK: index-0, value-0 Inside TopK: index-1, value-0 Inside TopK: index-2, value-0 Inside TopK: index-3, value-0 Inside TopK: index-4, value-0 Inside TopK: index-5, value-0 debug_TopK_output: k-6, eltType-3 indexes - 0 1 2 3 4 5 values - 0 0 0 0 0 0 debug_TIDL_refDataConvertVarOutType: will convert to long integer debug_TIDL_refDataConvertVarOutType: will convert to long integer T 5603.62 .... ..... ... dumping outputs 795 1x64x40x100 ele_size_in_bytes 4 607 1x1x1000x67 ele_size_in_bytes 4 514 1x1x1000x67 ele_size_in_bytes 4 seeds 1x1x6x1 ele_size_in_bytes 8 507 1x1x1x6 ele_size_in_bytes 8 .... ..... # 2 . ..In Transpose: perm - 0 1 3 2 4 5, pp - 1 In Transpose: indata width-50 height-20 #ch-134 dim2-1 dim1-1 batch-1 In Transpose: outdata width-50 height-20 #ch-1 dim2-134 dim1-1 batch-1 ****** in TOPK *********** Inside TopK: index-0, value-0 Inside TopK: index-1, value-0 Inside TopK: index-2, value-0 Inside TopK: index-3, value-0 Inside TopK: index-4, value-0 Inside TopK: index-5, value-0 debug_TopK_output: k-6, eltType-3 indexes - 0 1 2 3 4 5 values - 0 0 0 0 0 0 debug_TIDL_refDataConvertVarOutType: will convert to long integer debug_TIDL_refDataConvertVarOutType: will convert to long integer T 5516.04 .... ..... ... dumping outputs 795 1x64x40x100 ele_size_in_bytes 4 607 1x1x1000x67 ele_size_in_bytes 4 514 1x1x1000x67 ele_size_in_bytes 4 seeds 1x1x6x1 ele_size_in_bytes 8 507 1x1x1x6 ele_size_in_bytes 8 .... ..... ***************** Calibration iteration number 1 completed ************************ ***************** Calibration iteration number 2 started ************************ Empty prototxt path, running calibration ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ tidl_import_core.cpp 654 cd /home/deepanshu/EdgeAI/edgeai-tidl-tools/tidl_tools && ./PC_dsp_test_dl_algo.out s:/home/deepanshu/EdgeAI/edgeai-tidl-tools/model-artifacts/fnc_safety_fp32/tempDir/795514607501507_tidl_io_.qunat_stats_config.txt Processing config file #0 : /home/deepanshu/EdgeAI/edgeai-tidl-tools/model-artifacts/fnc_safety_fp32/tempDir/795514607501507_tidl_io_.qunat_stats_config.txt debug_TIDL_alloc: inside TIDL_alloc debug_TIDL_alloc0: status-0, ok-0 fail--1 debug_TIDL_alloc0: lIdx-1 mem-0 32128 0 lT-39 debug_TIDL_alloc0: lIdx-2 mem-0 32128 0 lT-39 debug_TIDL_alloc0: lIdx-3 mem-0 2128 0 lT-39 debug_TIDL_alloc0: lIdx-4 mem-0 2128 0 lT-39 debug_TIDL_alloc0: lIdx-5 mem-0 2128 0 lT-39 debug_TIDL_alloc0: lIdx-6 mem-0 2128 0 lT-39 debug_TIDL_alloc0: lIdx-7 mem-0 2128 0 lT-39 debug_TIDL_alloc0: lIdx-8 mem-0 2128 0 lT-39 debug_TIDL_alloc0: lIdx-9 mem-128 128 1575614 lT-29 debug_TIDL_alloc0: lIdx-10 mem-100397696 1024 8366592 lT-1 debug_TIDL_alloc0: lIdx-11 mem-25625216 128 2135552 lT-2 debug_TIDL_alloc0: lIdx-12 mem-25625216 1024 2135552 lT-1 debug_TIDL_alloc0: lIdx-13 mem-24576128 1024 2048128 lT-1 debug_TIDL_alloc0: lIdx-14 mem-25625216 128 128 lT-5 debug_TIDL_alloc0: lIdx-15 mem-25625216 1024 128 lT-1 debug_TIDL_alloc0: lIdx-16 mem-24576128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-17 mem-25625216 128 128 lT-5 debug_TIDL_alloc0: lIdx-18 mem-12288128 1792 1024128 lT-1 debug_TIDL_alloc0: lIdx-19 mem-13341824 1792 1111936 lT-1 debug_TIDL_alloc0: lIdx-20 mem-12288128 1792 1024128 lT-1 debug_TIDL_alloc0: lIdx-21 mem-13341824 128 128 lT-5 debug_TIDL_alloc0: lIdx-22 mem-13341824 1792 1111936 lT-1 debug_TIDL_alloc0: lIdx-23 mem-12288128 1792 128 lT-1 debug_TIDL_alloc0: lIdx-24 mem-13341824 128 128 lT-5 debug_TIDL_alloc0: lIdx-25 mem-6144128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-26 mem-6144128 3328 512128 lT-1 debug_TIDL_alloc0: lIdx-27 mem-7207040 3328 600704 lT-1 debug_TIDL_alloc0: lIdx-28 mem-6144128 3328 512128 lT-1 debug_TIDL_alloc0: lIdx-29 mem-7207040 128 128 lT-5 debug_TIDL_alloc0: lIdx-30 mem-7207040 3328 600704 lT-1 debug_TIDL_alloc0: lIdx-31 mem-6144128 3328 128 lT-1 debug_TIDL_alloc0: lIdx-32 mem-7207040 128 128 lT-5 debug_TIDL_alloc0: lIdx-33 mem-1536128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-34 mem-3072128 6400 256128 lT-1 debug_TIDL_alloc0: lIdx-35 mem-4153472 6400 346240 lT-1 debug_TIDL_alloc0: lIdx-36 mem-3072128 6400 256128 lT-1 debug_TIDL_alloc0: lIdx-37 mem-4153472 128 128 lT-5 debug_TIDL_alloc0: lIdx-38 mem-4153472 6400 346240 lT-1 debug_TIDL_alloc0: lIdx-39 mem-3072128 6400 128 lT-1 debug_TIDL_alloc0: lIdx-40 mem-4153472 128 128 lT-5 debug_TIDL_alloc0: lIdx-41 mem-384128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-42 mem-384128 128 128 lT-5 debug_TIDL_alloc0: lIdx-43 mem-384128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-44 mem-96128 448 8128 lT-1 debug_TIDL_alloc0: lIdx-45 mem-96128 448 8128 lT-1 debug_TIDL_alloc0: lIdx-46 mem-128 128 32128 lT-29 debug_TIDL_alloc0: lIdx-47 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-48 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-49 mem-128 128 32128 lT-38 debug_TIDL_alloc0: lIdx-50 mem-128 128 8128 lT-38 debug_TIDL_alloc0: lIdx-51 mem-128 128 8128 lT-38 debug_TIDL_alloc0: lIdx-52 mem-128 128 32128 lT-29 debug_TIDL_alloc0: lIdx-53 mem-128 128 8128 lT-29 debug_TIDL_alloc0: lIdx-54 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-55 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-56 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-57 mem-128 128 8128 lT-38 debug_TIDL_alloc0: lIdx-58 mem-128 128 8128 lT-29 debug_TIDL_alloc0: lIdx-59 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-60 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-61 mem-128 128 8128 lT-38 debug_TIDL_alloc0: lIdx-62 mem-128 128 8128 lT-29 debug_TIDL_alloc0: lIdx-63 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-64 mem-1500128 256 125128 lT-6 debug_TIDL_alloc0: lIdx-65 mem-128 128 125128 lT-29 debug_TIDL_alloc0: lIdx-66 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-67 mem-128 128 125128 lT-38 debug_TIDL_alloc0: lIdx-68 mem-128 128 125128 lT-29 debug_TIDL_alloc0: lIdx-69 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-70 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-71 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-72 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-73 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-74 mem-128 128 128 lT-7 debug_TIDL_alloc0: lIdx-75 mem-384128 256 128 lT-6 debug_TIDL_alloc0: lIdx-76 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-77 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-78 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-79 mem-384128 1152 128 lT-8 debug_TIDL_alloc0: lIdx-80 mem-519296 128 128 lT-5 debug_TIDL_alloc0: lIdx-81 mem-519296 1024 128 lT-1 debug_TIDL_alloc0: lIdx-82 mem-384128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-83 mem-384128 128 128 lT-5 debug_TIDL_alloc0: lIdx-84 mem-384128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-85 mem-96128 448 128 lT-1 debug_TIDL_alloc0: lIdx-86 mem-96128 448 128 lT-1 debug_TIDL_alloc0: lIdx-87 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-88 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-89 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-90 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-91 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-92 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-93 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-94 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-95 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-96 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-97 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-98 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-99 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-100 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-101 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-102 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-103 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-104 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-105 mem-1500128 256 128 lT-6 debug_TIDL_alloc0: lIdx-106 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-107 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-108 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-109 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-110 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-111 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-112 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-113 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-114 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-115 mem-128 128 128 lT-7 debug_TIDL_alloc0: lIdx-116 mem-384128 256 128 lT-6 debug_TIDL_alloc0: lIdx-117 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-118 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-119 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-120 mem-384128 1152 128 lT-8 debug_TIDL_alloc0: lIdx-121 mem-519296 128 128 lT-5 debug_TIDL_alloc0: lIdx-122 mem-384128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-123 mem-519296 1024 128 lT-1 debug_TIDL_alloc0: lIdx-124 mem-128 128 128 lT-21 debug_TIDL_alloc0: lIdx-125 mem-1801856 128 128 lT-5 debug_TIDL_alloc0: lIdx-126 mem-128 128 128 lT-21 debug_TIDL_alloc0: lIdx-127 mem-6670976 128 128 lT-5 debug_TIDL_alloc0: lIdx-128 mem-6670976 1024 128 lT-1 debug_TIDL_alloc0: lIdx-129 mem-6670976 1024 128 lT-1 debug_TIDL_alloc0: lIdx-130 mem-6670976 1024 128 lT-1 debug_TIDL_alloc0: lIdx-131 mem-6144128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-132 mem-1801856 1024 128 lT-1 debug_TIDL_alloc0: lIdx-133 mem-1536128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-134 mem-3216128 1864 128 lT-1 debug_TIDL_alloc0: lIdx-135 mem-1536128 1024 128 lT-1 debug_TIDL_alloc0: lIdx-136 mem-24128 268 2128 lT-1 debug_TIDL_alloc0: lIdx-137 mem-24128 522 128 lT-8 debug_TIDL_alloc0: lIdx-138 mem-24128 128 128 lT-5 debug_TIDL_alloc0: lIdx-139 mem-24128 128 128 lT-5 debug_TIDL_alloc0: lIdx-140 mem-24128 128 128 lT-5 debug_TIDL_alloc0: lIdx-141 mem-24128 128 128 lT-5 debug_TIDL_alloc0: lIdx-142 mem-24128 128 128 lT-5 debug_TIDL_alloc0: lIdx-143 mem-28280 128 128 lT-5 debug_TIDL_alloc0: lIdx-144 mem-24128 128 128 lT-2 debug_TIDL_alloc0: lIdx-145 mem-24128 522 128 lT-8 debug_TIDL_alloc0: lIdx-146 mem-24128 128 128 lT-5 debug_TIDL_alloc0: lIdx-147 mem-24128 522 128 lT-8 debug_TIDL_alloc0: lIdx-148 mem-24128 522 128 lT-8 debug_TIDL_alloc0: lIdx-149 mem-24128 128 128 lT-5 debug_TIDL_alloc0: lIdx-151 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-152 mem-128 128 268128 lT-29 debug_TIDL_alloc0: lIdx-153 mem-128 128 128 lT-41 debug_TIDL_alloc0: lIdx-154 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-155 mem-128 128 268128 lT-38 debug_TIDL_alloc0: lIdx-156 mem-1608128 1060 134128 lT-1 debug_TIDL_alloc0: lIdx-157 mem-1608128 1060 134128 lT-1 debug_TIDL_alloc0: lIdx-158 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-159 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-160 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-161 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-162 mem-128 128 134128 lT-38 debug_TIDL_alloc0: lIdx-163 mem-128 128 134128 lT-38 debug_TIDL_alloc0: lIdx-164 mem-128 128 134128 lT-38 debug_TIDL_alloc0: lIdx-165 mem-128 128 134128 lT-38 debug_TIDL_alloc0: lIdx-166 mem-128 128 134128 lT-29 debug_TIDL_alloc0: lIdx-167 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-168 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-169 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-172 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-173 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-174 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-175 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-176 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-177 mem-128 65920 140 lT-43 debug_TIDL_alloc0: lIdx-178 mem-128 128 140 lT-38 debug_TIDL_alloc0: lIdx-179 mem-128 128 128 lT-38 debug_TIDL_alloc0: lIdx-182 mem-128 128 128 lT-29 debug_TIDL_alloc0: lIdx-183 mem-128 128 128 lT-29 debug_TIDL_init0: lIdx-1 0 32128 0 debug_TIDL_init0: lIdx-2 0 32128 0 debug_TIDL_init0: lIdx-3 0 2128 0 debug_TIDL_init0: lIdx-4 0 2128 0 debug_TIDL_init0: lIdx-5 0 2128 0 debug_TIDL_init0: lIdx-6 0 2128 0 debug_TIDL_init0: lIdx-7 0 2128 0 debug_TIDL_init0: lIdx-8 0 2128 0 debug_TIDL_init0: lIdx-9 128 128 1575614 debug_TIDL_init0: lIdx-10 100397696 1024 8366592 debug_TIDL_init0: lIdx-11 25625216 128 2135552 debug_TIDL_init0: lIdx-12 25625216 1024 2135552 debug_TIDL_init0: lIdx-13 24576128 1024 2048128 debug_TIDL_init0: lIdx-14 25625216 128 128 debug_TIDL_init0: lIdx-15 25625216 1024 128 debug_TIDL_init0: lIdx-16 24576128 1024 128 debug_TIDL_init0: lIdx-17 25625216 128 128 debug_TIDL_init0: lIdx-18 12288128 1792 1024128 debug_TIDL_init0: lIdx-19 13341824 1792 1111936 debug_TIDL_init0: lIdx-20 12288128 1792 1024128 debug_TIDL_init0: lIdx-21 13341824 128 128 debug_TIDL_init0: lIdx-22 13341824 1792 1111936 debug_TIDL_init0: lIdx-23 12288128 1792 128 debug_TIDL_init0: lIdx-24 13341824 128 128 debug_TIDL_init0: lIdx-25 6144128 1024 128 debug_TIDL_init0: lIdx-26 6144128 3328 512128 debug_TIDL_init0: lIdx-27 7207040 3328 600704 debug_TIDL_init0: lIdx-28 6144128 3328 512128 debug_TIDL_init0: lIdx-29 7207040 128 128 debug_TIDL_init0: lIdx-30 7207040 3328 600704 debug_TIDL_init0: lIdx-31 6144128 3328 128 debug_TIDL_init0: lIdx-32 7207040 128 128 debug_TIDL_init0: lIdx-33 1536128 1024 128 debug_TIDL_init0: lIdx-34 3072128 6400 256128 debug_TIDL_init0: lIdx-35 4153472 6400 346240 debug_TIDL_init0: lIdx-36 3072128 6400 256128 debug_TIDL_init0: lIdx-37 4153472 128 128 debug_TIDL_init0: lIdx-38 4153472 6400 346240 debug_TIDL_init0: lIdx-39 3072128 6400 128 debug_TIDL_init0: lIdx-40 4153472 128 128 debug_TIDL_init0: lIdx-41 384128 1024 128 debug_TIDL_init0: lIdx-42 384128 128 128 debug_TIDL_init0: lIdx-43 384128 1024 128 debug_TIDL_init0: lIdx-44 96128 448 8128 debug_TIDL_init0: lIdx-45 96128 448 8128 debug_TIDL_init0: lIdx-46 128 128 32128 debug_TIDL_init0: lIdx-47 128 128 128 debug_TIDL_init0: lIdx-48 128 128 128 debug_TIDL_init0: lIdx-49 128 128 32128 debug_TIDL_init0: lIdx-50 128 128 8128 debug_TIDL_init0: lIdx-51 128 128 8128 debug_TIDL_init0: lIdx-52 128 128 32128 debug_TIDL_init0: lIdx-53 128 128 8128 debug_TIDL_init0: lIdx-54 128 128 128 debug_TIDL_init0: lIdx-55 128 128 128 debug_TIDL_init0: lIdx-56 128 128 128 debug_TIDL_init0: lIdx-57 128 128 8128 debug_TIDL_init0: lIdx-58 128 128 8128 debug_TIDL_init0: lIdx-59 128 128 128 debug_TIDL_init0: lIdx-60 128 128 128 debug_TIDL_init0: lIdx-61 128 128 8128 debug_TIDL_init0: lIdx-62 128 128 8128 debug_TIDL_init0: lIdx-63 128 128 128 debug_TIDL_init0: lIdx-64 1500128 128 125128 debug_TIDL_init0: lIdx-65 128 128 125128 debug_TIDL_init0: lIdx-66 128 128 128 debug_TIDL_init0: lIdx-67 128 128 125128 debug_TIDL_init0: lIdx-68 128 128 125128 debug_TIDL_init0: lIdx-69 128 128 128 debug_TIDL_init0: lIdx-70 128 128 128 debug_TIDL_init0: lIdx-71 128 128 128 debug_TIDL_init0: lIdx-72 128 128 128 debug_TIDL_init0: lIdx-73 128 128 128 debug_TIDL_init0: lIdx-74 128 128 128 debug_TIDL_init0: lIdx-75 384128 128 128 debug_TIDL_init0: lIdx-76 128 128 128 debug_TIDL_init0: lIdx-77 128 128 128 debug_TIDL_init0: lIdx-78 128 128 128 debug_TIDL_init0: lIdx-79 384128 768 128 debug_TIDL_init0: lIdx-80 519296 128 128 debug_TIDL_init0: lIdx-81 519296 1024 128 debug_TIDL_init0: lIdx-82 384128 1024 128 debug_TIDL_init0: lIdx-83 384128 128 128 debug_TIDL_init0: lIdx-84 384128 1024 128 debug_TIDL_init0: lIdx-85 96128 448 128 debug_TIDL_init0: lIdx-86 96128 448 128 debug_TIDL_init0: lIdx-87 128 128 128 debug_TIDL_init0: lIdx-88 128 128 128 debug_TIDL_init0: lIdx-89 128 128 128 debug_TIDL_init0: lIdx-90 128 128 128 debug_TIDL_init0: lIdx-91 128 128 128 debug_TIDL_init0: lIdx-92 128 128 128 debug_TIDL_init0: lIdx-93 128 128 128 debug_TIDL_init0: lIdx-94 128 128 128 debug_TIDL_init0: lIdx-95 128 128 128 debug_TIDL_init0: lIdx-96 128 128 128 debug_TIDL_init0: lIdx-97 128 128 128 debug_TIDL_init0: lIdx-98 128 128 128 debug_TIDL_init0: lIdx-99 128 128 128 debug_TIDL_init0: lIdx-100 128 128 128 debug_TIDL_init0: lIdx-101 128 128 128 debug_TIDL_init0: lIdx-102 128 128 128 debug_TIDL_init0: lIdx-103 128 128 128 debug_TIDL_init0: lIdx-104 128 128 128 debug_TIDL_init0: lIdx-105 1500128 128 128 debug_TIDL_init0: lIdx-106 128 128 128 debug_TIDL_init0: lIdx-107 128 128 128 debug_TIDL_init0: lIdx-108 128 128 128 debug_TIDL_init0: lIdx-109 128 128 128 debug_TIDL_init0: lIdx-110 128 128 128 debug_TIDL_init0: lIdx-111 128 128 128 debug_TIDL_init0: lIdx-112 128 128 128 debug_TIDL_init0: lIdx-113 128 128 128 debug_TIDL_init0: lIdx-114 128 128 128 debug_TIDL_init0: lIdx-115 128 128 128 debug_TIDL_init0: lIdx-116 384128 128 128 debug_TIDL_init0: lIdx-117 128 128 128 debug_TIDL_init0: lIdx-118 128 128 128 debug_TIDL_init0: lIdx-119 128 128 128 debug_TIDL_init0: lIdx-120 384128 768 128 debug_TIDL_init0: lIdx-121 519296 128 128 debug_TIDL_init0: lIdx-122 384128 1024 128 debug_TIDL_init0: lIdx-123 519296 1024 128 debug_TIDL_init0: lIdx-124 128 128 128 debug_TIDL_init0: lIdx-125 1801856 128 128 debug_TIDL_init0: lIdx-126 128 128 128 debug_TIDL_init0: lIdx-127 6670976 128 128 debug_TIDL_init0: lIdx-128 6670976 1024 128 debug_TIDL_init0: lIdx-129 6670976 1024 128 debug_TIDL_init0: lIdx-130 6670976 1024 128 debug_TIDL_init0: lIdx-131 6144128 1024 128 debug_TIDL_init0: lIdx-132 1801856 1024 128 debug_TIDL_init0: lIdx-133 1536128 1024 128 debug_TIDL_init0: lIdx-134 3216128 1864 128 debug_TIDL_init0: lIdx-135 1536128 1024 128 debug_TIDL_init0: lIdx-136 24128 268 2128 debug_TIDL_init0: lIdx-137 24128 512 128 debug_TIDL_init0: lIdx-138 24128 128 128 debug_TIDL_init0: lIdx-139 24128 128 128 debug_TIDL_init0: lIdx-140 24128 128 128 debug_TIDL_init0: lIdx-141 24128 128 128 debug_TIDL_init0: lIdx-142 24128 128 128 debug_TIDL_init0: lIdx-143 28280 128 128 debug_TIDL_init0: lIdx-144 24128 128 128 debug_TIDL_init0: lIdx-145 24128 512 128 debug_TIDL_init0: lIdx-146 24128 128 128 debug_TIDL_init0: lIdx-147 24128 512 128 debug_TIDL_init0: lIdx-148 24128 512 128 debug_TIDL_init0: lIdx-149 24128 128 128 debug_TIDL_init0: lIdx-151 128 128 128 debug_TIDL_init0: lIdx-152 128 128 268128 debug_TIDL_init0: lIdx-153 128 128 128 debug_TIDL_init0: lIdx-154 128 128 128 debug_TIDL_init0: lIdx-155 128 128 268128 debug_TIDL_init0: lIdx-156 1608128 1060 134128 debug_TIDL_init0: lIdx-157 1608128 1060 134128 debug_TIDL_init0: lIdx-158 128 128 128 debug_TIDL_init0: lIdx-159 128 128 128 debug_TIDL_init0: lIdx-160 128 128 128 debug_TIDL_init0: lIdx-161 128 128 128 debug_TIDL_init0: lIdx-162 128 128 134128 debug_TIDL_init0: lIdx-163 128 128 134128 debug_TIDL_init0: lIdx-164 128 128 134128 debug_TIDL_init0: lIdx-165 128 128 134128 debug_TIDL_init0: lIdx-166 128 128 134128 debug_TIDL_init0: lIdx-167 128 128 128 debug_TIDL_init0: lIdx-168 128 128 128 debug_TIDL_init0: lIdx-169 128 128 128 debug_TIDL_init0: lIdx-172 128 128 128 debug_TIDL_init0: lIdx-173 128 128 128 debug_TIDL_init0: lIdx-174 128 128 128 debug_TIDL_init0: lIdx-175 128 128 128 debug_TIDL_init0: lIdx-176 128 128 128 debug_TIDL_init0: lIdx-177 128 65792 140 debug_TIDL_init0: lIdx-178 128 128 140 debug_TIDL_init0: lIdx-179 128 128 128 debug_TIDL_init0: lIdx-182 128 128 128 debug_TIDL_init0: lIdx-183 128 128 128 Freeing memory for user provided Net ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . ..In Transpose: perm - 0 1 3 2 4 5, pp - 1 In Transpose: indata width-50 height-20 #ch-134 dim2-1 dim1-1 batch-1 In Transpose: outdata width-50 height-20 #ch-1 dim2-134 dim1-1 batch-1 ****** in TOPK *********** Inside TopK: index-0, value--1 Inside TopK: index-1, value--1 Inside TopK: index-2, value--1 Inside TopK: index-3, value--1 Inside TopK: index-4, value--1 Inside TopK: index-5, value--1 debug_TopK_output: k-6, eltType-3 indexes - 0 1 2 3 4 5 values - -1 -1 -1 -1 -1 -1 debug_TIDL_refDataConvertVarOutType: will convert to long integer debug_TIDL_refDataConvertVarOutType: will convert to long integer T 5432.56 .... ..... ... dumping outputs 795 1x64x40x100 ele_size_in_bytes 4 607 1x1x1000x67 ele_size_in_bytes 4 514 1x1x1000x67 ele_size_in_bytes 4 seeds 1x1x6x1 ele_size_in_bytes 8 507 1x1x1x6 ele_size_in_bytes 8 .... ..... # 1 . ..In Transpose: perm - 0 1 3 2 4 5, pp - 1 In Transpose: indata width-50 height-20 #ch-134 dim2-1 dim1-1 batch-1 In Transpose: outdata width-50 height-20 #ch-1 dim2-134 dim1-1 batch-1 ****** in TOPK *********** Inside TopK: index-0, value--1 Inside TopK: index-1, value--1 Inside TopK: index-2, value--1 Inside TopK: index-3, value--1 Inside TopK: index-4, value--1 Inside TopK: index-5, value--1 debug_TopK_output: k-6, eltType-3 indexes - 0 1 2 3 4 5 values - -1 -1 -1 -1 -1 -1 debug_TIDL_refDataConvertVarOutType: will convert to long integer debug_TIDL_refDataConvertVarOutType: will convert to long integer T 5493.20 .... ..... ... dumping outputs 795 1x64x40x100 ele_size_in_bytes 4 607 1x1x1000x67 ele_size_in_bytes 4 514 1x1x1000x67 ele_size_in_bytes 4 seeds 1x1x6x1 ele_size_in_bytes 8 507 1x1x1x6 ele_size_in_bytes 8 .... ..... # 2 . ..In Transpose: perm - 0 1 3 2 4 5, pp - 1 In Transpose: indata width-50 height-20 #ch-134 dim2-1 dim1-1 batch-1 In Transpose: outdata width-50 height-20 #ch-1 dim2-134 dim1-1 batch-1 ****** in TOPK *********** Inside TopK: index-0, value--1 Inside TopK: index-1, value--1 Inside TopK: index-2, value--1 Inside TopK: index-3, value--1 Inside TopK: index-4, value--1 Inside TopK: index-5, value--1 debug_TopK_output: k-6, eltType-3 indexes - 0 1 2 3 4 5 values - -1 -1 -1 -1 -1 -1 debug_TIDL_refDataConvertVarOutType: will convert to long integer debug_TIDL_refDataConvertVarOutType: will convert to long integer T 5505.48 .... ..... ... dumping outputs 795 1x64x40x100 ele_size_in_bytes 4 607 1x1x1000x67 ele_size_in_bytes 4 514 1x1x1000x67 ele_size_in_bytes 4 seeds 1x1x6x1 ele_size_in_bytes 8 507 1x1x1x6 ele_size_in_bytes 8 .... ..... ***************** Calibration iteration number 2 completed ************************ Empty prototxt path, running calibration 0 image : 1x3x320x800 1 : 1x64x10x25 2 : 1x64x10x25 3 : 1x1x20x50 4 : 1x1x20x50 5 : 1x1x20x50 6 : 1x1x20x50 7 : 1x1x20x50 8 : 1x1x20x50 9 : 1x3x320x800 10 Conv_0 : 1x64x160x400 11 MaxPool_2 : 1x64x80x200 12 Conv_3 : 1x64x80x200 13 Conv_5 : 1x64x80x200 14 Add_6 : 1x64x80x200 15 Conv_8 : 1x64x80x200 16 Conv_10 : 1x64x80x200 17 Add_11 : 1x64x80x200 18 Conv_16 : 1x128x40x100 19 Conv_13 : 1x128x40x100 20 Conv_15 : 1x128x40x100 21 Add_17 : 1x128x40x100 22 Conv_19 : 1x128x40x100 23 Conv_21 : 1x128x40x100 24 Add_22 : 1x128x40x100 25 Conv_140 : 1x64x40x100 26 Conv_27 : 1x256x20x50 27 Conv_24 : 1x256x20x50 28 Conv_26 : 1x256x20x50 29 Add_28 : 1x256x20x50 30 Conv_30 : 1x256x20x50 31 Conv_32 : 1x256x20x50 32 Add_33 : 1x256x20x50 33 Conv_141 : 1x64x20x50 34 Conv_38 : 1x512x10x25 35 Conv_35 : 1x512x10x25 36 Conv_37 : 1x512x10x25 37 Add_39 : 1x512x10x25 38 Conv_41 : 1x512x10x25 39 Conv_43 : 1x512x10x25 40 Add_44 : 1x512x10x25 41 Conv_46 : 1x64x10x25 42 Add_58 : 1x64x10x25 43 Conv_77 : 1x64x10x25 44 Conv_66 : 1x16x10x25 45 Conv_59 : 1x16x10x25 46 : 1x64x10x25 47 : 1x16x10x25 48 : 1x16x10x25 49 Reshape_82 : 1x1x64x250 50 Reshape_71 : 1x1x16x250 51 Reshape_64 : 1x1x16x250 52 : 1x1x64x250 53 : 1x1x16x250 54 : 1x1x16x250 55 : 1x1x16x250 56 : 1x1x16x250 57 : 1x250x1x16 58 : 1x250x1x16 59 : 1x250x1x16 60 : 1x250x1x16 61 Transpose_65 : 1x1x250x16 62 : 1x1x250x16 63 : 1x1x250x16 64 MatMul_72 : 1x1x250x250 65 : 1x1x250x250 66 : 1x1x250x250 67 : 1x250x1x250 68 : 1x250x1x250 69 : 1x250x1x250 70 : 1x250x1x250 71 : 1x1x250x250 72 : 1x1x250x250 73 : 1x1x250x250 74 Softmax_74 : 1x1x250x250 75 MatMul_83 : 1x1x64x250 76 : 1x1x64x250 77 Reshape_88 : 1x64x10x25 78 : 1x64x10x25 79 Mul_89 : 1x64x10x25 80 Add_90 : 1x64x10x25 81 Conv_91 : 1x64x10x25 82 Conv_93 : 1x64x10x25 83 Add_105 : 1x64x10x25 84 Conv_124 : 1x64x10x25 85 Conv_113 : 1x16x10x25 86 Conv_106 : 1x16x10x25 87 : 1x64x10x25 88 : 1x16x10x25 89 : 1x16x10x25 90 Reshape_129 : 1x1x64x250 91 Reshape_118 : 1x1x16x250 92 Reshape_111 : 1x1x16x250 93 : 1x1x64x250 94 : 1x1x16x250 95 : 1x1x16x250 96 : 1x1x16x250 97 : 1x1x16x250 98 : 1x250x1x16 99 : 1x250x1x16 100 : 1x250x1x16 101 : 1x250x1x16 102 Transpose_112 : 1x1x250x16 103 : 1x1x250x16 104 : 1x1x250x16 105 MatMul_119 : 1x1x250x250 106 : 1x1x250x250 107 : 1x1x250x250 108 : 1x250x1x250 109 : 1x250x1x250 110 : 1x250x1x250 111 : 1x250x1x250 112 : 1x1x250x250 113 : 1x1x250x250 114 : 1x1x250x250 115 Softmax_121 : 1x1x250x250 116 MatMul_130 : 1x1x64x250 117 : 1x1x64x250 118 Reshape_135 : 1x64x10x25 119 : 1x64x10x25 120 Mul_136 : 1x64x10x25 121 Add_137 : 1x64x10x25 122 Conv_138 : 1x64x10x25 123 Conv_142 : 1x64x10x25 124 Upsample_143 : 1x64x20x50 125 Add_144 : 1x64x20x50 126 Upsample_145 : 1x64x40x100 127 Add_146 : 1x64x40x100 128 Conv_147 : 1x64x40x100 129 Conv_185 : 1x64x40x100 130 Conv_187 : 1x64x40x100 131 Conv_189 : 1x64x40x100 132 Conv_148 : 1x64x20x50 133 Conv_155 : 1x64x20x50 134 Conv_157 : 1x134x20x50 135 Conv_152 : 1x64x20x50 136 Conv_154 : 1x1x20x50 137 Sigmoid_170 : 1x1x20x50 138 Add_172 : 1x1x20x50 139 Add_175 : 1x1x20x50 140 Mul_177 : 1x1x20x50 141 Add_179 : 1x1x20x50 142 Mul_182 : 1x1x20x50 143 Add_184 : 1x1x20x50 144 MaxPool_204 : 1x1x20x50 145 Mul_206 : 1x1x20x50 146 Add_207 : 1x1x20x50 147 Add_211 : 1x1x20x50 148 Mul_214 : 1x1x20x50 149 Mul_215 : 1x1x20x50 151 : 1x64x40x100 152 : 1x134x20x50 153 Transpose_196 : 1x1x20x50 154 : 1x1x20x50 155 Reshape_203 : 1x134x1x1000 156 Conv_228 : 1x67x1x1000 157 Conv_289 : 1x67x1x1000 158 : 1x67x1x1000 159 : 1x67x1x1000 160 : 1x67x1x1000 161 : 1x67x1x1000 162 : 1x1x1000x67 163 : 1x1x1000x67 164 Transpose_229 : 1x1000x1x67 165 Transpose_290 : 1x1000x1x67 166 : 1x1000x1x67 167 : 1x1000x1x67 168 Reshape_231 : 1x1x1000x67 169 Reshape_292 : 1x1x1000x67 172 : 1x1x1000x67 173 : 1x1x1000x67 174 : 1x1x20x50 175 Reshape_218 : 1x1x1x1000 176 : 1x1x1x1000 177 TopK_219 : 1x1x1x6 177 TopK_219 : 1x1x1x6 178 Reshape_221 : 1x1x6x1 179 Squeeze_224 : 1x1x1x6 182 : 1x1x6x1 183 : 1x1x1x6 ------------------ Network Compiler Traces ----------------------------- successful Memory allocation successful Workload Creation Rerunning network compiler ------------------ Network Compiler Traces ----------------------------- Invalid layer parameters for layer 137, 29 Error : Error Code = Segmentation fault (core dumped) SUGGESTION: [TIDL_BatchNormLayer] Mul_89 16 bits is not optimal in this release. SUGGESTION: [TIDL_BatchNormLayer] Mul_136 16 bits is not optimal in this release. INFORMATION: [TIDL_ResizeLayer] Upsample_143 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. INFORMATION: [TIDL_ResizeLayer] Upsample_145 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. SUGGESTION: [TIDL_BatchNormLayer] Mul_206 16 bits is not optimal in this release. SUGGESTION: [TIDL_BatchNormLayer] Add_211 16 bits is not optimal in this release. SUGGESTION: [TIDL_BatchNormLayer] Mul_214 16 bits is not optimal in this release. **************************************************** ** 7 WARNINGS 0 ERRORS ** **************************************************** [array([[[[[[ 5.8429313e-01, 5.8137351e-01, 6.0161245e-01, ..., 7.7918911e-01, 7.6146889e-01, 8.3987427e-01], [ 5.5357552e-01, 7.3137200e-01, 7.8970033e-01, ..., 8.0339038e-01, 7.9923862e-01, 7.3045230e-01], [ 6.2160945e-01, 1.1409656e+00, 1.2216612e+00, ..., 9.0128195e-01, 9.5692790e-01, 8.4235519e-01], ..., [-7.0889544e-01, -1.1139344e+00, -1.2381216e+00, ..., -6.9158846e-01, -3.5495824e-01, -8.0266736e-02], [-5.6974769e-01, -9.0380347e-01, -9.6869594e-01, ..., -4.8082736e-01, -1.8950458e-01, 1.0955110e-02], [-1.5459713e-02, -3.2005855e-01, -3.8543421e-01, ..., 2.8141786e-03, 1.1837547e-01, 3.4343490e-01]], [[ 2.1845236e+00, 1.0282898e+00, 1.7589425e+00, ..., 6.9715482e-01, 4.7512347e-01, 7.0547694e-01], [ 3.5629532e+00, 2.0513482e+00, 2.9890592e+00, ..., 1.8377534e+00, 1.3848813e+00, 1.5062071e+00], [ 2.0946176e+00, -5.7187349e-01, -3.9269710e-01, ..., -5.4641098e-01, -7.6983795e-02, 9.4557953e-01], ..., [ 3.1116779e+00, 1.1839546e+00, 1.3089232e+00, ..., -2.8635710e-01, 6.1638895e-02, 1.0357869e+00], [ 2.6723540e+00, 7.2361529e-01, 8.2815510e-01, ..., -7.0420638e-02, 2.4175154e-01, 1.2699234e+00], [ 2.0511680e+00, 7.2094399e-01, 7.0343798e-01, ..., -3.2699892e-01, -5.8602896e-02, 8.9274037e-01]], [[ 6.3930160e-01, 7.1791351e-01, 7.7189666e-01, ..., 2.7950069e-01, 6.0953099e-02, 3.8002811e-02], [ 1.8887080e-01, 1.4509840e-01, -1.2763078e-02, ..., -3.8047671e-02, -1.4560081e-01, -8.8423267e-02], [-5.0456870e-02, -2.4037702e-01, -3.9957604e-01, ..., -5.5109781e-01, -5.4906887e-01, -4.2871070e-01], ..., [ 8.0912000e-01, 3.3067027e-01, 3.6445373e-01, ..., -1.3332961e+00, -1.4273744e+00, -9.1538495e-01], [ 7.6688862e-01, 2.2216253e-01, 3.3895478e-01, ..., -1.1856099e+00, -1.2613846e+00, -8.1641400e-01], [ 5.7133180e-01, 1.0625559e-01, 2.9202482e-01, ..., -6.8526161e-01, -6.0077864e-01, -2.6179263e-01]], ..., [[ 1.5657558e+00, 1.2150850e+00, 1.5622789e+00, ..., 1.6741118e+00, 1.5905604e+00, 1.5199986e+00], [ 1.1998532e+00, 6.9341868e-01, 1.0055131e+00, ..., 1.0405719e+00, 1.3198696e+00, 1.6140919e+00], [ 1.1631986e+00, 3.3107004e-01, 5.2941525e-01, ..., 4.9203584e-01, 7.1676433e-01, 1.5516069e+00], ..., [ 1.1773806e+00, 2.8192866e-01, 1.6156311e-01, ..., 1.2171434e+00, 1.0622376e+00, 2.3700233e+00], [ 1.0499600e+00, 1.5696032e-01, 8.9321777e-02, ..., 9.6757913e-01, 8.5687512e-01, 2.1819227e+00], [ 8.8180715e-01, 2.4160975e-01, 2.2200467e-01, ..., 8.9714152e-01, 8.2368708e-01, 1.6691244e+00]], [[-6.8896972e-02, 2.3101429e-03, -8.0716044e-02, ..., 3.9448762e-01, 6.3722205e-01, 3.6976391e-03], [-1.6480042e-01, -9.8986216e-02, -2.2542390e-01, ..., 5.8549565e-01, 9.8245555e-01, -1.5042000e-01], [-6.1798647e-02, -6.4035706e-02, -6.8866372e-02, ..., 7.2889340e-01, 1.1626430e+00, 4.4376653e-02], ..., [-1.2043965e+00, -1.8115565e+00, -1.9308906e+00, ..., 1.0947831e+00, 1.4811252e+00, 1.9694971e-01], [-1.1092545e+00, -1.7008436e+00, -1.7770749e+00, ..., 9.1362083e-01, 1.2653601e+00, 2.0411122e-01], [-8.4763509e-01, -1.1242217e+00, -1.1228772e+00, ..., 7.5569421e-01, 8.9067465e-01, 2.1467447e-01]], [[ 3.4199128e-01, 6.8690521e-01, 1.3407186e-01, ..., 1.5803586e-01, 1.1042562e-01, 1.0269673e+00], [ 1.9273154e-02, 9.4717062e-01, 5.3737020e-01, ..., 6.3732630e-01, 5.8091265e-01, 1.3451629e+00], [ 2.3896532e-01, 1.0402517e+00, 7.1726930e-01, ..., 5.0005054e-01, 4.5847502e-01, 1.2232522e+00], ..., [ 4.9668148e-02, 1.1714108e+00, 6.8203312e-01, ..., -6.9958425e-01, -3.6890715e-01, 9.4677991e-01], [-5.5998527e-02, 7.1523505e-01, 2.9265437e-01, ..., -6.4995867e-01, -2.8534123e-01, 1.0912157e+00], [ 6.2122989e-01, 5.4857582e-01, 3.3666125e-01, ..., -5.0719869e-01, 7.6076671e-02, 9.8826659e-01]]]]]], dtype=float32), array([[[[[[961], [993], [550], [ 43], [764], [402]]]]]], dtype=int64), array([[[[[[-0.02738791, 0.03594083, 1.4777484 , ..., -1.3204159 , 0.0838058 , 1.5519203 ], [-0.05839041, 0.02115006, 1.6211818 , ..., -1.254875 , 0.16830909, 1.7292987 ], [-0.08049783, 0.02818689, 1.6700116 , ..., -1.1852341 , 0.25693095, 1.7874839 ], ..., [-0.00292106, 0.01356499, 0.7402741 , ..., -0.27228564, -0.04567659, 0.9349626 ], [-0.02622604, 0.02234557, 0.5444512 , ..., -0.2629285 , -0.21082354, 1.1448691 ], [-0.04030355, 0.0302201 , 0.4576242 , ..., -0.21990898, -0.29867202, 1.3306918 ]]]]]], dtype=float32), array([[[[[[-0.0176013 , 0.07332256, -0.8825849 , ..., 0.6103428 , 1.7997316 , -0.98356736], [-0.00605804, 0.03833637, -0.9483368 , ..., 1.5073001 , 1.5812664 , -0.76535 ], [-0.02709142, 0.09082706, -0.75069356, ..., 1.8835871 , 1.4147542 , -0.66575176], ..., [-0.00222679, 0.00660562, 0.38610876, ..., 1.5482444 , 1.7427728 , 0.06902499], [-0.01353629, 0.01476275, 0.13845617, ..., 1.5442007 , 1.6258283 , 0.02321265], [-0.05237656, 0.05411887, -0.07685801, ..., 1.570234 , 1.6639479 , -0.17476794]]]]]], dtype=float32), array([[[[[[961, 993, 550, 43, 764, 402]]]]]], dtype=int64)] ***************Running_Benchmark_Section ********** ***************Running_Inference Section ********** This is Lucid Model for image ../../../lucid/data_onnx/test_images/img0278.png [array([[[[[[ 5.09128094e-01, 4.23031718e-01, 4.75738019e-01, ..., 6.89531267e-01, 7.30610251e-01, 8.68140876e-01], [ 4.19388473e-01, 6.36482775e-01, 7.56725729e-01, ..., 1.20885158e+00, 1.09827268e+00, 9.23987925e-01], [ 5.04881084e-01, 1.02144527e+00, 1.14929879e+00, ..., 1.60033119e+00, 1.33913803e+00, 1.11429679e+00], ..., [-7.00375676e-01, -1.10146034e+00, -1.24865508e+00, ..., -4.46428597e-01, -9.22817215e-02, 4.29632626e-02], [-5.79901338e-01, -9.30738986e-01, -9.95222151e-01, ..., -2.95041144e-01, 3.33128087e-02, 1.25268772e-01], [-3.68251950e-02, -3.54814887e-01, -3.97921920e-01, ..., 4.08566147e-02, 2.19442859e-01, 3.79889578e-01]], [[ 2.31210542e+00, 1.18729794e+00, 2.00309134e+00, ..., 2.53741646e+00, 1.89485049e+00, 1.28356874e+00], [ 3.55687213e+00, 1.84065807e+00, 2.64112186e+00, ..., 3.19053602e+00, 2.30480909e+00, 1.78742087e+00], [ 2.45138025e+00, -2.28725612e-01, -1.35295689e-01, ..., 3.41135003e-02, 2.84141988e-01, 1.09544694e+00], ..., [ 3.03204346e+00, 1.13210607e+00, 1.28839386e+00, ..., -1.89715236e-01, 1.42379209e-01, 1.01124001e+00], [ 2.63510990e+00, 7.60541439e-01, 9.53691483e-01, ..., 1.18876785e-01, 3.35508198e-01, 1.15446639e+00], [ 2.04412389e+00, 7.45531499e-01, 7.87996292e-01, ..., -1.56137809e-01, 5.59094436e-02, 8.36223900e-01]], [[ 6.93697751e-01, 7.61834145e-01, 8.48613203e-01, ..., 8.94719541e-01, 5.16377985e-01, 2.66457379e-01], [ 3.09692770e-01, 2.13464275e-01, 3.64078209e-02, ..., 2.18277171e-01, -3.87639217e-02, -1.19198114e-01], [ 2.20490634e-01, 2.66462769e-02, -2.01059669e-01, ..., -5.20874381e-01, -6.01824760e-01, -4.61793959e-01], ..., [ 7.92948127e-01, 2.45629579e-01, 3.04913163e-01, ..., -1.17835736e+00, -1.29880357e+00, -8.41568649e-01], [ 7.69268692e-01, 1.68566748e-01, 2.87768751e-01, ..., -1.12445819e+00, -1.21444941e+00, -7.64395654e-01], [ 6.00817442e-01, 1.04060411e-01, 2.64632702e-01, ..., -6.70343637e-01, -6.01100802e-01, -2.65236467e-01]], ..., [[ 1.49357080e+00, 1.06666136e+00, 1.46532679e+00, ..., 1.86876380e+00, 1.67987347e+00, 1.63424420e+00], [ 1.10802221e+00, 7.16569185e-01, 1.12193227e+00, ..., 1.38819039e+00, 1.56729674e+00, 1.89267850e+00], [ 1.07856512e+00, 2.09265217e-01, 4.66174871e-01, ..., 6.99809134e-01, 7.42723703e-01, 1.50025916e+00], ..., [ 1.21165109e+00, 3.27838123e-01, 1.81313783e-01, ..., 1.30985439e+00, 1.04963231e+00, 2.28878021e+00], [ 1.07098842e+00, 2.01493531e-01, 1.21075369e-01, ..., 1.04237390e+00, 7.61269689e-01, 2.05284429e+00], [ 8.74509692e-01, 2.60938793e-01, 2.42751271e-01, ..., 1.07305598e+00, 9.07505631e-01, 1.69754994e+00]], [[-5.62967546e-02, -4.86427434e-02, -1.50778159e-01, ..., -1.85125582e-02, 2.55781054e-01, -2.35809341e-01], [-1.98358789e-01, -2.41529569e-01, -3.60275686e-01, ..., 1.41445488e-01, 5.70958614e-01, -4.08237189e-01], [-2.75825500e-01, -3.04622382e-01, -3.03579390e-01, ..., 2.65479714e-01, 7.83528090e-01, -2.42032513e-01], ..., [-1.23195171e+00, -1.86259115e+00, -1.99138141e+00, ..., 1.06618369e+00, 1.50572717e+00, 1.17199309e-01], [-1.12343919e+00, -1.75684381e+00, -1.85917163e+00, ..., 9.20194805e-01, 1.32029235e+00, 1.56263396e-01], [-8.57059777e-01, -1.14683104e+00, -1.11975205e+00, ..., 7.46331334e-01, 9.18752551e-01, 1.79251388e-01]], [[ 3.76743883e-01, 8.09569538e-01, 2.75532752e-01, ..., -3.14076006e-01, -4.39182103e-01, 6.22837007e-01], [ 1.90843612e-01, 1.21870720e+00, 8.78780842e-01, ..., 4.35706049e-01, 3.68555665e-01, 1.16538846e+00], [ 2.44144559e-01, 1.21741390e+00, 7.50397980e-01, ..., 4.46384549e-01, 3.35953027e-01, 1.06290555e+00], ..., [-6.60270452e-05, 1.04721916e+00, 6.35738611e-01, ..., -2.83168405e-01, -5.58742881e-02, 1.04771626e+00], [-9.27070454e-02, 6.52410448e-01, 2.83569813e-01, ..., -3.44742328e-01, 2.03860998e-02, 1.14701784e+00], [ 6.07244492e-01, 5.58644474e-01, 3.60400528e-01, ..., -2.00843543e-01, 3.67345095e-01, 1.13722885e+00]]]]]], dtype=float32), array([[[[[[550], [960], [992], [ 24], [ 18], [ 16]]]]]], dtype=int64), array([[[[[[-0.03194776, 0.03781539, 1.3086189 , ..., -1.3272467 , 0.14181273, 1.5036492 ], [-0.05784696, 0.00850305, 1.4623718 , ..., -1.3543577 , 0.2364052 , 1.6983721 ], [-0.08596016, 0.01147478, 1.537845 , ..., -1.2552482 , 0.28741735, 1.7824564 ], ..., [-0.0280683 , 0.02284336, 0.57390124, ..., -0.26675215, -0.21267752, 1.2012933 ], [-0.04780266, 0.04076076, 0.32827792, ..., -0.24838217, -0.35564172, 1.370935 ], [-0.04670017, 0.03980378, 0.33737648, ..., -0.20547625, -0.35832396, 1.4253457 ]]]]]], dtype=float32), array([[[[[[-0.03064575, 0.08202642, -0.91118526, ..., 0.7057067 , 1.5576305 , -0.9866921 ], [-0.00296133, 0.062828 , -0.9802314 , ..., 1.3920531 , 1.4030303 , -0.76904464], [-0.00540492, 0.1168592 , -0.80477464, ..., 1.624378 , 1.3536689 , -0.63594353], ..., [-0.03398703, 0.03311485, 0.14378148, ..., 1.4923049 , 1.652759 , -0.11111261], [-0.02990801, 0.03252907, -0.10739341, ..., 1.6054697 , 1.6222268 , -0.06331243], [-0.04502148, 0.06027184, -0.22559503, ..., 1.7513703 , 1.6881434 , -0.26510417]]]]]], dtype=float32), array([[[[[[550, 960, 992, 24, 18, 16]]]]]], dtype=int64)] ***************Running_Benchmark_Section ********** Completed_Model : 1, Name : fnc_safety_fp32 , Total time : 37779.79, Offload Time : 9738.85 , DDR RW MBs : 0, Output File : py_out_fnc_safety_fp32_img0278.png In TIDL_runtimesPostProcessNet 4 ************ in TIDL_subgraphRtDelete ************ MEM: Deinit ... !!! MEM: Alloc's: 30 alloc's of 345922161 bytes MEM: Free's : 30 free's of 345922161 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!