16282.93> =====================DSS clock script===================
16282.93> Dumps internal clocks and muxes of DSS
16282.93> 
16283.01> CTRL_CORE_DSS_PLL_CONTROL (0x4a002538) = 0x000002A6
16283.02> video1 PLL :  Enabled
16283.02> video2 PLL :  Disabled
16283.02> HDMI   PLL :  Disabled
16283.02> DSI1_A_CLK mux : DPLL Video1
16283.02> DSI1_B_CLK mux : DPLL video2
16283.02> DSI1_C_CLK mux : DPLL Video2
16283.02> 
16283.02> DSS_CTRL (0x58000040) = 0x00010001
16283.02>  2: LCD1 clk switch :  DSI1_A_CLK
16283.02>  3: LCD2 clk switch :  DSS clk
16283.02> 10: LCD3 clk switch :  DSS clk
16283.02>  1: func clk switch :  DSS clk
16283.02> 13: DPI1 output     :  LCD1
16283.04> 
16283.08> ========================================================
16283.08> Register dump for DPLL video1
16283.08> |----------------------------|
16283.08> | Address (hex) | Data (hex) |
16283.08> |----------------------------|
16283.10> | 0x58004300    | 0x00000018 |
16283.10> | 0x58004304    | 0x00002283 |
16283.10> | 0x58004308    | 0x00000000 |
16283.10> | 0x5800430C    | 0x00601E00 |
16283.10> | 0x58004310    | 0x00616008 |
16283.10> | 0x58004314    | 0x00000000 |
16283.10> | 0x58004318    | 0x00000000 |
16283.10> | 0x5800431C    | 0x00000000 |
16283.10> | 0x58004320    | 0x00000000 |
16283.10> |----------------------------|
16283.10> 
16283.10> Details for DPLL video1
16283.10> PLL status  :  Locked
16283.10> M4 hsdiv(1) :  Active
16283.12> M5 hsdiv(2) :  inactive
16283.12> M6 hsdiv(3) :  inactive
16283.12> M7 hsdiv(4) :  inactive
16283.12> 
16283.12> PLL_REGM =  15
16283.12> PLL_REGN =  0
16283.18> M4 DIV   =  3
16283.19> M6 DIV   =  0
16283.19> M7 DIV   =  0
16283.19> 
16283.19> Clock calculations (DPLL video1)
16283.19> sysclk = 20000000
16283.19> DCO clk = sysclk * 2 * REGM / (REGN + 1) = 600000000
16283.19> M4clk (clkcout1) = DCO clk / (M4 DIV + 1) = 150000000
16283.19> M6clk (clkcout1) = DCO clk / (M6 DIV + 1) = 0
16283.21> M7clk (clkcout1) = DCO clk / (M7 DIV + 1) = 0
16283.21> 
16283.21> ========================================================
16283.21> Clock O/P of MUXes
16283.21> Error: I2C Read failed
16283.21> Error: I2C Read failed
16283.21> Error: I2C Read failed
16283.21> omapconf: powerdm_deinit(): cpu not supported!!!
16283.21> omapconf: clockdm_deinit(): cpu not supported!!!
16283.21> DSI1_A_CLK :  150000000
16283.21> DSI1_B_CLK :  0
16283.21> DSI1_C_CLK :  0
16283.21> 
16283.22>  2: LCD1 clk :  150000000
16283.24>  3: LCD2 clk :  192000000
16283.24> 10: LCD3 clk :  192000000
16283.24>  1: func clk :  192000000
16283.24> 
16283.32> LCD1 logic clk(/ 1 ) :  150000000  pix clk(/ 2 ) :  75000000
16283.32> LCD2 logic clk(/ 4 ) :  48000000  pix clk(/ 1 ) :  48000000
16283.33> LCD3 logic clk(/ 4 ) :  48000000  pix clk(/ 1 ) :  48000000