commit 2ca6387bbf6d9ca548e9232174361cff9d226da9
Author: Nikhil Dasan <n-dasan@ti.com>
Date:   Fri Dec 13 11:11:30 2024 +0530

    2GB config
    
    Signed-off-by: Nikhil Dasan <n-dasan@ti.com>

diff --git a/platform/j784s4/rtos/c7x_1/main.c b/platform/j784s4/rtos/c7x_1/main.c
index 8d1cf3c..82ecf2f 100755
--- a/platform/j784s4/rtos/c7x_1/main.c
+++ b/platform/j784s4/rtos/c7x_1/main.c
@@ -256,167 +256,170 @@ void appMmuMap(Bool is_secure)
         goto mmu_exit;
     }
 
-    /* DDR Local heap non cacheable */
-    retVal = Mmu_map(DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_ADDR, DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    /*-------------------------------------------------------*/
+    /* Cacheable region memory attributes                     */
+    /*-------------------------------------------------------*/
+
+    attrs.attrIndx = Mmu_AttrIndx_MAIR7;
+
+    retVal = Mmu_map(0x80000000U, 0x80000000U, 0x20000000U, &attrs, is_secure); /* DRR - Marking DDR region as cacheable */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_1_2_LOCAL_HEAP_NON_CACHEABLE_ADDR, DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(0xA0000000U, 0xA0000000U, 0x20000000U, &attrs, is_secure); /* DRR - Marking DDR region as cacheable */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_1_3_LOCAL_HEAP_NON_CACHEABLE_ADDR, DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(0x70000000U, 0x70000000U, 0x00800000U, &attrs, is_secure); /* MSMC - 8MB */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_1_4_LOCAL_HEAP_NON_CACHEABLE_ADDR, DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(0x41C00000U, 0x41C00000U, 0x00100000U, &attrs, is_secure); /* OCMC - 1MB */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
-    
-    /* DDR Scratch non cacheable */
-    retVal = Mmu_map(DDR_C7X_1_SCRATCH_NON_CACHEABLE_ADDR, DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_1_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+
+    /*The region mapped by the MMU is intentionally set to 2MB for L2 SRAM since
+      page sizes are a function of the region size and having smaller page sizes
+      negatively affects the performance of L2 SRAM as the table walks with the
+      translation table in DDR are expensive, especially in context of high-
+      throughput, low-latency memory like L2 SRAM*/
+    retVal = Mmu_map(L2RAM_C7x_1_ADDR, L2RAM_C7x_1_ADDR, 0x00200000, &attrs, is_secure); /* L2 sram 448KB   */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_1_2_SCRATCH_NON_CACHEABLE_ADDR, DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_2_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7x_1_DTS_ADDR, DDR_C7x_1_DTS_ADDR, DDR_C7x_1_DTS_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_1_3_SCRATCH_NON_CACHEABLE_ADDR, DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_3_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    /* DDR Local heap */
+    retVal = Mmu_map(DDR_C7X_1_LOCAL_HEAP_ADDR, DDR_C7X_1_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_1_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_1_4_SCRATCH_NON_CACHEABLE_ADDR, DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_4_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_2_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_2_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_2_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    /*-------------------------------------------------------*/
-    /* Cacheable region memory attributes                     */
-    /*-------------------------------------------------------*/
-
-    attrs.attrIndx = Mmu_AttrIndx_MAIR7;
-
-    retVal = Mmu_map(0x80000000U, 0x80000000U, 0x20000000U, &attrs, is_secure); /* DRR - Marking DDR region as cacheable */
+    retVal = Mmu_map(DDR_C7X_3_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_3_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_3_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(0xA0000000U, 0xA0000000U, 0x20000000U, &attrs, is_secure); /* DRR - Marking DDR region as cacheable */
+    retVal = Mmu_map(DDR_C7X_4_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_4_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_4_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(0x70000000U, 0x70000000U, 0x00800000U, &attrs, is_secure); /* MSMC - 8MB */
+
+    /* DDR scratch */
+    retVal = Mmu_map(DDR_C7X_1_SCRATCH_ADDR, DDR_C7X_1_SCRATCH_PHYS_ADDR, DDR_C7X_1_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(0x41C00000U, 0x41C00000U, 0x00100000U, &attrs, is_secure); /* OCMC - 1MB */
+    retVal = Mmu_map(DDR_C7X_2_SCRATCH_PHYS_ADDR, DDR_C7X_2_SCRATCH_PHYS_ADDR, DDR_C7X_2_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    /*The region mapped by the MMU is intentionally set to 2MB for L2 SRAM since
-      page sizes are a function of the region size and having smaller page sizes
-      negatively affects the performance of L2 SRAM as the table walks with the
-      translation table in DDR are expensive, especially in context of high-
-      throughput, low-latency memory like L2 SRAM*/
-    retVal = Mmu_map(L2RAM_C7x_1_ADDR, L2RAM_C7x_1_ADDR, 0x00200000, &attrs, is_secure); /* L2 sram 448KB   */
+    retVal = Mmu_map(DDR_C7X_3_SCRATCH_PHYS_ADDR, DDR_C7X_3_SCRATCH_PHYS_ADDR, DDR_C7X_3_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7x_1_DTS_ADDR, DDR_C7x_1_DTS_ADDR, DDR_C7x_1_DTS_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_4_SCRATCH_PHYS_ADDR, DDR_C7X_4_SCRATCH_PHYS_ADDR, DDR_C7X_4_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    /* DDR Local heap */
-    retVal = Mmu_map(DDR_C7X_1_LOCAL_HEAP_ADDR, DDR_C7X_1_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_1_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
+    /* DDR Shared mem */
+    retVal = Mmu_map(DDR_SHARED_MEM_ADDR, DDR_SHARED_MEM_PHYS_ADDR, DDR_SHARED_MEM_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_1_2_LOCAL_HEAP_ADDR, DDR_C7X_2_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_2_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(MSMC_C7x_1_ADDR, MSMC_C7x_1_ADDR, MSMC_C7x_1_SIZE, &attrs, is_secure); /* Local MSMC   */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_1_3_LOCAL_HEAP_ADDR, DDR_C7X_3_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_3_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
+    attrs.attrIndx = Mmu_AttrIndx_MAIR0;
+
+    /* DDR Local heap non cacheable */
+    retVal = Mmu_map(DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_ADDR, DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_1_4_LOCAL_HEAP_ADDR, DDR_C7X_4_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_4_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-
-    /* DDR scratch */
-    retVal = Mmu_map(DDR_C7X_1_SCRATCH_ADDR, DDR_C7X_1_SCRATCH_PHYS_ADDR, DDR_C7X_1_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_1_2_SCRATCH_ADDR, DDR_C7X_2_SCRATCH_PHYS_ADDR, DDR_C7X_2_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
-
-    retVal = Mmu_map(DDR_C7X_1_3_SCRATCH_ADDR, DDR_C7X_3_SCRATCH_PHYS_ADDR, DDR_C7X_3_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
+    
+    /* DDR Scratch non cacheable */
+    retVal = Mmu_map(DDR_C7X_1_SCRATCH_NON_CACHEABLE_ADDR, DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_1_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_1_4_SCRATCH_ADDR, DDR_C7X_4_SCRATCH_PHYS_ADDR, DDR_C7X_4_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_2_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    /* DDR Shared mem */
-    retVal = Mmu_map(DDR_SHARED_MEM_ADDR, DDR_SHARED_MEM_PHYS_ADDR, DDR_SHARED_MEM_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_3_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(MSMC_C7x_1_ADDR, MSMC_C7x_1_ADDR, MSMC_C7x_1_SIZE, &attrs, is_secure); /* Local MSMC   */
+    retVal = Mmu_map(DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_4_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
+
     attrs.attrIndx = Mmu_AttrIndx_MAIR4;
 
     retVal = Mmu_map(APP_LOG_MEM_ADDR, APP_LOG_MEM_ADDR, APP_LOG_MEM_SIZE, &attrs, is_secure);
@@ -493,32 +496,6 @@ void InitMmu(void)
     appCacheInit();
 }
 
-/** Description : This function converts a virtual memory region address to physical memory region address given the base addresses of both memory regions 
- *  which are mapped using MMU in appMmuMap
- *  Arguments:
- *      - virtAddr : Virtual pointer
- *      - virtBase   : Base address of virtual memory space
- *      - physBase   : Base address of physical memory space
- *      - size       : Size of memory space
- *      - phyAddr :  Physical pointer to be returned after conversion if virtAddr belongs to memory space with base address virtBase
- *                     else, phyAddr is returned as it is without any modification
- */
-static void convertVirt2Phys(uint64_t virtAddr, uint64_t virtBase, uint64_t physBase, uint64_t size, uint64_t * phyAddr)
-{
-    if ( ((uint64_t)virtAddr >= virtBase) &&
-         ((uint64_t)virtAddr < (virtBase + size)) )
-    {
-        if (virtBase >= physBase)
-        {
-            *phyAddr = (uint64_t)virtAddr - (virtBase - physBase);
-        }
-        else
-        {
-            *phyAddr = (uint64_t)virtAddr + (physBase - virtBase);
-        }
-    }
-}
-
 uint64_t appTarget2SharedConversion(const uint64_t virtAddr)
 {
     uint64_t phyAddr = (uint64_t)virtAddr; /* Default : Return virtAddr without any modification */
@@ -536,48 +513,6 @@ uint64_t appTarget2SharedConversion(const uint64_t virtAddr)
             phyAddr = (uint64_t)virtAddr - (DDR_SHARED_MEM_ADDR - DDR_SHARED_MEM_PHYS_ADDR);
         }
     }
-    else
-    {
-        /* Below code converts c7x_1 virtual addresses of all cores to C7x DDR physical addresses 
-           If virtAddr does not belong to any of the below defined virtual memory regions, it will be returned without any modification.
-           A virtAddr would belong to any one of the below memory spaces, so convertVirt2Phys call for that particular space would be executed
-           All other function calls would just pass through the phyAddr */
-        convertVirt2Phys(virtAddr, (uint64_t) DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_1_2_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_1_3_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_1_4_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-
-        convertVirt2Phys(virtAddr, (uint64_t) DDR_C7X_1_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_1_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_1_LOCAL_HEAP_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_1_2_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_2_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_2_LOCAL_HEAP_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_1_3_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_3_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_3_LOCAL_HEAP_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_1_4_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_4_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_4_LOCAL_HEAP_PHYS_SIZE, &phyAddr);
-
-        convertVirt2Phys(virtAddr, (uint64_t) DDR_C7X_1_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_1_2_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_1_3_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_1_4_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        
-        convertVirt2Phys(virtAddr, (uint64_t) DDR_C7X_1_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_1_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_1_SCRATCH_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_1_2_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_2_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_2_SCRATCH_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_1_3_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_3_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_3_SCRATCH_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_1_4_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_4_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_4_SCRATCH_PHYS_SIZE, &phyAddr);
-    }
     return phyAddr;
 }
 
@@ -588,32 +523,6 @@ uint64_t appUdmaVirtToPhyAddrConversion(const void *virtAddr,
     return appTarget2SharedConversion((uint64_t)virtAddr);
 }
 
-/** Description : This function converts a physical memory region address to virtual memory region address given the base addresses of both memory regions 
- *  which are mapped using MMU in appMmuMap
- *  Arguments:
- *      - shared_ptr : Physical pointer
- *      - virtBase   : Base address of virtual memory space
- *      - physBase   : Base address of physical memory space
- *      - size       : Size of memory space
- *      - target_ptr : Virtual pointer to be returned after conversion if shared_ptr belongs to memory space with base address physBase
- *                     else, target_ptr is returned as it is without any modification
- */
-static void convertPhys2Virt(uint64_t shared_ptr, uint64_t virtBase, uint64_t physBase, uint64_t size, uint64_t * target_ptr)
-{
-    if ( ((uint64_t)shared_ptr >= physBase) &&
-         ((uint64_t)shared_ptr < (physBase + size)) )
-    {
-        if (physBase >= virtBase)
-        {
-            *target_ptr = shared_ptr - (physBase - virtBase);
-        }
-        else
-        {
-            *target_ptr = (uint64_t)shared_ptr + (virtBase - physBase);
-        }
-    }
-}
-
 uint64_t appShared2TargetConversion(const uint64_t shared_ptr)
 {
     uint64_t target_ptr = shared_ptr; /* Default : Return shared_ptr without any modification */
@@ -631,48 +540,6 @@ uint64_t appShared2TargetConversion(const uint64_t shared_ptr)
             target_ptr = (uint64_t)shared_ptr + (DDR_SHARED_MEM_ADDR - DDR_SHARED_MEM_PHYS_ADDR);
         }
     }
-    else
-    {
-        /* Below code converts C7x DDR physical addresses of all cores to c7x_1 virtual addresses 
-           If shared_ptr does not belong to any of the below defined physical memory regions, it will be returned without any modification.
-           A shared_ptr would belong to any one of the below memory spaces, so convertPhys2Virt call for that particular space would be executed
-           All other function calls would just pass through the target_ptr */
-        convertPhys2Virt(shared_ptr, (uint64_t) DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_1_2_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_1_3_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_1_4_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-
-        convertPhys2Virt(shared_ptr, (uint64_t) DDR_C7X_1_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_1_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_1_LOCAL_HEAP_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_1_2_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_2_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_2_LOCAL_HEAP_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_1_3_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_3_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_3_LOCAL_HEAP_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_1_4_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_4_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_4_LOCAL_HEAP_PHYS_SIZE, &target_ptr);
-
-        convertPhys2Virt(shared_ptr, (uint64_t) DDR_C7X_1_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_1_2_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_1_3_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_1_4_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        
-        convertPhys2Virt(shared_ptr, (uint64_t) DDR_C7X_1_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_1_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_1_SCRATCH_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_1_2_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_2_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_2_SCRATCH_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_1_3_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_3_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_3_SCRATCH_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_1_4_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_4_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_4_SCRATCH_PHYS_SIZE, &target_ptr);
-    }
     return target_ptr;
 }
 
diff --git a/platform/j784s4/rtos/c7x_2/main.c b/platform/j784s4/rtos/c7x_2/main.c
index 92c1ab8..9599360 100755
--- a/platform/j784s4/rtos/c7x_2/main.c
+++ b/platform/j784s4/rtos/c7x_2/main.c
@@ -271,161 +271,163 @@ void appMmuMap(Bool is_secure)
     {
         goto mmu_exit;
     }
-    
-    /* DDR Local heap non cacheable */
-    retVal = Mmu_map(DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_ADDR, DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+
+    /*-------------------------------------------------------*/
+    /* Cachable region memory attributes                     */
+    /*-------------------------------------------------------*/
+
+    attrs.attrIndx = Mmu_AttrIndx_MAIR7;
+
+    retVal = Mmu_map(0x80000000U, 0x80000000U, 0x20000000U, &attrs, is_secure); /* OCMC - 1MB */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_2_1_LOCAL_HEAP_NON_CACHEABLE_ADDR, DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(0xA0000000U, 0xA0000000U, 0x20000000U, &attrs, is_secure); /* OCMC - 1MB */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_2_3_LOCAL_HEAP_NON_CACHEABLE_ADDR, DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(0x70000000U, 0x70000000U, 0x00800000U, &attrs, is_secure); /* MSMC - 8MB */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_2_4_LOCAL_HEAP_NON_CACHEABLE_ADDR, DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(0x41C00000U, 0x41C00000U, 0x00100000U, &attrs, is_secure); /* OCMC - 1MB */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
-    
-    /* DDR scratch non cacheable */
-    retVal = Mmu_map(DDR_C7X_2_SCRATCH_NON_CACHEABLE_ADDR, DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_2_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+
+    /*The region mapped by the MMU is intentionally set to 2MB for L2 SRAM since
+      page sizes are a function of the region size and having smaller page sizes
+      negatively affects the performance of L2 SRAM as the table walks with the
+      translation table in DDR are expensive, especially in context of high-
+      throughput, low-latency memory like L2 SRAM*/
+    retVal = Mmu_map(L2RAM_C7x_2_ADDR, L2RAM_C7x_2_ADDR, 0x00200000, &attrs, is_secure); /* L2 sram 448KB        */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_2_1_SCRATCH_NON_CACHEABLE_ADDR, DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_1_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7x_2_DTS_ADDR, DDR_C7x_2_DTS_ADDR, DDR_C7x_2_DTS_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_2_3_SCRATCH_NON_CACHEABLE_ADDR, DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_3_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    /* DDR local heap */
+    retVal = Mmu_map(DDR_C7X_2_LOCAL_HEAP_ADDR, DDR_C7X_2_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_2_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_2_4_SCRATCH_NON_CACHEABLE_ADDR, DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_4_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_1_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_1_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_1_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    /*-------------------------------------------------------*/
-    /* Cachable region memory attributes                     */
-    /*-------------------------------------------------------*/
-
-    attrs.attrIndx = Mmu_AttrIndx_MAIR7;
-
-    retVal = Mmu_map(0x80000000U, 0x80000000U, 0x20000000U, &attrs, is_secure); /* OCMC - 1MB */
+    retVal = Mmu_map(DDR_C7X_3_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_3_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_3_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(0xA0000000U, 0xA0000000U, 0x20000000U, &attrs, is_secure); /* OCMC - 1MB */
+    retVal = Mmu_map(DDR_C7X_4_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_4_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_4_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
-
-    retVal = Mmu_map(0x70000000U, 0x70000000U, 0x00800000U, &attrs, is_secure); /* MSMC - 8MB */
+    
+    /* DDR scratch */
+    retVal = Mmu_map(DDR_C7X_2_SCRATCH_ADDR, DDR_C7X_2_SCRATCH_PHYS_ADDR, DDR_C7X_2_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(0x41C00000U, 0x41C00000U, 0x00100000U, &attrs, is_secure); /* OCMC - 1MB */
+    retVal = Mmu_map(DDR_C7X_1_SCRATCH_PHYS_ADDR, DDR_C7X_1_SCRATCH_PHYS_ADDR, DDR_C7X_1_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    /*The region mapped by the MMU is intentionally set to 2MB for L2 SRAM since
-      page sizes are a function of the region size and having smaller page sizes
-      negatively affects the performance of L2 SRAM as the table walks with the
-      translation table in DDR are expensive, especially in context of high-
-      throughput, low-latency memory like L2 SRAM*/
-    retVal = Mmu_map(L2RAM_C7x_2_ADDR, L2RAM_C7x_2_ADDR, 0x00200000, &attrs, is_secure); /* L2 sram 448KB        */
+    retVal = Mmu_map(DDR_C7X_3_SCRATCH_PHYS_ADDR, DDR_C7X_3_SCRATCH_PHYS_ADDR, DDR_C7X_3_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7x_2_DTS_ADDR, DDR_C7x_2_DTS_ADDR, DDR_C7x_2_DTS_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_4_SCRATCH_PHYS_ADDR, DDR_C7X_4_SCRATCH_PHYS_ADDR, DDR_C7X_4_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    /* DDR local heap */
-    retVal = Mmu_map(DDR_C7X_2_LOCAL_HEAP_ADDR, DDR_C7X_2_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_2_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_SHARED_MEM_ADDR, DDR_SHARED_MEM_PHYS_ADDR, DDR_SHARED_MEM_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_2_1_LOCAL_HEAP_ADDR, DDR_C7X_1_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_1_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(MSMC_C7x_2_ADDR, MSMC_C7x_2_ADDR, MSMC_C7x_2_SIZE, &attrs, is_secure); /* Local MSMC   */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_2_3_LOCAL_HEAP_ADDR, DDR_C7X_3_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_3_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
+    attrs.attrIndx = Mmu_AttrIndx_MAIR0;
+
+    /* DDR Local heap non cacheable */
+    retVal = Mmu_map(DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_ADDR, DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_2_4_LOCAL_HEAP_ADDR, DDR_C7X_4_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_4_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
-    
-    /* DDR scratch */
-    retVal = Mmu_map(DDR_C7X_2_SCRATCH_ADDR, DDR_C7X_2_SCRATCH_PHYS_ADDR, DDR_C7X_2_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
+
+    retVal = Mmu_map(DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_2_1_SCRATCH_ADDR, DDR_C7X_1_SCRATCH_PHYS_ADDR, DDR_C7X_1_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
-
-    retVal = Mmu_map(DDR_C7X_2_3_SCRATCH_ADDR, DDR_C7X_3_SCRATCH_PHYS_ADDR, DDR_C7X_3_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
+    
+    /* DDR scratch non cacheable */
+    retVal = Mmu_map(DDR_C7X_2_SCRATCH_NON_CACHEABLE_ADDR, DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_2_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_2_4_SCRATCH_ADDR, DDR_C7X_4_SCRATCH_PHYS_ADDR, DDR_C7X_4_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_1_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_SHARED_MEM_ADDR, DDR_SHARED_MEM_PHYS_ADDR, DDR_SHARED_MEM_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_3_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(MSMC_C7x_2_ADDR, MSMC_C7x_2_ADDR, MSMC_C7x_2_SIZE, &attrs, is_secure); /* Local MSMC   */
+    retVal = Mmu_map(DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_4_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
@@ -507,22 +509,6 @@ void InitMmu(void)
     appCacheInit();
 }
 
-static void convertVirt2Phys(uint64_t virtAddr, uint64_t virtBase, uint64_t physBase, uint64_t size, uint64_t * phyAddr)
-{
-    if ( ((uint64_t)virtAddr >= virtBase) &&
-         ((uint64_t)virtAddr < (virtBase + size)) )
-    {
-        if (virtBase >= physBase)
-        {
-            *phyAddr = (uint64_t)virtAddr - (virtBase - physBase);
-        }
-        else
-        {
-            *phyAddr = (uint64_t)virtAddr + (physBase - virtBase);
-        }
-    }
-}
-
 uint64_t appTarget2SharedConversion(const uint64_t virtAddr)
 {
     uint64_t phyAddr = (uint64_t)virtAddr; /* Default : Return virtAddr without any modification */
@@ -540,44 +526,6 @@ uint64_t appTarget2SharedConversion(const uint64_t virtAddr)
             phyAddr = (uint64_t)virtAddr - (DDR_SHARED_MEM_ADDR - DDR_SHARED_MEM_PHYS_ADDR);
         }
     }
-    else
-    {
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_2_1_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_2_3_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_2_4_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_2_1_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_1_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_1_LOCAL_HEAP_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_2_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_2_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_2_LOCAL_HEAP_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_2_3_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_3_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_3_LOCAL_HEAP_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_2_4_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_4_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_4_LOCAL_HEAP_PHYS_SIZE, &phyAddr);
-        
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_2_1_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_2_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_2_3_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_2_4_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_2_1_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_1_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_1_SCRATCH_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_2_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_2_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_2_SCRATCH_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_2_3_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_3_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_3_SCRATCH_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_2_4_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_4_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_4_SCRATCH_PHYS_SIZE, &phyAddr);
-    }
 
   return phyAddr;
 }
@@ -589,22 +537,6 @@ uint64_t appUdmaVirtToPhyAddrConversion(const void *virtAddr,
     return appTarget2SharedConversion((uint64_t)virtAddr);
 }
 
-static void convertPhys2Virt(uint64_t shared_ptr, uint64_t virtBase, uint64_t physBase, uint64_t size, uint64_t * target_ptr)
-{
-    if ( ((uint64_t)shared_ptr >= physBase) &&
-         ((uint64_t)shared_ptr < (physBase + size)) )
-    {
-        if (physBase >= virtBase)
-        {
-            *target_ptr = shared_ptr - (physBase - virtBase);
-        }
-        else
-        {
-            *target_ptr = (uint64_t)shared_ptr + (virtBase - physBase);
-        }
-    }
-}
-
 uint64_t appShared2TargetConversion(const uint64_t shared_ptr)
 {
     uint64_t target_ptr = shared_ptr;
@@ -622,44 +554,6 @@ uint64_t appShared2TargetConversion(const uint64_t shared_ptr)
             target_ptr = (uint64_t)shared_ptr + (DDR_SHARED_MEM_ADDR - DDR_SHARED_MEM_PHYS_ADDR);
         }
     }
-    else
-    {
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_2_1_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_2_3_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_2_4_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_2_1_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_1_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_1_LOCAL_HEAP_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_2_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_2_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_2_LOCAL_HEAP_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_2_3_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_3_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_3_LOCAL_HEAP_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_2_4_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_4_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_4_LOCAL_HEAP_PHYS_SIZE, &target_ptr);
-        
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_2_1_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_2_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_2_3_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_2_4_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_2_1_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_1_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_1_SCRATCH_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_2_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_2_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_2_SCRATCH_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_2_3_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_3_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_3_SCRATCH_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_2_4_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_4_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_4_SCRATCH_PHYS_SIZE, &target_ptr);
-    }
     return target_ptr;
 }
 
diff --git a/platform/j784s4/rtos/c7x_3/main.c b/platform/j784s4/rtos/c7x_3/main.c
index f239a39..abaf2e5 100755
--- a/platform/j784s4/rtos/c7x_3/main.c
+++ b/platform/j784s4/rtos/c7x_3/main.c
@@ -271,163 +271,165 @@ void appMmuMap(Bool is_secure)
     {
         goto mmu_exit;
     }
-    
-    /* DDR Local heap non cacheable */
-    retVal = Mmu_map(DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_ADDR, DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+
+    /*-------------------------------------------------------*/
+    /* Cachable region memory attributes                     */
+    /*-------------------------------------------------------*/
+
+
+    attrs.attrIndx = Mmu_AttrIndx_MAIR7;
+
+    retVal = Mmu_map(0x80000000U, 0x80000000U, 0x20000000U, &attrs, is_secure); /* OCMC - 1MB */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_3_1_LOCAL_HEAP_NON_CACHEABLE_ADDR, DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(0xA0000000U, 0xA0000000U, 0x20000000U, &attrs, is_secure); /* OCMC - 1MB */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_3_2_LOCAL_HEAP_NON_CACHEABLE_ADDR, DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(0x70000000U, 0x70000000U, 0x00800000U, &attrs, is_secure); /* MSMC - 8MB */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_3_4_LOCAL_HEAP_NON_CACHEABLE_ADDR, DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(0x41C00000U, 0x41C00000U, 0x00100000U, &attrs, is_secure); /* OCMC - 1MB */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
-    
-    /* DDR scratch non cacheable */
-    retVal = Mmu_map(DDR_C7X_3_SCRATCH_NON_CACHEABLE_ADDR, DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_3_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+
+    /*The region mapped by the MMU is intentionally set to 2MB for L2 SRAM since
+      page sizes are a function of the region size and having smaller page sizes
+      negatively affects the performance of L2 SRAM as the table walks with the
+      translation table in DDR are expensive, especially in context of high-
+      throughput, low-latency memory like L2 SRAM*/
+    retVal = Mmu_map(L2RAM_C7x_3_ADDR, L2RAM_C7x_3_ADDR, 0x00200000, &attrs, is_secure); /* L2 sram 448KB        */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_3_1_SCRATCH_NON_CACHEABLE_ADDR, DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_1_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7x_3_DTS_ADDR, DDR_C7x_3_DTS_ADDR, DDR_C7x_3_DTS_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_3_2_SCRATCH_NON_CACHEABLE_ADDR, DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_2_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    /* DDR Local heap */
+    retVal = Mmu_map(DDR_C7X_3_LOCAL_HEAP_ADDR, DDR_C7X_3_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_3_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_3_4_SCRATCH_NON_CACHEABLE_ADDR, DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_4_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_1_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_1_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_1_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    /*-------------------------------------------------------*/
-    /* Cachable region memory attributes                     */
-    /*-------------------------------------------------------*/
-
-
-    attrs.attrIndx = Mmu_AttrIndx_MAIR7;
-
-    retVal = Mmu_map(0x80000000U, 0x80000000U, 0x20000000U, &attrs, is_secure); /* OCMC - 1MB */
+    retVal = Mmu_map(DDR_C7X_2_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_2_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_2_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(0xA0000000U, 0xA0000000U, 0x20000000U, &attrs, is_secure); /* OCMC - 1MB */
+    retVal = Mmu_map(DDR_C7X_4_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_4_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_4_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(0x70000000U, 0x70000000U, 0x00800000U, &attrs, is_secure); /* MSMC - 8MB */
+    /* DDR scratch */
+    retVal = Mmu_map(DDR_C7X_3_SCRATCH_ADDR, DDR_C7X_3_SCRATCH_PHYS_ADDR, DDR_C7X_3_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(0x41C00000U, 0x41C00000U, 0x00100000U, &attrs, is_secure); /* OCMC - 1MB */
+    retVal = Mmu_map(DDR_C7X_1_SCRATCH_PHYS_ADDR, DDR_C7X_1_SCRATCH_PHYS_ADDR, DDR_C7X_1_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    /*The region mapped by the MMU is intentionally set to 2MB for L2 SRAM since
-      page sizes are a function of the region size and having smaller page sizes
-      negatively affects the performance of L2 SRAM as the table walks with the
-      translation table in DDR are expensive, especially in context of high-
-      throughput, low-latency memory like L2 SRAM*/
-    retVal = Mmu_map(L2RAM_C7x_3_ADDR, L2RAM_C7x_3_ADDR, 0x00200000, &attrs, is_secure); /* L2 sram 448KB        */
+    retVal = Mmu_map(DDR_C7X_2_SCRATCH_PHYS_ADDR, DDR_C7X_2_SCRATCH_PHYS_ADDR, DDR_C7X_2_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7x_3_DTS_ADDR, DDR_C7x_3_DTS_ADDR, DDR_C7x_3_DTS_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_4_SCRATCH_PHYS_ADDR, DDR_C7X_4_SCRATCH_PHYS_ADDR, DDR_C7X_4_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
-
-    /* DDR Local heap */
-    retVal = Mmu_map(DDR_C7X_3_LOCAL_HEAP_ADDR, DDR_C7X_3_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_3_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
+     
+    /* DDR shared mem */
+    retVal = Mmu_map(DDR_SHARED_MEM_ADDR, DDR_SHARED_MEM_PHYS_ADDR, DDR_SHARED_MEM_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_3_1_LOCAL_HEAP_ADDR, DDR_C7X_1_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_1_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(MSMC_C7x_3_ADDR, MSMC_C7x_3_ADDR, MSMC_C7x_3_SIZE, &attrs, is_secure); /* Local MSMC   */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_3_2_LOCAL_HEAP_ADDR, DDR_C7X_2_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_2_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
+    attrs.attrIndx = Mmu_AttrIndx_MAIR0;
+
+    /* DDR Local heap non cacheable */
+    retVal = Mmu_map(DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_ADDR, DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_3_4_LOCAL_HEAP_ADDR, DDR_C7X_4_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_4_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    /* DDR scratch */
-    retVal = Mmu_map(DDR_C7X_3_SCRATCH_ADDR, DDR_C7X_3_SCRATCH_PHYS_ADDR, DDR_C7X_3_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_3_1_SCRATCH_ADDR, DDR_C7X_1_SCRATCH_PHYS_ADDR, DDR_C7X_1_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
-
-    retVal = Mmu_map(DDR_C7X_3_2_SCRATCH_ADDR, DDR_C7X_2_SCRATCH_PHYS_ADDR, DDR_C7X_2_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
+    
+    /* DDR scratch non cacheable */
+    retVal = Mmu_map(DDR_C7X_3_SCRATCH_NON_CACHEABLE_ADDR, DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_3_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_3_4_SCRATCH_ADDR, DDR_C7X_4_SCRATCH_PHYS_ADDR, DDR_C7X_4_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_1_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
-     
-    /* DDR shared mem */
-    retVal = Mmu_map(DDR_SHARED_MEM_ADDR, DDR_SHARED_MEM_PHYS_ADDR, DDR_SHARED_MEM_SIZE, &attrs, is_secure); /* ddr            */
+
+    retVal = Mmu_map(DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_2_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(MSMC_C7x_3_ADDR, MSMC_C7x_3_ADDR, MSMC_C7x_3_SIZE, &attrs, is_secure); /* Local MSMC   */
+    retVal = Mmu_map(DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_4_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
@@ -509,22 +511,6 @@ void InitMmu(void)
     appCacheInit();
 }
 
-static void convertVirt2Phys(uint64_t virtAddr, uint64_t virtBase, uint64_t physBase, uint64_t size, uint64_t * phyAddr)
-{
-    if ( ((uint64_t)virtAddr >= virtBase) &&
-         ((uint64_t)virtAddr < (virtBase + size)) )
-    {
-        if (virtBase >= physBase)
-        {
-            *phyAddr = (uint64_t)virtAddr - (virtBase - physBase);
-        }
-        else
-        {
-            *phyAddr = (uint64_t)virtAddr + (physBase - virtBase);
-        }
-    }
-}
-
 uint64_t appTarget2SharedConversion(const uint64_t virtAddr)
 {
     uint64_t phyAddr = (uint64_t)virtAddr; /* Default : Return virtAddr without any modification */
@@ -542,44 +528,6 @@ uint64_t appTarget2SharedConversion(const uint64_t virtAddr)
             phyAddr = (uint64_t)virtAddr - (DDR_SHARED_MEM_ADDR - DDR_SHARED_MEM_PHYS_ADDR);
         }
     }
-    else
-    {
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_3_1_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_3_2_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_3_4_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_3_1_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_1_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_1_LOCAL_HEAP_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_3_2_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_2_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_2_LOCAL_HEAP_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_3_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_3_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_3_LOCAL_HEAP_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_3_4_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_4_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_4_LOCAL_HEAP_PHYS_SIZE, &phyAddr);
-        
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_3_1_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_3_2_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_3_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_3_4_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_3_1_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_1_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_1_SCRATCH_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_3_2_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_2_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_2_SCRATCH_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_3_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_3_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_3_SCRATCH_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_3_4_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_4_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_4_SCRATCH_PHYS_SIZE, &phyAddr);
-    }
 
   return phyAddr;
 }
@@ -591,22 +539,6 @@ uint64_t appUdmaVirtToPhyAddrConversion(const void *virtAddr,
     return appTarget2SharedConversion((uint64_t)virtAddr);
 }
 
-static void convertPhys2Virt(uint64_t shared_ptr, uint64_t virtBase, uint64_t physBase, uint64_t size, uint64_t * target_ptr)
-{
-    if ( ((uint64_t)shared_ptr >= physBase) &&
-         ((uint64_t)shared_ptr < (physBase + size)) )
-    {
-        if (physBase >= virtBase)
-        {
-            *target_ptr = shared_ptr - (physBase - virtBase);
-        }
-        else
-        {
-            *target_ptr = (uint64_t)shared_ptr + (virtBase - physBase);
-        }
-    }
-}
-
 uint64_t appShared2TargetConversion(const uint64_t shared_ptr)
 {
     uint64_t target_ptr = shared_ptr;
@@ -624,44 +556,6 @@ uint64_t appShared2TargetConversion(const uint64_t shared_ptr)
             target_ptr = (uint64_t)shared_ptr + (DDR_SHARED_MEM_ADDR - DDR_SHARED_MEM_PHYS_ADDR);
         }
     }
-    else
-    {
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_3_1_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_3_2_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_3_4_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_3_1_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_1_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_1_LOCAL_HEAP_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_3_2_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_2_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_2_LOCAL_HEAP_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_3_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_3_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_3_LOCAL_HEAP_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_3_4_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_4_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_4_LOCAL_HEAP_PHYS_SIZE, &target_ptr);
-        
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_3_1_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_3_2_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_3_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_3_4_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_3_1_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_1_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_1_SCRATCH_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_3_2_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_2_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_2_SCRATCH_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_3_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_3_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_3_SCRATCH_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_3_4_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_4_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_4_SCRATCH_PHYS_SIZE, &target_ptr);
-    }
     return target_ptr;
 }
 
diff --git a/platform/j784s4/rtos/c7x_4/main.c b/platform/j784s4/rtos/c7x_4/main.c
index e4eb3d4..cd17e27 100755
--- a/platform/j784s4/rtos/c7x_4/main.c
+++ b/platform/j784s4/rtos/c7x_4/main.c
@@ -271,162 +271,164 @@ void appMmuMap(Bool is_secure)
     {
         goto mmu_exit;
     }
-    
-    /* DDR Local heap non cacheable */
-    retVal = Mmu_map(DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_ADDR, DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+
+    /*-------------------------------------------------------*/
+    /* Cachable region memory attributes                     */
+    /*-------------------------------------------------------*/
+
+    attrs.attrIndx = Mmu_AttrIndx_MAIR7;
+
+    retVal = Mmu_map(0x80000000U, 0x80000000U, 0x20000000U, &attrs, is_secure); /* OCMC - 1MB */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_4_1_LOCAL_HEAP_NON_CACHEABLE_ADDR, DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(0xA0000000U, 0xA0000000U, 0x20000000U, &attrs, is_secure); /* OCMC - 1MB */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_4_2_LOCAL_HEAP_NON_CACHEABLE_ADDR, DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(0x70000000U, 0x70000000U, 0x00800000U, &attrs, is_secure); /* MSMC - 8MB */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_4_3_LOCAL_HEAP_NON_CACHEABLE_ADDR, DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(0x41C00000U, 0x41C00000U, 0x00100000U, &attrs, is_secure); /* OCMC - 1MB */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    /* DDR scratch non cacheable */
-    retVal = Mmu_map(DDR_C7X_4_SCRATCH_NON_CACHEABLE_ADDR, DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_4_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    /*The region mapped by the MMU is intentionally set to 2MB for L2 SRAM since
+      page sizes are a function of the region size and having smaller page sizes
+      negatively affects the performance of L2 SRAM as the table walks with the
+      translation table in DDR are expensive, especially in context of high-
+      throughput, low-latency memory like L2 SRAM*/
+    retVal = Mmu_map(L2RAM_C7x_4_ADDR, L2RAM_C7x_4_ADDR, 0x00200000, &attrs, is_secure); /* L2 sram 448KB        */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_4_1_SCRATCH_NON_CACHEABLE_ADDR, DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_1_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7x_4_DTS_ADDR, DDR_C7x_4_DTS_ADDR, DDR_C7x_4_DTS_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_4_2_SCRATCH_NON_CACHEABLE_ADDR, DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_2_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    /* DDR Local heap */
+    retVal = Mmu_map(DDR_C7X_4_LOCAL_HEAP_ADDR, DDR_C7X_4_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_4_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_4_3_SCRATCH_NON_CACHEABLE_ADDR, DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_3_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_1_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_1_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_1_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    /*-------------------------------------------------------*/
-    /* Cachable region memory attributes                     */
-    /*-------------------------------------------------------*/
-
-    attrs.attrIndx = Mmu_AttrIndx_MAIR7;
-
-    retVal = Mmu_map(0x80000000U, 0x80000000U, 0x20000000U, &attrs, is_secure); /* OCMC - 1MB */
+    retVal = Mmu_map(DDR_C7X_2_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_2_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_2_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(0xA0000000U, 0xA0000000U, 0x20000000U, &attrs, is_secure); /* OCMC - 1MB */
+    retVal = Mmu_map(DDR_C7X_3_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_3_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_3_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
-
-    retVal = Mmu_map(0x70000000U, 0x70000000U, 0x00800000U, &attrs, is_secure); /* MSMC - 8MB */
+    
+    /* DDR scratch */
+    retVal = Mmu_map(DDR_C7X_4_SCRATCH_ADDR, DDR_C7X_4_SCRATCH_PHYS_ADDR, DDR_C7X_4_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(0x41C00000U, 0x41C00000U, 0x00100000U, &attrs, is_secure); /* OCMC - 1MB */
+    retVal = Mmu_map(DDR_C7X_1_SCRATCH_PHYS_ADDR, DDR_C7X_1_SCRATCH_PHYS_ADDR, DDR_C7X_1_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    /*The region mapped by the MMU is intentionally set to 2MB for L2 SRAM since
-      page sizes are a function of the region size and having smaller page sizes
-      negatively affects the performance of L2 SRAM as the table walks with the
-      translation table in DDR are expensive, especially in context of high-
-      throughput, low-latency memory like L2 SRAM*/
-    retVal = Mmu_map(L2RAM_C7x_4_ADDR, L2RAM_C7x_4_ADDR, 0x00200000, &attrs, is_secure); /* L2 sram 448KB        */
+    retVal = Mmu_map(DDR_C7X_2_SCRATCH_PHYS_ADDR, DDR_C7X_2_SCRATCH_PHYS_ADDR, DDR_C7X_2_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7x_4_DTS_ADDR, DDR_C7x_4_DTS_ADDR, DDR_C7x_4_DTS_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_3_SCRATCH_PHYS_ADDR, DDR_C7X_3_SCRATCH_PHYS_ADDR, DDR_C7X_3_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
-
-    /* DDR Local heap */
-    retVal = Mmu_map(DDR_C7X_4_LOCAL_HEAP_ADDR, DDR_C7X_4_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_4_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
+    
+    /* DDR shared mem */
+    retVal = Mmu_map(DDR_SHARED_MEM_ADDR, DDR_SHARED_MEM_PHYS_ADDR, DDR_SHARED_MEM_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_4_1_LOCAL_HEAP_ADDR, DDR_C7X_1_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_1_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(MSMC_C7x_4_ADDR, MSMC_C7x_4_ADDR, MSMC_C7x_4_SIZE, &attrs, is_secure); /* Local MSMC   */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_4_2_LOCAL_HEAP_ADDR, DDR_C7X_2_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_2_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
+    attrs.attrIndx = Mmu_AttrIndx_MAIR0;
+
+    /* DDR Local heap non cacheable */
+    retVal = Mmu_map(DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_ADDR, DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_4_3_LOCAL_HEAP_ADDR, DDR_C7X_3_LOCAL_HEAP_PHYS_ADDR, DDR_C7X_3_LOCAL_HEAP_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
-    
-    /* DDR scratch */
-    retVal = Mmu_map(DDR_C7X_4_SCRATCH_ADDR, DDR_C7X_4_SCRATCH_PHYS_ADDR, DDR_C7X_4_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
+
+    retVal = Mmu_map(DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_4_1_SCRATCH_ADDR, DDR_C7X_1_SCRATCH_PHYS_ADDR, DDR_C7X_1_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_4_2_SCRATCH_ADDR, DDR_C7X_2_SCRATCH_PHYS_ADDR, DDR_C7X_2_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
+    /* DDR scratch non cacheable */
+    retVal = Mmu_map(DDR_C7X_4_SCRATCH_NON_CACHEABLE_ADDR, DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_4_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(DDR_C7X_4_3_SCRATCH_ADDR, DDR_C7X_3_SCRATCH_PHYS_ADDR, DDR_C7X_3_SCRATCH_SIZE, &attrs, is_secure); /* ddr            */
+    retVal = Mmu_map(DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_1_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
-    
-    /* DDR shared mem */
-    retVal = Mmu_map(DDR_SHARED_MEM_ADDR, DDR_SHARED_MEM_PHYS_ADDR, DDR_SHARED_MEM_SIZE, &attrs, is_secure); /* ddr            */
+
+    retVal = Mmu_map(DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_2_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
     }
 
-    retVal = Mmu_map(MSMC_C7x_4_ADDR, MSMC_C7x_4_ADDR, MSMC_C7x_4_SIZE, &attrs, is_secure); /* Local MSMC   */
+    retVal = Mmu_map(DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_ADDR, DDR_C7X_3_SCRATCH_NON_CACHEABLE_SIZE, &attrs, is_secure); /* ddr            */
     if(retVal == UFALSE)
     {
         goto mmu_exit;
@@ -508,22 +510,6 @@ void InitMmu(void)
     appCacheInit();
 }
 
-static void convertVirt2Phys(uint64_t virtAddr, uint64_t virtBase, uint64_t physBase, uint64_t size, uint64_t * phyAddr)
-{
-    if ( ((uint64_t)virtAddr >= virtBase) &&
-         ((uint64_t)virtAddr < (virtBase + size)) )
-    {
-        if (virtBase >= physBase)
-        {
-            *phyAddr = (uint64_t)virtAddr - (virtBase - physBase);
-        }
-        else
-        {
-            *phyAddr = (uint64_t)virtAddr + (physBase - virtBase);
-        }
-    }
-}
-
 uint64_t appTarget2SharedConversion(const uint64_t virtAddr)
 {
     uint64_t phyAddr = (uint64_t)virtAddr; /* Default : Return virtAddr without any modification */
@@ -541,44 +527,6 @@ uint64_t appTarget2SharedConversion(const uint64_t virtAddr)
             phyAddr = (uint64_t)virtAddr - (DDR_SHARED_MEM_ADDR - DDR_SHARED_MEM_PHYS_ADDR);
         }
     }
-    else
-    {
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_4_1_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_4_2_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_4_3_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_4_1_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_1_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_1_LOCAL_HEAP_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_4_2_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_2_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_2_LOCAL_HEAP_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_4_3_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_3_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_3_LOCAL_HEAP_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_4_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_4_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_4_LOCAL_HEAP_PHYS_SIZE, &phyAddr);
-        
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_4_1_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_4_2_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_4_3_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_4_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &phyAddr);
-        
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_4_1_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_1_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_1_SCRATCH_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_4_2_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_2_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_2_SCRATCH_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_4_3_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_3_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_3_SCRATCH_PHYS_SIZE, &phyAddr);
-        convertVirt2Phys(virtAddr, (uint64_t)DDR_C7X_4_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_4_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_4_SCRATCH_PHYS_SIZE, &phyAddr);        
-    }
 
   return phyAddr;
 }
@@ -590,22 +538,6 @@ uint64_t appUdmaVirtToPhyAddrConversion(const void *virtAddr,
     return appTarget2SharedConversion((uint64_t)virtAddr);
 }
 
-static void convertPhys2Virt(uint64_t shared_ptr, uint64_t virtBase, uint64_t physBase, uint64_t size, uint64_t * target_ptr)
-{
-    if ( ((uint64_t)shared_ptr >= physBase) &&
-         ((uint64_t)shared_ptr < (physBase + size)) )
-    {
-        if (physBase >= virtBase)
-        {
-            *target_ptr = shared_ptr - (physBase - virtBase);
-        }
-        else
-        {
-            *target_ptr = (uint64_t)shared_ptr + (virtBase - physBase);
-        }
-    }
-}
-
 uint64_t appShared2TargetConversion(const uint64_t shared_ptr)
 {
     uint64_t target_ptr = shared_ptr;
@@ -623,44 +555,6 @@ uint64_t appShared2TargetConversion(const uint64_t shared_ptr)
             target_ptr = (uint64_t)shared_ptr + (DDR_SHARED_MEM_ADDR - DDR_SHARED_MEM_PHYS_ADDR);
         }
     }
-    else
-    {
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_4_1_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_4_2_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_4_3_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_3_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_4_LOCAL_HEAP_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_4_1_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_1_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_1_LOCAL_HEAP_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_4_2_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_2_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_2_LOCAL_HEAP_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_4_3_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_3_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_3_LOCAL_HEAP_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_4_LOCAL_HEAP_ADDR, 
-            (uint64_t) DDR_C7X_4_LOCAL_HEAP_PHYS_ADDR, (uint64_t)DDR_C7X_4_LOCAL_HEAP_PHYS_SIZE, &target_ptr);
-        
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_4_1_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_4_2_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_4_3_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_3_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_4_SCRATCH_NON_CACHEABLE_ADDR, 
-            (uint64_t) DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_ADDR, (uint64_t)DDR_C7X_4_SCRATCH_NON_CACHEABLE_PHYS_SIZE, &target_ptr);
-        
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_4_1_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_1_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_1_SCRATCH_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_4_2_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_2_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_2_SCRATCH_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_4_3_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_3_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_3_SCRATCH_PHYS_SIZE, &target_ptr);
-        convertPhys2Virt(shared_ptr, (uint64_t)DDR_C7X_4_SCRATCH_ADDR, 
-            (uint64_t) DDR_C7X_4_SCRATCH_PHYS_ADDR, (uint64_t)DDR_C7X_4_SCRATCH_PHYS_SIZE, &target_ptr);
-    }
     return target_ptr;
 }
 
diff --git a/platform/j784s4/rtos/gen_linker_mem_map.py b/platform/j784s4/rtos/gen_linker_mem_map.py
index 41ae483..f58884f 100755
--- a/platform/j784s4/rtos/gen_linker_mem_map.py
+++ b/platform/j784s4/rtos/gen_linker_mem_map.py
@@ -88,7 +88,7 @@ KB = 1024;
 MB = KB*KB;
 GB = KB*MB;
 
-SHARED_MEM_SIZE = 1024*MB;
+SHARED_MEM_SIZE = 512*MB;
 
 #
 # Notes,
@@ -115,7 +115,7 @@ SHARED_MEM_SIZE = 1024*MB;
 # virtual lower DDR address range 0x0001_0000_0000
 #
 
-ddr_mem_addr  = 0xa0000000;
+ddr_mem_addr  = 0x90000000;
 ddr_mem_size  = 1*GB + 448*MB; # Last 64MB is used by Linux
 
 ddr_mem_addr_hi_phys = 0x880000000;
@@ -309,11 +309,17 @@ c7x_4_ddr_secure_vecs_size = 16*KB;
 c7x_4_ddr_addr = c7x_4_ddr_resource_table_addr + 7*MB;
 c7x_4_ddr_size = 24*MB;
 
+ddr_intercore_eth_desc_addr = c7x_4_ddr_addr + c7x_4_ddr_size;
+ddr_intercore_eth_desc_size = 8*MB;
+
+ddr_intercore_eth_data_addr = ddr_intercore_eth_desc_addr + ddr_intercore_eth_desc_size;
+ddr_intercore_eth_data_size = 24*MB;
+
 #
 # DDR memory allocation for various shared memories
 #
 
-mcu1_0_ddr_local_heap_addr  = c7x_4_ddr_addr + c7x_4_ddr_size;
+mcu1_0_ddr_local_heap_addr  = ddr_intercore_eth_data_addr + ddr_intercore_eth_data_size;
 mcu1_0_ddr_local_heap_size  = 8*MB;
 mcu1_1_ddr_local_heap_addr  = mcu1_0_ddr_local_heap_addr + mcu1_0_ddr_local_heap_size;
 mcu1_1_ddr_local_heap_size  = 8*MB;
@@ -334,167 +340,90 @@ mcu4_0_ddr_viss_heap_size   = 2*MB;
 mcu4_1_ddr_local_heap_addr  = mcu4_0_ddr_viss_heap_addr + mcu4_0_ddr_viss_heap_size;
 mcu4_1_ddr_local_heap_size  = 8*MB;
 
-ddr_intercore_eth_desc_addr = mcu4_1_ddr_local_heap_addr + mcu4_1_ddr_local_heap_size;
-ddr_intercore_eth_desc_size = 8*MB;
-
-ddr_intercore_eth_data_addr = ddr_intercore_eth_desc_addr + ddr_intercore_eth_desc_size;
-ddr_intercore_eth_data_size = 24*MB;
-
-# Shared memory for DMA Buf FD carveout
-ddr_shared_mem_addr     = ddr_intercore_eth_data_addr + ddr_intercore_eth_data_size;
-ddr_shared_mem_size     = SHARED_MEM_SIZE - uboot_reloc_mem_size;
-
 # C7x 1 Persistent DDR
-c7x_1_ddr_local_heap_non_cacheable_addr  = ddr_mem_addr_hi;
-c7x_1_ddr_local_heap_non_cacheable_addr_phys  = ddr_mem_addr_hi_phys;
-c7x_1_ddr_local_heap_non_cacheable_size  = 128*MB;
+c7x_1_ddr_local_heap_non_cacheable_addr  = mcu4_1_ddr_local_heap_addr + mcu4_1_ddr_local_heap_size;
+c7x_1_ddr_local_heap_non_cacheable_addr_phys  = mcu4_1_ddr_local_heap_addr + mcu4_1_ddr_local_heap_size;
+c7x_1_ddr_local_heap_non_cacheable_size  = 32*MB;
 c7x_1_ddr_local_heap_addr = c7x_1_ddr_local_heap_non_cacheable_addr + c7x_1_ddr_local_heap_non_cacheable_size;
 c7x_1_ddr_local_heap_addr_phys = c7x_1_ddr_local_heap_non_cacheable_addr_phys + c7x_1_ddr_local_heap_non_cacheable_size;
-c7x_1_ddr_local_heap_size = 128*MB;
+c7x_1_ddr_local_heap_size = 32*MB;
 total_c7x_1_local_ddr = c7x_1_ddr_local_heap_non_cacheable_size + c7x_1_ddr_local_heap_size;
 
 # C7x 1 Scratch DDR
 c7x_1_ddr_scratch_non_cacheable_addr      = c7x_1_ddr_local_heap_addr + c7x_1_ddr_local_heap_size;
 c7x_1_ddr_scratch_non_cacheable_addr_phys = c7x_1_ddr_local_heap_addr_phys + c7x_1_ddr_local_heap_size;
-c7x_1_ddr_scratch_non_cacheable_size      = 128*MB;
+c7x_1_ddr_scratch_non_cacheable_size      = 32*MB;
 c7x_1_ddr_scratch_addr = c7x_1_ddr_scratch_non_cacheable_addr + c7x_1_ddr_scratch_non_cacheable_size;
 c7x_1_ddr_scratch_addr_phys = c7x_1_ddr_scratch_non_cacheable_addr_phys + c7x_1_ddr_scratch_non_cacheable_size;
-c7x_1_ddr_scratch_size = 128*MB;
+c7x_1_ddr_scratch_size = 32*MB;
 total_c7x_1_scratch_ddr = c7x_1_ddr_scratch_non_cacheable_size + c7x_1_ddr_scratch_size
 
 total_c7x_1_ddr = total_c7x_1_local_ddr + total_c7x_1_scratch_ddr
 
 # C7x 2 Persistent DDR
-c7x_2_ddr_local_heap_non_cacheable_addr  = ddr_mem_addr_hi;
+c7x_2_ddr_local_heap_non_cacheable_addr  = c7x_1_ddr_scratch_addr + c7x_1_ddr_scratch_size;
 c7x_2_ddr_local_heap_non_cacheable_addr_phys  = c7x_1_ddr_scratch_addr_phys + c7x_1_ddr_scratch_size;
-c7x_2_ddr_local_heap_non_cacheable_size  = 128*MB;
+c7x_2_ddr_local_heap_non_cacheable_size  = 32*MB;
 c7x_2_ddr_local_heap_addr = c7x_2_ddr_local_heap_non_cacheable_addr + c7x_2_ddr_local_heap_non_cacheable_size;
 c7x_2_ddr_local_heap_addr_phys = c7x_2_ddr_local_heap_non_cacheable_addr_phys + c7x_2_ddr_local_heap_non_cacheable_size;
-c7x_2_ddr_local_heap_size = 128*MB;
+c7x_2_ddr_local_heap_size = 32*MB;
 total_c7x_2_local_ddr = c7x_2_ddr_local_heap_non_cacheable_size + c7x_2_ddr_local_heap_size
 
 # C7x 2 Scratch DDR
 c7x_2_ddr_scratch_non_cacheable_addr     = c7x_2_ddr_local_heap_addr + c7x_2_ddr_local_heap_size;
 c7x_2_ddr_scratch_non_cacheable_addr_phys     = c7x_2_ddr_local_heap_addr_phys + c7x_2_ddr_local_heap_size;
-c7x_2_ddr_scratch_non_cacheable_size     = 128*MB;
+c7x_2_ddr_scratch_non_cacheable_size     = 32*MB;
 c7x_2_ddr_scratch_addr = c7x_2_ddr_scratch_non_cacheable_addr + c7x_2_ddr_scratch_non_cacheable_size;
 c7x_2_ddr_scratch_addr_phys = c7x_2_ddr_scratch_non_cacheable_addr_phys + c7x_2_ddr_scratch_non_cacheable_size;
-c7x_2_ddr_scratch_size = 128*MB;
+c7x_2_ddr_scratch_size = 32*MB;
 total_c7x_2_scratch_ddr = c7x_2_ddr_scratch_non_cacheable_size + c7x_2_ddr_scratch_size
 
 total_c7x_2_ddr = total_c7x_2_local_ddr + total_c7x_2_scratch_ddr
 
 # C7x 3 Persistent DDR
-c7x_3_ddr_local_heap_non_cacheable_addr  = ddr_mem_addr_hi;
+c7x_3_ddr_local_heap_non_cacheable_addr  = c7x_2_ddr_scratch_addr + c7x_2_ddr_scratch_size;
 c7x_3_ddr_local_heap_non_cacheable_addr_phys  = c7x_2_ddr_scratch_addr_phys + c7x_2_ddr_scratch_size;
-c7x_3_ddr_local_heap_non_cacheable_size  = 128*MB;
+c7x_3_ddr_local_heap_non_cacheable_size  = 32*MB;
 c7x_3_ddr_local_heap_addr = c7x_3_ddr_local_heap_non_cacheable_addr + c7x_3_ddr_local_heap_non_cacheable_size;
 c7x_3_ddr_local_heap_addr_phys = c7x_3_ddr_local_heap_non_cacheable_addr_phys + c7x_3_ddr_local_heap_non_cacheable_size;
-c7x_3_ddr_local_heap_size = 128*MB;
+c7x_3_ddr_local_heap_size = 32*MB;
 total_c7x_3_local_ddr = c7x_3_ddr_local_heap_non_cacheable_size + c7x_3_ddr_local_heap_size
 # C7x 3 Scratch DDR
 c7x_3_ddr_scratch_non_cacheable_addr     = c7x_3_ddr_local_heap_addr + c7x_3_ddr_local_heap_size;
 c7x_3_ddr_scratch_non_cacheable_addr_phys     = c7x_3_ddr_local_heap_addr_phys + c7x_3_ddr_local_heap_size;
-c7x_3_ddr_scratch_non_cacheable_size     = 128*MB;
+c7x_3_ddr_scratch_non_cacheable_size     = 32*MB;
 c7x_3_ddr_scratch_addr = c7x_3_ddr_scratch_non_cacheable_addr + c7x_3_ddr_scratch_non_cacheable_size;
 c7x_3_ddr_scratch_addr_phys = c7x_3_ddr_scratch_non_cacheable_addr_phys + c7x_3_ddr_scratch_non_cacheable_size;
-c7x_3_ddr_scratch_size = 128*MB;
+c7x_3_ddr_scratch_size = 32*MB;
 total_c7x_3_scratch_ddr = c7x_3_ddr_scratch_non_cacheable_size + c7x_3_ddr_scratch_size
 
 total_c7x_3_ddr = total_c7x_3_local_ddr + total_c7x_3_scratch_ddr
 
 # C7x 4 Persistent DDR
-c7x_4_ddr_local_heap_non_cacheable_addr  = ddr_mem_addr_hi;
+c7x_4_ddr_local_heap_non_cacheable_addr  = c7x_3_ddr_scratch_addr + c7x_3_ddr_scratch_size;
 c7x_4_ddr_local_heap_non_cacheable_addr_phys  = c7x_3_ddr_scratch_addr_phys + c7x_3_ddr_scratch_size;
-c7x_4_ddr_local_heap_non_cacheable_size  = 128*MB;
+c7x_4_ddr_local_heap_non_cacheable_size  = 32*MB;
 c7x_4_ddr_local_heap_addr = c7x_4_ddr_local_heap_non_cacheable_addr + c7x_4_ddr_local_heap_non_cacheable_size;
 c7x_4_ddr_local_heap_addr_phys = c7x_4_ddr_local_heap_non_cacheable_addr_phys + c7x_4_ddr_local_heap_non_cacheable_size;
-c7x_4_ddr_local_heap_size = 128*MB;
+c7x_4_ddr_local_heap_size = 32*MB;
 total_c7x_4_local_ddr = c7x_4_ddr_local_heap_non_cacheable_size + c7x_4_ddr_local_heap_size
 
 # C7x 4 Scratch DDR
 c7x_4_ddr_scratch_non_cacheable_addr     = c7x_4_ddr_local_heap_addr + c7x_4_ddr_local_heap_size;
 c7x_4_ddr_scratch_non_cacheable_addr_phys     = c7x_4_ddr_local_heap_addr_phys + c7x_4_ddr_local_heap_size;
-c7x_4_ddr_scratch_non_cacheable_size     = 128*MB;
+c7x_4_ddr_scratch_non_cacheable_size     = 32*MB;
 c7x_4_ddr_scratch_addr = c7x_4_ddr_scratch_non_cacheable_addr + c7x_4_ddr_scratch_non_cacheable_size;
 c7x_4_ddr_scratch_addr_phys = c7x_4_ddr_scratch_non_cacheable_addr_phys + c7x_4_ddr_scratch_non_cacheable_size;
-c7x_4_ddr_scratch_size = 128*MB;
+c7x_4_ddr_scratch_size = 32*MB;
 total_c7x_4_scratch_ddr = c7x_4_ddr_scratch_non_cacheable_size + c7x_4_ddr_scratch_size
 
 total_c7x_4_ddr = total_c7x_4_local_ddr + total_c7x_4_scratch_ddr
 
 total_c7x_ddr = total_c7x_1_ddr + total_c7x_2_ddr + total_c7x_3_ddr + total_c7x_4_ddr
 
-# Virtual address for C7x 1 corresponding to physical addresses for C7x2, C7x3, C7x4
-c7x_1_2_ddr_local_heap_non_cacheable_addr = c7x_1_ddr_scratch_addr + c7x_1_ddr_scratch_size;
-c7x_1_3_ddr_local_heap_non_cacheable_addr = c7x_1_2_ddr_local_heap_non_cacheable_addr + c7x_2_ddr_local_heap_non_cacheable_size;
-c7x_1_4_ddr_local_heap_non_cacheable_addr = c7x_1_3_ddr_local_heap_non_cacheable_addr + c7x_3_ddr_local_heap_non_cacheable_size;
-
-c7x_1_2_ddr_local_heap_addr = c7x_1_4_ddr_local_heap_non_cacheable_addr + c7x_4_ddr_local_heap_non_cacheable_size;
-c7x_1_3_ddr_local_heap_addr = c7x_1_2_ddr_local_heap_addr + c7x_2_ddr_local_heap_size;
-c7x_1_4_ddr_local_heap_addr = c7x_1_3_ddr_local_heap_addr + c7x_3_ddr_local_heap_size;
-
-c7x_1_2_ddr_scratch_non_cacheable_addr = c7x_1_4_ddr_local_heap_addr + c7x_4_ddr_local_heap_size;
-c7x_1_3_ddr_scratch_non_cacheable_addr = c7x_1_2_ddr_scratch_non_cacheable_addr + c7x_2_ddr_scratch_non_cacheable_size;
-c7x_1_4_ddr_scratch_non_cacheable_addr = c7x_1_3_ddr_scratch_non_cacheable_addr + c7x_3_ddr_scratch_non_cacheable_size;
-
-c7x_1_2_ddr_scratch_addr = c7x_1_4_ddr_scratch_non_cacheable_addr + c7x_4_ddr_scratch_non_cacheable_size;
-c7x_1_3_ddr_scratch_addr = c7x_1_2_ddr_scratch_addr + c7x_2_ddr_scratch_size;
-c7x_1_4_ddr_scratch_addr = c7x_1_3_ddr_scratch_addr + c7x_3_ddr_scratch_size;
-
-# Virtual address for C7x 2 corresponding to physical addresses for C7x1, C7x3, C7x4
-c7x_2_1_ddr_local_heap_non_cacheable_addr = c7x_2_ddr_scratch_addr + c7x_2_ddr_scratch_size;
-c7x_2_3_ddr_local_heap_non_cacheable_addr = c7x_2_1_ddr_local_heap_non_cacheable_addr + c7x_1_ddr_local_heap_non_cacheable_size;
-c7x_2_4_ddr_local_heap_non_cacheable_addr = c7x_2_3_ddr_local_heap_non_cacheable_addr + c7x_3_ddr_local_heap_non_cacheable_size;
-
-c7x_2_1_ddr_local_heap_addr = c7x_2_4_ddr_local_heap_non_cacheable_addr + c7x_4_ddr_local_heap_non_cacheable_size;
-c7x_2_3_ddr_local_heap_addr = c7x_2_1_ddr_local_heap_addr + c7x_1_ddr_local_heap_size;
-c7x_2_4_ddr_local_heap_addr = c7x_2_3_ddr_local_heap_addr + c7x_3_ddr_local_heap_size;
-
-c7x_2_1_ddr_scratch_non_cacheable_addr = c7x_2_4_ddr_local_heap_addr + c7x_4_ddr_local_heap_size;
-c7x_2_3_ddr_scratch_non_cacheable_addr = c7x_2_1_ddr_scratch_non_cacheable_addr + c7x_1_ddr_scratch_non_cacheable_size;
-c7x_2_4_ddr_scratch_non_cacheable_addr = c7x_2_3_ddr_scratch_non_cacheable_addr + c7x_3_ddr_scratch_non_cacheable_size;
-
-c7x_2_1_ddr_scratch_addr = c7x_2_4_ddr_scratch_non_cacheable_addr + c7x_4_ddr_scratch_non_cacheable_size;
-c7x_2_3_ddr_scratch_addr = c7x_2_1_ddr_scratch_addr + c7x_1_ddr_scratch_size;
-c7x_2_4_ddr_scratch_addr = c7x_2_3_ddr_scratch_addr + c7x_3_ddr_scratch_size;
-
-# Virtual address for C7x 3 corresponding to physical addresses for C7x1, C7x2, C7x4
-c7x_3_1_ddr_local_heap_non_cacheable_addr = c7x_3_ddr_scratch_addr + c7x_3_ddr_scratch_size;
-c7x_3_2_ddr_local_heap_non_cacheable_addr = c7x_3_1_ddr_local_heap_non_cacheable_addr + c7x_1_ddr_local_heap_non_cacheable_size;
-c7x_3_4_ddr_local_heap_non_cacheable_addr = c7x_3_2_ddr_local_heap_non_cacheable_addr + c7x_2_ddr_local_heap_non_cacheable_size;
-
-c7x_3_1_ddr_local_heap_addr = c7x_3_4_ddr_local_heap_non_cacheable_addr + c7x_4_ddr_local_heap_non_cacheable_size;
-c7x_3_2_ddr_local_heap_addr = c7x_3_1_ddr_local_heap_addr + c7x_1_ddr_local_heap_size;
-c7x_3_4_ddr_local_heap_addr = c7x_3_2_ddr_local_heap_addr + c7x_2_ddr_local_heap_size;
-
-c7x_3_1_ddr_scratch_non_cacheable_addr = c7x_3_4_ddr_local_heap_addr + c7x_4_ddr_local_heap_size;
-c7x_3_2_ddr_scratch_non_cacheable_addr = c7x_3_1_ddr_scratch_non_cacheable_addr + c7x_1_ddr_scratch_non_cacheable_size;
-c7x_3_4_ddr_scratch_non_cacheable_addr = c7x_3_2_ddr_scratch_non_cacheable_addr + c7x_2_ddr_scratch_non_cacheable_size;
-
-c7x_3_1_ddr_scratch_addr = c7x_3_4_ddr_scratch_non_cacheable_addr + c7x_4_ddr_scratch_non_cacheable_size;
-c7x_3_2_ddr_scratch_addr = c7x_3_1_ddr_scratch_addr + c7x_1_ddr_scratch_size;
-c7x_3_4_ddr_scratch_addr = c7x_3_2_ddr_scratch_addr + c7x_2_ddr_scratch_size;
-
-# Virtual address for C7x 4 corresponding to physical addresses for C7x1, C7x2, C7x3
-c7x_4_1_ddr_local_heap_non_cacheable_addr = c7x_4_ddr_scratch_addr + c7x_4_ddr_scratch_size;
-c7x_4_2_ddr_local_heap_non_cacheable_addr = c7x_4_1_ddr_local_heap_non_cacheable_addr + c7x_1_ddr_local_heap_non_cacheable_size;
-c7x_4_3_ddr_local_heap_non_cacheable_addr = c7x_4_2_ddr_local_heap_non_cacheable_addr + c7x_2_ddr_local_heap_non_cacheable_size;
-
-c7x_4_1_ddr_local_heap_addr = c7x_4_3_ddr_local_heap_non_cacheable_addr + c7x_3_ddr_local_heap_non_cacheable_size;
-c7x_4_2_ddr_local_heap_addr = c7x_4_1_ddr_local_heap_addr + c7x_1_ddr_local_heap_size;
-c7x_4_3_ddr_local_heap_addr = c7x_4_2_ddr_local_heap_addr + c7x_2_ddr_local_heap_size;
-
-c7x_4_1_ddr_scratch_non_cacheable_addr = c7x_4_3_ddr_local_heap_addr + c7x_3_ddr_local_heap_size;
-c7x_4_2_ddr_scratch_non_cacheable_addr = c7x_4_1_ddr_scratch_non_cacheable_addr + c7x_1_ddr_scratch_non_cacheable_size;
-c7x_4_3_ddr_scratch_non_cacheable_addr = c7x_4_2_ddr_scratch_non_cacheable_addr + c7x_2_ddr_scratch_non_cacheable_size;
-
-c7x_4_1_ddr_scratch_addr = c7x_4_3_ddr_scratch_non_cacheable_addr + c7x_3_ddr_scratch_non_cacheable_size;
-c7x_4_2_ddr_scratch_addr = c7x_4_1_ddr_scratch_addr + c7x_1_ddr_scratch_size;
-c7x_4_3_ddr_scratch_addr = c7x_4_2_ddr_scratch_addr + c7x_2_ddr_scratch_size;
-
 # Shared memory for DMA Buf FD carveout (located in high mem)
 ddr_shared_mem_addr_phys  = c7x_4_ddr_scratch_addr_phys + c7x_4_ddr_scratch_size;
+ddr_shared_mem_addr       = c7x_4_ddr_scratch_addr_phys + c7x_4_ddr_scratch_size;
 ddr_shared_mem_size       = SHARED_MEM_SIZE - uboot_reloc_mem_size;
 
 #
@@ -642,21 +571,6 @@ c7x_1_ddr_scratch_non_cacheable_phys    = MemSection("DDR_C7X_1_SCRATCH_NON_CACH
 c7x_1_ddr_scratch         = MemSection("DDR_C7X_1_SCRATCH", "RWIX", c7x_1_ddr_scratch_addr, c7x_1_ddr_scratch_size, "Virtual address of cacheable DDR for c7x_1 for Scratch Memory");
 c7x_1_ddr_scratch_phys    = MemSection("DDR_C7X_1_SCRATCH_PHYS", "RWIX", c7x_1_ddr_scratch_addr_phys, c7x_1_ddr_scratch_size, "Physical address of cacheable DDR for c7x_1 for Scratch Memory");
 
-c7x_1_2_ddr_local_heap_non_cacheable = MemSection("DDR_C7X_1_2_LOCAL_HEAP_NON_CACHEABLE", "RWIX", c7x_1_2_ddr_local_heap_non_cacheable_addr, c7x_2_ddr_local_heap_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_2 for local heap wrt c7x_1");
-c7x_1_2_ddr_local_heap      = MemSection("DDR_C7X_1_2_LOCAL_HEAP", "RWIX", c7x_1_2_ddr_local_heap_addr, c7x_2_ddr_local_heap_size, "Virtual address of cacheable DDR for c7x_2 for local heap wrt c7x_1");
-c7x_1_2_ddr_scratch_non_cacheable         = MemSection("DDR_C7X_1_2_SCRATCH_NON_CACHEABLE", "RWIX", c7x_1_2_ddr_scratch_non_cacheable_addr, c7x_2_ddr_scratch_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_2 for Scratch Memory wrt c7x_1");
-c7x_1_2_ddr_scratch         = MemSection("DDR_C7X_1_2_SCRATCH", "RWIX", c7x_1_2_ddr_scratch_addr, c7x_2_ddr_scratch_size, "Virtual address of cacheable DDR for c7x_2 for Scratch Memory wrt c7x_1");
-
-c7x_1_3_ddr_local_heap_non_cacheable = MemSection("DDR_C7X_1_3_LOCAL_HEAP_NON_CACHEABLE", "RWIX", c7x_1_3_ddr_local_heap_non_cacheable_addr, c7x_3_ddr_local_heap_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_3 for local heap wrt c7x_1");
-c7x_1_3_ddr_local_heap      = MemSection("DDR_C7X_1_3_LOCAL_HEAP", "RWIX", c7x_1_3_ddr_local_heap_addr, c7x_3_ddr_local_heap_size, "Virtual address of cacheable DDR for c7x_3 for local heap wrt c7x_1");
-c7x_1_3_ddr_scratch_non_cacheable         = MemSection("DDR_C7X_1_3_SCRATCH_NON_CACHEABLE", "RWIX", c7x_1_3_ddr_scratch_non_cacheable_addr, c7x_3_ddr_scratch_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_3 for Scratch Memory wrt c7x_1");
-c7x_1_3_ddr_scratch         = MemSection("DDR_C7X_1_3_SCRATCH", "RWIX", c7x_1_3_ddr_scratch_addr, c7x_3_ddr_scratch_size, "Virtual address of cacheable DDR for c7x_3 for Scratch Memory wrt c7x_1");
-
-c7x_1_4_ddr_local_heap_non_cacheable = MemSection("DDR_C7X_1_4_LOCAL_HEAP_NON_CACHEABLE", "RWIX", c7x_1_4_ddr_local_heap_non_cacheable_addr, c7x_4_ddr_local_heap_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_4 for local heap wrt c7x_1");
-c7x_1_4_ddr_local_heap      = MemSection("DDR_C7X_1_4_LOCAL_HEAP", "RWIX", c7x_1_4_ddr_local_heap_addr, c7x_4_ddr_local_heap_size, "Virtual address of cacheable DDR for c7x_4 for local heap wrt c7x_1");
-c7x_1_4_ddr_scratch_non_cacheable         = MemSection("DDR_C7X_1_4_SCRATCH_NON_CACHEABLE", "RWIX", c7x_1_4_ddr_scratch_non_cacheable_addr, c7x_4_ddr_scratch_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_4 for Scratch Memory wrt c7x_1");
-c7x_1_4_ddr_scratch         = MemSection("DDR_C7X_1_4_SCRATCH", "RWIX", c7x_1_4_ddr_scratch_addr, c7x_4_ddr_scratch_size, "Virtual address of cacheable DDR for c7x_4 for Scratch Memory wrt c7x_1");
-
 c7x_1_ddr_total           = MemSection("DDR_C7x_1_DTS", "", 0, 0, "DDR for C7x_1 for all sections, used for reserving memory in DTS file");
 c7x_1_ddr_total.concat(c7x_1_ddr_resource_table);
 c7x_1_ddr_total.concat(c7x_1_ddr_boot);
@@ -681,21 +595,6 @@ c7x_2_ddr_scratch_non_cacheable_phys    = MemSection("DDR_C7X_2_SCRATCH_NON_CACH
 c7x_2_ddr_scratch         = MemSection("DDR_C7X_2_SCRATCH", "RWIX", c7x_2_ddr_scratch_addr, c7x_2_ddr_scratch_size, "Virtual address of cacheable DDR for c7x_2 for Scratch Memory");
 c7x_2_ddr_scratch_phys    = MemSection("DDR_C7X_2_SCRATCH_PHYS", "RWIX", c7x_2_ddr_scratch_addr_phys, c7x_2_ddr_scratch_size, "Physical address of cacheable DDR for c7x_2 for Scratch Memory");
 
-c7x_2_1_ddr_local_heap_non_cacheable = MemSection("DDR_C7X_2_1_LOCAL_HEAP_NON_CACHEABLE", "RWIX", c7x_2_1_ddr_local_heap_non_cacheable_addr, c7x_1_ddr_local_heap_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_1 for local heap wrt c7x_2");
-c7x_2_1_ddr_local_heap      = MemSection("DDR_C7X_2_1_LOCAL_HEAP", "RWIX", c7x_2_1_ddr_local_heap_addr, c7x_1_ddr_local_heap_size, "Virtual address of cacheable DDR for c7x_1 for local heap wrt c7x_2");
-c7x_2_1_ddr_scratch_non_cacheable         = MemSection("DDR_C7X_2_1_SCRATCH_NON_CACHEABLE", "RWIX", c7x_2_1_ddr_scratch_non_cacheable_addr, c7x_1_ddr_scratch_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_1 for Scratch Memory wrt c7x_2");
-c7x_2_1_ddr_scratch         = MemSection("DDR_C7X_2_1_SCRATCH", "RWIX", c7x_2_1_ddr_scratch_addr, c7x_1_ddr_scratch_size, "Virtual address of cacheable DDR for c7x_1 for Scratch Memory wrt c7x_2");
-
-c7x_2_3_ddr_local_heap_non_cacheable = MemSection("DDR_C7X_2_3_LOCAL_HEAP_NON_CACHEABLE", "RWIX", c7x_2_3_ddr_local_heap_non_cacheable_addr, c7x_3_ddr_local_heap_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_3 for local heap wrt c7x_2");
-c7x_2_3_ddr_local_heap      = MemSection("DDR_C7X_2_3_LOCAL_HEAP", "RWIX", c7x_2_3_ddr_local_heap_addr, c7x_3_ddr_local_heap_size, "Virtual address of cacheable DDR for c7x_3 for local heap wrt c7x_2");
-c7x_2_3_ddr_scratch_non_cacheable         = MemSection("DDR_C7X_2_3_SCRATCH_NON_CACHEABLE", "RWIX", c7x_2_3_ddr_scratch_non_cacheable_addr, c7x_3_ddr_scratch_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_3 for Scratch Memory wrt c7x_2");
-c7x_2_3_ddr_scratch         = MemSection("DDR_C7X_2_3_SCRATCH", "RWIX", c7x_2_3_ddr_scratch_addr, c7x_3_ddr_scratch_size, "Virtual address of cacheable DDR for c7x_3 for Scratch Memory wrt c7x_2");
-
-c7x_2_4_ddr_local_heap_non_cacheable = MemSection("DDR_C7X_2_4_LOCAL_HEAP_NON_CACHEABLE", "RWIX", c7x_2_4_ddr_local_heap_non_cacheable_addr, c7x_4_ddr_local_heap_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_4 for local heap wrt c7x_2");
-c7x_2_4_ddr_local_heap      = MemSection("DDR_C7X_2_4_LOCAL_HEAP", "RWIX", c7x_2_4_ddr_local_heap_addr, c7x_4_ddr_local_heap_size, "Virtual address of cacheable DDR for c7x_4 for local heap wrt c7x_2");
-c7x_2_4_ddr_scratch_non_cacheable         = MemSection("DDR_C7X_2_4_SCRATCH_NON_CACHEABLE", "RWIX", c7x_2_4_ddr_scratch_non_cacheable_addr, c7x_4_ddr_scratch_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_4 for Scratch Memory wrt c7x_2");
-c7x_2_4_ddr_scratch         = MemSection("DDR_C7X_2_4_SCRATCH", "RWIX", c7x_2_4_ddr_scratch_addr, c7x_4_ddr_scratch_size, "Virtual address of cacheable DDR for c7x_4 for Scratch Memory wrt c7x_2");
-
 c7x_2_ddr_total           = MemSection("DDR_C7x_2_DTS", "", 0, 0, "DDR for C7x_2 for all sections, used for reserving memory in DTS file");
 c7x_2_ddr_total.concat(c7x_2_ddr_resource_table);
 c7x_2_ddr_total.concat(c7x_2_ddr_boot);
@@ -720,21 +619,6 @@ c7x_3_ddr_scratch_non_cacheable_phys    = MemSection("DDR_C7X_3_SCRATCH_NON_CACH
 c7x_3_ddr_scratch         = MemSection("DDR_C7X_3_SCRATCH", "RWIX", c7x_3_ddr_scratch_addr, c7x_3_ddr_scratch_size, "Virtual address of cacheable DDR for c7x_3 for Scratch Memory");
 c7x_3_ddr_scratch_phys    = MemSection("DDR_C7X_3_SCRATCH_PHYS", "RWIX", c7x_3_ddr_scratch_addr_phys, c7x_3_ddr_scratch_size, "Physical address of cacheable DDR for c7x_3 for Scratch Memory");
 
-c7x_3_1_ddr_local_heap_non_cacheable = MemSection("DDR_C7X_3_1_LOCAL_HEAP_NON_CACHEABLE", "RWIX", c7x_3_1_ddr_local_heap_non_cacheable_addr, c7x_1_ddr_local_heap_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_1 for local heap wrt c7x_3");
-c7x_3_1_ddr_local_heap      = MemSection("DDR_C7X_3_1_LOCAL_HEAP", "RWIX", c7x_3_1_ddr_local_heap_addr, c7x_1_ddr_local_heap_size, "Virtual address of cacheable DDR for c7x_1 for local heap wrt c7x_3");
-c7x_3_1_ddr_scratch_non_cacheable         = MemSection("DDR_C7X_3_1_SCRATCH_NON_CACHEABLE", "RWIX", c7x_3_1_ddr_scratch_non_cacheable_addr, c7x_1_ddr_scratch_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_1 for Scratch Memory wrt c7x_3");
-c7x_3_1_ddr_scratch         = MemSection("DDR_C7X_3_1_SCRATCH", "RWIX", c7x_3_1_ddr_scratch_addr, c7x_1_ddr_scratch_size, "Virtual address of cacheable DDR for c7x_1 for Scratch Memory wrt c7x_3");
-
-c7x_3_2_ddr_local_heap_non_cacheable = MemSection("DDR_C7X_3_2_LOCAL_HEAP_NON_CACHEABLE", "RWIX", c7x_3_2_ddr_local_heap_non_cacheable_addr, c7x_2_ddr_local_heap_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_2 for local heap wrt c7x_3");
-c7x_3_2_ddr_local_heap      = MemSection("DDR_C7X_3_2_LOCAL_HEAP", "RWIX", c7x_3_2_ddr_local_heap_addr, c7x_2_ddr_local_heap_size, "Virtual address of cacheable DDR for c7x_2 for local heap wrt c7x_3");
-c7x_3_2_ddr_scratch_non_cacheable         = MemSection("DDR_C7X_3_2_SCRATCH_NON_CACHEABLE", "RWIX", c7x_3_2_ddr_scratch_non_cacheable_addr, c7x_2_ddr_scratch_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_2 for Scratch Memory wrt c7x_3");
-c7x_3_2_ddr_scratch         = MemSection("DDR_C7X_3_2_SCRATCH", "RWIX", c7x_3_2_ddr_scratch_addr, c7x_2_ddr_scratch_size, "Virtual address of cacheable DDR for c7x_2 for Scratch Memory wrt c7x_3");
-
-c7x_3_4_ddr_local_heap_non_cacheable = MemSection("DDR_C7X_3_4_LOCAL_HEAP_NON_CACHEABLE", "RWIX", c7x_3_4_ddr_local_heap_non_cacheable_addr, c7x_4_ddr_local_heap_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_4 for local heap wrt c7x_3");
-c7x_3_4_ddr_local_heap      = MemSection("DDR_C7X_3_4_LOCAL_HEAP", "RWIX", c7x_3_4_ddr_local_heap_addr, c7x_4_ddr_local_heap_size, "Virtual address of cacheable DDR for c7x_4 for local heap wrt c7x_3");
-c7x_3_4_ddr_scratch_non_cacheable         = MemSection("DDR_C7X_3_4_SCRATCH_NON_CACHEABLE", "RWIX", c7x_3_4_ddr_scratch_non_cacheable_addr, c7x_4_ddr_scratch_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_4 for Scratch Memory wrt c7x_3");
-c7x_3_4_ddr_scratch         = MemSection("DDR_C7X_3_4_SCRATCH", "RWIX", c7x_3_4_ddr_scratch_addr, c7x_4_ddr_scratch_size, "Virtual address of cacheable DDR for c7x_4 for Scratch Memory wrt c7x_3");
-
 c7x_3_ddr_total           = MemSection("DDR_C7x_3_DTS", "", 0, 0, "DDR for C7x_3 for all sections, used for reserving memory in DTS file");
 c7x_3_ddr_total.concat(c7x_3_ddr_resource_table);
 c7x_3_ddr_total.concat(c7x_3_ddr_boot);
@@ -759,21 +643,6 @@ c7x_4_ddr_scratch_non_cacheable_phys    = MemSection("DDR_C7X_4_SCRATCH_NON_CACH
 c7x_4_ddr_scratch         = MemSection("DDR_C7X_4_SCRATCH", "RWIX", c7x_4_ddr_scratch_addr, c7x_4_ddr_scratch_size, "Virtual address of cacheable DDR for c7x_4 for Scratch Memory");
 c7x_4_ddr_scratch_phys    = MemSection("DDR_C7X_4_SCRATCH_PHYS", "RWIX", c7x_4_ddr_scratch_addr_phys, c7x_4_ddr_scratch_size, "Physical address of cacheable DDR for c7x_4 for Scratch Memory");
 
-c7x_4_1_ddr_local_heap_non_cacheable = MemSection("DDR_C7X_4_1_LOCAL_HEAP_NON_CACHEABLE", "RWIX", c7x_4_1_ddr_local_heap_non_cacheable_addr, c7x_1_ddr_local_heap_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_1 for local heap wrt c7x_4");
-c7x_4_1_ddr_local_heap      = MemSection("DDR_C7X_4_1_LOCAL_HEAP", "RWIX", c7x_4_1_ddr_local_heap_addr, c7x_1_ddr_local_heap_size, "Virtual address of cacheable DDR for c7x_1 for local heap wrt c7x_4");
-c7x_4_1_ddr_scratch_non_cacheable         = MemSection("DDR_C7X_4_1_SCRATCH_NON_CACHEABLE", "RWIX", c7x_4_1_ddr_scratch_non_cacheable_addr, c7x_1_ddr_scratch_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_1 for Scratch Memory wrt c7x_4");
-c7x_4_1_ddr_scratch         = MemSection("DDR_C7X_4_1_SCRATCH", "RWIX", c7x_4_1_ddr_scratch_addr, c7x_1_ddr_scratch_size, "Virtual address of cacheable DDR for c7x_1 for Scratch Memory wrt c7x_4");
-
-c7x_4_2_ddr_local_heap_non_cacheable = MemSection("DDR_C7X_4_2_LOCAL_HEAP_NON_CACHEABLE", "RWIX", c7x_4_2_ddr_local_heap_non_cacheable_addr, c7x_2_ddr_local_heap_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_2 for local heap wrt c7x_4");
-c7x_4_2_ddr_local_heap      = MemSection("DDR_C7X_4_2_LOCAL_HEAP", "RWIX", c7x_4_2_ddr_local_heap_addr, c7x_2_ddr_local_heap_size, "Virtual address of cacheable DDR for c7x_2 for local heap wrt c7x_4");
-c7x_4_2_ddr_scratch_non_cacheable         = MemSection("DDR_C7X_4_2_SCRATCH_NON_CACHEABLE", "RWIX", c7x_4_2_ddr_scratch_non_cacheable_addr, c7x_2_ddr_scratch_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_2 for Scratch Memory wrt c7x_4");
-c7x_4_2_ddr_scratch         = MemSection("DDR_C7X_4_2_SCRATCH", "RWIX", c7x_4_2_ddr_scratch_addr, c7x_2_ddr_scratch_size, "Virtual address of cacheable DDR for c7x_2 for Scratch Memory wrt c7x_4");
-
-c7x_4_3_ddr_local_heap_non_cacheable = MemSection("DDR_C7X_4_3_LOCAL_HEAP_NON_CACHEABLE", "RWIX", c7x_4_3_ddr_local_heap_non_cacheable_addr, c7x_3_ddr_local_heap_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_3 for local heap wrt c7x_4");
-c7x_4_3_ddr_local_heap      = MemSection("DDR_C7X_4_3_LOCAL_HEAP", "RWIX", c7x_4_3_ddr_local_heap_addr, c7x_3_ddr_local_heap_size, "Virtual address of cacheable DDR for c7x_3 for local heap wrt c7x_4");
-c7x_4_3_ddr_scratch_non_cacheable         = MemSection("DDR_C7X_4_3_SCRATCH_NON_CACHEABLE", "RWIX", c7x_4_3_ddr_scratch_non_cacheable_addr, c7x_3_ddr_scratch_non_cacheable_size, "Virtual address of non-cacheable DDR for c7x_3 for Scratch Memory wrt c7x_4");
-c7x_4_3_ddr_scratch         = MemSection("DDR_C7X_4_3_SCRATCH", "RWIX", c7x_4_3_ddr_scratch_addr, c7x_3_ddr_scratch_size, "Virtual address of cacheable DDR for c7x_3 for Scratch Memory wrt c7x_4");
-
 c7x_4_ddr_total           = MemSection("DDR_C7x_4_DTS", "", 0, 0, "DDR for C7x_4 for all sections, used for reserving memory in DTS file");
 c7x_4_ddr_total.concat(c7x_4_ddr_resource_table);
 c7x_4_ddr_total.concat(c7x_4_ddr_boot);
@@ -782,6 +651,8 @@ c7x_4_ddr_total.concat(c7x_4_ddr_secure_vecs);
 c7x_4_ddr_total.concat(c7x_4_ddr);
 c7x_4_ddr_total.setDtsName("vision_apps_c71_3_memory_region", "vision-apps-c71_3-memory");
 
+c7x_ddr_high_mem_phy  = MemSection("DDR_C7X_HIGH_MEM", "RWIX", c7x_1_ddr_local_heap_non_cacheable_addr_phys, total_c7x_ddr, "High mem sections for c7x-1 thru c7x-4 for code/data, local heap and scratch");
+
 # Shared memory memory sections in DDR
 app_log_mem            = MemSection("APP_LOG_MEM"        , "", app_log_mem_addr       , app_log_mem_size       , "Memory for remote core logging");
 tiovx_obj_desc_mem     = MemSection("TIOVX_OBJ_DESC_MEM" , "", tiovx_obj_desc_mem_addr, tiovx_obj_desc_mem_size, "Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent");
@@ -808,15 +679,9 @@ vision_apps_core_heaps_lo.concat(mcu3_1_ddr_local_heap);
 vision_apps_core_heaps_lo.concat(mcu4_0_ddr_local_heap);
 vision_apps_core_heaps_lo.concat(mcu4_0_ddr_viss_config_heap);
 vision_apps_core_heaps_lo.concat(mcu4_1_ddr_local_heap);
+vision_apps_core_heaps_lo.concat(c7x_ddr_high_mem_phy);
 vision_apps_core_heaps_lo.setDtsName("vision_apps_core_heaps_lo", "vision-apps-core-heap-memory-lo");
 
-c7x_ddr_high_mem_phy  = MemSection("DDR_C7X_HIGH_MEM", "RWIX", ddr_mem_addr_hi_phys, total_c7x_ddr, "High mem sections for c7x-1 thru c7x-4 for code/data, local heap and scratch");
-
-c7x_ddr_heaps_hi = MemSection("DDR_C7X_HIGH_MEM_DTS", "", 0, 0, "C7X DDR memory sections in 40bit address range of DDR");
-c7x_ddr_heaps_hi.concat(c7x_ddr_high_mem_phy);
-c7x_ddr_heaps_hi.setDtsName("c7x_ddr_heaps_hi", "c7x-ddr-heaps-hi");
-c7x_ddr_heaps_hi.splitOrigin(True)
-
 # this region should NOT have the "no-map" flag since we want ION to map this memory and do cache ops on it as needed
 ddr_shared_mem     = MemSection("DDR_SHARED_MEM"    , "", ddr_shared_mem_addr    , ddr_shared_mem_size    , "Memory for shared memory buffers in DDR");
 ddr_shared_mem_phys  = MemSection("DDR_SHARED_MEM_PHYS"    , "", ddr_shared_mem_addr_phys  , ddr_shared_mem_size    , "Physical address of memory for shared memory buffers in DDR");
@@ -985,18 +850,6 @@ c7x_1_mmap.addMemSection( c7x_1_ddr_local_heap_non_cacheable  );
 c7x_1_mmap.addMemSection( c7x_1_ddr_local_heap  );
 c7x_1_mmap.addMemSection( c7x_1_ddr_scratch_non_cacheable  );
 c7x_1_mmap.addMemSection( c7x_1_ddr_scratch  );
-c7x_1_mmap.addMemSection( c7x_1_2_ddr_local_heap_non_cacheable  );
-c7x_1_mmap.addMemSection( c7x_1_2_ddr_local_heap  );
-c7x_1_mmap.addMemSection( c7x_1_2_ddr_scratch_non_cacheable  );
-c7x_1_mmap.addMemSection( c7x_1_2_ddr_scratch  );
-c7x_1_mmap.addMemSection( c7x_1_3_ddr_local_heap_non_cacheable  );
-c7x_1_mmap.addMemSection( c7x_1_3_ddr_local_heap  );
-c7x_1_mmap.addMemSection( c7x_1_3_ddr_scratch_non_cacheable  );
-c7x_1_mmap.addMemSection( c7x_1_3_ddr_scratch  );
-c7x_1_mmap.addMemSection( c7x_1_4_ddr_local_heap_non_cacheable  );
-c7x_1_mmap.addMemSection( c7x_1_4_ddr_local_heap  );
-c7x_1_mmap.addMemSection( c7x_1_4_ddr_scratch_non_cacheable  );
-c7x_1_mmap.addMemSection( c7x_1_4_ddr_scratch  );
 c7x_1_mmap.addMemSection( ddr_shared_mem     );
 c7x_1_mmap.checkOverlap();
 
@@ -1018,18 +871,6 @@ c7x_2_mmap.addMemSection( c7x_2_ddr_local_heap_non_cacheable  );
 c7x_2_mmap.addMemSection( c7x_2_ddr_local_heap  );
 c7x_2_mmap.addMemSection( c7x_2_ddr_scratch_non_cacheable  );
 c7x_2_mmap.addMemSection( c7x_2_ddr_scratch  );
-c7x_2_mmap.addMemSection( c7x_2_1_ddr_local_heap_non_cacheable  );
-c7x_2_mmap.addMemSection( c7x_2_1_ddr_local_heap  );
-c7x_2_mmap.addMemSection( c7x_2_1_ddr_scratch_non_cacheable  );
-c7x_2_mmap.addMemSection( c7x_2_1_ddr_scratch  );
-c7x_2_mmap.addMemSection( c7x_2_3_ddr_local_heap_non_cacheable  );
-c7x_2_mmap.addMemSection( c7x_2_3_ddr_local_heap  );
-c7x_2_mmap.addMemSection( c7x_2_3_ddr_scratch_non_cacheable  );
-c7x_2_mmap.addMemSection( c7x_2_3_ddr_scratch  );
-c7x_2_mmap.addMemSection( c7x_2_4_ddr_local_heap_non_cacheable  );
-c7x_2_mmap.addMemSection( c7x_2_4_ddr_local_heap  );
-c7x_2_mmap.addMemSection( c7x_2_4_ddr_scratch_non_cacheable  );
-c7x_2_mmap.addMemSection( c7x_2_4_ddr_scratch  );
 c7x_2_mmap.addMemSection( ddr_shared_mem     );
 c7x_2_mmap.checkOverlap();
 
@@ -1051,18 +892,6 @@ c7x_3_mmap.addMemSection( c7x_3_ddr_local_heap_non_cacheable  );
 c7x_3_mmap.addMemSection( c7x_3_ddr_local_heap  );
 c7x_3_mmap.addMemSection( c7x_3_ddr_scratch_non_cacheable  );
 c7x_3_mmap.addMemSection( c7x_3_ddr_scratch  );
-c7x_3_mmap.addMemSection( c7x_3_1_ddr_local_heap_non_cacheable  );
-c7x_3_mmap.addMemSection( c7x_3_1_ddr_local_heap  );
-c7x_3_mmap.addMemSection( c7x_3_1_ddr_scratch_non_cacheable  );
-c7x_3_mmap.addMemSection( c7x_3_1_ddr_scratch  );
-c7x_3_mmap.addMemSection( c7x_3_2_ddr_local_heap_non_cacheable  );
-c7x_3_mmap.addMemSection( c7x_3_2_ddr_local_heap  );
-c7x_3_mmap.addMemSection( c7x_3_2_ddr_scratch_non_cacheable  );
-c7x_3_mmap.addMemSection( c7x_3_2_ddr_scratch  );
-c7x_3_mmap.addMemSection( c7x_3_4_ddr_local_heap_non_cacheable  );
-c7x_3_mmap.addMemSection( c7x_3_4_ddr_local_heap  );
-c7x_3_mmap.addMemSection( c7x_3_4_ddr_scratch_non_cacheable  );
-c7x_3_mmap.addMemSection( c7x_3_4_ddr_scratch  );
 c7x_3_mmap.addMemSection( ddr_shared_mem     );
 c7x_3_mmap.checkOverlap();
 
@@ -1084,18 +913,6 @@ c7x_4_mmap.addMemSection( c7x_4_ddr_local_heap_non_cacheable  );
 c7x_4_mmap.addMemSection( c7x_4_ddr_local_heap  );
 c7x_4_mmap.addMemSection( c7x_4_ddr_scratch_non_cacheable  );
 c7x_4_mmap.addMemSection( c7x_4_ddr_scratch  );
-c7x_4_mmap.addMemSection( c7x_4_1_ddr_local_heap_non_cacheable  );
-c7x_4_mmap.addMemSection( c7x_4_1_ddr_local_heap  );
-c7x_4_mmap.addMemSection( c7x_4_1_ddr_scratch_non_cacheable  );
-c7x_4_mmap.addMemSection( c7x_4_1_ddr_scratch  );
-c7x_4_mmap.addMemSection( c7x_4_2_ddr_local_heap_non_cacheable  );
-c7x_4_mmap.addMemSection( c7x_4_2_ddr_local_heap  );
-c7x_4_mmap.addMemSection( c7x_4_2_ddr_scratch_non_cacheable  );
-c7x_4_mmap.addMemSection( c7x_4_2_ddr_scratch  );
-c7x_4_mmap.addMemSection( c7x_4_3_ddr_local_heap_non_cacheable  );
-c7x_4_mmap.addMemSection( c7x_4_3_ddr_local_heap  );
-c7x_4_mmap.addMemSection( c7x_4_3_ddr_scratch_non_cacheable  );
-c7x_4_mmap.addMemSection( c7x_4_3_ddr_scratch  );
 c7x_4_mmap.addMemSection( ddr_shared_mem     );
 c7x_4_mmap.checkOverlap();
 
@@ -1158,18 +975,6 @@ html_mmap.addMemSection( c7x_1_ddr_local_heap_non_cacheable         );
 html_mmap.addMemSection( c7x_1_ddr_local_heap         );
 html_mmap.addMemSection( c7x_1_ddr_scratch_non_cacheable );
 html_mmap.addMemSection( c7x_1_ddr_scratch );
-html_mmap.addMemSection( c7x_1_2_ddr_local_heap_non_cacheable         );
-html_mmap.addMemSection( c7x_1_2_ddr_local_heap         );
-html_mmap.addMemSection( c7x_1_2_ddr_scratch_non_cacheable );
-html_mmap.addMemSection( c7x_1_2_ddr_scratch );
-html_mmap.addMemSection( c7x_1_3_ddr_local_heap_non_cacheable         );
-html_mmap.addMemSection( c7x_1_3_ddr_local_heap         );
-html_mmap.addMemSection( c7x_1_3_ddr_scratch_non_cacheable );
-html_mmap.addMemSection( c7x_1_3_ddr_scratch );
-html_mmap.addMemSection( c7x_1_4_ddr_local_heap_non_cacheable         );
-html_mmap.addMemSection( c7x_1_4_ddr_local_heap         );
-html_mmap.addMemSection( c7x_1_4_ddr_scratch_non_cacheable );
-html_mmap.addMemSection( c7x_1_4_ddr_scratch );
 html_mmap.addMemSection( c7x_2_ddr_ipc     );
 html_mmap.addMemSection( c7x_2_ddr_resource_table     );
 html_mmap.addMemSection( c7x_2_ddr_boot    );
@@ -1180,18 +985,6 @@ html_mmap.addMemSection( c7x_2_ddr_local_heap_non_cacheable         );
 html_mmap.addMemSection( c7x_2_ddr_local_heap         );
 html_mmap.addMemSection( c7x_2_ddr_scratch_non_cacheable );
 html_mmap.addMemSection( c7x_2_ddr_scratch );
-html_mmap.addMemSection( c7x_2_1_ddr_local_heap_non_cacheable         );
-html_mmap.addMemSection( c7x_2_1_ddr_local_heap         );
-html_mmap.addMemSection( c7x_2_1_ddr_scratch_non_cacheable );
-html_mmap.addMemSection( c7x_2_1_ddr_scratch );
-html_mmap.addMemSection( c7x_2_3_ddr_local_heap_non_cacheable         );
-html_mmap.addMemSection( c7x_2_3_ddr_local_heap         );
-html_mmap.addMemSection( c7x_2_3_ddr_scratch_non_cacheable );
-html_mmap.addMemSection( c7x_2_3_ddr_scratch );
-html_mmap.addMemSection( c7x_2_4_ddr_local_heap_non_cacheable         );
-html_mmap.addMemSection( c7x_2_4_ddr_local_heap         );
-html_mmap.addMemSection( c7x_2_4_ddr_scratch_non_cacheable );
-html_mmap.addMemSection( c7x_2_4_ddr_scratch );
 html_mmap.addMemSection( c7x_3_ddr_ipc     );
 html_mmap.addMemSection( c7x_3_ddr_resource_table     );
 html_mmap.addMemSection( c7x_3_ddr_boot    );
@@ -1202,18 +995,6 @@ html_mmap.addMemSection( c7x_3_ddr_local_heap_non_cacheable         );
 html_mmap.addMemSection( c7x_3_ddr_local_heap         );
 html_mmap.addMemSection( c7x_3_ddr_scratch_non_cacheable );
 html_mmap.addMemSection( c7x_3_ddr_scratch );
-html_mmap.addMemSection( c7x_3_1_ddr_local_heap_non_cacheable         );
-html_mmap.addMemSection( c7x_3_1_ddr_local_heap         );
-html_mmap.addMemSection( c7x_3_1_ddr_scratch_non_cacheable );
-html_mmap.addMemSection( c7x_3_1_ddr_scratch );
-html_mmap.addMemSection( c7x_3_2_ddr_local_heap_non_cacheable         );
-html_mmap.addMemSection( c7x_3_2_ddr_local_heap         );
-html_mmap.addMemSection( c7x_3_2_ddr_scratch_non_cacheable );
-html_mmap.addMemSection( c7x_3_2_ddr_scratch );
-html_mmap.addMemSection( c7x_3_4_ddr_local_heap_non_cacheable         );
-html_mmap.addMemSection( c7x_3_4_ddr_local_heap         );
-html_mmap.addMemSection( c7x_3_4_ddr_scratch_non_cacheable );
-html_mmap.addMemSection( c7x_3_4_ddr_scratch );
 html_mmap.addMemSection( c7x_4_ddr_ipc     );
 html_mmap.addMemSection( c7x_4_ddr_resource_table     );
 html_mmap.addMemSection( c7x_4_ddr_boot    );
@@ -1224,18 +1005,6 @@ html_mmap.addMemSection( c7x_4_ddr_local_heap_non_cacheable         );
 html_mmap.addMemSection( c7x_4_ddr_local_heap         );
 html_mmap.addMemSection( c7x_4_ddr_scratch_non_cacheable );
 html_mmap.addMemSection( c7x_4_ddr_scratch );
-html_mmap.addMemSection( c7x_4_1_ddr_local_heap_non_cacheable         );
-html_mmap.addMemSection( c7x_4_1_ddr_local_heap         );
-html_mmap.addMemSection( c7x_4_1_ddr_scratch_non_cacheable );
-html_mmap.addMemSection( c7x_4_1_ddr_scratch );
-html_mmap.addMemSection( c7x_4_2_ddr_local_heap_non_cacheable         );
-html_mmap.addMemSection( c7x_4_2_ddr_local_heap         );
-html_mmap.addMemSection( c7x_4_2_ddr_scratch_non_cacheable );
-html_mmap.addMemSection( c7x_4_2_ddr_scratch );
-html_mmap.addMemSection( c7x_4_3_ddr_local_heap_non_cacheable         );
-html_mmap.addMemSection( c7x_4_3_ddr_local_heap         );
-html_mmap.addMemSection( c7x_4_3_ddr_scratch_non_cacheable );
-html_mmap.addMemSection( c7x_4_3_ddr_scratch );
 
 html_mmap.addMemSection( c7x_1_ddr_local_heap_non_cacheable_phys         );
 html_mmap.addMemSection( c7x_1_ddr_local_heap_phys         );
@@ -1325,18 +1094,6 @@ c_header_mmap.addMemSection( c7x_1_ddr_scratch_non_cacheable);
 c_header_mmap.addMemSection( c7x_1_ddr_scratch_non_cacheable_phys);
 c_header_mmap.addMemSection( c7x_1_ddr_scratch);
 c_header_mmap.addMemSection( c7x_1_ddr_scratch_phys);
-c_header_mmap.addMemSection( c7x_1_2_ddr_local_heap_non_cacheable);
-c_header_mmap.addMemSection( c7x_1_2_ddr_local_heap);
-c_header_mmap.addMemSection( c7x_1_2_ddr_scratch_non_cacheable);
-c_header_mmap.addMemSection( c7x_1_2_ddr_scratch);
-c_header_mmap.addMemSection( c7x_1_3_ddr_local_heap_non_cacheable);
-c_header_mmap.addMemSection( c7x_1_3_ddr_local_heap);
-c_header_mmap.addMemSection( c7x_1_3_ddr_scratch_non_cacheable);
-c_header_mmap.addMemSection( c7x_1_3_ddr_scratch);
-c_header_mmap.addMemSection( c7x_1_4_ddr_local_heap_non_cacheable);
-c_header_mmap.addMemSection( c7x_1_4_ddr_local_heap);
-c_header_mmap.addMemSection( c7x_1_4_ddr_scratch_non_cacheable);
-c_header_mmap.addMemSection( c7x_1_4_ddr_scratch);
 
 c_header_mmap.addMemSection( c7x_2_ddr_local_heap_non_cacheable);
 c_header_mmap.addMemSection( c7x_2_ddr_local_heap_non_cacheable_phys);
@@ -1346,18 +1103,6 @@ c_header_mmap.addMemSection( c7x_2_ddr_scratch_non_cacheable);
 c_header_mmap.addMemSection( c7x_2_ddr_scratch_non_cacheable_phys);
 c_header_mmap.addMemSection( c7x_2_ddr_scratch);
 c_header_mmap.addMemSection( c7x_2_ddr_scratch_phys);
-c_header_mmap.addMemSection( c7x_2_1_ddr_local_heap_non_cacheable);
-c_header_mmap.addMemSection( c7x_2_1_ddr_local_heap);
-c_header_mmap.addMemSection( c7x_2_1_ddr_scratch_non_cacheable);
-c_header_mmap.addMemSection( c7x_2_1_ddr_scratch);
-c_header_mmap.addMemSection( c7x_2_3_ddr_local_heap_non_cacheable);
-c_header_mmap.addMemSection( c7x_2_3_ddr_local_heap);
-c_header_mmap.addMemSection( c7x_2_3_ddr_scratch_non_cacheable);
-c_header_mmap.addMemSection( c7x_2_3_ddr_scratch);
-c_header_mmap.addMemSection( c7x_2_4_ddr_local_heap_non_cacheable);
-c_header_mmap.addMemSection( c7x_2_4_ddr_local_heap);
-c_header_mmap.addMemSection( c7x_2_4_ddr_scratch_non_cacheable);
-c_header_mmap.addMemSection( c7x_2_4_ddr_scratch);
 
 c_header_mmap.addMemSection( c7x_3_ddr_local_heap_non_cacheable);
 c_header_mmap.addMemSection( c7x_3_ddr_local_heap_non_cacheable_phys);
@@ -1367,18 +1112,6 @@ c_header_mmap.addMemSection( c7x_3_ddr_scratch_non_cacheable);
 c_header_mmap.addMemSection( c7x_3_ddr_scratch_non_cacheable_phys);
 c_header_mmap.addMemSection( c7x_3_ddr_scratch);
 c_header_mmap.addMemSection( c7x_3_ddr_scratch_phys);
-c_header_mmap.addMemSection( c7x_3_1_ddr_local_heap_non_cacheable);
-c_header_mmap.addMemSection( c7x_3_1_ddr_local_heap);
-c_header_mmap.addMemSection( c7x_3_1_ddr_scratch_non_cacheable);
-c_header_mmap.addMemSection( c7x_3_1_ddr_scratch);
-c_header_mmap.addMemSection( c7x_3_2_ddr_local_heap_non_cacheable);
-c_header_mmap.addMemSection( c7x_3_2_ddr_local_heap);
-c_header_mmap.addMemSection( c7x_3_2_ddr_scratch_non_cacheable);
-c_header_mmap.addMemSection( c7x_3_2_ddr_scratch);
-c_header_mmap.addMemSection( c7x_3_4_ddr_local_heap_non_cacheable);
-c_header_mmap.addMemSection( c7x_3_4_ddr_local_heap);
-c_header_mmap.addMemSection( c7x_3_4_ddr_scratch_non_cacheable);
-c_header_mmap.addMemSection( c7x_3_4_ddr_scratch);
 
 c_header_mmap.addMemSection( c7x_4_ddr_local_heap_non_cacheable);
 c_header_mmap.addMemSection( c7x_4_ddr_local_heap_non_cacheable_phys);
@@ -1388,18 +1121,6 @@ c_header_mmap.addMemSection( c7x_4_ddr_scratch_non_cacheable);
 c_header_mmap.addMemSection( c7x_4_ddr_scratch_non_cacheable_phys);
 c_header_mmap.addMemSection( c7x_4_ddr_scratch);
 c_header_mmap.addMemSection( c7x_4_ddr_scratch_phys);
-c_header_mmap.addMemSection( c7x_4_1_ddr_local_heap_non_cacheable);
-c_header_mmap.addMemSection( c7x_4_1_ddr_local_heap);
-c_header_mmap.addMemSection( c7x_4_1_ddr_scratch_non_cacheable);
-c_header_mmap.addMemSection( c7x_4_1_ddr_scratch);
-c_header_mmap.addMemSection( c7x_4_2_ddr_local_heap_non_cacheable);
-c_header_mmap.addMemSection( c7x_4_2_ddr_local_heap);
-c_header_mmap.addMemSection( c7x_4_2_ddr_scratch_non_cacheable);
-c_header_mmap.addMemSection( c7x_4_2_ddr_scratch);
-c_header_mmap.addMemSection( c7x_4_3_ddr_local_heap_non_cacheable);
-c_header_mmap.addMemSection( c7x_4_3_ddr_local_heap);
-c_header_mmap.addMemSection( c7x_4_3_ddr_scratch_non_cacheable);
-c_header_mmap.addMemSection( c7x_4_3_ddr_scratch);
 c_header_mmap.addMemSection( tiovx_log_rt_mem );
 c_header_mmap.addMemSection( app_log_mem        );
 c_header_mmap.addMemSection( tiovx_obj_desc_mem );
@@ -1450,7 +1171,6 @@ dts_mmap.addMemSection( c7x_4_ddr_total    );
 dts_mmap.addMemSection( vision_apps_ddr_total );
 dts_mmap.addMemSection( ipc_vring_mem      );
 dts_mmap.addMemSection( vision_apps_core_heaps_lo );
-dts_mmap.addMemSection( c7x_ddr_heaps_hi );
 dts_mmap.addMemSection( ddr_shared_mem_phys );
 dts_mmap.addMemSection( intercore_eth_desc_mem );
 dts_mmap.addMemSection( intercore_eth_data_mem );
