From c0fbf2c3db69a6aee0b5d86b98579adce88f8f9c Mon Sep 17 00:00:00 2001
From: Tarun Mukesh Puvvada <t-puvvada@ti.com>
Date: Thu, 16 Feb 2023 15:16:16 +0530
Subject: [PATCH] Added Communication for CDD IPC on mcu2_1 with A72

Signed-off-by: Tarun Mukesh Puvvada <t-puvvada@ti.com>
---
 build/Rules.make                              |  11 +
 build/j721e/r5_mpu_freertos.c                 |   4 +-
 .../CddIpc/ipc_baremetal_hw/src/ipc_virtio.c  |  12 +
 .../CddIpcRProcLinux/CddIpcAppRProcLinux.c    |  59 ++-
 .../CddIpcRProcLinux/CddIpcAppRProcLinux.h    |   2 +-
 .../examples/CddIpcRProcLinux/IpcRscTable.h   |   4 +-
 .../mcal/examples/CddIpcRProcLinux/IpcTrace.c |   2 +-
 .../mcal/examples/CddIpcRProcLinux/IpcTrace.h |   4 +-
 .../mcal/examples/CddIpcRProcLinux/makefile   |   3 +-
 .../soc/j721e/mcu2_1/CddIpcAppStartup.c       |  42 +-
 .../soc/j721e/mcu2_1/CddIpcR5Mpu.c            |   8 +-
 .../soc/j721e/mcu2_1/include/Cdd_IpcCfg.h     | 441 ++++++++++++++++
 .../soc/j721e/mcu2_1/src/Cdd_IpcCfg.c         | 475 ++++++++++++++++++
 13 files changed, 1024 insertions(+), 43 deletions(-)
 create mode 100644 mcal_drv/mcal/examples_config/CddIpcLinux_Demo_Cfg/output/generated/soc/j721e/mcu2_1/include/Cdd_IpcCfg.h
 create mode 100644 mcal_drv/mcal/examples_config/CddIpcLinux_Demo_Cfg/output/generated/soc/j721e/mcu2_1/src/Cdd_IpcCfg.c

diff --git a/build/Rules.make b/build/Rules.make
index 6cc7241..58c0e29 100644
--- a/build/Rules.make
+++ b/build/Rules.make
@@ -225,6 +225,11 @@ export CPLUSPLUS_BUILD ?= no
 #Default MCAL config - use base directory
 MCAL_CONFIG ?= 0
 
+#Variable to build Linux application
+CDD_IPC_LINUX_BUILD ?= no
+
+ifeq ($(CDD_IPC_LINUX_BUILD),no)
+
 # Get config path for each component
 MCAL_COMP_DIR_LIST = Mcu Adc Can Dio Eth EthTrcv Gpt Spi Wdg Pwm CddIpc Fls Icu
 define GET_MCAL_COMP_CONFIG_PATH
@@ -235,6 +240,12 @@ define GET_MCAL_COMP_CONFIG_PATH
     $(1)_CONFIG_PATH += $(MCUSW_INSTALL_PATH)/mcal_drv/mcal_test/ut_config/$(1)/config/config_$(MCAL_CONFIG)
   endif
 endef
+else
+MCAL_COMP_DIR_LIST = CddIpc
+define GET_MCAL_COMP_CONFIG_PATH
+    $(1)_CONFIG_PATH += $(autosarConfigSrc_PATH)/CddIpcLinux_Demo_Cfg/output/generated/soc/$(SOC)/$(CORE)/include
+  endef
+endif
 $(foreach MCAL_COMP,$(MCAL_COMP_DIR_LIST),$(eval $(call GET_MCAL_COMP_CONFIG_PATH,$(MCAL_COMP))))
 
 #Autosar generated config include files
diff --git a/build/j721e/r5_mpu_freertos.c b/build/j721e/r5_mpu_freertos.c
index 5b54e9a..e9dd67f 100644
--- a/build/j721e/r5_mpu_freertos.c
+++ b/build/j721e/r5_mpu_freertos.c
@@ -38,7 +38,9 @@
  *
  */
 
-#include <ti/csl/arch/csl_arch.h>
+#include <hw_include/arch/lld_arch.h>
+#include <hw_include/arch/r5/lld_arm_r5.h>
+#include <hw_include/arch/r5/lld_arm_r5_mpu.h>
 
 const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
 {
diff --git a/mcal_drv/mcal/CddIpc/ipc_baremetal_hw/src/ipc_virtio.c b/mcal_drv/mcal/CddIpc/ipc_baremetal_hw/src/ipc_virtio.c
index 6691991..1497025 100644
--- a/mcal_drv/mcal/CddIpc/ipc_baremetal_hw/src/ipc_virtio.c
+++ b/mcal_drv/mcal/CddIpc/ipc_baremetal_hw/src/ipc_virtio.c
@@ -933,3 +933,15 @@ int32_t VirtioIPC_init(Ipc_VirtIoParams *vqParams)
     }
     return retVal;
 }
+
+
+/**
+ *  \brief Saves the resourcetable to be used for
+ *  vring for remotecore A72/A53 running Linux
+ */
+
+int32_t Ipc_loadResourceTable(void *rsctable)
+{
+	rscTable = rsctable;
+	return IPC_SOK;
+}
diff --git a/mcal_drv/mcal/examples/CddIpcRProcLinux/CddIpcAppRProcLinux.c b/mcal_drv/mcal/examples/CddIpcRProcLinux/CddIpcAppRProcLinux.c
index 9a68b79..c92b31a 100644
--- a/mcal_drv/mcal/examples/CddIpcRProcLinux/CddIpcAppRProcLinux.c
+++ b/mcal_drv/mcal/examples/CddIpcRProcLinux/CddIpcAppRProcLinux.c
@@ -76,16 +76,16 @@
 #include "CddIpcAppRProcLinux.h"
 
 #include "app_utils.h"
-#include <ti/csl/csl_intr_router.h> /* CSL for interrupt router */
+#include <hw_include/lld_intr_router.h> /* CSL for interrupt router */
 #include "IntRtr_Cfg.h" /* Defines the map / cfg for
                          * interrupt router, for this example
                          */
 #include "SchM_Cdd_Ipc.h" /* Exclusive area */
 
-#include <ti/csl/soc.h>
+#include <hw_include/soc.h>
 /* Interrupts, Clear MCU Timer 0 */
-#include <ti/csl/arch/csl_arch.h>
-#include <ti/csl/hw_types.h>
+#include <hw_include/arch/lld_arch.h>
+#include <hw_include/hw_types.h>
 
 /* SCI Client */
 #include <ti/drv/sciclient/sciclient.h>
@@ -107,6 +107,10 @@
 /* ========================================================================== */
 /*                           Macros & Typedefs                                */
 /* ========================================================================== */
+#define MSG_NORMAL      (APP_UTILS_PRINT_MSG_NORMAL)
+/**< Message type */
+#define MSG_STATUS      (APP_UTILS_PRINT_MSG_STATUS)
+/**< Message type */
 #define CDD_IPC_APP_MSG_DATA_SIZE   (256U)
 /**< Size of message buffer to be transmitted */
 #define CDD_IPC_APP_MSG_TX_RX_CNT   (10U)
@@ -161,11 +165,9 @@ void Cdd_IpcNewMessageNotify(uint32 comId)
 void Cdd_IpcNewCtrlMessageNotify(uint32 remoteProcId)
 {
 }
-
 #endif /* (STD_ON == CDD_IPC_ANNOUNCE_API) */
 
 
-
 /** \brief Main Entry point for demo application
  *
  *  Application flow
@@ -201,12 +203,16 @@ int main(void)
 
     /* Step 1 */
     Cdd_IpcAppDemoStatus = E_NOT_OK;
+#ifdef UART_ENABLED
+    AppUtils_Init();
+#endif
+    AppUtils_LogResult(APP_UTILS_TEST_STATUS_INIT);
 
     Cdd_IpcApp_PrintVersion();
 
     Cdd_IpcApp_Startup();
 
-    System_printf(" Sample Application - STARTS !!! \n");
+    AppUtils_Printf(MSG_NORMAL, cdd_ipc_app_rc_linux " Sample Application - STARTS !!! \n");
 
     Cdd_IpcAppIterCntMpu10 = CDD_IPC_APP_MSG_TX_RX_CNT;
 
@@ -223,7 +229,7 @@ int main(void)
      * load resource table
      */
     Ipc_loadResourceTable((void*)&ti_ipc_remoteproc_ResourceTable);
-    System_printf(" Resource Table loaded, chanCount %d \n",
+    AppUtils_Printf(MSG_NORMAL," Resource Table loaded, chanCount %d \n",
                         chanCount);
 
     /* Wait for Linux VDev ready... */
@@ -234,12 +240,12 @@ int main(void)
         }
     }
 
-   System_printf("Linux VDEV ready now .....\n");
+   AppUtils_Printf(MSG_NORMAL, "Linux VDEV ready now .....\n");
 
     /* Step 2 */
     Cdd_IpcInit();
 
-   System_printf("CDD Ipc Inited now .....\n");
+   AppUtils_Printf(MSG_NORMAL, cdd_ipc_app_rc_linux "CDD Ipc Inited now .....\n");
 
 #if (STD_ON == CDD_IPC_ANNOUNCE_API)
     /* For every remote core, Announce once */
@@ -268,20 +274,23 @@ int main(void)
     const Cdd_IpcChannelType *pChanCfg = CddIpcConfiguraions_PC.pChCfg;
 	while ((0U != Cdd_IpcAppNmsgCntMpu10) && (0U != Cdd_IpcAppIterCntMpu10))
     {
-		System_printf("waiting for message from MPU 1 0, EP[%d], ProcId[%d]\n", pChanCfg[CddIpcConf_IpcComChanId_Cdd_IpcMpu10].remoteEp, pChanCfg[CddIpcConf_IpcComChanId_Cdd_IpcMpu10].remoteProcId);
-
+		AppUtils_Printf(MSG_NORMAL, cdd_ipc_app_rc_linux  \
+                            "waiting for message from MPU 1 0, EP[%d], ProcId[%d]\n", \
+                              pChanCfg[CddIpcConf_IpcComChanId_Cdd_IpcMpu10].remoteEp, \
+                              pChanCfg[CddIpcConf_IpcComChanId_Cdd_IpcMpu10].remoteProcId);
+        AppUtils_Printf(MSG_NORMAL, "");
         rtnVal = Cdd_IpcReceiveMsg(CddIpcConf_IpcComChanId_Cdd_IpcMpu10,
                                 &Cdd_IpcAppMpu10Buffer[0U], &mpu10Bufsize);
 
 		if (rtnVal != E_OK)
 		{
-			System_printf("IPC Receive message timedout!!!");
+			AppUtils_Printf(MSG_NORMAL, cdd_ipc_app_rc_linux"IPC Receive message timedout!!!");
 		}
         SchM_Enter_Cdd_Ipc_IPC_EXCLUSIVE_AREA_0();
         Cdd_IpcAppNmsgCntMpu10--;
         SchM_Exit_Cdd_Ipc_IPC_EXCLUSIVE_AREA_0();
 
-        System_printf(" Received %s Iteration %d from MPU 1 0\n",
+       AppUtils_Printf(MSG_NORMAL, cdd_ipc_app_rc_linux  " Received %s Iteration %d from MPU 1 0\n",
                       &Cdd_IpcAppMpu10Buffer[0U], Cdd_IpcAppIterCntMpu10);
 
         Cdd_IpcAppIterCntMpu10--;
@@ -291,9 +300,11 @@ int main(void)
 #endif /* CDD_IPC_REMOTE_CORE_MPU1_0_USED */
     }
 
-    System_printf(" Transmitted and Received %d times\n",
-                                    CDD_IPC_APP_MSG_TX_RX_CNT);
-    System_printf(" Sample Application - Completes !!!\n");
+    AppUtils_Printf(MSG_NORMAL, cdd_ipc_app_rc_linux
+                                        " Transmitted and Received %d times\n",
+                                        CDD_IPC_APP_MSG_TX_RX_CNT);                                   
+    AppUtils_Printf(MSG_NORMAL, cdd_ipc_app_rc_linux
+                                        " Sample Application - Completes !!!\n");
 
     Cdd_IpcAppDemoStatus = E_OK;
     return (0);
@@ -309,17 +320,17 @@ static void Cdd_IpcApp_PrintVersion(void)
     Std_VersionInfoType versioninfo;
 
     Cdd_IpcGetVersionInfo(&versioninfo);
-    System_printf(" CDD IPC MCAL Version Info\n");
-    System_printf("---------------------\n");
-    System_printf(" Vendor ID           : %d\n",
+    AppUtils_Printf(MSG_NORMAL," CDD IPC MCAL Version Info\n");
+    AppUtils_Printf(MSG_NORMAL,"---------------------\n");
+    AppUtils_Printf(MSG_NORMAL," Vendor ID           : %d\n",
                                                versioninfo.vendorID);
-    System_printf(" Module ID           : %d\n",
+    AppUtils_Printf(MSG_NORMAL," Module ID           : %d\n",
                                                 versioninfo.moduleID);
-    System_printf(" SW Major Version    : %d\n",
+    AppUtils_Printf(MSG_NORMAL," SW Major Version    : %d\n",
                                                 versioninfo.sw_major_version);
-    System_printf(" SW Minor Version    : %d\n",
+    AppUtils_Printf(MSG_NORMAL," SW Minor Version    : %d\n",
                                                 versioninfo.sw_minor_version);
-    System_printf(" SW Patch Version    : %d\n",
+    AppUtils_Printf(MSG_NORMAL," SW Patch Version    : %d\n",
                                                 versioninfo.sw_patch_version);
 #endif
 
diff --git a/mcal_drv/mcal/examples/CddIpcRProcLinux/CddIpcAppRProcLinux.h b/mcal_drv/mcal/examples/CddIpcRProcLinux/CddIpcAppRProcLinux.h
index ff90c26..1616b0c 100644
--- a/mcal_drv/mcal/examples/CddIpcRProcLinux/CddIpcAppRProcLinux.h
+++ b/mcal_drv/mcal/examples/CddIpcRProcLinux/CddIpcAppRProcLinux.h
@@ -94,7 +94,7 @@ extern "C"
 /* ========================================================================== */
 /*                           Macros & Typedefs                                */
 /* ========================================================================== */
-#define CDD_IPC_APP                        "CDD_IPC_APP :"
+#define cdd_ipc_app_rc_linux                        "CDD_IPC_LINUX_APP :"
 /**< App identifier string */
 
 /* ========================================================================== */
diff --git a/mcal_drv/mcal/examples/CddIpcRProcLinux/IpcRscTable.h b/mcal_drv/mcal/examples/CddIpcRProcLinux/IpcRscTable.h
index 4c12c8b..7c9ddda 100644
--- a/mcal_drv/mcal/examples/CddIpcRProcLinux/IpcRscTable.h
+++ b/mcal_drv/mcal/examples/CddIpcRProcLinux/IpcRscTable.h
@@ -48,7 +48,7 @@ extern "C" {
 
 #define BAREMETAL
 
-#include <ti/drv/ipc/include/ipc_rsctypes.h>
+#include <CddIpc/ipc_baremetal_hw/include/ipc_rsctypes.h>
 #ifdef BAREMETAL
 #include "IpcTrace.h"
 #else
@@ -74,7 +74,7 @@ extern "C" {
 #ifdef BAREMETAL
 #define TRACEBUFADDR ((uintptr_t)&Ipc_traceBuffer)
 #else
-extern __T1_xdc_runtime_SysMin_Module_State__outbuf xdc_runtime_SysMin_Module_State_0_outbuf__A[];
+extern __T1_xdc_runtime_SysMin_Module_State__outbuf     xdc_runtime_SysMin_Module_State_0_outbuf__A[];
 #define TRACEBUFADDR ((uintptr_t)&xdc_runtime_SysMin_Module_State_0_outbuf__A)
 #endif
 
diff --git a/mcal_drv/mcal/examples/CddIpcRProcLinux/IpcTrace.c b/mcal_drv/mcal/examples/CddIpcRProcLinux/IpcTrace.c
index da7dbdf..70a8135 100644
--- a/mcal_drv/mcal/examples/CddIpcRProcLinux/IpcTrace.c
+++ b/mcal_drv/mcal/examples/CddIpcRProcLinux/IpcTrace.c
@@ -50,7 +50,7 @@
 #include "IpcTrace.h"
 
 #if defined(BUILD_MCU)
-#pragma DATA_SECTION(Ipc_traceBuffer, ".tracebuf");
+__attribute__((section(".tracebuf")))
 #endif
 char Ipc_traceBuffer[IPC_TRACE_BUFFER_MAX_SIZE];
 
diff --git a/mcal_drv/mcal/examples/CddIpcRProcLinux/IpcTrace.h b/mcal_drv/mcal/examples/CddIpcRProcLinux/IpcTrace.h
index c0d74c5..4fe4c37 100644
--- a/mcal_drv/mcal/examples/CddIpcRProcLinux/IpcTrace.h
+++ b/mcal_drv/mcal/examples/CddIpcRProcLinux/IpcTrace.h
@@ -31,9 +31,9 @@
  */
 
 /*
- *  \file IpcTrace.h
+ *  file IpcTrace.h
  *
- *  \brief Define the functions for trace
+ *  brief Define the functions for trace
  *
  */
 
diff --git a/mcal_drv/mcal/examples/CddIpcRProcLinux/makefile b/mcal_drv/mcal/examples/CddIpcRProcLinux/makefile
index d46570b..80ee922 100755
--- a/mcal_drv/mcal/examples/CddIpcRProcLinux/makefile
+++ b/mcal_drv/mcal/examples/CddIpcRProcLinux/makefile
@@ -1,8 +1,9 @@
 include $(MCUSW_INSTALL_PATH)/build/Rules.make
 
+#Application name
 APP_NAME = cdd_ipc_app_rc_linux
 
-SRCDIR = . ./soc/$(SOC)/$(CORE) $(autosarConfigSrc_PATH)/CddIpc_Demo_Cfg/output/generated/soc/$(SOC)/$(CORE)/src $(app_utils_PATH)/src soc/$(SOC)
+SRCDIR = ./soc/$(SOC)/$(CORE) $(autosarConfigSrc_PATH)/CddIpcLinux_Demo_Cfg/output/generated/soc/$(SOC)/$(CORE)/src $(app_utils_PATH)/src soc/$(SOC)
 INCDIR = . $(autosarConfigSrc_PATH)/IntRtr_Cfg/soc/$(SOC)/$(CORE)/
 INCDIR += $(mcal_PATH)
 
diff --git a/mcal_drv/mcal/examples/CddIpcRProcLinux/soc/j721e/mcu2_1/CddIpcAppStartup.c b/mcal_drv/mcal/examples/CddIpcRProcLinux/soc/j721e/mcu2_1/CddIpcAppStartup.c
index d4e6efb..a53f1e9 100755
--- a/mcal_drv/mcal/examples/CddIpcRProcLinux/soc/j721e/mcu2_1/CddIpcAppStartup.c
+++ b/mcal_drv/mcal/examples/CddIpcRProcLinux/soc/j721e/mcu2_1/CddIpcAppStartup.c
@@ -75,16 +75,16 @@
 #include "CddIpcAppRProcLinux.h"
 
 #include "app_utils.h"
-#include <ti/csl/csl_intr_router.h> /* CSL for interrupt router */
+#include <hw_include/lld_intr_router.h> /* CSL for interrupt router */
 #include "IntRtr_Cfg.h" /* Defines the map / cfg for
                          * interrupt router, for this example
                          */
 #include "SchM_Cdd_Ipc.h" /* Exclusive area */
 
-#include <ti/csl/soc.h>
+#include <hw_include/soc.h>
 /* Interrupts, Clear MCU Timer 0 */
-#include <ti/csl/arch/csl_arch.h>
-#include <ti/csl/hw_types.h>
+#include <hw_include/arch/lld_arch.h>
+#include <hw_include/hw_types.h>
 
 /* SCI Client */
 #include <ti/drv/sciclient/sciclient.h>
@@ -103,6 +103,11 @@
 /* ========================================================================== */
 #define System_printf Ipc_Trace_printf
 
+#define MSG_NORMAL      (APP_UTILS_PRINT_MSG_NORMAL)
+/**< Message type */
+#define MSG_STATUS      (APP_UTILS_PRINT_MSG_STATUS)
+/**< Message type */
+
 /* ========================================================================== */
 /*                 Internal Function Declarations                             */
 /* ========================================================================== */
@@ -232,11 +237,32 @@ static void Cdd_IpcApp_MbIntRegForMpu10(void)
 {
     struct tisci_msg_rm_irq_set_req     rmIrqReq;
     struct tisci_msg_rm_irq_set_resp    rmIrqResp;
+    struct tisci_msg_rm_irq_release_req rmIrqRel;
     OsalRegisterIntrParams_t    intrPrms;
     OsalInterruptRetCode_e      osalRetVal;
     Int32 retVal;
     HwiP_Handle hwiHandle;
 
+
+    /* Since the same mailbox, user but different FIFO is being used to receive
+        data from multiple cores, we can at most have one ISR only.
+        The ISR implementation will process all FIFOs */
+    rmIrqRel.ia_id                  = 0U;
+    rmIrqRel.vint                   = 0U;
+    rmIrqRel.global_event           = 0U;
+    rmIrqRel.vint_status_bit_index  = 0U;
+
+    rmIrqRel.valid_params   = TISCI_MSG_VALUE_RM_DST_ID_VALID |
+                              TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID |
+                              TISCI_MSG_VALUE_RM_SECONDARY_HOST_VALID;
+    rmIrqRel.src_id         = TISCI_DEV_NAVSS0_MAILBOX_1;
+    rmIrqRel.src_index      = 2U;
+    rmIrqRel.dst_id         = TISCI_DEV_R5FSS0_CORE1;
+    rmIrqRel.secondary_host = TISCI_HOST_ID_MAIN_0_R5_2;
+    rmIrqRel.dst_host_irq   = INTRTR_CFG_MBX_CLST1_USR2_434_MPU_1_0_TO_MCU_2_1_248;
+
+    retVal = Sciclient_rmIrqRelease(&rmIrqRel, SCICLIENT_SERVICE_WAIT_FOREVER);
+    
     rmIrqReq.valid_params           = TISCI_MSG_VALUE_RM_DST_ID_VALID;
     rmIrqReq.valid_params          |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
     rmIrqReq.valid_params          |= TISCI_MSG_VALUE_RM_SECONDARY_HOST_VALID;
@@ -251,7 +277,8 @@ static void Cdd_IpcApp_MbIntRegForMpu10(void)
                  &rmIrqReq, &rmIrqResp, APP_SCICLIENT_TIMEOUT);
     if(CSL_PASS != retVal)
     {
-	System_printf("Error in SciClient Interrupt Params Configuration!!!\n");
+	        AppUtils_Printf(MSG_NORMAL,cdd_ipc_app_rc_linux
+        ": Error in SciClient Interrupt Params Configuration!!!\n");
     }
 
     /* Interrupt hookup */
@@ -265,8 +292,9 @@ static void Cdd_IpcApp_MbIntRegForMpu10(void)
     osalRetVal = Osal_RegisterInterrupt(&intrPrms, &hwiHandle);
     if(OSAL_INT_SUCCESS != osalRetVal)
     {
-	System_printf( "Error Could not register ISR to receive"
-                        " from MPU 1 0 !!!\n");
+        AppUtils_Printf(MSG_NORMAL,
+                cdd_ipc_app_rc_linux ": Error Could not register ISR to receive"
+                " from MPU 1 0 !!!\n");
     }
     return;
 }
diff --git a/mcal_drv/mcal/examples/CddIpcRProcLinux/soc/j721e/mcu2_1/CddIpcR5Mpu.c b/mcal_drv/mcal/examples/CddIpcRProcLinux/soc/j721e/mcu2_1/CddIpcR5Mpu.c
index 7501378..b06899a 100644
--- a/mcal_drv/mcal/examples/CddIpcRProcLinux/soc/j721e/mcu2_1/CddIpcR5Mpu.c
+++ b/mcal_drv/mcal/examples/CddIpcRProcLinux/soc/j721e/mcu2_1/CddIpcR5Mpu.c
@@ -33,10 +33,10 @@
 
 #include <stdlib.h>
 #include <stdint.h>
-#include <ti/csl/arch/r5/csl_arm_r5.h>
-#include <ti/csl/arch/r5/csl_arm_r5_mpu.h>
-#include <ti/csl/arch/r5/interrupt.h>
-#include <ti/csl/arch/r5/csl_cache.h>
+#include <hw_include/arch/r5/lld_arm_r5.h>
+#include <hw_include/arch/r5/lld_arm_r5_mpu.h>
+#include <hw_include/arch/r5/interrupt.h>
+#include <hw_include/arch/r5/lld_cache.h>
 
 /*
  * This structure specifies the entries for mpu configuration to override the
diff --git a/mcal_drv/mcal/examples_config/CddIpcLinux_Demo_Cfg/output/generated/soc/j721e/mcu2_1/include/Cdd_IpcCfg.h b/mcal_drv/mcal/examples_config/CddIpcLinux_Demo_Cfg/output/generated/soc/j721e/mcu2_1/include/Cdd_IpcCfg.h
new file mode 100644
index 0000000..7fc32ac
--- /dev/null
+++ b/mcal_drv/mcal/examples_config/CddIpcLinux_Demo_Cfg/output/generated/soc/j721e/mcu2_1/include/Cdd_IpcCfg.h
@@ -0,0 +1,441 @@
+/*
+*
+* Copyright (c) 2019 Texas Instruments Incorporated
+*
+* All rights reserved not granted herein.
+*
+* Limited License.
+*
+* Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
+* license under copyrights and patents it now or hereafter owns or controls to make,
+* have made, use, import, offer to sell and sell ("Utilize") this software subject to the
+* terms herein.  With respect to the foregoing patent license, such license is granted
+* solely to the extent that any such patent is necessary to Utilize the software alone.
+* The patent license shall not apply to any combinations which include this software,
+* other than combinations with devices manufactured by or for TI ("TI Devices").
+* No hardware patent is licensed hereunder.
+*
+* Redistributions must preserve existing copyright notices and reproduce this license
+* (including the above copyright notice and the disclaimer and (if applicable) source
+* code license limitations below) in the documentation and/or other materials provided
+* with the distribution
+*
+* Redistribution and use in binary form, without modification, are permitted provided
+* that the following conditions are met:
+*
+* *       No reverse engineering, decompilation, or disassembly of this software is
+* permitted with respect to any software provided in binary form.
+*
+* *       any redistribution and use are licensed by TI for use only with TI Devices.
+*
+* *       Nothing shall obligate TI to provide you with source code for the software
+* licensed and provided to you in object code.
+*
+* If software source code is provided to you, modification and redistribution of the
+* source code are permitted provided that the following conditions are met:
+*
+* *       any redistribution and use of the source code, including any resulting derivative
+* works, are licensed by TI for use only with TI Devices.
+*
+* *       any redistribution and use of any object code compiled from the source code
+* and any resulting derivative works, are licensed by TI for use only with TI Devices.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of its suppliers
+*
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* DISCLAIMER.
+*
+* THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS
+* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+* OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+/**
+ *  \file     Cdd_IpcCfg.h
+ *
+ *  \brief    This file contains generated pre compile configurations
+ *            for CDD IPC MCAL driver
+ *
+ */
+
+/******************************************************************************
+    Project         : CDD_IPC_LINUX_CONFIG_J721E
+    Date            : 2023-02-07 17:24:13
+    SW Ver          : 3.0
+    Module Rele Ver : AUTOSAR 4.3.1 0
+
+    This file is generated by EB Tresos
+    Do not modify this file,otherwise the software may behave in unexpected way.
+******************************************************************************/
+
+/**
+ *  \defgroup MCAL_IPC_CFG CDD Ipc Configuration
+ *
+ *  This files defines CDD Ipc configuration structures
+ *  @{
+ */
+
+#ifndef CDD_IPC_CFG_H_
+#define CDD_IPC_CFG_H_
+/* Generic requirements covered mapping */
+/*
+ * Design : DES_CDD_IPC_020
+ */
+/*
+ * Requirements : MCAL-3698
+ */
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+#include "Dem.h"
+#include "Os.h"
+#include <CddIpc/ipc_baremetal_hw/include/ipc_config.h>
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/*                           Macros & Typedefs                                */
+/* ========================================================================== */
+/*
+ * Design : DES_CDD_IPC_004, DES_CDD_IPC_002, DES_CDD_IPC_017
+ */
+/*
+ * Requirements : MCAL-921, MCAL-3703
+ */
+/**
+*  \brief Pre-Compile Build Variant flag.
+*   STD_ON for VariantPreCompile / STD_OFF for VariantPostBuild
+*/
+#define CDD_IPC_PRE_COMPILE_VARIANT    (STD_ON)
+/*
+ * Design : DES_CDD_IPC_012
+ */
+/*
+ * Requirements : MCAL-3693
+ */
+/** \brief Enable/disable CDD Ipc dev detect error */
+#define CDD_IPC_DEV_ERROR_DETECT       (STD_ON)
+/*
+ * Design : DES_CDD_IPC_012
+ */
+/*
+ * Requirements : MCAL-3692
+ */
+/** \brief ISR type */
+#define CDD_IPC_ISR_TYPE               (CDD_IPC_ISR_CAT2)
+
+/**
+ *  \name Pre-Compile Switches for API Services
+ *  @{
+ */
+/*
+ * Design : DES_CDD_IPC_012
+ */
+/*
+ * Requirements : MCAL-3741
+ */
+/** \brief Enable/disable version info API */
+#define CDD_IPC_VERSION_INFO_API       (STD_ON)
+/*
+ * Design : DES_CDD_IPC_012
+ */
+/*
+ * Requirements : MCAL-3688
+ */
+/** \brief Enable/disable De Initialization API */
+#define CDD_IPC_DEINIT_API             (STD_ON)
+/*
+ * Design : DES_CDD_IPC_012
+ */
+/*
+ * Requirements : MCAL-3689
+ */
+/** \brief Enable/disable Service Announcement API */
+#define CDD_IPC_ANNOUNCE_API           (STD_ON)
+/*
+ * Design : DES_CDD_IPC_005, DES_CDD_IPC_012
+ */
+/*
+ * Requirements : MCAL-3687
+ */
+/** \brief Enable/disable Critical Register read back API */
+#define CDD_IPC_REGISTER_READBACK_API  (STD_ON)
+/*
+ * Design :
+ */
+/*
+ * Requirements : MCAL-8266
+ */
+/** \brief Enable/disable safety diagnostics API */
+#define CDD_IPC_SAFETY_DIAGNOSTIC_API                (STD_ON)
+/*
+ * Design : DES_CDD_IPC_040
+ */
+/*
+ * Requirements : MCAL-4452
+ */
+
+/** \brief Enable/disable Cdd_IpcIsInitDone API */
+#define CDD_IPC_IS_INIT_DONE_API       (STD_ON)
+
+/*
+ * Design : DES_CDD_IPC_041
+ */
+/*
+ * Requirements : MCAL-4453
+ */
+
+/** \brief Enable/disable Cdd_IpcGetMaxMsgSize API */
+#define CDD_IPC_GET_MAX_MSG_SIZE_API   (STD_ON)
+
+
+/* @} */
+
+/**
+ *  \name Dependency configurations
+ *  @{
+ */
+/*
+ * Design : DES_CDD_IPC_012
+ */
+/*
+ * Requirements : MCAL-3694, MCAL-3694
+ */
+/** \brief Counter ID for counter used to count wait ticks */
+#define CDD_IPC_OS_COUNTER_ID          ((CounterType)OsCounter_0)
+
+/**
+ *  \name Cdd Ipc DEM Error codes to report
+ *
+ *  Pre-compile switches for enabling/disabling DEM events
+ *  @{
+ */
+/*
+ * Design : DES_CDD_IPC_020
+ */
+/*
+ * Requirements : MCAL-3693
+ */
+#define DemConf_DemEventParameter_CDD_IPC_DEM_NO_EVENT (0xFFFFU)
+#define CDD_IPC_DEM_NO_EVENT DemConf_DemEventParameter_CDD_IPC_DEM_NO_EVENT
+
+#ifndef CDD_IPC_E_HARDWARE_ERROR
+/** \brief Hardware failed */
+#define CDD_IPC_E_HARDWARE_ERROR       (DemConf_DemEventParameter_CDD_IPC_E_HARDWARE_ERROR)
+#endif
+/* @} */
+
+/**
+ *  \name CORE Names
+ *  @{
+ */
+/*
+ * Design : DES_CDD_IPC_018
+ */
+/*
+ * Requirements : MCAL-3699, MCAL-3700
+ */
+#define    CDD_IPC_CORE_MPU1_0          (0U)
+/**< ARM A72 - VM0 */
+#define    CDD_IPC_CORE_MCU1_0          (1U)
+/**< ARM MCU  R5F - core0 */
+#define    CDD_IPC_CORE_MCU1_1          (2U)
+/**< ARM MCU  R5F - core1 */
+#define    CDD_IPC_CORE_MCU2_0          (3U)
+/**< ARM Main R5F - core0 */
+#define    CDD_IPC_CORE_MCU2_1          (4U)
+/**< ARM Main R5F - core1 */
+#define    CDD_IPC_CORE_MCU3_0          (5U)
+/**< ARM Main R5F - core2 */
+#define    CDD_IPC_CORE_MCU3_1          (6U)
+/**< ARM Main R5F - core3 */
+#define    CDD_IPC_CORE_C66X_1          (7U)
+/**< DSP C66x - core0 */
+#define    CDD_IPC_CORE_C66X_2          (8U)
+/**< DSP C66x - core1 */
+#define    CDD_IPC_CORE_C7X_1           (9U)
+/**< DSP C7x - core0 */
+#define    CDD_IPC_CORE_MAX_PROCS       (11U)
+/**< MAX processors */
+
+/** \brief Used core identifiers */
+#define CDD_IPC_OWN_CORE_ID    (CDD_IPC_CORE_MCU2_1)
+/**< Own core ID */
+#define CDD_IPC_REMOTE_CORE_MPU1_0_USED
+/**< Remote core MPU 1 0 is being used */
+
+/* @} */
+
+
+/**
+ *  \name VirtIO Object
+ *  @{
+ */
+/*
+ * Design : DES_CDD_IPC_005, DES_CDD_IPC_016
+ */
+/*
+ * Requirements : MCAL-3686,
+ */
+#define CDD_IPC_VERTIO_OBJECT_SIZE     (0x1000U)
+ /* @} */
+
+/**
+ *  \name Communication Channel ID & Configured Buffer sizes
+ *  @{
+ */
+/*
+ * Design : DES_CDD_IPC_016
+ */
+/*
+ * Requirements : MCAL-3686,
+ */
+#define CddIpcConf_IpcComChanId_Cdd_IpcMpu10      (0U)
+/**< Channel identifiers */
+
+/*
+ * Design : DES_CDD_IPC_016
+ */
+/*
+ * Requirements : MCAL-3755, MCAL-3682
+ */
+#define CDD_IPC_RPMSG_OBJ_SIZE      (256U)
+/**< Size of RP Message Object */
+#define CDD_IPC_CH_0_BUFF_SIZE   ((256U * (496U + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE)
+/**< Size of buffer allocated to the channel */
+#define CDD_IPC_MAX_CHANNEL_CFG  (1U)
+/**< Maximum number of communication channels configured */
+
+/**
+ * \brief VRing Buffer Size required for all core
+ * combinations.
+ */
+#define IPC_VRING_BUFFER_SIZE   (0x1C00000U)
+
+/** \brief Core definitions */
+#define    IPC_MPU1_0           (0U)    /**< ARM A72 - VM0 */
+#define    IPC_MCU1_0           (1U)    /**< ARM MCU  R5F - core0 */
+#define    IPC_MCU1_1           (2U)    /**< ARM MCU  R5F - core1 */
+#define    IPC_MCU2_0           (3U)    /**< ARM Main R5F - core0 */
+#define    IPC_MCU2_1           (4U)    /**< ARM Main R5F - core1 */
+#define    IPC_MCU3_0           (5U)    /**< ARM Main R5F - core2 */
+#define    IPC_MCU3_1           (6U)    /**< ARM Main R5F - core3 */
+#define    IPC_C66X_1           (7U)    /**< DSP C66x - core0 */
+#define    IPC_C66X_2           (8U)    /**< DSP C66x - core1 */
+#define    IPC_C7X_1            (9U)    /**< DSP C7x - core0 */
+#define    IPC_MPU1_1          (10U)    /**< ARM A72 - VM1 */
+#define    IPC_MAX_PROCS       (11U)    /**< Maximum Processors */
+
+/** \brief IPC maximum possible core ID
+ */
+#define CDD_IPC_CORE_ID_MAX         (11U)
+
+#define IPC_MAILBOX_CLUSTER_CNT     (12U)
+
+/* @} */
+/* ========================================================================== */
+/*                           Globals Variables                                */
+/* ========================================================================== */
+/* Mailbox Cluster Base Address */
+extern const uint32 IPC_Mailbox_BasePhyAddr[IPC_MAILBOX_CLUSTER_CNT];
+
+/**
+ *  \brief Processor IDs to name mapping for all processor in Jacinto7
+ */
+extern Ipc_ProcInfo g_Ipc_mp_procInfo[IPC_MAX_PROCS];
+
+extern Ipc_MailboxInfo   g_IPC_MailboxInfo[IPC_MAX_PROCS][IPC_MAX_PROCS];
+
+/* ========================================================================== */
+/*                          Function Declarations                             */
+/* ========================================================================== */
+/*
+ * Design : DES_CDD_IPC_002, DES_CDD_IPC_017
+ */
+/*
+ * Requirements : MCAL-3703
+ */
+extern const struct Cdd_IpcConfigType_s CddIpcConfiguraions_PC;
+
+/**
+ * \brief New Message notification function
+ *
+ */
+/*
+ * Design : DES_CDD_IPC_012, DES_CDD_IPC_026
+ */
+/*
+ * Requirements : MCAL-3701, MCAL-3691
+ */
+extern void Cdd_IpcNewMessageNotify(uint32 comId);
+
+#define CDD_IPC_NEW_MSG_NTFY_FXN Cdd_IpcNewMessageNotify
+
+#if (STD_ON == CDD_IPC_ANNOUNCE_API)
+
+/**
+ * \brief New Control Message notification function
+ *
+ */
+/*
+ * Design : DES_CDD_IPC_039
+ */
+/*
+ * Requirements : MCAL-4067, MCAL-4066
+ */
+extern void Cdd_IpcNewCtrlMessageNotify(uint32 remoteProcId);
+
+#define CDD_IPC_NEW_CTRL_MSG_NTFY_FXN Cdd_IpcNewCtrlMessageNotify
+
+#endif /* STD_ON == CDD_IPC_ANNOUNCE_API */
+
+/*
+ * Design : DES_CDD_IPC_013
+ */
+/*
+ * Requirements : MCAL-3674
+ */
+/**
+ *  \brief Communication Channels configured
+ *
+ */
+extern uint8 Cdd_IpcDrvVertIoObj[CDD_IPC_VERTIO_OBJECT_SIZE];
+
+/** \brief A Mailbox can raise multiple interrupts. In this implementation, the
+ *          Mailbox new message interrupt is used determine presence of data
+ *          from the remote core in the vring.
+ *
+ *          Typically, we would have 1 interrupt for each remote core. Due to
+ *          system resource needs, multiple remote cores could use a single
+ *          interrupt.
+ *
+ *          Depending on the SoC variant, the isr to registered with interrupt
+ *          will change. Please refer CDD IPC example application to associate
+ *          right ISR with interrupt.
+ */
+
+/** \brief ISR for New Message, from MPU 1 0*/
+ISR( Cdd_IpcIrqMbxFromMpu_10 );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* #ifndef CDD_IPC_CFG_H_ */
+
+/* @} */
diff --git a/mcal_drv/mcal/examples_config/CddIpcLinux_Demo_Cfg/output/generated/soc/j721e/mcu2_1/src/Cdd_IpcCfg.c b/mcal_drv/mcal/examples_config/CddIpcLinux_Demo_Cfg/output/generated/soc/j721e/mcu2_1/src/Cdd_IpcCfg.c
new file mode 100644
index 0000000..b90a948
--- /dev/null
+++ b/mcal_drv/mcal/examples_config/CddIpcLinux_Demo_Cfg/output/generated/soc/j721e/mcu2_1/src/Cdd_IpcCfg.c
@@ -0,0 +1,475 @@
+/*
+*
+* Copyright (c) 2019 Texas Instruments Incorporated
+*
+* All rights reserved not granted herein.
+*
+* Limited License.
+*
+* Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
+* license under copyrights and patents it now or hereafter owns or controls to make,
+* have made, use, import, offer to sell and sell ("Utilize") this software subject to the
+* terms herein.  With respect to the foregoing patent license, such license is granted
+* solely to the extent that any such patent is necessary to Utilize the software alone.
+* The patent license shall not apply to any combinations which include this software,
+* other than combinations with devices manufactured by or for TI ("TI Devices").
+* No hardware patent is licensed hereunder.
+*
+* Redistributions must preserve existing copyright notices and reproduce this license
+* (including the above copyright notice and the disclaimer and (if applicable) source
+* code license limitations below) in the documentation and/or other materials provided
+* with the distribution
+*
+* Redistribution and use in binary form, without modification, are permitted provided
+* that the following conditions are met:
+*
+* *       No reverse engineering, decompilation, or disassembly of this software is
+* permitted with respect to any software provided in binary form.
+*
+* *       any redistribution and use are licensed by TI for use only with TI Devices.
+*
+* *       Nothing shall obligate TI to provide you with source code for the software
+* licensed and provided to you in object code.
+*
+* If software source code is provided to you, modification and redistribution of the
+* source code are permitted provided that the following conditions are met:
+*
+* *       any redistribution and use of the source code, including any resulting derivative
+* works, are licensed by TI for use only with TI Devices.
+*
+* *       any redistribution and use of any object code compiled from the source code
+* and any resulting derivative works, are licensed by TI for use only with TI Devices.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of its suppliers
+*
+* may be used to endorse or promote products derived from this software without
+* specific prior written permission.
+*
+* DISCLAIMER.
+*
+* THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS
+* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+* IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+* OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+/**
+ *  \file     Cdd_IpcCfg.c
+ *
+ *  \brief    This file contains generated pre compile configurations
+ *            for CDD IPC MCAL driver
+ *
+ */
+
+/******************************************************************************
+    Project         : CDD_IPC_LINUX_CONFIG_J721E
+    Date            : 2023-02-07 17:24:13
+    SW Ver          : 3.0
+    Module Rele Ver : AUTOSAR 4.3.1 0
+
+    This file is generated by EB Tresos
+    Do not modify this file,otherwise the software may behave in unexpected way.
+******************************************************************************/
+
+/*******************************************************************************
+ *  INCLUDES
+ ******************************************************************************/
+#include "Std_Types.h"
+#include "Cdd_Ipc.h"
+#include "Cdd_IpcIrq.h"
+
+/*
+ * Design : DES_CDD_IPC_012
+ */
+/*
+ * Requirements : MCAL-3701
+ */
+
+/** \brief Version checking  */
+#if ((CDD_IPC_SW_MAJOR_VERSION != (2U))||(CDD_IPC_SW_MINOR_VERSION != (0U)))
+    #error "Version numbers of Cdd_IpcCfg.c and Cdd_Ipc.h are inconsistent!"
+#endif
+
+/*******************************************************************************
+ *  Local Data
+ ******************************************************************************/
+#define CDD_IPC_START_SEC_VAR_NO_INIT_8_ALIGN_8B
+#include "Cdd_Ipc_MemMap.h"
+
+/*
+ * Design : DES_CDD_IPC_036
+ */
+/**
+ *  \brief Local Memory required for communication channel
+ *
+ */
+CDD_IPC_CONFIG_DATA_SECTION static uint8
+            Cdd_IpcCommChBuf_0[CDD_IPC_CH_0_BUFF_SIZE];
+/**< Communication Channel local buffer */
+
+#define CDD_IPC_STOP_SEC_VAR_NO_INIT_8_ALIGN_8B
+#include "Cdd_Ipc_MemMap.h"
+
+#define CDD_IPC_START_SEC_CONFIG_DATA
+#include "Cdd_Ipc_MemMap.h"
+/*******************************************************************************
+ *  Global Data
+ ******************************************************************************/
+ /**
+  * \brief A array of buffer pointers that describe memory allocated to local
+  *          communication channels
+  */
+ extern const struct Cdd_IpcChannelBufType_s
+                             Cdd_IpcCommChanBufferPtr [CDD_IPC_MAX_CHANNEL_CFG];
+
+/*
+ * Design : DES_CDD_IPC_027
+ */
+/*
+ * Requirements : MCAL-3713
+ */
+/**
+ *  \brief Collated communication channel buffer pointers
+ *
+ */
+CDD_IPC_CONFIG_DATA_SECTION CONST(Cdd_IpcChannelBufType,
+            CDD_IPC_CONFIG_DATA) Cdd_IpcCommChanBufferPtr [CDD_IPC_MAX_CHANNEL_CFG] =
+{
+    [0U] =
+    {
+        .pBuf = &Cdd_IpcCommChBuf_0[0U],
+        .bufSize = CDD_IPC_CH_0_BUFF_SIZE,
+    }
+};
+
+/*
+ * Design : DES_CDD_IPC_016
+ */
+/*
+ * Requirements : MCAL-3677, MCAL-3685, MCAL-3678, MCAL-3679, MCAL-3680,
+ *                  MCAL-3681, MCAL-3682, MCAL-3755
+ */
+/**
+ *  \brief Communication Channels configured
+ *
+ */
+CDD_IPC_CONFIG_DATA_SECTION CONST(struct Cdd_IpcChannelType_s,
+            CDD_IPC_CONFIG_DATA) CddIpcCommChs[1U] =
+{
+    [0U] =
+    {
+        .id = CddIpcConf_IpcComChanId_Cdd_IpcMpu10,
+        /**< Unique identifiers for a channel */
+        .localEp = 13U,
+        /**< Local End Point identifier, on which MCAL/AUTOSAR is hosted */
+        .remoteEp = 13U,
+        /**< Remote End Point identifier, on remote cores */
+        .remoteProcId = CDD_IPC_CORE_MPU1_0,
+        /**< Remote Processor Identifier */
+        .numMsgQueued = 256U,
+        /**< Number of buffer allocated to this communication channel */
+        .maxMsgSize = 496,
+        /**< Defines the pointer to memory */
+        .reserved = 0U,
+        /**< Future use if any */
+    }
+};
+
+/*
+ * Design : DES_CDD_IPC_013
+ */
+/*
+ * Requirements : MCAL-3674
+ */
+/**
+ *  \brief Communication Channels configured
+ *
+ */
+CDD_IPC_VAR_DATA_NO_INIT_UNSPECIFIED_SECTION VAR(uint8, CDD_IPC_VAR_NO_INIT)
+            Cdd_IpcDrvVertIoObj[CDD_IPC_VERTIO_OBJECT_SIZE];
+
+/*
+ * Design : DES_CDD_IPC_013, DES_CDD_IPC_014, DES_CDD_IPC_015, DES_CDD_IPC_016
+ */
+/*
+ * Requirements : MCAL-3676, MCAL-3675, MCAL-3669, MCAL-3671, MCAL-3678,
+ *                  MCAL-3679, MCAL-3680, MCAL-3681, MCAL-3682, MCAL-3755
+ */
+/**
+ *  \brief IPC Configurations
+ *
+ */
+CDD_IPC_CONFIG_DATA_SECTION CONST(Cdd_IpcConfigType, CDD_IPC_CONFIG_DATA)
+            CddIpcConfiguraions_PC =
+{
+    .coreIds =
+    {
+        .ownProcID = CDD_IPC_CORE_MCU2_1,
+        /**< Defines processor ID on which MCAL/AUTOSAR is being hosted */
+        .numProcs = 1,
+        /**< Number of processor which with IPC is desired */
+        .remoteProcID =
+        {
+            CDD_IPC_CORE_MPU1_0
+        },
+        /**< Remote processor identifiers */
+        .reserved = 0U,
+        /**< Future use if any */
+    },
+
+    .vertIoCfg =
+    {
+        .vertIoRingAddr = (void *)0xaa000000U,
+        /**< Defines address that shall be shared between cores */
+        .vertIoRingSize = 0x1c00000U,
+        /**< Size of the shared memory */
+        .reserved = 0U,
+        /**< Future use if any */
+    },
+
+    .channelCount = 1U,
+    /**<  Number of channels configured  */
+    .pChCfg = CddIpcCommChs,
+    /**< Pointer to array of channel conditions */
+    .reserved = 0U
+    /**< Reserved field */
+};
+
+/* Mailbox Cluster Base Address */
+const uint32 IPC_Mailbox_BasePhyAddr[IPC_MAILBOX_CLUSTER_CNT] =
+{
+    (uint32)(0x31F80000U),     /* Mailbox - cluster0   */
+    (uint32)(0x31F81000U),     /* Mailbox - cluster1   */
+    (uint32)(0x31F82000U),     /* Mailbox - cluster2   */
+    (uint32)(0x31F83000U),     /* Mailbox - cluster3   */
+    (uint32)(0x31F84000U),     /* Mailbox - cluster4   */
+    (uint32)(0x31F85000U),     /* Mailbox - cluster5   */
+    (uint32)(0x31F86000U),     /* Mailbox - cluster6   */
+    (uint32)(0x31F87000U),     /* Mailbox - cluster7   */
+    (uint32)(0x31F88000U),     /* Mailbox - cluster8   */
+    (uint32)(0x31F89000U),     /* Mailbox - cluster9   */
+    (uint32)(0x31F8A000U),     /* Mailbox - cluster10  */
+    (uint32)(0x31F8B000U),     /* Mailbox - cluster11  */
+};
+
+/**
+ *  \brief Processor IDs to name mapping for all processor in Jacinto7
+ */
+Ipc_ProcInfo g_Ipc_mp_procInfo[IPC_MAX_PROCS] =
+{
+    {IPC_MPU1_0,      "mpu1_0"},      /**< ARM A72 - VM0 */
+    {IPC_MCU1_0,      "mcu1_0"},      /**< ARM MCU  R5F - core0 */
+    {IPC_MCU1_1,      "mcu1_1"},      /**< ARM MCU  R5F - core1 */
+    {IPC_MCU2_0,      "mcu2_0"},      /**< ARM Main R5F - core0 */
+    {IPC_MCU2_1,      "mcu2_1"},      /**< ARM Main R5F - core1 */
+    {IPC_MCU3_0,      "mcu3_0"},      /**< ARM Main R5F - core2 */
+    {IPC_MCU3_1,      "mcu3_1"},      /**< ARM Main R5F - core3 */
+    {IPC_C66X_1,      "C66X_1"},      /**< DSP C66x - core0  */
+    {IPC_C66X_2,      "C66X_2"},      /**< DSP C66x - core1  */
+    {IPC_C7X_1,       "C7X_1"},       /**< DSP C7x - core0 */
+    {IPC_MPU1_1,      "mpu1_1"}       /**< ARM A72 - VM1 */
+};
+
+Ipc_MailboxInfo   g_IPC_MailboxInfo[IPC_MAX_PROCS][IPC_MAX_PROCS] =
+{
+    /* Host Processor - A72-vm0	*/
+    {
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MPU1_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU1_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU1_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU2_0 */
+        { { 1U, 0U,  2U}, { 1U, 0U, 3U} },                /* IPC_MCU2_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU3_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU3_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C66X_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C66X_2 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C7X_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MPU1_1 */
+    },
+
+    /* Host Processor - mcu1_0 	*/
+    {
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MPU1_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU1_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU1_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU2_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU2_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU3_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU3_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C66X_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C66X_2 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C7X_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MPU1_1 */
+    },
+
+    /* Host Processor - mcu1_1 	*/
+    {
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MPU1_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU1_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU1_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU2_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU2_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU3_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU3_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C66X_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C66X_2 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C7X_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MPU1_1 */
+    },
+
+    /* Host Processor - mcu2_0 	*/
+    {
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MPU1_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU1_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU1_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU2_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU2_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU3_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU3_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C66X_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C66X_2 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C7X_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MPU1_1 */
+    },
+
+    /* Host Processor - mcu2_1 	*/
+    {
+        { { 1U, 2U,  3U}, { 1U, 2U, 2U} },    /* IPC_MPU1_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU1_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU1_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU2_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU2_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU3_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU3_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C66X_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C66X_2 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C7X_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MPU1_1 */
+    },
+
+    /* Host Processor - mcu3_0 	*/
+    {
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MPU1_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU1_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU1_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU2_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU2_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU3_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU3_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C66X_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C66X_2 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C7X_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MPU1_1 */
+    },
+
+    /* Host Processor - mcu3_1 	*/
+    {
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MPU1_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU1_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU1_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU2_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU2_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU3_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU3_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C66X_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C66X_2 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C7X_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MPU1_1 */
+    },
+
+    /* Host Processor - c66xdsp_1 	*/
+    {
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MPU1_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU1_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU1_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU2_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU2_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU3_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU3_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C66X_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C66X_2 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C7X_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MPU1_1 */
+    },
+
+    /* Host Processor - c66xdsp_2 	*/
+    {
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MPU1_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU1_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU1_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU2_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU2_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU3_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU3_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C66X_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C66X_2 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C7X_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MPU1_1 */
+    },
+
+    /* Host Processor - c7x_1 	*/
+    {
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MPU1_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU1_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU1_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU2_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU2_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU3_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU3_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C66X_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C66X_2 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C7X_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MPU1_1 */
+    },
+
+    /* Host Processor - A72-vm1 	*/
+    {
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MPU1_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU1_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU1_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU2_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU2_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU3_0 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MCU3_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C66X_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C66X_2 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_C7X_1 */
+        { { 255U, 255U,  255U}, { 255U, 255U, 255U} },    /* IPC_MPU1_1 */
+    },
+};
+
+/* @} */
+#define  CDD_IPC_STOP_SEC_CONFIG_DATA
+#include "Cdd_Ipc_MemMap.h"
+
+#define CDD_IPC_START_SEC_ISR_CODE
+#include "Cdd_Ipc_MemMap.h"
+
+/** \brief ISR for New Message, from MPU 1 0*/
+CDD_IPC_ISR_TEXT_SECTION ISR(Cdd_IpcIrqMbxFromMpu_10)
+{
+    Cdd_IpcIrq_Fun(CDD_IPC_CORE_MPU1_0);
+    return;
+}
+
+
+#define CDD_IPC_STOP_SEC_ISR_CODE
+#include "Cdd_Ipc_MemMap.h"
+
+
+
+    
+
+    
+    
+
+/*******************************************************************************
+ *  END OF FILE: Cdd_IpcCfg.c
+ ******************************************************************************/
-- 
2.34.1

