root@am62axx-evm:~/tidl_inference# python3 tidl_model_inference.py -i test_image/sample2MP.jpg libtidl_onnxrt_EP loaded 0xadab450 artifacts_folder = ./artifacts/artifact_multihead_20250722_mod_w_datacvt_8bit_12_10 debug_level = 2 target_priority = 0 max_pre_empt_delay = 340282346638528859811704183484516925440.000000 Final number of subgraphs created are : 16, - Offloaded Nodes - 380, Total Nodes - 420 In TIDL_createStateInfer Compute on node : TIDLExecutionProvider_TIDL_0_0 ************ in TIDL_subgraphRtCreate ************ APP: Init ... !!! 104.584624 s: MEM: Init ... !!! 104.584703 s: MEM: Initialized DMA HEAP (fd=5) !!! 104.584927 s: MEM: Init ... Done !!! 104.584962 s: IPC: Init ... !!! 104.602896 s: IPC: Init ... Done !!! REMOTE_SERVICE: Init ... !!! REMOTE_SERVICE: Init ... Done !!! 104.609501 s: GTC Frequency = 200 MHz APP: Init ... Done !!! 104.614739 s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 104.614790 s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 104.614809 s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 104.617467 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target MPU-0 104.617685 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target MPU-1 104.617861 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target MPU-2 104.617986 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:134] Added target MPU-3 104.618005 s: VX_ZONE_INFO: [tivxInitLocal:126] Initialization Done !!! 104.618038 s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO [C7x_1 ] 104.650403 s: PREEMPTION: Requesting memory of size 1048576 for targetPriority = 0 [C7x_1 ] 104.650433 s: [C7x_1 ] 104.650455 s: -------------------------------------------- [C7x_1 ] 104.650486 s: TIDL Memory size requiement (record wise): [C7x_1 ] 104.650537 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 104.650592 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0x00000000 [C7x_1 ] 104.650646 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0x00000000 [C7x_1 ] 104.650700 s: 2 , L1D , Scratch , 128, 16.00 , 0x00000000 [C7x_1 ] 104.650761 s: 3 , L2 , Scratch , 128, 224.00 , 0x00000000 [C7x_1 ] 104.650814 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x00000000 [C7x_1 ] 104.650866 s: 5 , DDR Cacheable , Persistent , 128, 1295.51 , 0x00000000 [C7x_1 ] 104.650916 s: 6 , DDR Cacheable , Scratch , 128, 15.25 , 0x00000000 [C7x_1 ] 104.650968 s: 7 , DDR Cacheable , Persistent , 128, 7762.75 , 0x00000000 [C7x_1 ] 104.651020 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0x00000000 [C7x_1 ] 104.651071 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0x00000000 [C7x_1 ] 104.651120 s: 10 , DDR Cacheable , Persistent , 128, 1381.44 , 0x00000000 [C7x_1 ] 104.651171 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0x00000000 [C7x_1 ] 104.651222 s: 12 , DDR Cacheable , Persistent , 128, 1024.00 , 0x00000000 [C7x_1 ] 104.651273 s: 13 , DDR Cacheable , Persistent , 128, 1691.92 , 0x00000000 [C7x_1 ] 104.651323 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0x00000000 [C7x_1 ] 104.651373 s: 15 , DDR Cacheable , Persistent , 128, 2066.25 , 0x00000000 [C7x_1 ] 104.651410 s: -------------------------------------------- [C7x_1 ] 104.651440 s: Total memory size requirement (space wise): [C7x_1 ] 104.651466 s: Mem Space , Size(KBytes) [C7x_1 ] 104.651491 s: L1D , 16.00 [C7x_1 ] 104.651517 s: L2 , 224.00 [C7x_1 ] 104.651541 s: L3/MSMC , 1024.00 [C7x_1 ] 104.651567 s: DDR Cacheable, 15772.54 [C7x_1 ] 104.651596 s: -------------------------------------------- [C7x_1 ] 104.651637 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 104.651683 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 104.651711 s: debugTraceLevel = 2 [C7x_1 ] 104.651723 s: [C7x_1 ] 104.651757 s: -------------------------------------------- [C7x_1 ] 104.652675 s: TIDL init call from ivision API [C7x_1 ] 104.652697 s: [C7x_1 ] 104.652717 s: -------------------------------------------- [C7x_1 ] 104.652752 s: TIDL Memory size requiement (record wise): [C7x_1 ] 104.652800 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 104.652852 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0xb2026cc0 [C7x_1 ] 104.652905 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0xb202ba80 [C7x_1 ] 104.652956 s: 2 , L1D , Scratch , 128, 16.00 , 0x7f03c000 [C7x_1 ] 104.653007 s: 3 , L2 , Scratch , 128, 224.00 , 0x7f000000 [C7x_1 ] 104.653058 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x7e000000 [C7x_1 ] 104.653110 s: 5 , DDR Cacheable , Persistent , 128, 1295.51 , 0xb202bdc0 [C7x_1 ] 104.653161 s: 6 , DDR Cacheable , Scratch , 128, 15.25 , 0xb9000000 [C7x_1 ] 104.653212 s: 7 , DDR Cacheable , Persistent , 128, 7762.75 , 0xb216fc80 [C7x_1 ] 104.653263 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0xb9004000 [C7x_1 ] 104.653314 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0xb9004400 [C7x_1 ] 104.653365 s: 10 , DDR Cacheable , Persistent , 128, 1381.44 , 0xb29047c0 [C7x_1 ] 104.653416 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0xb9005400 [C7x_1 ] 104.653467 s: 12 , DDR Cacheable , Persistent , 128, 1024.00 , 0xb2a5de00 [C7x_1 ] 104.653517 s: 13 , DDR Cacheable , Persistent , 128, 1691.92 , 0xb2b5de40 [C7x_1 ] 104.653567 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0xb2d04e80 [C7x_1 ] 104.653616 s: 15 , DDR Cacheable , Persistent , 128, 2066.25 , 0xb2d04f40 [C7x_1 ] 104.653650 s: -------------------------------------------- [C7x_1 ] 104.653679 s: Total memory size requirement (space wise): [C7x_1 ] 104.653704 s: Mem Space , Size(KBytes) [C7x_1 ] 104.653727 s: L1D , 16.00 [C7x_1 ] 104.653758 s: L2 , 224.00 [C7x_1 ] 104.653784 s: L3/MSMC , 1024.00 [C7x_1 ] 104.653811 s: DDR Cacheable, 15772.54 [C7x_1 ] 104.653838 s: -------------------------------------------- [C7x_1 ] 104.653879 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 104.653923 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 104.653950 s: debugTraceLevel = 2 [C7x_1 ] 104.653963 s: [C7x_1 ] 104.653987 s: -------------------------------------------- [C7x_1 ] 104.658815 s: Alg Init for Layer # - 1 [C7x_1 ] 104.658963 s: Alg Init for Layer # - 2 [C7x_1 ] 104.659307 s: Alg Init for Layer # - 3 [C7x_1 ] 104.659649 s: Alg Init for Layer # - 4 [C7x_1 ] 104.660083 s: Alg Init for Layer # - 5 [C7x_1 ] 104.660380 s: Alg Init for Layer # - 6 [C7x_1 ] 104.660658 s: Alg Init for Layer # - 7 [C7x_1 ] 104.660923 s: Alg Init for Layer # - 8 [C7x_1 ] 104.661184 s: Alg Init for Layer # - 9 [C7x_1 ] 104.661364 s: Alg Init for Layer # - 10 [C7x_1 ] 104.661553 s: Alg Init for Layer # - 11 [C7x_1 ] 104.661846 s: Alg Init for Layer # - 12 [C7x_1 ] 104.662204 s: Alg Init for Layer # - 13 [C7x_1 ] 104.662453 s: Alg Init for Layer # - 14 [C7x_1 ] 104.662708 s: Alg Init for Layer # - 15 [C7x_1 ] 104.662955 s: Alg Init for Layer # - 16 [C7x_1 ] 104.663223 s: Alg Init for Layer # - 17 [C7x_1 ] 104.663405 s: Alg Init for Layer # - 18 [C7x_1 ] 104.663644 s: Alg Init for Layer # - 19 [C7x_1 ] 104.663924 s: Alg Init for Layer # - 20 [C7x_1 ] 104.664103 s: Alg Init for Layer # - 21 [C7x_1 ] 104.664344 s: Alg Init for Layer # - 22 [C7x_1 ] 104.664610 s: Alg Init for Layer # - 23 [C7x_1 ] 104.664803 s: Alg Init for Layer # - 24 [C7x_1 ] 104.664978 s: Alg Init for Layer # - 25 [C7x_1 ] 104.665249 s: Alg Init for Layer # - 26 [C7x_1 ] 104.665805 s: Alg Init for Layer # - 27 [C7x_1 ] 104.666098 s: Alg Init for Layer # - 28 [C7x_1 ] 104.666378 s: Alg Init for Layer # - 29 [C7x_1 ] 104.666631 s: Alg Init for Layer # - 30 [C7x_1 ] 104.667008 s: Alg Init for Layer # - 31 [C7x_1 ] 104.667203 s: Alg Init for Layer # - 32 [C7x_1 ] 104.667449 s: Alg Init for Layer # - 33 [C7x_1 ] 104.667828 s: Alg Init for Layer # - 34 [C7x_1 ] 104.668015 s: Alg Init for Layer # - 35 [C7x_1 ] 104.668268 s: Alg Init for Layer # - 36 [C7x_1 ] 104.668631 s: Alg Init for Layer # - 37 [C7x_1 ] 104.668830 s: Alg Init for Layer # - 38 [C7x_1 ] 104.669011 s: Alg Init for Layer # - 39 [C7x_1 ] 104.669332 s: Alg Init for Layer # - 40 [C7x_1 ] 104.670617 s: Alg Init for Layer # - 41 [C7x_1 ] 104.671025 s: Alg Init for Layer # - 42 [C7x_1 ] 104.671173 s: Alg Init for Layer # - 43 [C7x_1 ] 104.671297 s: Alg Init for Layer # - 44 [C7x_1 ] 104.671424 s: Alg Init for Layer # - 45 [C7x_1 ] 104.671553 s: Alg Init for Layer # - 46 [C7x_1 ] 104.671681 s: Alg Init for Layer # - 47 [C7x_1 ] 104.671821 s: Alg Init for Layer # - 48 [C7x_1 ] 104.672136 s: Alg Init for Layer # - 49 [C7x_1 ] 104.672894 s: Alg Init for Layer # - 50 [C7x_1 ] 104.673293 s: Alg Init for Layer # - 51 [C7x_1 ] 104.673676 s: Alg Init for Layer # - 52 [C7x_1 ] 104.674025 s: Alg Init for Layer # - 53 [C7x_1 ] 104.674804 s: Alg Init for Layer # - 54 [C7x_1 ] 104.675007 s: Alg Init for Layer # - 55 [C7x_1 ] 104.675531 s: Alg Init for Layer # - 56 [C7x_1 ] 104.675928 s: Alg Init for Layer # - 57 [C7x_1 ] 104.676085 s: Alg Init for Layer # - 58 [C7x_1 ] 104.676274 s: Alg Init for Layer # - 59 [C7x_1 ] 104.676625 s: Alg Init for Layer # - 60 [C7x_1 ] 104.676984 s: Alg Init for Layer # - 61 [C7x_1 ] 104.677258 s: Alg Init for Layer # - 62 [C7x_1 ] 104.677659 s: Alg Init for Layer # - 63 [C7x_1 ] 104.677878 s: Alg Init for Layer # - 64 [C7x_1 ] 104.678215 s: Alg Init for Layer # - 65 [C7x_1 ] 104.678506 s: Alg Init for Layer # - 66 [C7x_1 ] 104.678656 s: Alg Init for Layer # - 67 [C7x_1 ] 104.678853 s: Alg Init for Layer # - 68 [C7x_1 ] 104.679182 s: Alg Init for Layer # - 69 [C7x_1 ] 104.679504 s: Alg Init for Layer # - 70 [C7x_1 ] 104.679792 s: Alg Init for Layer # - 71 [C7x_1 ] 104.680104 s: Alg Init for Layer # - 72 [C7x_1 ] 104.680311 s: Alg Init for Layer # - 73 [C7x_1 ] 104.680615 s: Alg Init for Layer # - 74 [C7x_1 ] 104.680759 s: Alg Init for Layer # - 75 [C7x_1 ] 104.681093 s: Alg Init for Layer # - 76 [C7x_1 ] 104.681531 s: Alg Init for Layer # - 77 [C7x_1 ] 104.681741 s: Alg Init for Layer # - 78 [C7x_1 ] 104.682051 s: Alg Init for Layer # - 79 [C7x_1 ] 104.682369 s: Alg Init for Layer # - 80 [C7x_1 ] 104.682654 s: Alg Init for Layer # - 81 [C7x_1 ] 104.683075 s: Alg Init for Layer # - 82 [C7x_1 ] 104.683276 s: Alg Init for Layer # - 83 [C7x_1 ] 104.683650 s: Alg Init for Layer # - 85 [C7x_1 ] 104.683793 s: Alg Init for Layer # - 86 [C7x_1 ] 104.684117 s: Alg Init for Layer # - 87 [C7x_1 ] 104.684269 s: Alg Init for Layer # - 88 [C7x_1 ] 104.685081 s: Alg Init for Layer # - 89 [C7x_1 ] 104.685293 s: Alg Init for Layer # - 90 [C7x_1 ] 104.685705 s: Alg Init for Layer # - 91 [C7x_1 ] 104.686124 s: Alg Init for Layer # - 92 [C7x_1 ] 104.686486 s: Alg Init for Layer # - 93 [C7x_1 ] 104.687310 s: Alg Init for Layer # - 94 [C7x_1 ] 104.687516 s: Alg Init for Layer # - 95 [C7x_1 ] 104.688106 s: Alg Init for Layer # - 97 [C7x_1 ] 104.688250 s: Alg Init for Layer # - 98 [C7x_1 ] 104.688606 s: Alg Init for Layer # - 99 [C7x_1 ] 104.688775 s: Alg Init for Layer # - 100 [C7x_1 ] 104.689027 s: Alg Init for Layer # - 101 [C7x_1 ] 104.689830 s: Alg Init for Layer # - 102 [C7x_1 ] 104.690303 s: Alg Init for Layer # - 103 [C7x_1 ] 104.690636 s: Alg Init for Layer # - 104 [C7x_1 ] 104.690826 s: Alg Init for Layer # - 105 [C7x_1 ] 104.690971 s: Alg Init for Layer # - 106 [C7x_1 ] 104.691144 s: Alg Init for Layer # - 107 [C7x_1 ] 104.691328 s: Alg Init for Layer # - 108 [C7x_1 ] 104.691608 s: Alg Init for Layer # - 116 [C7x_1 ] 104.691683 s: Alg Init for Layer # - 118 [C7x_1 ] 104.691879 s: Alg Init for Layer # - 119 [C7x_1 ] 104.692057 s: Alg Init for Layer # - 122 [C7x_1 ] 104.692131 s: Alg Init for Layer # - 123 [C7x_1 ] 104.692318 s: Alg Init for Layer # - 124 [C7x_1 ] 104.692399 s: Alg Init for Layer # - 125 [C7x_1 ] 104.692528 s: Alg Init for Layer # - 109 [C7x_1 ] 104.693336 s: Alg Init for Layer # - 110 [C7x_1 ] 104.693850 s: Alg Init for Layer # - 112 [C7x_1 ] 104.693989 s: Alg Init for Layer # - 113 [C7x_1 ] 104.694308 s: Alg Init for Layer # - 115 [C7x_1 ] 104.694423 s: Alg Init for Layer # - 117 [C7x_1 ] 104.694506 s: Alg Init for Layer # - 120 [C7x_1 ] 104.694708 s: PREEMPTION: Adding a new priority object for targetPriority = 0, handle = b2026cc0 [C7x_1 ] 104.694783 s: PREEMPTION: Now total number of priority objects = 1 at priorityId = 0, with new memRec of base = b2a5de00 and size = 1048576 [C7x_1 ] 104.694852 s: PREEMPTION: Requesting context memory addr for handle b2026cc0, return Addr = 9a2cfff0 [C7x_1 ] 104.694890 s: Print preEmption Hnadle during init stage : [C7x_1 ] 104.694922 s: ProcTime, ctxSize, dataId [C7x_1 ] 104.694956 s: 0.000, 7948, 0 [C7x_1 ] 104.694991 s: 0.892, 7948, 1 [C7x_1 ] 104.695022 s: 0.359, 7948, 2 [C7x_1 ] 104.695053 s: 0.466, 7948, 3 [C7x_1 ] 104.695083 s: 0.337, 812812, 4 [C7x_1 ] 104.695113 s: 0.094, 812812, 5 [C7x_1 ] 104.695143 s: 0.041, 410380, 6 [C7x_1 ] 104.695173 s: 0.041, 812812, 7 [C7x_1 ] 104.695205 s: 0.153, 812812, 8 [C7x_1 ] 104.695235 s: 0.034, 410380, 9 [C7x_1 ] 104.695266 s: 0.200, 7948, 10 [C7x_1 ] 104.695297 s: 0.125, 812812, 11 [C7x_1 ] 104.695326 s: 0.301, 7948, 12 [C7x_1 ] 104.695357 s: 0.065, 210700, 13 [C7x_1 ] 104.695386 s: 0.066, 413452, 14 [C7x_1 ] 104.695415 s: 0.019, 616204, 15 [C7x_1 ] 104.695444 s: 0.070, 616204, 16 [C7x_1 ] 104.695474 s: 0.020, 413452, 17 [C7x_1 ] 104.695505 s: 0.019, 616204, 18 [C7x_1 ] 104.695534 s: 0.070, 616204, 19 [C7x_1 ] 104.695563 s: 0.020, 413452, 20 [C7x_1 ] 104.695593 s: 0.019, 616204, 21 [C7x_1 ] 104.695622 s: 0.070, 616204, 22 [C7x_1 ] 104.695653 s: 0.020, 413452, 23 [C7x_1 ] 104.695683 s: 0.028, 413452, 24 [C7x_1 ] 104.695714 s: 0.042, 413452, 25 [C7x_1 ] 104.695752 s: 0.306, 618252, 26 [C7x_1 ] 104.695783 s: 0.028, 720652, 27 [C7x_1 ] 104.695813 s: 0.028, 618252, 28 [C7x_1 ] 104.695842 s: 0.019, 720652, 29 [C7x_1 ] 104.695871 s: 0.078, 720652, 30 [C7x_1 ] 104.695900 s: 0.014, 618252, 31 [C7x_1 ] 104.695930 s: 0.019, 720652, 32 [C7x_1 ] 104.695960 s: 0.078, 720652, 33 [C7x_1 ] 104.695989 s: 0.014, 618252, 34 [C7x_1 ] 104.696018 s: 0.019, 720652, 35 [C7x_1 ] 104.696047 s: 0.078, 720652, 36 [C7x_1 ] 104.696078 s: 0.014, 618252, 37 [C7x_1 ] 104.696108 s: 0.021, 618252, 38 [C7x_1 ] 104.696138 s: 0.045, 618252, 39 [C7x_1 ] 104.696167 s: 0.621, 618252, 40 [C7x_1 ] 104.696197 s: 0.043, 675596, 41 [C7x_1 ] 104.696228 s: 0.011, 732940, 42 [C7x_1 ] 104.696259 s: 0.011, 732940, 43 [C7x_1 ] 104.696289 s: 0.011, 790284, 44 [C7x_1 ] 104.696319 s: 0.011, 790284, 45 [C7x_1 ] 104.696350 s: 0.011, 847628, 46 [C7x_1 ] 104.696380 s: 0.011, 847628, 47 [C7x_1 ] 104.696412 s: 0.065, 618252, 48 [C7x_1 ] 104.696444 s: 0.109, 732940, 49 [C7x_1 ] 104.696474 s: 0.031, 790284, 50 [C7x_1 ] 104.696504 s: 0.031, 732940, 51 [C7x_1 ] 104.696534 s: 0.020, 732940, 52 [C7x_1 ] 104.696564 s: 0.096, 732940, 53 [C7x_1 ] 104.696595 s: 0.016, 732940, 54 [C7x_1 ] 104.696626 s: 0.051, 732940, 55 [C7x_1 ] 104.696655 s: 0.031, 675596, 56 [C7x_1 ] 104.696684 s: 0.017, 896780, 57 [C7x_1 ] 104.696714 s: 0.087, 470796, 58 [C7x_1 ] 104.696752 s: 0.071, 573196, 59 [C7x_1 ] 104.696786 s: 0.071, 675596, 60 [C7x_1 ] 104.696818 s: 0.019, 675596, 61 [C7x_1 ] 104.696849 s: 0.078, 675596, 62 [C7x_1 ] 104.696877 s: 0.021, 691980, 63 [C7x_1 ] 104.696907 s: 0.045, 691980, 64 [C7x_1 ] 104.696937 s: 0.028, 581388, 65 [C7x_1 ] 104.696967 s: 0.072, 581388, 66 [C7x_1 ] 104.696998 s: 0.199, 175884, 67 [C7x_1 ] 104.697028 s: 0.129, 378636, 68 [C7x_1 ] 104.697058 s: 0.129, 581388, 69 [C7x_1 ] 104.697089 s: 0.019, 581388, 70 [C7x_1 ] 104.697119 s: 0.070, 581388, 71 [C7x_1 ] 104.697152 s: 0.083, 175884, 72 [C7x_1 ] 104.697184 s: 0.067, 581388, 73 [C7x_1 ] 104.697213 s: 0.480, 581388, 74 [C7x_1 ] 104.697244 s: 0.000, 581388, 84 [C7x_1 ] 104.697275 s: 0.082, 581388, 75 [C7x_1 ] 104.697306 s: 0.159, 278284, 76 [C7x_1 ] 104.697338 s: 0.021, 270092, 77 [C7x_1 ] 104.697368 s: 0.028, 372492, 78 [C7x_1 ] 104.697398 s: 0.028, 270092, 79 [C7x_1 ] 104.697427 s: 0.019, 270092, 80 [C7x_1 ] 104.697456 s: 0.078, 270092, 81 [C7x_1 ] 104.697487 s: 0.021, 286476, 82 [C7x_1 ] 104.697517 s: 0.048, 65292, 83 [C7x_1 ] 104.697547 s: 0.155, 65292, 85 [C7x_1 ] 104.697577 s: 0.000, 65292, 96 [C7x_1 ] 104.697609 s: 0.040, 175884, 86 [C7x_1 ] 104.697640 s: 0.026, 487180, 87 [C7x_1 ] 104.697672 s: 0.326, 544524, 88 [C7x_1 ] 104.697705 s: 0.016, 544524, 89 [C7x_1 ] 104.697739 s: 0.031, 601868, 90 [C7x_1 ] 104.697771 s: 0.031, 544524, 91 [C7x_1 ] 104.697802 s: 0.020, 544524, 92 [C7x_1 ] 104.697832 s: 0.096, 544524, 93 [C7x_1 ] 104.697862 s: 0.016, 544524, 94 [C7x_1 ] 104.697893 s: 0.053, 429836, 95 [C7x_1 ] 104.697924 s: 0.088, 429836, 97 [C7x_1 ] 104.697953 s: 0.000, 429836, 111 [C7x_1 ] 104.697983 s: 0.033, 458508, 98 [C7x_1 ] 104.698013 s: 0.025, 859916, 99 [C7x_1 ] 104.698043 s: 0.282, 7948, 100 [C7x_1 ] 104.698075 s: 0.782, 413452, 101 [C7x_1 ] 104.698104 s: 0.265, 413452, 102 [C7x_1 ] 104.698134 s: 0.026, 71308, 103 [C7x_1 ] 104.698163 s: 0.013, 71308, 104 [C7x_1 ] 104.698193 s: 0.010, 134668, 105 [C7x_1 ] 104.698225 s: 0.013, 198028, 106 [C7x_1 ] 104.698253 s: 0.011, 134668, 107 [C7x_1 ] 104.698282 s: 0.013, 134028, 108 [C7x_1 ] 104.698311 s: 0.006, 134028, 116 [C7x_1 ] 104.698340 s: 0.012, 134156, 118 [C7x_1 ] 104.698372 s: 0.012, 134028, 119 [C7x_1 ] 104.698400 s: 0.006, 134028, 122 [C7x_1 ] 104.698429 s: 0.011, 70668, 123 [C7x_1 ] 104.698459 s: 0.006, 70668, 124 [C7x_1 ] 104.698488 s: 0.045, 7948, 125 [C7x_1 ] 104.698519 s: 0.000, 7948, 126 [C7x_1 ] 104.698549 s: 0.782, 413452, 109 [C7x_1 ] 104.698578 s: 0.267, 7948, 110 [C7x_1 ] 104.698607 s: 0.298, 7948, 112 [C7x_1 ] 104.698637 s: 0.000, 7948, 114 [C7x_1 ] 104.698668 s: 0.068, 7948, 113 [C7x_1 ] 104.698696 s: 0.031, 14220, 115 [C7x_1 ] 104.698726 s: 0.006, 14220, 117 [C7x_1 ] 104.698761 s: 0.011, 7948, 120 [C7x_1 ] 104.698792 s: 0.000, 0, 121 [C7x_1 ] 104.698917 s: TIDL_initializeHandleForPreemption is completed RT-Profile: TIDLRT_init_profiling tidlrt_create : 122917450 ns, tidl_rt_ovx_Init : 37334288 ns, vxCreateContext : 2928111 ns, init_tidl_tiovx : 6044542 ns, create_graph_tidl_tiovx : 6475117 ns, verify_graph_tidl_tiovx : 69598628 ns, tivxTIDLLoadKernels : 36295 ns, mapConfig : 637734 ns, tivxAddKernelTIDL : 108845 ns, mapNetwork : 4640159 ns, setCreateParams : 282090 ns, setArgs : 336165 ns, vxCreateUserDataObject : 37390 ns, vxMapUserDataObject : 2214142 ns, memcopy_network_buffer : 2122233 ns, vxUnmapUserDataObject : 263139 ns, ************ TIDL_subgraphRtCreate done ************ In TIDL_createStateInfer Compute on node : TIDLExecutionProvider_TIDL_1_1 ************ in TIDL_subgraphRtCreate ************ [C7x_1 ] 104.728361 s: PREEMPTION: Requesting memory of size 128 for targetPriority = 0 [C7x_1 ] 104.728389 s: [C7x_1 ] 104.728411 s: -------------------------------------------- [C7x_1 ] 104.728441 s: TIDL Memory size requiement (record wise): [C7x_1 ] 104.728489 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 104.728543 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0x00000000 [C7x_1 ] 104.728596 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0x00000000 [C7x_1 ] 104.728648 s: 2 , L1D , Scratch , 128, 16.00 , 0x00000000 [C7x_1 ] 104.728698 s: 3 , L2 , Scratch , 128, 224.00 , 0x00000000 [C7x_1 ] 104.728761 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x00000000 [C7x_1 ] 104.728813 s: 5 , DDR Cacheable , Persistent , 128, 291.40 , 0x00000000 [C7x_1 ] 104.728865 s: 6 , DDR Cacheable , Scratch , 128, 0.88 , 0x00000000 [C7x_1 ] 104.728914 s: 7 , DDR Cacheable , Persistent , 128, 2.75 , 0x00000000 [C7x_1 ] 104.728964 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0x00000000 [C7x_1 ] 104.729013 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0x00000000 [C7x_1 ] 104.729064 s: 10 , DDR Cacheable , Persistent , 128, 293.43 , 0x00000000 [C7x_1 ] 104.729115 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0x00000000 [C7x_1 ] 104.729167 s: 12 , DDR Cacheable , Persistent , 128, 0.13 , 0x00000000 [C7x_1 ] 104.729218 s: 13 , DDR Cacheable , Persistent , 128, 1254.90 , 0x00000000 [C7x_1 ] 104.729268 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0x00000000 [C7x_1 ] 104.729319 s: 15 , DDR Cacheable , Persistent , 128, 0.25 , 0x00000000 [C7x_1 ] 104.729354 s: -------------------------------------------- [C7x_1 ] 104.729386 s: Total memory size requirement (space wise): [C7x_1 ] 104.729412 s: Mem Space , Size(KBytes) [C7x_1 ] 104.729436 s: L1D , 16.00 [C7x_1 ] 104.729462 s: L2 , 224.00 [C7x_1 ] 104.729488 s: L3/MSMC , 1024.00 [C7x_1 ] 104.729516 s: DDR Cacheable, 2379.16 [C7x_1 ] 104.729544 s: -------------------------------------------- [C7x_1 ] 104.729586 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 104.729632 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 104.729661 s: debugTraceLevel = 2 [C7x_1 ] 104.729673 s: [C7x_1 ] 104.729697 s: -------------------------------------------- [C7x_1 ] 104.729860 s: TIDL init call from ivision API [C7x_1 ] 104.729882 s: [C7x_1 ] 104.729902 s: -------------------------------------------- [C7x_1 ] 104.729932 s: TIDL Memory size requiement (record wise): [C7x_1 ] 104.729977 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 104.730029 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0xb2f30340 [C7x_1 ] 104.730081 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0xb2f35100 [C7x_1 ] 104.730134 s: 2 , L1D , Scratch , 128, 16.00 , 0x7f03c000 [C7x_1 ] 104.730186 s: 3 , L2 , Scratch , 128, 224.00 , 0x7f000000 [C7x_1 ] 104.730238 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x7e000000 [C7x_1 ] 104.730289 s: 5 , DDR Cacheable , Persistent , 128, 291.40 , 0xb2f35440 [C7x_1 ] 104.730340 s: 6 , DDR Cacheable , Scratch , 128, 0.88 , 0xb9000000 [C7x_1 ] 104.730392 s: 7 , DDR Cacheable , Persistent , 128, 2.75 , 0xb2f7e280 [C7x_1 ] 104.730444 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0xb9000400 [C7x_1 ] 104.730494 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0xb9000800 [C7x_1 ] 104.730546 s: 10 , DDR Cacheable , Persistent , 128, 293.43 , 0xb2f7edc0 [C7x_1 ] 104.730597 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0xb9001800 [C7x_1 ] 104.730650 s: 12 , DDR Cacheable , Persistent , 128, 0.13 , 0xb2fc8400 [C7x_1 ] 104.730703 s: 13 , DDR Cacheable , Persistent , 128, 1254.90 , 0xb2fc84c0 [C7x_1 ] 104.730760 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0xb3102100 [C7x_1 ] 104.730814 s: 15 , DDR Cacheable , Persistent , 128, 0.25 , 0xb31021c0 [C7x_1 ] 104.730849 s: -------------------------------------------- [C7x_1 ] 104.730880 s: Total memory size requirement (space wise): [C7x_1 ] 104.730904 s: Mem Space , Size(KBytes) [C7x_1 ] 104.730929 s: L1D , 16.00 [C7x_1 ] 104.730956 s: L2 , 224.00 [C7x_1 ] 104.730981 s: L3/MSMC , 1024.00 [C7x_1 ] 104.731007 s: DDR Cacheable, 2379.16 [C7x_1 ] 104.731036 s: -------------------------------------------- [C7x_1 ] 104.731076 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 104.731122 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 104.731151 s: debugTraceLevel = 2 [C7x_1 ] 104.731164 s: [C7x_1 ] 104.731189 s: -------------------------------------------- [C7x_1 ] 104.735245 s: Alg Init for Layer # - 1 [C7x_1 ] 104.735331 s: Alg Init for Layer # - 2 [C7x_1 ] 104.735413 s: Alg Init for Layer # - 3 [C7x_1 ] 104.735607 s: Alg Init for Layer # - 4 [C7x_1 ] 104.735682 s: Alg Init for Layer # - 5 [C7x_1 ] 104.735799 s: PREEMPTION: Adding a new priority object for targetPriority = 0, handle = b2f30340 [C7x_1 ] 104.735866 s: PREEMPTION: Now total number of priority objects = 2 at priorityId = 0, with new memRec of base = b2fc8400 and size = 128 [C7x_1 ] 104.735939 s: PREEMPTION: Requesting context memory addr for handle b2f30340, return Addr = 9a2cfff0 [C7x_1 ] 104.735975 s: Print preEmption Hnadle during init stage : [C7x_1 ] 104.736004 s: ProcTime, ctxSize, dataId [C7x_1 ] 104.736037 s: 0.000, 6508, 0 [C7x_1 ] 104.736068 s: 0.006, 6636, 1 [C7x_1 ] 104.736100 s: 0.006, 6636, 2 [C7x_1 ] 104.736132 s: 0.006, 6636, 3 [C7x_1 ] 104.736161 s: 0.006, 6636, 4 [C7x_1 ] 104.736191 s: 0.008, 6508, 5 [C7x_1 ] 104.736221 s: 0.000, 0, 6 [C7x_1 ] 104.736261 s: TIDL_initializeHandleForPreemption is completed RT-Profile: TIDLRT_init_profiling tidlrt_create : 16732794 ns, tidl_rt_ovx_Init : 11490 ns, vxCreateContext : 11490 ns, init_tidl_tiovx : 2830446 ns, create_graph_tidl_tiovx : 283665 ns, verify_graph_tidl_tiovx : 13314633 ns, tivxTIDLLoadKernels : 950 ns, mapConfig : 514004 ns, tivxAddKernelTIDL : 105790 ns, mapNetwork : 1591663 ns, setCreateParams : 280060 ns, setArgs : 335774 ns, vxCreateUserDataObject : 35060 ns, vxMapUserDataObject : 822884 ns, memcopy_network_buffer : 639984 ns, vxUnmapUserDataObject : 91115 ns, ************ TIDL_subgraphRtCreate done ************ In TIDL_createStateInfer Compute on node : TIDLExecutionProvider_TIDL_2_2 ************ in TIDL_subgraphRtCreate ************ [C7x_1 ] 104.768123 s: PREEMPTION: Requesting memory of size 128 for targetPriority = 0 [C7x_1 ] 104.768151 s: [C7x_1 ] 104.768174 s: -------------------------------------------- [C7x_1 ] 104.768205 s: TIDL Memory size requiement (record wise): [C7x_1 ] 104.768251 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 104.768308 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0x00000000 [C7x_1 ] 104.768360 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0x00000000 [C7x_1 ] 104.768413 s: 2 , L1D , Scratch , 128, 16.00 , 0x00000000 [C7x_1 ] 104.768465 s: 3 , L2 , Scratch , 128, 224.00 , 0x00000000 [C7x_1 ] 104.768516 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x00000000 [C7x_1 ] 104.768567 s: 5 , DDR Cacheable , Persistent , 128, 464.18 , 0x00000000 [C7x_1 ] 104.768617 s: 6 , DDR Cacheable , Scratch , 128, 5.38 , 0x00000000 [C7x_1 ] 104.768670 s: 7 , DDR Cacheable , Persistent , 128, 1598.38 , 0x00000000 [C7x_1 ] 104.768719 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0x00000000 [C7x_1 ] 104.768779 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0x00000000 [C7x_1 ] 104.768830 s: 10 , DDR Cacheable , Persistent , 128, 634.02 , 0x00000000 [C7x_1 ] 104.768883 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0x00000000 [C7x_1 ] 104.768934 s: 12 , DDR Cacheable , Persistent , 128, 0.13 , 0x00000000 [C7x_1 ] 104.768983 s: 13 , DDR Cacheable , Persistent , 128, 1379.88 , 0x00000000 [C7x_1 ] 104.769034 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0x00000000 [C7x_1 ] 104.769085 s: 15 , DDR Cacheable , Persistent , 128, 0.88 , 0x00000000 [C7x_1 ] 104.769119 s: -------------------------------------------- [C7x_1 ] 104.769150 s: Total memory size requirement (space wise): [C7x_1 ] 104.769178 s: Mem Space , Size(KBytes) [C7x_1 ] 104.769205 s: L1D , 16.00 [C7x_1 ] 104.769232 s: L2 , 224.00 [C7x_1 ] 104.769257 s: L3/MSMC , 1024.00 [C7x_1 ] 104.769284 s: DDR Cacheable, 4618.26 [C7x_1 ] 104.769311 s: -------------------------------------------- [C7x_1 ] 104.769351 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 104.769396 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 104.769424 s: debugTraceLevel = 2 [C7x_1 ] 104.769437 s: [C7x_1 ] 104.769461 s: -------------------------------------------- [C7x_1 ] 104.769751 s: TIDL init call from ivision API [C7x_1 ] 104.769772 s: [C7x_1 ] 104.769793 s: -------------------------------------------- [C7x_1 ] 104.769823 s: TIDL Memory size requiement (record wise): [C7x_1 ] 104.769869 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 104.769922 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0xb3128dc0 [C7x_1 ] 104.769974 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0xb312db80 [C7x_1 ] 104.770023 s: 2 , L1D , Scratch , 128, 16.00 , 0x7f03c000 [C7x_1 ] 104.770076 s: 3 , L2 , Scratch , 128, 224.00 , 0x7f000000 [C7x_1 ] 104.770126 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x7e000000 [C7x_1 ] 104.770178 s: 5 , DDR Cacheable , Persistent , 128, 464.18 , 0xb312dec0 [C7x_1 ] 104.770229 s: 6 , DDR Cacheable , Scratch , 128, 5.38 , 0xb9000000 [C7x_1 ] 104.770281 s: 7 , DDR Cacheable , Persistent , 128, 1598.38 , 0xb31a2000 [C7x_1 ] 104.770331 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0xb9001800 [C7x_1 ] 104.770382 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0xb9001c00 [C7x_1 ] 104.770432 s: 10 , DDR Cacheable , Persistent , 128, 634.02 , 0xb33319c0 [C7x_1 ] 104.770484 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0xb9002c00 [C7x_1 ] 104.770536 s: 12 , DDR Cacheable , Persistent , 128, 0.13 , 0xb33d0280 [C7x_1 ] 104.770587 s: 13 , DDR Cacheable , Persistent , 128, 1379.88 , 0xb33d0340 [C7x_1 ] 104.770638 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0xb3529380 [C7x_1 ] 104.770687 s: 15 , DDR Cacheable , Persistent , 128, 0.88 , 0xb3529440 [C7x_1 ] 104.770721 s: -------------------------------------------- [C7x_1 ] 104.770756 s: Total memory size requirement (space wise): [C7x_1 ] 104.770783 s: Mem Space , Size(KBytes) [C7x_1 ] 104.770808 s: L1D , 16.00 [C7x_1 ] 104.770835 s: L2 , 224.00 [C7x_1 ] 104.770860 s: L3/MSMC , 1024.00 [C7x_1 ] 104.770886 s: DDR Cacheable, 4618.26 [C7x_1 ] 104.770915 s: -------------------------------------------- [C7x_1 ] 104.770956 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 104.771001 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 104.771030 s: debugTraceLevel = 2 [C7x_1 ] 104.771042 s: [C7x_1 ] 104.771066 s: -------------------------------------------- [C7x_1 ] 104.775284 s: Alg Init for Layer # - 3 [C7x_1 ] 104.775388 s: Alg Init for Layer # - 8 [C7x_1 ] 104.775443 s: Alg Init for Layer # - 12 [C7x_1 ] 104.775484 s: Alg Init for Layer # - 16 [C7x_1 ] 104.775576 s: Alg Init for Layer # - 17 [C7x_1 ] 104.775666 s: Alg Init for Layer # - 4 [C7x_1 ] 104.775751 s: Alg Init for Layer # - 7 [C7x_1 ] 104.775954 s: Alg Init for Layer # - 11 [C7x_1 ] 104.776037 s: Alg Init for Layer # - 15 [C7x_1 ] 104.776082 s: Alg Init for Layer # - 21 [C7x_1 ] 104.776135 s: Alg Init for Layer # - 29 [C7x_1 ] 104.776176 s: Alg Init for Layer # - 38 [C7x_1 ] 104.776262 s: Alg Init for Layer # - 44 [C7x_1 ] 104.776378 s: Alg Init for Layer # - 51 [C7x_1 ] 104.776465 s: Alg Init for Layer # - 5 [C7x_1 ] 104.776660 s: Alg Init for Layer # - 9 [C7x_1 ] 104.776750 s: Alg Init for Layer # - 13 [C7x_1 ] 104.776794 s: Alg Init for Layer # - 19 [C7x_1 ] 104.776845 s: Alg Init for Layer # - 22 [C7x_1 ] 104.776908 s: Alg Init for Layer # - 27 [C7x_1 ] 104.776996 s: Alg Init for Layer # - 23 [C7x_1 ] 104.777058 s: Alg Init for Layer # - 30 [C7x_1 ] 104.777101 s: Alg Init for Layer # - 43 [C7x_1 ] 104.777185 s: Alg Init for Layer # - 6 [C7x_1 ] 104.777376 s: Alg Init for Layer # - 10 [C7x_1 ] 104.777459 s: Alg Init for Layer # - 14 [C7x_1 ] 104.777504 s: Alg Init for Layer # - 20 [C7x_1 ] 104.777555 s: Alg Init for Layer # - 24 [C7x_1 ] 104.777617 s: Alg Init for Layer # - 31 [C7x_1 ] 104.777660 s: Alg Init for Layer # - 34 [C7x_1 ] 104.777775 s: Alg Init for Layer # - 42 [C7x_1 ] 104.777866 s: Alg Init for Layer # - 35 [C7x_1 ] 104.777968 s: Alg Init for Layer # - 41 [C7x_1 ] 104.778056 s: Alg Init for Layer # - 25 [C7x_1 ] 104.778125 s: Alg Init for Layer # - 32 [C7x_1 ] 104.778168 s: Alg Init for Layer # - 36 [C7x_1 ] 104.778268 s: Alg Init for Layer # - 40 [C7x_1 ] 104.778355 s: Alg Init for Layer # - 26 [C7x_1 ] 104.778417 s: Alg Init for Layer # - 33 [C7x_1 ] 104.778460 s: Alg Init for Layer # - 37 [C7x_1 ] 104.778556 s: Alg Init for Layer # - 39 [C7x_1 ] 104.778680 s: PREEMPTION: Adding a new priority object for targetPriority = 0, handle = b3128dc0 [C7x_1 ] 104.778752 s: PREEMPTION: Now total number of priority objects = 3 at priorityId = 0, with new memRec of base = b33d0280 and size = 128 [C7x_1 ] 104.778821 s: PREEMPTION: Requesting context memory addr for handle b3128dc0, return Addr = 9a2cfff0 [C7x_1 ] 104.778858 s: Print preEmption Hnadle during init stage : [C7x_1 ] 104.778888 s: ProcTime, ctxSize, dataId [C7x_1 ] 104.778921 s: 0.000, 7060, 0 [C7x_1 ] 104.778953 s: 0.009, 13460, 3 [C7x_1 ] 104.778984 s: 0.000, 13460, 2 [C7x_1 ] 104.779016 s: 0.010, 7060, 8 [C7x_1 ] 104.779047 s: 0.006, 7060, 12 [C7x_1 ] 104.779078 s: 0.006, 7060, 16 [C7x_1 ] 104.779109 s: 0.008, 7060, 17 [C7x_1 ] 104.779138 s: 0.000, 7060, 18 [C7x_1 ] 104.779169 s: 0.000, 7060, 1 [C7x_1 ] 104.779200 s: 0.238, 7060, 4 [C7x_1 ] 104.779231 s: 0.025, 7060, 7 [C7x_1 ] 104.779264 s: 0.030, 7060, 11 [C7x_1 ] 104.779296 s: 0.006, 418836, 15 [C7x_1 ] 104.779327 s: 0.010, 7060, 21 [C7x_1 ] 104.779358 s: 0.006, 7060, 29 [C7x_1 ] 104.779387 s: 0.008, 7060, 38 [C7x_1 ] 104.779419 s: 0.000, 7060, 45 [C7x_1 ] 104.779450 s: 0.008, 7060, 44 [C7x_1 ] 104.779482 s: 0.008, 7060, 51 [C7x_1 ] 104.779511 s: 0.000, 7060, 52 [C7x_1 ] 104.779542 s: 0.025, 7060, 5 [C7x_1 ] 104.779572 s: 0.030, 7060, 9 [C7x_1 ] 104.779602 s: 0.006, 425108, 13 [C7x_1 ] 104.779633 s: 0.010, 7060, 19 [C7x_1 ] 104.779663 s: 0.002, 7060, 22 [C7x_1 ] 104.779692 s: 0.008, 7060, 27 [C7x_1 ] 104.779722 s: 0.000, 7060, 28 [C7x_1 ] 104.779758 s: 0.002, 7060, 23 [C7x_1 ] 104.779789 s: 0.006, 7060, 30 [C7x_1 ] 104.779821 s: 0.008, 7060, 43 [C7x_1 ] 104.779854 s: 0.000, 7060, 50 [C7x_1 ] 104.779884 s: 0.025, 7060, 6 [C7x_1 ] 104.779914 s: 0.030, 7060, 10 [C7x_1 ] 104.779943 s: 0.006, 25876, 14 [C7x_1 ] 104.779974 s: 0.010, 234644, 20 [C7x_1 ] 104.780005 s: 0.002, 234644, 24 [C7x_1 ] 104.780036 s: 0.006, 234644, 31 [C7x_1 ] 104.780065 s: 0.006, 234644, 34 [C7x_1 ] 104.780095 s: 0.008, 234644, 42 [C7x_1 ] 104.780124 s: 0.000, 234644, 49 [C7x_1 ] 104.780154 s: 0.006, 234772, 35 [C7x_1 ] 104.780184 s: 0.008, 234644, 41 [C7x_1 ] 104.780216 s: 0.000, 234644, 48 [C7x_1 ] 104.780245 s: 0.002, 234644, 25 [C7x_1 ] 104.780275 s: 0.006, 234644, 32 [C7x_1 ] 104.780306 s: 0.006, 234772, 36 [C7x_1 ] 104.780338 s: 0.008, 234644, 40 [C7x_1 ] 104.780370 s: 0.000, 234644, 47 [C7x_1 ] 104.780400 s: 0.002, 7060, 26 [C7x_1 ] 104.780429 s: 0.006, 7060, 33 [C7x_1 ] 104.780460 s: 0.006, 7188, 37 [C7x_1 ] 104.780490 s: 0.008, 7060, 39 [C7x_1 ] 104.780523 s: 0.000, 0, 46 [C7x_1 ] 104.780597 s: TIDL_initializeHandleForPreemption is completed RT-Profile: TIDLRT_init_profiling tidlrt_create : 24716679 ns, tidl_rt_ovx_Init : 14315 ns, vxCreateContext : 10605 ns, init_tidl_tiovx : 3134066 ns, create_graph_tidl_tiovx : 1690917 ns, verify_graph_tidl_tiovx : 19594891 ns, tivxTIDLLoadKernels : 1265 ns, mapConfig : 520284 ns, tivxAddKernelTIDL : 109955 ns, mapNetwork : 1806602 ns, setCreateParams : 281205 ns, setArgs : 412190 ns, vxCreateUserDataObject : 43545 ns, vxMapUserDataObject : 833909 ns, memcopy_network_buffer : 821979 ns, vxUnmapUserDataObject : 105004 ns, ************ TIDL_subgraphRtCreate done ************ In TIDL_createStateInfer Compute on node : TIDLExecutionProvider_TIDL_3_3 ************ in TIDL_subgraphRtCreate ************ [C7x_1 ] 104.809730 s: PREEMPTION: Requesting memory of size 128 for targetPriority = 0 [C7x_1 ] 104.809776 s: [C7x_1 ] 104.809798 s: -------------------------------------------- [C7x_1 ] 104.809828 s: TIDL Memory size requiement (record wise): [C7x_1 ] 104.809877 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 104.809932 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0x00000000 [C7x_1 ] 104.809986 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0x00000000 [C7x_1 ] 104.810037 s: 2 , L1D , Scratch , 128, 16.00 , 0x00000000 [C7x_1 ] 104.810089 s: 3 , L2 , Scratch , 128, 224.00 , 0x00000000 [C7x_1 ] 104.810140 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x00000000 [C7x_1 ] 104.810191 s: 5 , DDR Cacheable , Persistent , 128, 355.78 , 0x00000000 [C7x_1 ] 104.810242 s: 6 , DDR Cacheable , Scratch , 128, 2.00 , 0x00000000 [C7x_1 ] 104.810294 s: 7 , DDR Cacheable , Persistent , 128, 7.75 , 0x00000000 [C7x_1 ] 104.810344 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0x00000000 [C7x_1 ] 104.810395 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0x00000000 [C7x_1 ] 104.810446 s: 10 , DDR Cacheable , Persistent , 128, 378.58 , 0x00000000 [C7x_1 ] 104.810497 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0x00000000 [C7x_1 ] 104.810547 s: 12 , DDR Cacheable , Persistent , 128, 0.13 , 0x00000000 [C7x_1 ] 104.810598 s: 13 , DDR Cacheable , Persistent , 128, 1290.74 , 0x00000000 [C7x_1 ] 104.810647 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0x00000000 [C7x_1 ] 104.810698 s: 15 , DDR Cacheable , Persistent , 128, 0.25 , 0x00000000 [C7x_1 ] 104.810733 s: -------------------------------------------- [C7x_1 ] 104.810772 s: Total memory size requirement (space wise): [C7x_1 ] 104.810799 s: Mem Space , Size(KBytes) [C7x_1 ] 104.810825 s: L1D , 16.00 [C7x_1 ] 104.810853 s: L2 , 224.00 [C7x_1 ] 104.810878 s: L3/MSMC , 1024.00 [C7x_1 ] 104.810904 s: DDR Cacheable, 2570.64 [C7x_1 ] 104.810935 s: -------------------------------------------- [C7x_1 ] 104.810977 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 104.811022 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 104.811051 s: debugTraceLevel = 2 [C7x_1 ] 104.811065 s: [C7x_1 ] 104.811090 s: -------------------------------------------- [C7x_1 ] 104.811263 s: TIDL init call from ivision API [C7x_1 ] 104.811283 s: [C7x_1 ] 104.811305 s: -------------------------------------------- [C7x_1 ] 104.811336 s: TIDL Memory size requiement (record wise): [C7x_1 ] 104.811382 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 104.811435 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0xb35502c0 [C7x_1 ] 104.811489 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0xb3555080 [C7x_1 ] 104.811539 s: 2 , L1D , Scratch , 128, 16.00 , 0x7f03c000 [C7x_1 ] 104.811589 s: 3 , L2 , Scratch , 128, 224.00 , 0x7f000000 [C7x_1 ] 104.811638 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x7e000000 [C7x_1 ] 104.811687 s: 5 , DDR Cacheable , Persistent , 128, 355.78 , 0xb35553c0 [C7x_1 ] 104.811738 s: 6 , DDR Cacheable , Scratch , 128, 2.00 , 0xb9000000 [C7x_1 ] 104.811797 s: 7 , DDR Cacheable , Persistent , 128, 7.75 , 0xb35ae380 [C7x_1 ] 104.811848 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0xb9000800 [C7x_1 ] 104.811897 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0xb9000c00 [C7x_1 ] 104.811947 s: 10 , DDR Cacheable , Persistent , 128, 378.58 , 0xb35b02c0 [C7x_1 ] 104.811997 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0xb9001c00 [C7x_1 ] 104.812046 s: 12 , DDR Cacheable , Persistent , 128, 0.13 , 0xb360ed80 [C7x_1 ] 104.812097 s: 13 , DDR Cacheable , Persistent , 128, 1290.74 , 0xb360ee40 [C7x_1 ] 104.812147 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0xb3751980 [C7x_1 ] 104.812196 s: 15 , DDR Cacheable , Persistent , 128, 0.25 , 0xb3751a40 [C7x_1 ] 104.812230 s: -------------------------------------------- [C7x_1 ] 104.812260 s: Total memory size requirement (space wise): [C7x_1 ] 104.812284 s: Mem Space , Size(KBytes) [C7x_1 ] 104.812307 s: L1D , 16.00 [C7x_1 ] 104.812334 s: L2 , 224.00 [C7x_1 ] 104.812359 s: L3/MSMC , 1024.00 [C7x_1 ] 104.812384 s: DDR Cacheable, 2570.64 [C7x_1 ] 104.812413 s: -------------------------------------------- [C7x_1 ] 104.812455 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 104.812499 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 104.812528 s: debugTraceLevel = 2 [C7x_1 ] 104.812540 s: [C7x_1 ] 104.812565 s: -------------------------------------------- [C7x_1 ] 104.816667 s: Alg Init for Layer # - 5 [C7x_1 ] 104.816765 s: Alg Init for Layer # - 6 [C7x_1 ] 104.816836 s: Alg Init for Layer # - 10 [C7x_1 ] 104.816928 s: Alg Init for Layer # - 11 [C7x_1 ] 104.817016 s: Alg Init for Layer # - 7 [C7x_1 ] 104.817086 s: Alg Init for Layer # - 12 [C7x_1 ] 104.817173 s: Alg Init for Layer # - 13 [C7x_1 ] 104.817257 s: Alg Init for Layer # - 8 [C7x_1 ] 104.817330 s: Alg Init for Layer # - 14 [C7x_1 ] 104.817418 s: Alg Init for Layer # - 15 [C7x_1 ] 104.817498 s: Alg Init for Layer # - 16 [C7x_1 ] 104.817579 s: Alg Init for Layer # - 9 [C7x_1 ] 104.817646 s: Alg Init for Layer # - 18 [C7x_1 ] 104.817684 s: Alg Init for Layer # - 19 [C7x_1 ] 104.817798 s: PREEMPTION: Adding a new priority object for targetPriority = 0, handle = b35502c0 [C7x_1 ] 104.817863 s: PREEMPTION: Now total number of priority objects = 4 at priorityId = 0, with new memRec of base = b360ed80 and size = 128 [C7x_1 ] 104.817930 s: PREEMPTION: Requesting context memory addr for handle b35502c0, return Addr = 9a2cfff0 [C7x_1 ] 104.817968 s: Print preEmption Hnadle during init stage : [C7x_1 ] 104.817997 s: ProcTime, ctxSize, dataId [C7x_1 ] 104.818031 s: 0.000, 6676, 0 [C7x_1 ] 104.818062 s: 0.006, 6804, 5 [C7x_1 ] 104.818092 s: 0.000, 6804, 1 [C7x_1 ] 104.818123 s: 0.006, 6932, 6 [C7x_1 ] 104.818155 s: 0.008, 6804, 10 [C7x_1 ] 104.818185 s: 0.006, 6804, 11 [C7x_1 ] 104.818214 s: 0.000, 6804, 2 [C7x_1 ] 104.818245 s: 0.006, 6932, 7 [C7x_1 ] 104.818275 s: 0.008, 6804, 12 [C7x_1 ] 104.818306 s: 0.006, 6804, 13 [C7x_1 ] 104.818337 s: 0.000, 6804, 3 [C7x_1 ] 104.818367 s: 0.006, 6932, 8 [C7x_1 ] 104.818396 s: 0.008, 6804, 14 [C7x_1 ] 104.818426 s: 0.006, 6804, 15 [C7x_1 ] 104.818456 s: 0.008, 6676, 16 [C7x_1 ] 104.818487 s: 0.000, 6676, 17 [C7x_1 ] 104.818516 s: 0.000, 6676, 4 [C7x_1 ] 104.818546 s: 0.006, 6804, 9 [C7x_1 ] 104.818577 s: 0.006, 6804, 18 [C7x_1 ] 104.818607 s: 0.008, 6676, 19 [C7x_1 ] 104.818639 s: 0.000, 0, 20 [C7x_1 ] 104.818686 s: TIDL_initializeHandleForPreemption is completed RT-Profile: TIDLRT_init_profiling tidlrt_create : 18743501 ns, tidl_rt_ovx_Init : 11840 ns, vxCreateContext : 13355 ns, init_tidl_tiovx : 2989071 ns, create_graph_tidl_tiovx : 760914 ns, verify_graph_tidl_tiovx : 14701541 ns, tivxTIDLLoadKernels : 1100 ns, mapConfig : 486284 ns, tivxAddKernelTIDL : 125110 ns, mapNetwork : 1709408 ns, setCreateParams : 312799 ns, setArgs : 351870 ns, vxCreateUserDataObject : 37910 ns, vxMapUserDataObject : 804874 ns, memcopy_network_buffer : 770009 ns, vxUnmapUserDataObject : 94625 ns, ************ TIDL_subgraphRtCreate done ************ In TIDL_createStateInfer Compute on node : TIDLExecutionProvider_TIDL_4_4 ************ in TIDL_subgraphRtCreate ************ [C7x_1 ] 104.847309 s: PREEMPTION: Requesting memory of size 128 for targetPriority = 0 [C7x_1 ] 104.847340 s: [C7x_1 ] 104.847362 s: -------------------------------------------- [C7x_1 ] 104.847393 s: TIDL Memory size requiement (record wise): [C7x_1 ] 104.847440 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 104.847496 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0x00000000 [C7x_1 ] 104.847548 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0x00000000 [C7x_1 ] 104.847599 s: 2 , L1D , Scratch , 128, 16.00 , 0x00000000 [C7x_1 ] 104.847649 s: 3 , L2 , Scratch , 128, 224.00 , 0x00000000 [C7x_1 ] 104.847701 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x00000000 [C7x_1 ] 104.847764 s: 5 , DDR Cacheable , Persistent , 128, 340.40 , 0x00000000 [C7x_1 ] 104.847817 s: 6 , DDR Cacheable , Scratch , 128, 1.63 , 0x00000000 [C7x_1 ] 104.847868 s: 7 , DDR Cacheable , Persistent , 128, 6.50 , 0x00000000 [C7x_1 ] 104.847917 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0x00000000 [C7x_1 ] 104.847968 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0x00000000 [C7x_1 ] 104.848019 s: 10 , DDR Cacheable , Persistent , 128, 350.20 , 0x00000000 [C7x_1 ] 104.848070 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0x00000000 [C7x_1 ] 104.848121 s: 12 , DDR Cacheable , Persistent , 128, 0.13 , 0x00000000 [C7x_1 ] 104.848170 s: 13 , DDR Cacheable , Persistent , 128, 1280.37 , 0x00000000 [C7x_1 ] 104.848220 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0x00000000 [C7x_1 ] 104.848270 s: 15 , DDR Cacheable , Persistent , 128, 0.25 , 0x00000000 [C7x_1 ] 104.848305 s: -------------------------------------------- [C7x_1 ] 104.848335 s: Total memory size requirement (space wise): [C7x_1 ] 104.848360 s: Mem Space , Size(KBytes) [C7x_1 ] 104.848385 s: L1D , 16.00 [C7x_1 ] 104.848412 s: L2 , 224.00 [C7x_1 ] 104.848436 s: L3/MSMC , 1024.00 [C7x_1 ] 104.848462 s: DDR Cacheable, 2514.89 [C7x_1 ] 104.848492 s: -------------------------------------------- [C7x_1 ] 104.848533 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 104.848577 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 104.848605 s: debugTraceLevel = 2 [C7x_1 ] 104.848618 s: [C7x_1 ] 104.848642 s: -------------------------------------------- [C7x_1 ] 104.848813 s: TIDL init call from ivision API [C7x_1 ] 104.848834 s: [C7x_1 ] 104.848857 s: -------------------------------------------- [C7x_1 ] 104.848887 s: TIDL Memory size requiement (record wise): [C7x_1 ] 104.848931 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 104.848985 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0xb3778640 [C7x_1 ] 104.849036 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0xb377d400 [C7x_1 ] 104.849090 s: 2 , L1D , Scratch , 128, 16.00 , 0x7f03c000 [C7x_1 ] 104.849141 s: 3 , L2 , Scratch , 128, 224.00 , 0x7f000000 [C7x_1 ] 104.849191 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x7e000000 [C7x_1 ] 104.849244 s: 5 , DDR Cacheable , Persistent , 128, 340.40 , 0xb377d740 [C7x_1 ] 104.849294 s: 6 , DDR Cacheable , Scratch , 128, 1.63 , 0xb9000000 [C7x_1 ] 104.849344 s: 7 , DDR Cacheable , Persistent , 128, 6.50 , 0xb37d2980 [C7x_1 ] 104.849396 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0xb9000800 [C7x_1 ] 104.849447 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0xb9000c00 [C7x_1 ] 104.849497 s: 10 , DDR Cacheable , Persistent , 128, 350.20 , 0xb37d43c0 [C7x_1 ] 104.849547 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0xb9001c00 [C7x_1 ] 104.849598 s: 12 , DDR Cacheable , Persistent , 128, 0.13 , 0xb382bd00 [C7x_1 ] 104.849649 s: 13 , DDR Cacheable , Persistent , 128, 1280.37 , 0xb382bdc0 [C7x_1 ] 104.849699 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0xb396bf80 [C7x_1 ] 104.849754 s: 15 , DDR Cacheable , Persistent , 128, 0.25 , 0xb396c040 [C7x_1 ] 104.849792 s: -------------------------------------------- [C7x_1 ] 104.849823 s: Total memory size requirement (space wise): [C7x_1 ] 104.849849 s: Mem Space , Size(KBytes) [C7x_1 ] 104.849873 s: L1D , 16.00 [C7x_1 ] 104.849899 s: L2 , 224.00 [C7x_1 ] 104.849924 s: L3/MSMC , 1024.00 [C7x_1 ] 104.849949 s: DDR Cacheable, 2514.89 [C7x_1 ] 104.849976 s: -------------------------------------------- [C7x_1 ] 104.850017 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 104.850061 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 104.850089 s: debugTraceLevel = 2 [C7x_1 ] 104.850102 s: [C7x_1 ] 104.850127 s: -------------------------------------------- [C7x_1 ] 104.854238 s: Alg Init for Layer # - 4 [C7x_1 ] 104.854328 s: Alg Init for Layer # - 5 [C7x_1 ] 104.854398 s: Alg Init for Layer # - 9 [C7x_1 ] 104.854491 s: Alg Init for Layer # - 10 [C7x_1 ] 104.854579 s: Alg Init for Layer # - 6 [C7x_1 ] 104.854647 s: Alg Init for Layer # - 11 [C7x_1 ] 104.854734 s: Alg Init for Layer # - 12 [C7x_1 ] 104.854826 s: Alg Init for Layer # - 13 [C7x_1 ] 104.854909 s: Alg Init for Layer # - 7 [C7x_1 ] 104.854982 s: Alg Init for Layer # - 8 [C7x_1 ] 104.855065 s: Alg Init for Layer # - 14 [C7x_1 ] 104.855173 s: PREEMPTION: Adding a new priority object for targetPriority = 0, handle = b3778640 [C7x_1 ] 104.855238 s: PREEMPTION: Now total number of priority objects = 5 at priorityId = 0, with new memRec of base = b382bd00 and size = 128 RT-Profile: TIDLRT_init_profiling tidlrt_create : 18181182 ns, tidl_rt_ovx_Init : 12765 ns, vxCreateContext : 5245 ns, init_tidl_tiovx : 3062051 ns, create_graph_tidl_tiovx : 575325 ns, verify_graph_tidl_tiovx : 14261842 ns, tivxTIDLLoadKernels : 925 ns, mapConfig : 510864 ns, tivxAddKernelTIDL : 115780 ns, mapNetwork : 1788938 ns, setCreateParams : 310625 ns, setArgs : 332449 ns, vxCreateUserDataObject : 36770 ns, vxMapUserDataObject : 887894 ns, memcopy_network_buffer : 763429 ns, vxUnmapUserDataObject : 97605 ns, ************ TIDL_subgraphRtCreate done ************ In TIDL_createStateInfer Compute on node : TIDLExecutionProvider_TIDL_5_5 ************ in TIDL_subgraphRtCreate ************ [C7x_1 ] 104.855308 s: PREEMPTION: Requesting context memory addr for handle b3778640, return Addr = 9a2cfff0 [C7x_1 ] 104.855345 s: Print preEmption Hnadle during init stage : [C7x_1 ] 104.855376 s: ProcTime, ctxSize, dataId [C7x_1 ] 104.855409 s: 0.000, 6628, 0 [C7x_1 ] 104.855442 s: 0.006, 6756, 4 [C7x_1 ] 104.855472 s: 0.000, 6756, 1 [C7x_1 ] 104.855502 s: 0.006, 6884, 5 [C7x_1 ] 104.855533 s: 0.008, 6756, 9 [C7x_1 ] 104.855562 s: 0.006, 6756, 10 [C7x_1 ] 104.855593 s: 0.000, 6756, 2 [C7x_1 ] 104.855623 s: 0.006, 6884, 6 [C7x_1 ] 104.855651 s: 0.008, 6756, 11 [C7x_1 ] 104.855682 s: 0.006, 6756, 12 [C7x_1 ] 104.855712 s: 0.008, 6628, 13 [C7x_1 ] 104.855749 s: 0.000, 6628, 15 [C7x_1 ] 104.855783 s: 0.000, 6628, 3 [C7x_1 ] 104.855817 s: 0.006, 6756, 7 [C7x_1 ] 104.855849 s: 0.006, 6756, 8 [C7x_1 ] 104.855879 s: 0.008, 6628, 14 [C7x_1 ] 104.855910 s: 0.000, 0, 16 [C7x_1 ] 104.855956 s: TIDL_initializeHandleForPreemption is completed [C7x_1 ] 104.890665 s: PREEMPTION: Requesting memory of size 128 for targetPriority = 0 [C7x_1 ] 104.890693 s: [C7x_1 ] 104.890718 s: -------------------------------------------- [C7x_1 ] 104.890755 s: TIDL Memory size requiement (record wise): [C7x_1 ] 104.890807 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 104.890866 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0x00000000 [C7x_1 ] 104.890920 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0x00000000 [C7x_1 ] 104.890970 s: 2 , L1D , Scratch , 128, 16.00 , 0x00000000 [C7x_1 ] 104.891022 s: 3 , L2 , Scratch , 128, 224.00 , 0x00000000 [C7x_1 ] 104.891073 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x00000000 [C7x_1 ] 104.891125 s: 5 , DDR Cacheable , Persistent , 128, 483.76 , 0x00000000 [C7x_1 ] 104.891176 s: 6 , DDR Cacheable , Scratch , 128, 4.25 , 0x00000000 [C7x_1 ] 104.891227 s: 7 , DDR Cacheable , Persistent , 128, 4738.75 , 0x00000000 [C7x_1 ] 104.891278 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0x00000000 [C7x_1 ] 104.891327 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0x00000000 [C7x_1 ] 104.891377 s: 10 , DDR Cacheable , Persistent , 128, 548.88 , 0x00000000 [C7x_1 ] 104.891427 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0x00000000 [C7x_1 ] 104.891477 s: 12 , DDR Cacheable , Persistent , 128, 0.13 , 0x00000000 [C7x_1 ] 104.891525 s: 13 , DDR Cacheable , Persistent , 128, 1354.52 , 0x00000000 [C7x_1 ] 104.891575 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0x00000000 [C7x_1 ] 104.891627 s: 15 , DDR Cacheable , Persistent , 128, 174.75 , 0x00000000 [C7x_1 ] 104.891662 s: -------------------------------------------- [C7x_1 ] 104.891692 s: Total memory size requirement (space wise): [C7x_1 ] 104.891717 s: Mem Space , Size(KBytes) [C7x_1 ] 104.891745 s: L1D , 16.00 [C7x_1 ] 104.891781 s: L2 , 224.00 [C7x_1 ] 104.891806 s: L3/MSMC , 1024.00 [C7x_1 ] 104.891833 s: DDR Cacheable, 7840.46 [C7x_1 ] 104.891863 s: -------------------------------------------- [C7x_1 ] 104.891904 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 104.891949 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 104.891977 s: debugTraceLevel = 2 [C7x_1 ] 104.891989 s: [C7x_1 ] 104.892014 s: -------------------------------------------- [C7x_1 ] 104.892486 s: TIDL init call from ivision API [C7x_1 ] 104.892506 s: [C7x_1 ] 104.892528 s: -------------------------------------------- [C7x_1 ] 104.892557 s: TIDL Memory size requiement (record wise): [C7x_1 ] 104.892603 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 104.892656 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0xb3992c40 [C7x_1 ] 104.892709 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0xb3997a00 [C7x_1 ] 104.892765 s: 2 , L1D , Scratch , 128, 16.00 , 0x7f03c000 [C7x_1 ] 104.892819 s: 3 , L2 , Scratch , 128, 224.00 , 0x7f000000 [C7x_1 ] 104.892870 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x7e000000 [C7x_1 ] 104.892922 s: 5 , DDR Cacheable , Persistent , 128, 483.76 , 0xb3997d40 [C7x_1 ] 104.892972 s: 6 , DDR Cacheable , Scratch , 128, 4.25 , 0xb9000000 [C7x_1 ] 104.893025 s: 7 , DDR Cacheable , Persistent , 128, 4738.75 , 0xb3a10d00 [C7x_1 ] 104.893074 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0xb9001400 [C7x_1 ] 104.893124 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0xb9001800 [C7x_1 ] 104.893175 s: 10 , DDR Cacheable , Persistent , 128, 548.88 , 0xb3eb1840 [C7x_1 ] 104.893225 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0xb9002800 [C7x_1 ] 104.893276 s: 12 , DDR Cacheable , Persistent , 128, 0.13 , 0xb3f3ac00 [C7x_1 ] 104.893325 s: 13 , DDR Cacheable , Persistent , 128, 1354.52 , 0xb3f3acc0 [C7x_1 ] 104.893375 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0xb408d780 [C7x_1 ] 104.893426 s: 15 , DDR Cacheable , Persistent , 128, 174.75 , 0xb408d840 [C7x_1 ] 104.893461 s: -------------------------------------------- [C7x_1 ] 104.893492 s: Total memory size requirement (space wise): [C7x_1 ] 104.893520 s: Mem Space , Size(KBytes) [C7x_1 ] 104.893543 s: L1D , 16.00 [C7x_1 ] 104.893568 s: L2 , 224.00 [C7x_1 ] 104.893596 s: L3/MSMC , 1024.00 [C7x_1 ] 104.893622 s: DDR Cacheable, 7840.46 [C7x_1 ] 104.893651 s: -------------------------------------------- [C7x_1 ] 104.893692 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 104.893735 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 104.893770 s: debugTraceLevel = 2 [C7x_1 ] 104.893785 s: [C7x_1 ] 104.893809 s: -------------------------------------------- [C7x_1 ] 104.897974 s: Alg Init for Layer # - 4 [C7x_1 ] 104.898074 s: Alg Init for Layer # - 16 [C7x_1 ] 104.898169 s: Alg Init for Layer # - 17 [C7x_1 ] 104.898255 s: Alg Init for Layer # - 5 [C7x_1 ] 104.898330 s: Alg Init for Layer # - 11 [C7x_1 ] 104.898582 s: Alg Init for Layer # - 12 [C7x_1 ] 104.898689 s: Alg Init for Layer # - 6 [C7x_1 ] 104.898774 s: Alg Init for Layer # - 9 [C7x_1 ] 104.898988 s: Alg Init for Layer # - 10 [C7x_1 ] 104.899078 s: Alg Init for Layer # - 7 [C7x_1 ] 104.899156 s: Alg Init for Layer # - 8 [C7x_1 ] 104.899381 s: Alg Init for Layer # - 13 [C7x_1 ] 104.899523 s: Alg Init for Layer # - 14 [C7x_1 ] 104.900215 s: Alg Init for Layer # - 15 [C7x_1 ] 104.900556 s: Alg Init for Layer # - 18 [C7x_1 ] 104.900658 s: Alg Init for Layer # - 19 [C7x_1 ] 104.900857 s: Alg Init for Layer # - 20 [C7x_1 ] 104.900955 s: Alg Init for Layer # - 21 [C7x_1 ] 104.901043 s: Alg Init for Layer # - 22 [C7x_1 ] 104.901134 s: Alg Init for Layer # - 23 [C7x_1 ] 104.901238 s: Alg Init for Layer # - 24 [C7x_1 ] 104.901442 s: Alg Init for Layer # - 29 [C7x_1 ] 104.901486 s: Alg Init for Layer # - 31 [C7x_1 ] 104.901577 s: Alg Init for Layer # - 32 [C7x_1 ] 104.901668 s: Alg Init for Layer # - 35 [C7x_1 ] 104.901712 s: Alg Init for Layer # - 36 [C7x_1 ] 104.901816 s: Alg Init for Layer # - 37 [C7x_1 ] 104.901862 s: Alg Init for Layer # - 38 [C7x_1 ] 104.901952 s: Alg Init for Layer # - 25 [C7x_1 ] 104.902166 s: Alg Init for Layer # - 28 [C7x_1 ] 104.902248 s: Alg Init for Layer # - 30 [C7x_1 ] 104.902293 s: Alg Init for Layer # - 33 [C7x_1 ] 104.902416 s: PREEMPTION: Adding a new priority object for targetPriority = 0, handle = b3992c40 [C7x_1 ] 104.902483 s: PREEMPTION: Now total number of priority objects = 6 at priorityId = 0, with new memRec of base = b3f3ac00 and size = 128 [C7x_1 ] 104.902551 s: PREEMPTION: Requesting context memory addr for handle b3992c40, return Addr = 9a2cfff0 [C7x_1 ] 104.902590 s: Print preEmption Hnadle during init stage : [C7x_1 ] 104.902623 s: ProcTime, ctxSize, dataId [C7x_1 ] 104.902658 s: 0.000, 6904, 0 [C7x_1 ] 104.902692 s: 0.006, 7032, 4 [C7x_1 ] 104.902723 s: 0.006, 7032, 16 [C7x_1 ] 104.902762 s: 0.008, 6904, 17 [C7x_1 ] 104.902792 s: 0.000, 6904, 26 [C7x_1 ] 104.902824 s: 0.000, 6904, 1 [C7x_1 ] 104.902856 s: 0.071, 121592, 5 [C7x_1 ] 104.902888 s: 0.021, 35576, 11 [C7x_1 ] 104.902921 s: 0.070, 6904, 12 [C7x_1 ] 104.902951 s: 0.000, 6904, 2 [C7x_1 ] 104.902982 s: 0.123, 228088, 6 [C7x_1 ] 104.903011 s: 0.026, 117496, 9 [C7x_1 ] 104.903041 s: 0.026, 428792, 10 [C7x_1 ] 104.903072 s: 0.000, 428792, 3 [C7x_1 ] 104.903104 s: 0.238, 834296, 7 [C7x_1 ] 104.903134 s: 0.042, 834296, 8 [C7x_1 ] 104.903163 s: 0.283, 6904, 13 [C7x_1 ] 104.903194 s: 0.782, 412408, 14 [C7x_1 ] 104.903224 s: 0.259, 412408, 15 [C7x_1 ] 104.903254 s: 0.252, 412408, 18 [C7x_1 ] 104.903285 s: 0.000, 412408, 27 RT-Profile: TIDLRT_init_profiling [C7x_1 ] 104.903316 s: 0.025, 437752, 19 tidlrt_create : 26277452 ns, [C7x_1 ] 104.903345 s: 0.009, 437752, 20 tidl_rt_ovx_Init : 11700 ns, vxCreateContext : 4780 ns, [C7x_1 ] 104.903376 s: 0.007, 463096, 21 init_tidl_tiovx : 3378530 ns, create_graph_tidl_tiovx : 2413207 ns, [C7x_1 ] 104.903406 s: 0.009, 488440, 22 verify_graph_tidl_tiovx : 20184535 ns, tivxTIDLLoadKernels : 915 ns, [C7x_1 ] 104.903438 s: 0.009, 463096, 23 mapConfig : 495914 ns, tivxAddKernelTIDL : 106745 ns, [C7x_1 ] 104.903468 s: 0.009, 462840, 24 mapNetwork : 2104502 ns, setCreateParams : 333515 ns, [C7x_1 ] 104.903498 s: 0.006, 462840, 29 setArgs : 334069 ns, vxCreateUserDataObject : 44025 ns, [C7x_1 ] 104.903528 s: 0.008, 462968, 31 vxMapUserDataObject : 1032739 ns, memcopy_network_buffer : 911748 ns, [C7x_1 ] 104.903557 s: 0.008, 462840, 32 vxUnmapUserDataObject : 112705 ns, [C7x_1 ] 104.903588 s: 0.006, 462840, 35 ************ TIDL_subgraphRtCreate done ************ [C7x_1 ] 104.903618 s: 0.009, 437496, 36 [C7x_1 ] 104.903647 s: 0.006, 437496, 37 [C7x_1 ] 104.903677 s: 0.023, 412408, 38 In TIDL_createStateInfer Compute on node : TIDLExecutionProvider_TIDL_6_6 [C7x_1 ] 104.903709 s: 0.000, 412408, 39 [C7x_1 ] 104.903739 s: 0.027, 6904, 25 [C7x_1 ] 104.903778 s: 0.032, 19448, 28 [C7x_1 ] 104.903811 s: 0.006, 19448, 30 [C7x_1 ] 104.903841 s: 0.015, 6904, 33 [C7x_1 ] 104.903871 s: 0.000, 0, 34 [C7x_1 ] 104.903931 s: TIDL_initializeHandleForPreemption is completed ************ in TIDL_subgraphRtCreate ************ [C7x_1 ] 104.931932 s: PREEMPTION: Requesting memory of size 128 for targetPriority = 0 [C7x_1 ] 104.931960 s: [C7x_1 ] 104.931982 s: -------------------------------------------- [C7x_1 ] 104.932012 s: TIDL Memory size requiement (record wise): [C7x_1 ] 104.932061 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 104.932117 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0x00000000 [C7x_1 ] 104.932169 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0x00000000 [C7x_1 ] 104.932220 s: 2 , L1D , Scratch , 128, 16.00 , 0x00000000 [C7x_1 ] 104.932272 s: 3 , L2 , Scratch , 128, 224.00 , 0x00000000 [C7x_1 ] 104.932324 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x00000000 [C7x_1 ] 104.932376 s: 5 , DDR Cacheable , Persistent , 128, 291.40 , 0x00000000 [C7x_1 ] 104.932427 s: 6 , DDR Cacheable , Scratch , 128, 0.88 , 0x00000000 [C7x_1 ] 104.932476 s: 7 , DDR Cacheable , Persistent , 128, 2.75 , 0x00000000 [C7x_1 ] 104.932528 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0x00000000 [C7x_1 ] 104.932577 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0x00000000 [C7x_1 ] 104.932626 s: 10 , DDR Cacheable , Persistent , 128, 293.43 , 0x00000000 [C7x_1 ] 104.932678 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0x00000000 [C7x_1 ] 104.932728 s: 12 , DDR Cacheable , Persistent , 128, 0.13 , 0x00000000 [C7x_1 ] 104.932791 s: 13 , DDR Cacheable , Persistent , 128, 1254.90 , 0x00000000 [C7x_1 ] 104.932844 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0x00000000 [C7x_1 ] 104.932896 s: 15 , DDR Cacheable , Persistent , 128, 0.25 , 0x00000000 [C7x_1 ] 104.932930 s: -------------------------------------------- [C7x_1 ] 104.932962 s: Total memory size requirement (space wise): [C7x_1 ] 104.932988 s: Mem Space , Size(KBytes) [C7x_1 ] 104.933012 s: L1D , 16.00 [C7x_1 ] 104.933038 s: L2 , 224.00 [C7x_1 ] 104.933063 s: L3/MSMC , 1024.00 [C7x_1 ] 104.933088 s: DDR Cacheable, 2379.16 [C7x_1 ] 104.933117 s: -------------------------------------------- [C7x_1 ] 104.933159 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 104.933203 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 104.933231 s: debugTraceLevel = 2 [C7x_1 ] 104.933243 s: [C7x_1 ] 104.933266 s: -------------------------------------------- [C7x_1 ] 104.933425 s: TIDL init call from ivision API [C7x_1 ] 104.933445 s: [C7x_1 ] 104.933466 s: -------------------------------------------- [C7x_1 ] 104.933494 s: TIDL Memory size requiement (record wise): [C7x_1 ] 104.933542 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 104.933596 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0xb40dfe40 [C7x_1 ] 104.933647 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0xb40e4c00 [C7x_1 ] 104.933696 s: 2 , L1D , Scratch , 128, 16.00 , 0x7f03c000 [C7x_1 ] 104.933747 s: 3 , L2 , Scratch , 128, 224.00 , 0x7f000000 [C7x_1 ] 104.933811 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x7e000000 [C7x_1 ] 104.933863 s: 5 , DDR Cacheable , Persistent , 128, 291.40 , 0xb40e4f40 [C7x_1 ] 104.933916 s: 6 , DDR Cacheable , Scratch , 128, 0.88 , 0xb9000000 [C7x_1 ] 104.933967 s: 7 , DDR Cacheable , Persistent , 128, 2.75 , 0xb412dd80 [C7x_1 ] 104.934017 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0xb9000400 [C7x_1 ] 104.934067 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0xb9000800 [C7x_1 ] 104.934118 s: 10 , DDR Cacheable , Persistent , 128, 293.43 , 0xb412e8c0 [C7x_1 ] 104.934168 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0xb9001800 [C7x_1 ] 104.934217 s: 12 , DDR Cacheable , Persistent , 128, 0.13 , 0xb4177f00 [C7x_1 ] 104.934270 s: 13 , DDR Cacheable , Persistent , 128, 1254.90 , 0xb4177fc0 [C7x_1 ] 104.934319 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0xb42b1c00 [C7x_1 ] 104.934370 s: 15 , DDR Cacheable , Persistent , 128, 0.25 , 0xb42b1cc0 [C7x_1 ] 104.934405 s: -------------------------------------------- [C7x_1 ] 104.934435 s: Total memory size requirement (space wise): [C7x_1 ] 104.934460 s: Mem Space , Size(KBytes) [C7x_1 ] 104.934483 s: L1D , 16.00 [C7x_1 ] 104.934510 s: L2 , 224.00 [C7x_1 ] 104.934536 s: L3/MSMC , 1024.00 [C7x_1 ] 104.934561 s: DDR Cacheable, 2379.16 [C7x_1 ] 104.934590 s: -------------------------------------------- [C7x_1 ] 104.934630 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 104.934675 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 104.934703 s: debugTraceLevel = 2 [C7x_1 ] 104.934715 s: [C7x_1 ] 104.934739 s: -------------------------------------------- [C7x_1 ] 104.938797 s: Alg Init for Layer # - 1 [C7x_1 ] 104.938878 s: Alg Init for Layer # - 2 [C7x_1 ] 104.938961 s: Alg Init for Layer # - 3 [C7x_1 ] 104.939153 s: Alg Init for Layer # - 4 [C7x_1 ] 104.939229 s: Alg Init for Layer # - 5 [C7x_1 ] 104.939331 s: PREEMPTION: Adding a new priority object for targetPriority = 0, handle = b40dfe40 [C7x_1 ] 104.939397 s: PREEMPTION: Now total number of priority objects = 7 at priorityId = 0, with new memRec of base = b4177f00 and size = 128 [C7x_1 ] 104.939465 s: PREEMPTION: Requesting context memory addr for handle b40dfe40, return Addr = 9a2cfff0 [C7x_1 ] 104.939502 s: Print preEmption Hnadle during init stage : [C7x_1 ] 104.939532 s: ProcTime, ctxSize, dataId [C7x_1 ] 104.939565 s: 0.000, 6508, 0 [C7x_1 ] 104.939599 s: 0.006, 6636, 1 [C7x_1 ] 104.939630 s: 0.006, 6636, 2 [C7x_1 ] 104.939659 s: 0.006, 6636, 3 [C7x_1 ] 104.939689 s: 0.006, 6636, 4 [C7x_1 ] 104.939720 s: 0.008, 6508, 5 [C7x_1 ] 104.939758 s: 0.000, 0, 6 [C7x_1 ] 104.939799 s: TIDL_initializeHandleForPreemption is completed RT-Profile: TIDLRT_init_profiling tidlrt_create : 16839764 ns, tidl_rt_ovx_Init : 11410 ns, vxCreateContext : 5115 ns, init_tidl_tiovx : 2946452 ns, create_graph_tidl_tiovx : 286209 ns, verify_graph_tidl_tiovx : 13330484 ns, tivxTIDLLoadKernels : 880 ns, mapConfig : 613070 ns, tivxAddKernelTIDL : 33565 ns, mapNetwork : 1619747 ns, setCreateParams : 317055 ns, setArgs : 359290 ns, vxCreateUserDataObject : 48444 ns, vxMapUserDataObject : 813769 ns, memcopy_network_buffer : 660815 ns, vxUnmapUserDataObject : 93694 ns, ************ TIDL_subgraphRtCreate done ************ In TIDL_createStateInfer Compute on node : TIDLExecutionProvider_TIDL_7_7 ************ in TIDL_subgraphRtCreate ************ [C7x_1 ] 104.969738 s: PREEMPTION: Requesting memory of size 128 for targetPriority = 0 [C7x_1 ] 104.969776 s: [C7x_1 ] 104.969798 s: -------------------------------------------- [C7x_1 ] 104.969828 s: TIDL Memory size requiement (record wise): [C7x_1 ] 104.969876 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 104.969933 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0x00000000 [C7x_1 ] 104.969987 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0x00000000 [C7x_1 ] 104.970038 s: 2 , L1D , Scratch , 128, 16.00 , 0x00000000 [C7x_1 ] 104.970090 s: 3 , L2 , Scratch , 128, 224.00 , 0x00000000 [C7x_1 ] 104.970140 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x00000000 [C7x_1 ] 104.970192 s: 5 , DDR Cacheable , Persistent , 128, 349.39 , 0x00000000 [C7x_1 ] 104.970242 s: 6 , DDR Cacheable , Scratch , 128, 2.50 , 0x00000000 [C7x_1 ] 104.970293 s: 7 , DDR Cacheable , Persistent , 128, 1621.75 , 0x00000000 [C7x_1 ] 104.970342 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0x00000000 [C7x_1 ] 104.970391 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0x00000000 [C7x_1 ] 104.970442 s: 10 , DDR Cacheable , Persistent , 128, 416.42 , 0x00000000 [C7x_1 ] 104.970491 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0x00000000 [C7x_1 ] 104.970542 s: 12 , DDR Cacheable , Persistent , 128, 0.13 , 0x00000000 [C7x_1 ] 104.970590 s: 13 , DDR Cacheable , Persistent , 128, 1302.18 , 0x00000000 [C7x_1 ] 104.970639 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0x00000000 [C7x_1 ] 104.970689 s: 15 , DDR Cacheable , Persistent , 128, 0.50 , 0x00000000 [C7x_1 ] 104.970724 s: -------------------------------------------- [C7x_1 ] 104.970760 s: Total memory size requirement (space wise): [C7x_1 ] 104.970788 s: Mem Space , Size(KBytes) [C7x_1 ] 104.970813 s: L1D , 16.00 [C7x_1 ] 104.970837 s: L2 , 224.00 [C7x_1 ] 104.970862 s: L3/MSMC , 1024.00 [C7x_1 ] 104.970886 s: DDR Cacheable, 4228.29 [C7x_1 ] 104.970914 s: -------------------------------------------- [C7x_1 ] 104.970955 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 104.971001 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 104.971030 s: debugTraceLevel = 2 [C7x_1 ] 104.971043 s: [C7x_1 ] 104.971067 s: -------------------------------------------- [C7x_1 ] 104.971330 s: TIDL init call from ivision API [C7x_1 ] 104.971350 s: [C7x_1 ] 104.971371 s: -------------------------------------------- [C7x_1 ] 104.971400 s: TIDL Memory size requiement (record wise): [C7x_1 ] 104.971448 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 104.971502 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0xb42d88c0 [C7x_1 ] 104.971554 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0xb42dd680 [C7x_1 ] 104.971605 s: 2 , L1D , Scratch , 128, 16.00 , 0x7f03c000 [C7x_1 ] 104.971656 s: 3 , L2 , Scratch , 128, 224.00 , 0x7f000000 [C7x_1 ] 104.971708 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x7e000000 [C7x_1 ] 104.971766 s: 5 , DDR Cacheable , Persistent , 128, 349.39 , 0xb42dd9c0 [C7x_1 ] 104.971819 s: 6 , DDR Cacheable , Scratch , 128, 2.50 , 0xb9000000 [C7x_1 ] 104.971872 s: 7 , DDR Cacheable , Persistent , 128, 1621.75 , 0xb4335000 [C7x_1 ] 104.971923 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0xb9000c00 [C7x_1 ] 104.971975 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0xb9001000 [C7x_1 ] 104.972027 s: 10 , DDR Cacheable , Persistent , 128, 416.42 , 0xb44ca740 [C7x_1 ] 104.972078 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0xb9002000 [C7x_1 ] 104.972130 s: 12 , DDR Cacheable , Persistent , 128, 0.13 , 0xb4532980 [C7x_1 ] 104.972181 s: 13 , DDR Cacheable , Persistent , 128, 1302.18 , 0xb4532a40 [C7x_1 ] 104.972231 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0xb4678380 [C7x_1 ] 104.972283 s: 15 , DDR Cacheable , Persistent , 128, 0.50 , 0xb4678440 [C7x_1 ] 104.972317 s: -------------------------------------------- [C7x_1 ] 104.972347 s: Total memory size requirement (space wise): [C7x_1 ] 104.972371 s: Mem Space , Size(KBytes) [C7x_1 ] 104.972395 s: L1D , 16.00 [C7x_1 ] 104.972420 s: L2 , 224.00 [C7x_1 ] 104.972447 s: L3/MSMC , 1024.00 [C7x_1 ] 104.972474 s: DDR Cacheable, 4228.29 [C7x_1 ] 104.972503 s: -------------------------------------------- [C7x_1 ] 104.972543 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 104.972587 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 104.972615 s: debugTraceLevel = 2 [C7x_1 ] 104.972629 s: [C7x_1 ] 104.972652 s: -------------------------------------------- [C7x_1 ] 104.976775 s: Alg Init for Layer # - 3 [C7x_1 ] 104.976862 s: Alg Init for Layer # - 6 [C7x_1 ] 104.976906 s: Alg Init for Layer # - 7 [C7x_1 ] 104.976963 s: Alg Init for Layer # - 9 [C7x_1 ] 104.977045 s: Alg Init for Layer # - 8 [C7x_1 ] 104.977103 s: Alg Init for Layer # - 12 [C7x_1 ] 104.977141 s: Alg Init for Layer # - 14 [C7x_1 ] 104.977228 s: Alg Init for Layer # - 15 [C7x_1 ] 104.977306 s: Alg Init for Layer # - 4 [C7x_1 ] 104.977376 s: Alg Init for Layer # - 5 [C7x_1 ] 104.977573 s: Alg Init for Layer # - 11 [C7x_1 ] 104.977648 s: Alg Init for Layer # - 13 [C7x_1 ] 104.977687 s: Alg Init for Layer # - 17 [C7x_1 ] 104.977729 s: Alg Init for Layer # - 18 [C7x_1 ] 104.977792 s: Alg Init for Layer # - 20 [C7x_1 ] 104.977871 s: Alg Init for Layer # - 19 [C7x_1 ] 104.977928 s: Alg Init for Layer # - 22 [C7x_1 ] 104.977968 s: Alg Init for Layer # - 23 [C7x_1 ] 104.978078 s: PREEMPTION: Adding a new priority object for targetPriority = 0, handle = b42d88c0 [C7x_1 ] 104.978144 s: PREEMPTION: Now total number of priority objects = 8 at priorityId = 0, with new memRec of base = b4532980 and size = 128 [C7x_1 ] 104.978211 s: PREEMPTION: Requesting context memory addr for handle b42d88c0, return Addr = 9a2cfff0 [C7x_1 ] 104.978248 s: Print preEmption Hnadle during init stage : [C7x_1 ] 104.978277 s: ProcTime, ctxSize, dataId [C7x_1 ] 104.978315 s: 0.000, 6724, 0 [C7x_1 ] 104.978347 s: 0.013, 19396, 3 [C7x_1 ] 104.978377 s: 0.000, 19396, 2 [C7x_1 ] 104.978407 s: 0.010, 6724, 6 [C7x_1 ] 104.978436 s: 0.002, 6724, 7 [C7x_1 ] 104.978465 s: 0.008, 6724, 9 [C7x_1 ] 104.978495 s: 0.000, 6724, 10 [C7x_1 ] 104.978524 s: 0.002, 6724, 8 [C7x_1 ] 104.978553 s: 0.006, 6724, 12 [C7x_1 ] 104.978582 s: 0.006, 6724, 14 RT-Profile: TIDLRT_init_profiling [C7x_1 ] 104.978611 s: 0.008, 6724, 15 tidlrt_create : 20338080 ns, [C7x_1 ] 104.978641 s: 0.000, 6724, 16 tidl_rt_ovx_Init : 11790 ns, vxCreateContext : 7595 ns, [C7x_1 ] 104.978669 s: 0.000, 6724, 1 init_tidl_tiovx : 3047381 ns, create_graph_tidl_tiovx : 1647588 ns, [C7x_1 ] 104.978699 s: 0.238, 6724, 4 verify_graph_tidl_tiovx : 15298981 ns, tivxTIDLLoadKernels : 1035 ns, mapConfig : 590309 ns, [C7x_1 ] 104.978728 s: 0.025, 6724, 5 tivxAddKernelTIDL : 123415 ns, mapNetwork : 1649288 ns, [C7x_1 ] 104.978763 s: 0.030, 6724, 11 setCreateParams : 337360 ns, setArgs : 343779 ns, [C7x_1 ] 104.978794 s: 0.006, 19268, 13 vxCreateUserDataObject : 42870 ns, vxMapUserDataObject : 824479 ns, memcopy_network_buffer : 684019 ns, [C7x_1 ] 104.978824 s: 0.010, 234308, 17 vxUnmapUserDataObject : 95255 ns, ************ TIDL_subgraphRtCreate done ************ [C7x_1 ] 104.978853 s: 0.002, 234308, 18 [C7x_1 ] 104.978883 s: 0.008, 234308, 20 [C7x_1 ] 104.978914 s: 0.000, 234308, 21 In TIDL_createStateInfer [C7x_1 ] 104.978943 s: 0.002, 6724, 19 Compute on node : TIDLExecutionProvider_TIDL_8_8 [C7x_1 ] 104.978973 s: 0.006, 6724, 22 [C7x_1 ] 104.979004 s: 0.008, 6724, 23 [C7x_1 ] 104.979036 s: 0.000, 0, 24 [C7x_1 ] 104.979086 s: TIDL_initializeHandleForPreemption is completed ************ in TIDL_subgraphRtCreate ************ [C7x_1 ] 105.008389 s: PREEMPTION: Requesting memory of size 128 for targetPriority = 0 [C7x_1 ] 105.008416 s: [C7x_1 ] 105.008439 s: -------------------------------------------- [C7x_1 ] 105.008469 s: TIDL Memory size requiement (record wise): [C7x_1 ] 105.008515 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 105.008571 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0x00000000 [C7x_1 ] 105.008624 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0x00000000 [C7x_1 ] 105.008676 s: 2 , L1D , Scratch , 128, 16.00 , 0x00000000 [C7x_1 ] 105.008728 s: 3 , L2 , Scratch , 128, 224.00 , 0x00000000 [C7x_1 ] 105.008795 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x00000000 [C7x_1 ] 105.008851 s: 5 , DDR Cacheable , Persistent , 128, 364.27 , 0x00000000 [C7x_1 ] 105.008904 s: 6 , DDR Cacheable , Scratch , 128, 2.13 , 0x00000000 [C7x_1 ] 105.008953 s: 7 , DDR Cacheable , Persistent , 128, 7.75 , 0x00000000 [C7x_1 ] 105.009002 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0x00000000 [C7x_1 ] 105.009052 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0x00000000 [C7x_1 ] 105.009102 s: 10 , DDR Cacheable , Persistent , 128, 388.04 , 0x00000000 [C7x_1 ] 105.009154 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0x00000000 [C7x_1 ] 105.009204 s: 12 , DDR Cacheable , Persistent , 128, 0.13 , 0x00000000 [C7x_1 ] 105.009253 s: 13 , DDR Cacheable , Persistent , 128, 1297.66 , 0x00000000 [C7x_1 ] 105.009305 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0x00000000 [C7x_1 ] 105.009355 s: 15 , DDR Cacheable , Persistent , 128, 0.25 , 0x00000000 [C7x_1 ] 105.009390 s: -------------------------------------------- [C7x_1 ] 105.009420 s: Total memory size requirement (space wise): [C7x_1 ] 105.009448 s: Mem Space , Size(KBytes) [C7x_1 ] 105.009474 s: L1D , 16.00 [C7x_1 ] 105.009499 s: L2 , 224.00 [C7x_1 ] 105.009523 s: L3/MSMC , 1024.00 [C7x_1 ] 105.009551 s: DDR Cacheable, 2595.64 [C7x_1 ] 105.009578 s: -------------------------------------------- [C7x_1 ] 105.009618 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 105.009663 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 105.009692 s: debugTraceLevel = 2 [C7x_1 ] 105.009705 s: [C7x_1 ] 105.009730 s: -------------------------------------------- [C7x_1 ] 105.009908 s: TIDL init call from ivision API [C7x_1 ] 105.009929 s: [C7x_1 ] 105.009950 s: -------------------------------------------- [C7x_1 ] 105.009981 s: TIDL Memory size requiement (record wise): [C7x_1 ] 105.010027 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 105.010081 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0xb469f140 [C7x_1 ] 105.010132 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0xb46a3f00 [C7x_1 ] 105.010184 s: 2 , L1D , Scratch , 128, 16.00 , 0x7f03c000 [C7x_1 ] 105.010238 s: 3 , L2 , Scratch , 128, 224.00 , 0x7f000000 [C7x_1 ] 105.010288 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x7e000000 [C7x_1 ] 105.010340 s: 5 , DDR Cacheable , Persistent , 128, 364.27 , 0xb46a4240 [C7x_1 ] 105.010391 s: 6 , DDR Cacheable , Scratch , 128, 2.13 , 0xb9000000 [C7x_1 ] 105.010440 s: 7 , DDR Cacheable , Persistent , 128, 7.75 , 0xb46ff400 [C7x_1 ] 105.010491 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0xb9000c00 [C7x_1 ] 105.010540 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0xb9001000 [C7x_1 ] 105.010591 s: 10 , DDR Cacheable , Persistent , 128, 388.04 , 0xb4701340 [C7x_1 ] 105.010643 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0xb9002000 [C7x_1 ] 105.010693 s: 12 , DDR Cacheable , Persistent , 128, 0.13 , 0xb4762400 [C7x_1 ] 105.010745 s: 13 , DDR Cacheable , Persistent , 128, 1297.66 , 0xb47624c0 [C7x_1 ] 105.010804 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0xb48a6c00 [C7x_1 ] 105.010855 s: 15 , DDR Cacheable , Persistent , 128, 0.25 , 0xb48a6cc0 [C7x_1 ] 105.010890 s: -------------------------------------------- [C7x_1 ] 105.010921 s: Total memory size requirement (space wise): [C7x_1 ] 105.010946 s: Mem Space , Size(KBytes) [C7x_1 ] 105.010969 s: L1D , 16.00 [C7x_1 ] 105.010995 s: L2 , 224.00 [C7x_1 ] 105.011020 s: L3/MSMC , 1024.00 [C7x_1 ] 105.011046 s: DDR Cacheable, 2595.64 [C7x_1 ] 105.011076 s: -------------------------------------------- [C7x_1 ] 105.011118 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 105.011162 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 105.011190 s: debugTraceLevel = 2 [C7x_1 ] 105.011204 s: [C7x_1 ] 105.011227 s: -------------------------------------------- [C7x_1 ] 105.015311 s: Alg Init for Layer # - 5 [C7x_1 ] 105.015402 s: Alg Init for Layer # - 6 [C7x_1 ] 105.015471 s: Alg Init for Layer # - 10 [C7x_1 ] 105.015565 s: Alg Init for Layer # - 11 [C7x_1 ] 105.015649 s: Alg Init for Layer # - 7 [C7x_1 ] 105.015723 s: Alg Init for Layer # - 12 [C7x_1 ] 105.015826 s: Alg Init for Layer # - 13 [C7x_1 ] 105.015923 s: Alg Init for Layer # - 15 RT-Profile: TIDLRT_init_profiling tidlrt_create : 19164655 ns, tidl_rt_ovx_Init : 12960 ns, vxCreateContext : 6099 ns, init_tidl_tiovx : 3077737 ns, create_graph_tidl_tiovx : 789824 ns, verify_graph_tidl_tiovx : 14993946 ns, tivxTIDLLoadKernels : 890 ns, mapConfig : 502475 ns, tivxAddKernelTIDL : 118225 ns, mapNetwork : 1794247 ns, setCreateParams : 304445 ns, setArgs : 354520 ns, vxCreateUserDataObject : 118610 ns, vxMapUserDataObject : 895588 ns, memcopy_network_buffer : 678670 ns, vxUnmapUserDataObject : 97594 ns, ************ TIDL_subgraphRtCreate done ************ In TIDL_createStateInfer Compute on node : TIDLExecutionProvider_TIDL_9_9 ************ in TIDL_subgraphRtCreate ************ [C7x_1 ] 105.016006 s: Alg Init for Layer # - 8 [C7x_1 ] 105.016078 s: Alg Init for Layer # - 18 [C7x_1 ] 105.016116 s: Alg Init for Layer # - 19 [C7x_1 ] 105.016198 s: Alg Init for Layer # - 20 [C7x_1 ] 105.016275 s: Alg Init for Layer # - 9 [C7x_1 ] 105.016344 s: Alg Init for Layer # - 17 [C7x_1 ] 105.016383 s: Alg Init for Layer # - 21 [C7x_1 ] 105.016491 s: PREEMPTION: Adding a new priority object for targetPriority = 0, handle = b469f140 [C7x_1 ] 105.016558 s: PREEMPTION: Now total number of priority objects = 9 at priorityId = 0, with new memRec of base = b4762400 and size = 128 [C7x_1 ] 105.016625 s: PREEMPTION: Requesting context memory addr for handle b469f140, return Addr = 9a2cfff0 [C7x_1 ] 105.016662 s: Print preEmption Hnadle during init stage : [C7x_1 ] 105.016691 s: ProcTime, ctxSize, dataId [C7x_1 ] 105.016725 s: 0.000, 6712, 0 [C7x_1 ] 105.016764 s: 0.006, 6840, 5 [C7x_1 ] 105.016796 s: 0.000, 6840, 1 [C7x_1 ] 105.016828 s: 0.006, 6968, 6 [C7x_1 ] 105.016859 s: 0.008, 6840, 10 [C7x_1 ] 105.016890 s: 0.008, 6840, 11 [C7x_1 ] 105.016920 s: 0.000, 6840, 14 [C7x_1 ] 105.016950 s: 0.000, 6840, 2 [C7x_1 ] 105.016979 s: 0.006, 6968, 7 [C7x_1 ] 105.017009 s: 0.008, 6840, 12 [C7x_1 ] 105.017041 s: 0.008, 6712, 13 [C7x_1 ] 105.017071 s: 0.008, 6712, 15 [C7x_1 ] 105.017100 s: 0.000, 6712, 16 [C7x_1 ] 105.017129 s: 0.000, 6712, 3 [C7x_1 ] 105.017159 s: 0.006, 6840, 8 [C7x_1 ] 105.017190 s: 0.006, 6840, 18 [C7x_1 ] 105.017221 s: 0.006, 6840, 19 [C7x_1 ] 105.017250 s: 0.008, 6712, 20 [C7x_1 ] 105.017279 s: 0.000, 6712, 22 [C7x_1 ] 105.017309 s: 0.000, 6712, 4 [C7x_1 ] 105.017340 s: 0.006, 6840, 9 [C7x_1 ] 105.017371 s: 0.006, 6840, 17 [C7x_1 ] 105.017401 s: 0.008, 6712, 21 [C7x_1 ] 105.017430 s: 0.000, 0, 23 [C7x_1 ] 105.017483 s: TIDL_initializeHandleForPreemption is completed [C7x_1 ] 105.046872 s: PREEMPTION: Requesting memory of size 128 for targetPriority = 0 [C7x_1 ] 105.046902 s: [C7x_1 ] 105.046924 s: -------------------------------------------- [C7x_1 ] 105.046954 s: TIDL Memory size requiement (record wise): [C7x_1 ] 105.047001 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 105.047058 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0x00000000 [C7x_1 ] 105.047114 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0x00000000 [C7x_1 ] 105.047165 s: 2 , L1D , Scratch , 128, 16.00 , 0x00000000 [C7x_1 ] 105.047215 s: 3 , L2 , Scratch , 128, 224.00 , 0x00000000 [C7x_1 ] 105.047265 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x00000000 [C7x_1 ] 105.047316 s: 5 , DDR Cacheable , Persistent , 128, 383.17 , 0x00000000 [C7x_1 ] 105.047367 s: 6 , DDR Cacheable , Scratch , 128, 2.38 , 0x00000000 [C7x_1 ] 105.047418 s: 7 , DDR Cacheable , Persistent , 128, 7.75 , 0x00000000 [C7x_1 ] 105.047467 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0x00000000 [C7x_1 ] 105.047515 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0x00000000 [C7x_1 ] 105.047565 s: 10 , DDR Cacheable , Persistent , 128, 406.96 , 0x00000000 [C7x_1 ] 105.047615 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0x00000000 [C7x_1 ] 105.047664 s: 12 , DDR Cacheable , Persistent , 128, 0.13 , 0x00000000 [C7x_1 ] 105.047715 s: 13 , DDR Cacheable , Persistent , 128, 1302.11 , 0x00000000 [C7x_1 ] 105.047769 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0x00000000 [C7x_1 ] 105.047824 s: 15 , DDR Cacheable , Persistent , 128, 0.25 , 0x00000000 [C7x_1 ] 105.047859 s: -------------------------------------------- [C7x_1 ] 105.047892 s: Total memory size requirement (space wise): [C7x_1 ] 105.047918 s: Mem Space , Size(KBytes) [C7x_1 ] 105.047944 s: L1D , 16.00 [C7x_1 ] 105.047970 s: L2 , 224.00 [C7x_1 ] 105.047995 s: L3/MSMC , 1024.00 [C7x_1 ] 105.048022 s: DDR Cacheable, 2638.16 [C7x_1 ] 105.048049 s: -------------------------------------------- [C7x_1 ] 105.048090 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 105.048133 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 105.048161 s: debugTraceLevel = 2 [C7x_1 ] 105.048174 s: [C7x_1 ] 105.048198 s: -------------------------------------------- [C7x_1 ] 105.048370 s: TIDL init call from ivision API [C7x_1 ] 105.048391 s: [C7x_1 ] 105.048412 s: -------------------------------------------- [C7x_1 ] 105.048443 s: TIDL Memory size requiement (record wise): [C7x_1 ] 105.048489 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 105.048541 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0xb48cd8c0 [C7x_1 ] 105.048595 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0xb48d2680 [C7x_1 ] 105.048645 s: 2 , L1D , Scratch , 128, 16.00 , 0x7f03c000 [C7x_1 ] 105.048695 s: 3 , L2 , Scratch , 128, 224.00 , 0x7f000000 [C7x_1 ] 105.048745 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x7e000000 [C7x_1 ] 105.048805 s: 5 , DDR Cacheable , Persistent , 128, 383.17 , 0xb48d29c0 [C7x_1 ] 105.048859 s: 6 , DDR Cacheable , Scratch , 128, 2.38 , 0xb9000000 [C7x_1 ] 105.048909 s: 7 , DDR Cacheable , Persistent , 128, 7.75 , 0xb4932700 [C7x_1 ] 105.048960 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0xb9000c00 [C7x_1 ] 105.049010 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0xb9001000 [C7x_1 ] 105.049060 s: 10 , DDR Cacheable , Persistent , 128, 406.96 , 0xb4934640 [C7x_1 ] 105.049111 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0xb9002000 [C7x_1 ] 105.049160 s: 12 , DDR Cacheable , Persistent , 128, 0.13 , 0xb499a280 [C7x_1 ] 105.049209 s: 13 , DDR Cacheable , Persistent , 128, 1302.11 , 0xb499a340 [C7x_1 ] 105.049261 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0xb4adfc00 [C7x_1 ] 105.049311 s: 15 , DDR Cacheable , Persistent , 128, 0.25 , 0xb4adfcc0 [C7x_1 ] 105.049345 s: -------------------------------------------- [C7x_1 ] 105.049373 s: Total memory size requirement (space wise): [C7x_1 ] 105.049399 s: Mem Space , Size(KBytes) [C7x_1 ] 105.049422 s: L1D , 16.00 [C7x_1 ] 105.049445 s: L2 , 224.00 [C7x_1 ] 105.049470 s: L3/MSMC , 1024.00 [C7x_1 ] 105.049497 s: DDR Cacheable, 2638.16 [C7x_1 ] 105.049525 s: -------------------------------------------- [C7x_1 ] 105.049566 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 105.049609 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 105.049637 s: debugTraceLevel = 2 [C7x_1 ] 105.049651 s: [C7x_1 ] 105.049674 s: -------------------------------------------- [C7x_1 ] 105.053793 s: Alg Init for Layer # - 5 [C7x_1 ] 105.053879 s: Alg Init for Layer # - 6 [C7x_1 ] 105.053951 s: Alg Init for Layer # - 11 [C7x_1 ] 105.054044 s: Alg Init for Layer # - 7 [C7x_1 ] 105.054115 s: Alg Init for Layer # - 14 [C7x_1 ] 105.054201 s: Alg Init for Layer # - 8 [C7x_1 ] 105.054271 s: Alg Init for Layer # - 15 [C7x_1 ] 105.054360 s: Alg Init for Layer # - 16 [C7x_1 ] 105.054445 s: Alg Init for Layer # - 20 [C7x_1 ] 105.054525 s: Alg Init for Layer # - 9 [C7x_1 ] 105.054595 s: Alg Init for Layer # - 10 [C7x_1 ] 105.054673 s: Alg Init for Layer # - 12 [C7x_1 ] 105.054770 s: Alg Init for Layer # - 13 [C7x_1 ] 105.054851 s: Alg Init for Layer # - 21 [C7x_1 ] 105.054930 s: Alg Init for Layer # - 17 [C7x_1 ] 105.055020 s: Alg Init for Layer # - 18 [C7x_1 ] 105.055104 s: Alg Init for Layer # - 19 [C7x_1 ] 105.055215 s: PREEMPTION: Adding a new priority object for targetPriority = 0, handle = b48cd8c0 [C7x_1 ] 105.055281 s: PREEMPTION: Now total number of priority objects = 10 at priorityId = 0, with new memRec of base = b499a280 and size = 128 [C7x_1 ] 105.055350 s: PREEMPTION: Requesting context memory addr for handle b48cd8c0, return Addr = 9a2cfff0 [C7x_1 ] 105.055386 s: Print preEmption Hnadle during init stage : [C7x_1 ] 105.055416 s: ProcTime, ctxSize, dataId [C7x_1 ] 105.055448 s: 0.000, 6724, 0 [C7x_1 ] 105.055482 s: 0.006, 6852, 5 [C7x_1 ] 105.055513 s: 0.000, 6852, 1 [C7x_1 ] 105.055546 s: 0.006, 6980, 6 [C7x_1 ] 105.055578 s: 0.008, 6852, 11 [C7x_1 ] 105.055608 s: 0.000, 6852, 2 [C7x_1 ] 105.055639 s: 0.006, 6980, 7 [C7x_1 ] 105.055669 s: 0.006, 6980, 14 [C7x_1 ] 105.055701 s: 0.000, 6980, 3 [C7x_1 ] 105.055732 s: 0.006, 7108, 8 [C7x_1 ] 105.055770 s: 0.008, 6980, 15 [C7x_1 ] 105.055803 s: 0.006, 6980, 16 [C7x_1 ] 105.055834 s: 0.008, 6852, 20 [C7x_1 ] 105.055864 s: 0.000, 6852, 23 [C7x_1 ] 105.055893 s: 0.000, 6852, 4 [C7x_1 ] 105.055924 s: 0.006, 6980, 9 [C7x_1 ] 105.055955 s: 0.006, 7108, 10 [C7x_1 ] 105.055987 s: 0.008, 7108, 12 [C7x_1 ] 105.056017 s: 0.006, 7108, 13 [C7x_1 ] 105.056047 s: 0.008, 6980, 21 [C7x_1 ] 105.056077 s: 0.000, 6980, 24 [C7x_1 ] 105.056107 s: 0.008, 6852, 17 [C7x_1 ] 105.056138 s: 0.006, 6852, 18 [C7x_1 ] 105.056169 s: 0.008, 6724, 19 [C7x_1 ] 105.056199 s: 0.000, 0, 22 [C7x_1 ] 105.056250 s: TIDL_initializeHandleForPreemption is completed RT-Profile: TIDLRT_init_profiling tidlrt_create : 19338236 ns, tidl_rt_ovx_Init : 11485 ns, vxCreateContext : 5240 ns, init_tidl_tiovx : 3015476 ns, create_graph_tidl_tiovx : 747994 ns, verify_graph_tidl_tiovx : 15276321 ns, tivxTIDLLoadKernels : 860 ns, mapConfig : 496524 ns, tivxAddKernelTIDL : 122620 ns, mapNetwork : 1772563 ns, setCreateParams : 304620 ns, setArgs : 315474 ns, vxCreateUserDataObject : 58575 ns, vxMapUserDataObject : 837709 ns, memcopy_network_buffer : 770999 ns, vxUnmapUserDataObject : 102490 ns, ************ TIDL_subgraphRtCreate done ************ In TIDL_createStateInfer Compute on node : TIDLExecutionProvider_TIDL_10_10 ************ in TIDL_subgraphRtCreate ************ 105.098331 s: VX_ZONE_ERROR: [ownContextSendCmd:912] Command ack message returned failure cmd_status: -1 105.098570 s: VX_ZONE_ERROR: [ownNodeKernelInit:604] Target kernel, TIVX_CMD_NODE_CREATE failed for node TIDLNode 105.098599 s: VX_ZONE_ERROR: [ownNodeKernelInit:605] Please be sure the target callbacks have been registered for this core 105.098610 s: VX_ZONE_ERROR: [ownNodeKernelInit:606] If the target callbacks have been registered, please ensure no errors are occurring within the create callback of this kernel 105.098627 s: VX_ZONE_ERROR: [ownGraphNodeKernelInit:690] kernel init for node 0, kernel com.ti.tidl:4:3 ... failed !!! 105.098690 s: VX_ZONE_ERROR: [ TIDL subgraph cls_signal ] Node kernel init failed 105.098704 s: VX_ZONE_ERROR: [ TIDL subgraph cls_signal ] Graph verify failed TIDL_RT_OVX: ERROR: Verifying TIDL graph ... Failed !!! TIDL_RT_OVX: ERROR: Verify OpenVX graph failed RT-Profile: TIDLRT_init_profiling tidlrt_create : 16458175 ns, tidl_rt_ovx_Init : 11514 ns, vxCreateContext : 11925 ns, init_tidl_tiovx : 3284321 ns, create_graph_tidl_tiovx : 2395927 ns, verify_graph_tidl_tiovx : 10467218 ns, tivxTIDLLoadKernels : 870 ns, mapConfig : 516785 ns, tivxAddKernelTIDL : 112520 ns, mapNetwork : 1965602 ns, setCreateParams : 304770 ns, setArgs : 381769 ns, vxCreateUserDataObject : 37300 ns, vxMapUserDataObject : 1022893 ns, memcopy_network_buffer : 791034 ns, vxUnmapUserDataObject : 111820 ns, ************ TIDL_subgraphRtCreate done ************ In TIDL_createStateInfer Compute on node : TIDLExecutionProvider_TIDL_11_11 [C7x_1 ] 105.090600 s: PREEMPTION: Requesting memory of size 128 for targetPriority = 0 [C7x_1 ] 105.090630 s: ************ in TIDL_subgraphRtCreate ************ [C7x_1 ] 105.090652 s: -------------------------------------------- [C7x_1 ] 105.090683 s: TIDL Memory size requiement (record wise): [C7x_1 ] 105.090730 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 105.090793 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0x00000000 [C7x_1 ] 105.090848 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0x00000000 [C7x_1 ] 105.090899 s: 2 , L1D , Scratch , 128, 16.00 , 0x00000000 [C7x_1 ] 105.090950 s: 3 , L2 , Scratch , 128, 224.00 , 0x00000000 [C7x_1 ] 105.090999 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x00000000 [C7x_1 ] 105.091051 s: 5 , DDR Cacheable , Persistent , 128, 459.55 , 0x00000000 [C7x_1 ] 105.091101 s: 6 , DDR Cacheable , Scratch , 128, 3.88 , 0x00000000 [C7x_1 ] 105.091150 s: 7 , DDR Cacheable , Persistent , 128, 4346.75 , 0x00000000 [C7x_1 ] 105.091202 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0x00000000 [C7x_1 ] 105.091251 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0x00000000 [C7x_1 ] 105.091299 s: 10 , DDR Cacheable , Persistent , 128, 520.49 , 0x00000000 [C7x_1 ] 105.091351 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0x00000000 [C7x_1 ] 105.091400 s: 12 , DDR Cacheable , Persistent , 128, 0.13 , 0x00000000 [C7x_1 ] 105.091451 s: 13 , DDR Cacheable , Persistent , 128, 1343.89 , 0x00000000 [C7x_1 ] 105.091501 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0x00000000 [C7x_1 ] 105.091552 s: 15 , DDR Cacheable , Persistent , 128, 174.50 , 0x00000000 [C7x_1 ] 105.091587 s: -------------------------------------------- [C7x_1 ] 105.091618 s: Total memory size requirement (space wise): [C7x_1 ] 105.091643 s: Mem Space , Size(KBytes) [C7x_1 ] 105.091669 s: L1D , 16.00 [C7x_1 ] 105.091696 s: L2 , 224.00 [C7x_1 ] 105.091721 s: L3/MSMC , 1024.00 [C7x_1 ] 105.091747 s: DDR Cacheable, 7384.61 [C7x_1 ] 105.091781 s: -------------------------------------------- [C7x_1 ] 105.091824 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 105.091869 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 105.091897 s: debugTraceLevel = 2 [C7x_1 ] 105.091911 s: [C7x_1 ] 105.091936 s: -------------------------------------------- [C7x_1 ] 105.092378 s: TIDL init call from ivision API [C7x_1 ] 105.092399 s: [C7x_1 ] 105.092419 s: -------------------------------------------- [C7x_1 ] 105.092449 s: TIDL Memory size requiement (record wise): [C7x_1 ] 105.092494 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 105.092548 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0xb4b068c0 [C7x_1 ] 105.092600 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0xb4b0b680 [C7x_1 ] 105.092652 s: 2 , L1D , Scratch , 128, 16.00 , 0x7f03c000 [C7x_1 ] 105.092703 s: 3 , L2 , Scratch , 128, 224.00 , 0x7f000000 [C7x_1 ] 105.092754 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x7e000000 [C7x_1 ] 105.092815 s: 5 , DDR Cacheable , Persistent , 128, 459.55 , 0xb4b0b9c0 [C7x_1 ] 105.092869 s: 6 , DDR Cacheable , Scratch , 128, 3.88 , 0xb9000000 [C7x_1 ] 105.092919 s: 7 , DDR Cacheable , Persistent , 128, 4346.75 , 0xb4b7e880 [C7x_1 ] 105.092972 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0xb9001000 [C7x_1 ] 105.093023 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0xb9001400 [C7x_1 ] 105.093072 s: 10 , DDR Cacheable , Persistent , 128, 520.49 , 0xb4fbd3c0 [C7x_1 ] 105.093123 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0xb9002400 [C7x_1 ] 105.093173 s: 12 , DDR Cacheable , Persistent , 128, 0.13 , 0xb503f600 [C7x_1 ] 105.093224 s: 13 , DDR Cacheable , Persistent , 128, 1343.89 , 0xb503f6c0 [C7x_1 ] 105.093276 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0xb518f700 [C7x_1 ] 105.093325 s: 15 , DDR Cacheable , Persistent , 128, 174.50 , 0xb518f7c0 [C7x_1 ] 105.093361 s: -------------------------------------------- [C7x_1 ] 105.093393 s: Total memory size requirement (space wise): [C7x_1 ] 105.093418 s: Mem Space , Size(KBytes) [C7x_1 ] 105.093442 s: L1D , 16.00 [C7x_1 ] 105.093465 s: L2 , 224.00 [C7x_1 ] 105.093492 s: L3/MSMC , 1024.00 [C7x_1 ] 105.093519 s: DDR Cacheable, 7384.61 [C7x_1 ] 105.093546 s: -------------------------------------------- [C7x_1 ] 105.093587 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 105.093630 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 105.093659 s: debugTraceLevel = 2 [C7x_1 ] 105.093672 s: [C7x_1 ] 105.093696 s: -------------------------------------------- [C7x_1 ] 105.097846 s: Alg Init for Layer # - 7 [C7x_1 ] 105.097945 s: Error: Layer 7, MMALIB_CNN_tensor_convert_ixX_oxX_init 6 [C7x_1 ] 105.097998 s: WorkloadUnitExec_Init: initParams->linkInitParams[linkIdx].initFuncPtr Failed, Link Id 134217840 [C7x_1 ] 105.098036 s: VX_ZONE_ERROR: [tivxAlgiVisionCreate:335] Calling ialg.algInit failed with status = 1 [C7x_1 ] 105.098096 s: Error: handle (b4b068c0) doesn't exist in priority table [C7x_1 ] 105.098134 s: VX_ZONE_ERROR: [tivxKernelTIDLCreate:976] tivxAlgiVisionCreate returned NULL [C7x_1 ] 105.143443 s: PREEMPTION: Requesting memory of size 128 for targetPriority = 0 [C7x_1 ] 105.143472 s: [C7x_1 ] 105.143497 s: -------------------------------------------- [C7x_1 ] 105.143528 s: TIDL Memory size requiement (record wise): [C7x_1 ] 105.143575 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 105.143628 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0x00000000 [C7x_1 ] 105.143684 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0x00000000 [C7x_1 ] 105.143736 s: 2 , L1D , Scratch , 128, 16.00 , 0x00000000 [C7x_1 ] 105.143799 s: 3 , L2 , Scratch , 128, 224.00 , 0x00000000 [C7x_1 ] 105.143852 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x00000000 [C7x_1 ] 105.143906 s: 5 , DDR Cacheable , Persistent , 128, 256.00 , 0x00000000 [C7x_1 ] 105.143958 s: 6 , DDR Cacheable , Scratch , 128, 0.25 , 0x00000000 [C7x_1 ] 105.144008 s: 7 , DDR Cacheable , Persistent , 128, 0.13 , 0x00000000 [C7x_1 ] 105.144060 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0x00000000 [C7x_1 ] 105.144110 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0x00000000 [C7x_1 ] 105.144159 s: 10 , DDR Cacheable , Persistent , 128, 246.13 , 0x00000000 [C7x_1 ] 105.144211 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0x00000000 [C7x_1 ] 105.144261 s: 12 , DDR Cacheable , Persistent , 128, 0.13 , 0x00000000 [C7x_1 ] 105.144312 s: 13 , DDR Cacheable , Persistent , 128, 1299.39 , 0x00000000 [C7x_1 ] 105.144362 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0x00000000 [C7x_1 ] 105.144414 s: 15 , DDR Cacheable , Persistent , 128, 0.25 , 0x00000000 [C7x_1 ] 105.144449 s: -------------------------------------------- [C7x_1 ] 105.144478 s: Total memory size requirement (space wise): [C7x_1 ] 105.144503 s: Mem Space , Size(KBytes) [C7x_1 ] 105.144529 s: L1D , 16.00 [C7x_1 ] 105.144557 s: L2 , 224.00 [C7x_1 ] 105.144582 s: L3/MSMC , 1024.00 [C7x_1 ] 105.144608 s: DDR Cacheable, 2337.69 [C7x_1 ] 105.144638 s: -------------------------------------------- [C7x_1 ] 105.144679 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 105.144725 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 105.144754 s: debugTraceLevel = 2 [C7x_1 ] 105.144773 s: [C7x_1 ] 105.144799 s: -------------------------------------------- [C7x_1 ] 105.144955 s: TIDL init call from ivision API [C7x_1 ] 105.144978 s: [C7x_1 ] 105.144999 s: -------------------------------------------- [C7x_1 ] 105.145028 s: TIDL Memory size requiement (record wise): [C7x_1 ] 105.145073 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr [C7x_1 ] 105.145126 s: 0 , DDR Cacheable , Persistent , 128, 19.27 , 0xb51bb200 [C7x_1 ] 105.145177 s: 1 , DDR Cacheable , Persistent , 128, 0.65 , 0xb51bffc0 [C7x_1 ] 105.145227 s: 2 , L1D , Scratch , 128, 16.00 , 0x7f03c000 [C7x_1 ] 105.145279 s: 3 , L2 , Scratch , 128, 224.00 , 0x7f000000 [C7x_1 ] 105.145329 s: 4 , L3/MSMC , Scratch , 128, 1024.00 , 0x7e000000 [C7x_1 ] 105.145380 s: 5 , DDR Cacheable , Persistent , 128, 256.00 , 0xb51c0300 [C7x_1 ] 105.145431 s: 6 , DDR Cacheable , Scratch , 128, 0.25 , 0xb9000000 [C7x_1 ] 105.145481 s: 7 , DDR Cacheable , Persistent , 128, 0.13 , 0xb5200340 [C7x_1 ] 105.145532 s: 8 , DDR Cacheable , Scratch , 128, 0.13 , 0xb9000400 [C7x_1 ] 105.145582 s: 9 , DDR Cacheable , Scratch , 128, 3.13 , 0xb9000800 [C7x_1 ] 105.145633 s: 10 , DDR Cacheable , Persistent , 128, 246.13 , 0xb5200400 [C7x_1 ] 105.145686 s: 11 , DDR Cacheable , Scratch , 128, 512.25 , 0xb9001800 [C7x_1 ] 105.145738 s: 12 , DDR Cacheable , Persistent , 128, 0.13 , 0xb523dcc0 [C7x_1 ] 105.145799 s: 13 , DDR Cacheable , Persistent , 128, 1299.39 , 0xb523dd80 [C7x_1 ] 105.145852 s: 14 , DDR Cacheable , Persistent , 128, 0.00 , 0xb5382bc0 [C7x_1 ] 105.145904 s: 15 , DDR Cacheable , Persistent , 128, 0.25 , 0xb5382c80 [C7x_1 ] 105.145940 s: -------------------------------------------- [C7x_1 ] 105.145970 s: Total memory size requirement (space wise): [C7x_1 ] 105.145997 s: Mem Space , Size(KBytes) [C7x_1 ] 105.146020 s: L1D , 16.00 [C7x_1 ] 105.146047 s: L2 , 224.00 [C7x_1 ] 105.146075 s: L3/MSMC , 1024.00 [C7x_1 ] 105.146101 s: DDR Cacheable, 2337.69 [C7x_1 ] 105.146130 s: -------------------------------------------- [C7x_1 ] 105.146172 s: NOTE: Memory requirement in host emulation can be different from the same on EVM [C7x_1 ] 105.146216 s: To get the actual TIDL memory requirement make sure to run on EVM with [C7x_1 ] 105.146245 s: debugTraceLevel = 2 [C7x_1 ] 105.146258 s: [C7x_1 ] 105.146282 s: -------------------------------------------- [C7x_1 ] 105.150491 s: PREEMPTION: Adding a new priority object for targetPriority = 0, handle = b51bb200 [C7x_1 ] 105.150558 s: PREEMPTION: Now total number of priority objects = 11 at priorityId = 0, with new memRec of base = b523dcc0 and size = 128 [C7x_1 ] 105.150626 s: PREEMPTION: Requesting context memory addr for handle b51bb200, return Addr = 9a2cfff0 [C7x_1 ] 105.150665 s: Print preEmption Hnadle during init stage : [C7x_1 ] 105.150697 s: ProcTime, ctxSize, dataId [C7x_1 ] 105.154235 s: A0 =0xa5a5a5a5a5a5a5a5 A1 =0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.154294 s: A2 =0xa5a5a5a5a5a5a5a5 A3 =0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.154346 s: A4 =0xa5a5a5a5a5a5a5a5 A5 =0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.154400 s: A6 =0xa5a5a5a5a5a5a5a5 A7 =0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.154453 s: A8 =0xa5a5a5a5a5a5a5a5 A9 =0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.154506 s: A10=0xa5a5a5a5a5a5a5a5 A11=0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.154558 s: A12=0xa5a5a5a5a5a5a5a5 A13=0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.154610 s: A14=0xa5a5a5a5a5a5a5a5 A15=0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.154663 s: D0 =0xa5a5a5a5a5a5a5a5 D1 =0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.154715 s: D2 =0xa5a5a5a5a5a5a5a5 D3 =0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.154769 s: D4 =0xa5a5a5a5a5a5a5a5 D5 =0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.154822 s: D6 =0xa5a5a5a5a5a5a5a5 D7 =0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.154875 s: D8 =0xa5a5a5a5a5a5a5a5 D9 =0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.154928 s: D10=0xa5a5a5a5a5a5a5a5 D11=0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.154981 s: D12=0xa5a5a5a5a5a5a5a5 D13=0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.155033 s: D14=0xa5a5a5a5a5a5a5a5 D15=0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.155086 s: AM0=0xa5a5a5a5a5a5a5a5 AM1=0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.155140 s: AM2=0xa5a5a5a5a5a5a5a5 AM3=0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.155193 s: AM4=0xa5a5a5a5a5a5a5a5 AM5=0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.155247 s: AM6=0xa5a5a5a5a5a5a5a5 AM7=0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.155299 s: AL0=0xa5a5a5a5a5a5a5a5 AL1=0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.155351 s: AL2=0xa5a5a5a5a5a5a5a5 AL3=0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.155403 s: AL4=0xa5a5a5a5a5a5a5a5 AL5=0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.155455 s: AL6=0xa5a5a5a5a5a5a5a5 AL7=0xa5a5a5a5a5a5a5a5 [C7x_1 ] 105.155493 s: P0=0x000000000000003f P1=0x0000000000ffffff [C7x_1 ] 105.155531 s: P2=0x000000000001ffff P3=0x00000000364c0936 [C7x_1 ] 105.155571 s: P4=0x00000000412a58fb P5=0x00000000341af526 [C7x_1 ] 105.155610 s: P6=0x0000000080700e85 P7=0x000000007908da04 [C7x_1 ] 105.155646 s: FPCR=0x0000000000000010 FSR=0x0000000000000010 [C7x_1 ] 105.155685 s: GFPGFR=0x000000000700001d GPLY=0x0000000000000000 [C7x_1 ] 105.155707 s: [C7x_1 ] 105.155757 s: VBM0=0xa5a5a5a5a5a5a5a5 [0] VBM1=0xa5a5a5a5a5a5a5a5 [0] [C7x_1 ] 105.155818 s: 0xa5a5a5a5a5a5a5a5 [1] 0xa5a5a5a5a5a5a5a5 [1] [C7x_1 ] 105.155877 s: 0xa5a5a5a5a5a5a5a5 [2] 0xa5a5a5a5a5a5a5a5 [2] [C7x_1 ] 105.155937 s: 0xa5a5a5a5a5a5a5a5 [3] 0xa5a5a5a5a5a5a5a5 [3] [C7x_1 ] 105.155997 s: 0xa5a5a5a5a5a5a5a5 [4] 0xa5a5a5a5a5a5a5a5 [4] [C7x_1 ] 105.156055 s: 0xa5a5a5a5a5a5a5a5 [5] 0xa5a5a5a5a5a5a5a5 [5] [C7x_1 ] 105.156112 s: 0xa5a5a5a5a5a5a5a5 [6] 0xa5a5a5a5a5a5a5a5 [6] [C7x_1 ] 105.156170 s: 0xa5a5a5a5a5a5a5a5 [7] 0xa5a5a5a5a5a5a5a5 [7] [C7x_1 ] 105.156194 s: [C7x_1 ] 105.156243 s: VBM2=0xa5a5a5a5a5a5a5a5 [0] VBM3=0xa5a5a5a5a5a5a5a5 [0] [C7x_1 ] 105.156302 s: 0xa5a5a5a5a5a5a5a5 [1] 0xa5a5a5a5a5a5a5a5 [1] [C7x_1 ] 105.156359 s: 0xa5a5a5a5a5a5a5a5 [2] 0xa5a5a5a5a5a5a5a5 [2] [C7x_1 ] 105.156418 s: 0xa5a5a5a5a5a5a5a5 [3] 0xa5a5a5a5a5a5a5a5 [3] [C7x_1 ] 105.156476 s: 0xa5a5a5a5a5a5a5a5 [4] 0xa5a5a5a5a5a5a5a5 [4] [C7x_1 ] 105.156535 s: 0xa5a5a5a5a5a5a5a5 [5] 0xa5a5a5a5a5a5a5a5 [5] [C7x_1 ] 105.156592 s: 0xa5a5a5a5a5a5a5a5 [6] 0xa5a5a5a5a5a5a5a5 [6] [C7x_1 ] 105.156650 s: 0xa5a5a5a5a5a5a5a5 [7] 0xa5a5a5a5a5a5a5a5 [7] [C7x_1 ] 105.156673 s: [C7x_1 ] 105.156721 s: VBM4=0xa5a5a5a5a5a5a5a5 [0] VBM5=0xa5a5a5a5a5a5a5a5 [0] [C7x_1 ] 105.156780 s: 0xa5a5a5a5a5a5a5a5 [1] 0xa5a5a5a5a5a5a5a5 [1] [C7x_1 ] 105.156838 s: 0xa5a5a5a5a5a5a5a5 [2] 0xa5a5a5a5a5a5a5a5 [2] [C7x_1 ] 105.156895 s: 0xa5a5a5a5a5a5a5a5 [3] 0xa5a5a5a5a5a5a5a5 [3] [C7x_1 ] 105.156954 s: 0xa5a5a5a5a5a5a5a5 [4] 0xa5a5a5a5a5a5a5a5 [4] [C7x_1 ] 105.157013 s: 0xa5a5a5a5a5a5a5a5 [5] 0xa5a5a5a5a5a5a5a5 [5] [C7x_1 ] 105.157071 s: 0xa5a5a5a5a5a5a5a5 [6] 0xa5a5a5a5a5a5a5a5 [6] [C7x_1 ] 105.157128 s: 0xa5a5a5a5a5a5a5a5 [7] 0xa5a5a5a5a5a5a5a5 [7] [C7x_1 ] 105.157151 s: [C7x_1 ] 105.157190 s: VBM6=0xa5a5a5a5a5a5a5a5 [0] VBM7=0x0000000000000000 [0] [C7x_1 ] 105.157248 s: 0xa5a5a5a5a5a5a5a5 [1] 0x091000010100ff03 [1] [C7x_1 ] 105.157299 s: 0xa5a5a5a5a5a5a5a5 [2] 0x0000000000001918 [2] [C7x_1 ] 105.157347 s: 0xa5a5a5a5a5a5a5a5 [3] 0x0000000000000058 [3] [C7x_1 ] 105.157400 s: 0xa5a5a5a5a5a5a5a5 [4] 0x00000000b524f960 [4] [C7x_1 ] 105.157451 s: 0xa5a5a5a5a5a5a5a5 [5] 0x0000000000000000 [5] [C7x_1 ] 105.157499 s: 0xa5a5a5a5a5a5a5a5 [6] 0x0000000000000000 [6] [C7x_1 ] 105.157557 s: 0xa5a5a5a5a5a5a5a5 [7] 0xa5a5a5a5a5a5a5a5 [7] [C7x_1 ] 105.157580 s: [C7x_1 ] 105.157615 s: VBL0=0x000000000000000b [0] VBL1=0x00000000b51be428 [0] [C7x_1 ] 105.157662 s: 0x00000000b2a5de00 [1] 0x000000009a37fac0 [1] [C7x_1 ] 105.157703 s: 0x0000000000000000 [2] 0x00000000000003c4 [2] [C7x_1 ] 105.157756 s: 0x00000000b530f760 [3] 0xffffffe96abc0920 [3] [C7x_1 ] 105.157803 s: 0x00000000b530f760 [4] 0x00000000b53157e0 [4] [C7x_1 ] 105.157850 s: 0x00000000b524f95c [5] 0x00000000b5304570 [5] [C7x_1 ] 105.157901 s: 0x00000000b5312760 [6] 0xffffffea1fed6100 [6] [C7x_1 ] 105.157946 s: 0x0000000000000219 [7] 0x00000000b53157e0 [7] [C7x_1 ] 105.157969 s: [C7x_1 ] 105.158011 s: VBL2=0x0000000099d2acd8 [0] VBL3=0x956578e509932b04 [0] [C7x_1 ] 105.158066 s: 0x00000000b5200400 [1] 0x643994c03cec8022 [1] [C7x_1 ] 105.158116 s: 0x0000000000000080 [2] 0x08814029ba4038f7 [2] [C7x_1 ] 105.158159 s: 0x00000000b2026ba8 [3] 0x0000000000000001 [3] [C7x_1 ] 105.158204 s: 0x000000009a1d3500 [4] 0x00000000000031a0 [4] [C7x_1 ] 105.158255 s: 0x00000000b51bfee0 [5] 0xffffffffbe4dc5ec [5] [C7x_1 ] 105.158298 s: 0x00000000b51be420 [6] 0x0000000000000058 [6] [C7x_1 ] 105.158343 s: 0x00000000b51bfee8 [7] 0x0000000099d2b450 [7] [C7x_1 ] 105.158368 s: [C7x_1 ] 105.158399 s: VBL4=0x0000000000000fc0 [0] VBL5=0x0000000000000000 [0] [C7x_1 ] 105.158443 s: 0x0000000000000fa8 [1] 0x0000000000000000 [1] [C7x_1 ] 105.158482 s: 0x0000000000000000 [2] 0x0000000000000000 [2] [C7x_1 ] 105.158531 s: 0x0000000000000000 [3] 0x410bc5ddbe76a8b8 [3] [C7x_1 ] 105.158575 s: 0x0000000000000000 [4] 0x000000009a2d5cf8 [4] [C7x_1 ] 105.158633 s: 0xffffffffbe4dc5ec [5] 0xd888822124230094 [5] [C7x_1 ] 105.158682 s: 0x0000000000000000 [6] 0xca8a580108a9c8e5 [6] [C7x_1 ] 105.158731 s: 0x914b45d720425087 [7] 0x0000000000000fa0 [7] [C7x_1 ] 105.158756 s: [C7x_1 ] 105.158790 s: VBL6=0x000000009a3c0758 [0] VBL7=0x0000000000000000 [0] [C7x_1 ] 105.158831 s: 0x0000000000000000 [1] 0x0000000000000000 [1] [C7x_1 ] 105.158870 s: 0x0000000000000000 [2] 0x0000000000000000 [2] [C7x_1 ] 105.158922 s: 0x00000000b524dec0 [3] 0xffffffffffffffd0 [3] [C7x_1 ] 105.158965 s: 0x000000009a3c0767 [4] 0x0000000000000000 [4] [C7x_1 ] 105.159005 s: 0x0000000000000000 [5] 0x0000000000000000 [5] [C7x_1 ] 105.159045 s: 0x0000000000000000 [6] 0x0000000000000000 [6] [C7x_1 ] 105.159087 s: 0x000000000000199c [7] 0x0000000000000000 [7] [C7x_1 ] 105.159111 s: [C7x_1 ] 105.159159 s: VB0=0xa5a5a5a5a5a5a5a5 [0] VB1=0xa5a5a5a5a5a5a5a5 [0] [C7x_1 ] 105.159220 s: 0xa5a5a5a5a5a5a5a5 [1] 0xa5a5a5a5a5a5a5a5 [1] [C7x_1 ] 105.159277 s: 0xa5a5a5a5a5a5a5a5 [2] 0xa5a5a5a5a5a5a5a5 [2] [C7x_1 ] 105.159336 s: 0xa5a5a5a5a5a5a5a5 [3] 0xa5a5a5a5a5a5a5a5 [3] [C7x_1 ] 105.159393 s: 0xa5a5a5a5a5a5a5a5 [4] 0xa5a5a5a5a5a5a5a5 [4] [C7x_1 ] 105.159450 s: 0xa5a5a5a5a5a5a5a5 [5] 0xa5a5a5a5a5a5a5a5 [5] [C7x_1 ] 105.159507 s: 0xa5a5a5a5a5a5a5a5 [6] 0xa5a5a5a5a5a5a5a5 [6] [C7x_1 ] 105.159566 s: 0xa5a5a5a5a5a5a5a5 [7] 0xa5a5a5a5a5a5a5a5 [7] [C7x_1 ] 105.159591 s: [C7x_1 ] 105.159637 s: VB2=0xa5a5a5a5a5a5a5a5 [0] VB3=0xa5a5a5a5a5a5a5a5 [0] [C7x_1 ] 105.159699 s: 0xa5a5a5a5a5a5a5a5 [1] 0xa5a5a5a5a5a5a5a5 [1] [C7x_1 ] 105.159758 s: 0xa5a5a5a5a5a5a5a5 [2] 0xa5a5a5a5a5a5a5a5 [2] [C7x_1 ] 105.159815 s: 0xa5a5a5a5a5a5a5a5 [3] 0xa5a5a5a5a5a5a5a5 [3] [C7x_1 ] 105.159873 s: 0xa5a5a5a5a5a5a5a5 [4] 0xa5a5a5a5a5a5a5a5 [4] [C7x_1 ] 105.159931 s: 0xa5a5a5a5a5a5a5a5 [5] 0xa5a5a5a5a5a5a5a5 [5] [C7x_1 ] 105.159987 s: 0xa5a5a5a5a5a5a5a5 [6] 0xa5a5a5a5a5a5a5a5 [6] [C7x_1 ] 105.160044 s: 0xa5a5a5a5a5a5a5a5 [7] 0xa5a5a5a5a5a5a5a5 [7] [C7x_1 ] 105.160068 s: [C7x_1 ] 105.160115 s: VB4=0xa5a5a5a5a5a5a5a5 [0] VB5=0xa5a5a5a5a5a5a5a5 [0] [C7x_1 ] 105.160174 s: 0xa5a5a5a5a5a5a5a5 [1] 0xa5a5a5a5a5a5a5a5 [1] [C7x_1 ] 105.160234 s: 0xa5a5a5a5a5a5a5a5 [2] 0xa5a5a5a5a5a5a5a5 [2] [C7x_1 ] 105.160294 s: 0xa5a5a5a5a5a5a5a5 [3] 0xa5a5a5a5a5a5a5a5 [3] [C7x_1 ] 105.160351 s: 0xa5a5a5a5a5a5a5a5 [4] 0xa5a5a5a5a5a5a5a5 [4] [C7x_1 ] 105.160408 s: 0xa5a5a5a5a5a5a5a5 [5] 0xa5a5a5a5a5a5a5a5 [5] [C7x_1 ] 105.160466 s: 0xa5a5a5a5a5a5a5a5 [6] 0xa5a5a5a5a5a5a5a5 [6] [C7x_1 ] 105.160524 s: 0xa5a5a5a5a5a5a5a5 [7] 0xa5a5a5a5a5a5a5a5 [7] [C7x_1 ] 105.160548 s: [C7x_1 ] 105.160595 s: VB6=0xa5a5a5a5a5a5a5a5 [0] VB7=0xa5a5a5a5a5a5a5a5 [0] [C7x_1 ] 105.160653 s: 0xa5a5a5a5a5a5a5a5 [1] 0xa5a5a5a5a5a5a5a5 [1] [C7x_1 ] 105.160711 s: 0xa5a5a5a5a5a5a5a5 [2] 0xa5a5a5a5a5a5a5a5 [2] [C7x_1 ] 105.160769 s: 0xa5a5a5a5a5a5a5a5 [3] 0xa5a5a5a5a5a5a5a5 [3] [C7x_1 ] 105.160827 s: 0xa5a5a5a5a5a5a5a5 [4] 0xa5a5a5a5a5a5a5a5 [4] [C7x_1 ] 105.160886 s: 0xa5a5a5a5a5a5a5a5 [5] 0xa5a5a5a5a5a5a5a5 [5] [C7x_1 ] 105.160944 s: 0xa5a5a5a5a5a5a5a5 [6] 0xa5a5a5a5a5a5a5a5 [6] [C7x_1 ] 105.161001 s: 0xa5a5a5a5a5a5a5a5 [7] 0xa5a5a5a5a5a5a5a5 [7] [C7x_1 ] 105.161024 s: [C7x_1 ] 105.161072 s: VB8=0xa5a5a5a5a5a5a5a5 [0] VB9=0xa5a5a5a5a5a5a5a5 [0] [C7x_1 ] 105.161131 s: 0xa5a5a5a5a5a5a5a5 [1] 0xa5a5a5a5a5a5a5a5 [1] [C7x_1 ] 105.161188 s: 0xa5a5a5a5a5a5a5a5 [2] 0xa5a5a5a5a5a5a5a5 [2] [C7x_1 ] 105.161245 s: 0xa5a5a5a5a5a5a5a5 [3] 0xa5a5a5a5a5a5a5a5 [3] [C7x_1 ] 105.161302 s: 0xa5a5a5a5a5a5a5a5 [4] 0xa5a5a5a5a5a5a5a5 [4] [C7x_1 ] 105.161359 s: 0xa5a5a5a5a5a5a5a5 [5] 0xa5a5a5a5a5a5a5a5 [5] [C7x_1 ] 105.161419 s: 0xa5a5a5a5a5a5a5a5 [6] 0xa5a5a5a5a5a5a5a5 [6] [C7x_1 ] 105.161478 s: 0xa5a5a5a5a5a5a5a5 [7] 0xa5a5a5a5a5a5a5a5 [7] [C7x_1 ] 105.161501 s: [C7x_1 ] 105.161552 s: VB10=0xa5a5a5a5a5a5a5a5 [0] VB11=0xa5a5a5a5a5a5a5a5 [0] [C7x_1 ] 105.161610 s: 0xa5a5a5a5a5a5a5a5 [1] 0xa5a5a5a5a5a5a5a5 [1] [C7x_1 ] 105.161670 s: 0xa5a5a5a5a5a5a5a5 [2] 0xa5a5a5a5a5a5a5a5 [2] [C7x_1 ] 105.161727 s: 0xa5a5a5a5a5a5a5a5 [3] 0xa5a5a5a5a5a5a5a5 [3] [C7x_1 ] 105.161784 s: 0xa5a5a5a5a5a5a5a5 [4] 0xa5a5a5a5a5a5a5a5 [4] [C7x_1 ] 105.161841 s: 0xa5a5a5a5a5a5a5a5 [5] 0xa5a5a5a5a5a5a5a5 [5] [C7x_1 ] 105.161898 s: 0xa5a5a5a5a5a5a5a5 [6] 0xa5a5a5a5a5a5a5a5 [6] [C7x_1 ] 105.161954 s: 0xa5a5a5a5a5a5a5a5 [7] 0xa5a5a5a5a5a5a5a5 [7] [C7x_1 ] 105.161978 s: [C7x_1 ] 105.162025 s: VB12=0xa5a5a5a5a5a5a5a5 [0] VB13=0xa5a5a5a5a5a5a5a5 [0] [C7x_1 ] 105.162083 s: 0xa5a5a5a5a5a5a5a5 [1] 0xa5a5a5a5a5a5a5a5 [1] [C7x_1 ] 105.162141 s: 0xa5a5a5a5a5a5a5a5 [2] 0xa5a5a5a5a5a5a5a5 [2] [C7x_1 ] 105.162198 s: 0xa5a5a5a5a5a5a5a5 [3] 0xa5a5a5a5a5a5a5a5 [3] [C7x_1 ] 105.162254 s: 0xa5a5a5a5a5a5a5a5 [4] 0xa5a5a5a5a5a5a5a5 [4] [C7x_1 ] 105.162311 s: 0xa5a5a5a5a5a5a5a5 [5] 0xa5a5a5a5a5a5a5a5 [5] [C7x_1 ] 105.162368 s: 0xa5a5a5a5a5a5a5a5 [6] 0xa5a5a5a5a5a5a5a5 [6] [C7x_1 ] 105.162425 s: 0xa5a5a5a5a5a5a5a5 [7] 0xa5a5a5a5a5a5a5a5 [7] [C7x_1 ] 105.162451 s: [C7x_1 ] 105.162498 s: VB14=0xa5a5a5a5a5a5a5a5 [0] VB15=0xa5a5a5a5a5a5a5a5 [0] [C7x_1 ] 105.162557 s: 0xa5a5a5a5a5a5a5a5 [1] 0xa5a5a5a5a5a5a5a5 [1] [C7x_1 ] 105.162617 s: 0xa5a5a5a5a5a5a5a5 [2] 0xa5a5a5a5a5a5a5a5 [2] [C7x_1 ] 105.162675 s: 0xa5a5a5a5a5a5a5a5 [3] 0xa5a5a5a5a5a5a5a5 [3] [C7x_1 ] 105.162734 s: 0xa5a5a5a5a5a5a5a5 [4] 0xa5a5a5a5a5a5a5a5 [4] [C7x_1 ] 105.162792 s: 0xa5a5a5a5a5a5a5a5 [5] 0xa5a5a5a5a5a5a5a5 [5] [C7x_1 ] 105.162849 s: 0xa5a5a5a5a5a5a5a5 [6] 0xa5a5a5a5a5a5a5a5 [6] [C7x_1 ] 105.162906 s: 0xa5a5a5a5a5a5a5a5 [7] 0xa5a5a5a5a5a5a5a5 [7] [C7x_1 ] 105.162928 s: [C7x_1 ] 105.162976 s: CUCR0=0x9277893731f5952f [0] CUCR1=0x21a4b67e101226cd [0] [C7x_1 ] 105.163036 s: 0x230c88a441adc315 [1] 0x51ef1069ad00021e [1] [C7x_1 ] 105.163093 s: 0xc3d9ae2ea0f0a4d5 [2] 0x3376b6fa6a58d8ac [2] [C7x_1 ] 105.163139 s: 0x0000000000000002 [3] 0x000000007908da04 [3] [C7x_1 ] 105.163188 s: 0x1644d644712d3474 [4] 0x0000000000000000 [4] [C7x_1 ] 105.163247 s: 0xd92bed5f300975a0 [5] 0x6d654d7876697400 [5] [C7x_1 ] 105.163306 s: 0xf916465a42245308 [6] 0x614d726566667542 [6] [C7x_1 ] 105.163349 s: 0x000000000000000b [7] 0x0000000080700e85 [7] [C7x_1 ] 105.163372 s: [C7x_1 ] 105.163420 s: CUCR2=0x4edd005c74979bfb [0] CUCR3=0x08adb230e6d08afa [0] [C7x_1 ] 105.163478 s: 0x7e1a4519240280ce [1] 0x9b36a5b067b01314 [1] [C7x_1 ] 105.163535 s: 0xa9d2f01515b97314 [2] 0x680ae0c1f92284d7 [2] [C7x_1 ] 105.163578 s: 0x0000000000000647 [3] 0x000000000000099f [3] [C7x_1 ] 105.163637 s: 0x6645bf087750d280 [4] 0x3b379a7ac8148d60 [4] [C7x_1 ] 105.163697 s: 0xfd6dbfc21b0ab818 [5] 0xb8850800074e0a25 [5] [C7x_1 ] 105.163755 s: 0xf7f26b86b44406f0 [6] 0x2e739d1bb193b1f5 [6] [C7x_1 ] 105.163796 s: 0x000000000000099e [7] 0x00000000000009a0 [7] [C7x_1 ] 105.163818 s: [C7x_1 ] 105.163851 s: SE0_0=0x0000000000000000 [0] SE0_1=0x00000000b5382c80 [0] [C7x_1 ] 105.163896 s: 0x0000000000000000 [1] 0x00000000b5382c80 [1] [C7x_1 ] 105.163936 s: 0x0000000000000000 [2] 0x0000000000000000 [2] [C7x_1 ] 105.163978 s: 0x00000000b5382c80 [3] 0x0000000000000000 [3] [C7x_1 ] 105.164020 s: 0x00000000b5382c80 [4] 0x0000000000000000 [4] [C7x_1 ] 105.164063 s: 0x00000000b5382c80 [5] 0x0000000000000000 [5] [C7x_1 ] 105.164110 s: 0x00000000b5382c80 [6] 0x0000050000000500 [6] [C7x_1 ] 105.164158 s: 0x00000000b5382c80 [7] 0x0000050000000500 [7] [C7x_1 ] 105.164181 s: [C7x_1 ] 105.164211 s: SE0_2=0x0000000000000000 [0] SE0_3=0x0000000000000000 [0] [C7x_1 ] 105.164250 s: 0x0000000000000000 [1] 0x0000000000000000 [1] [C7x_1 ] 105.164289 s: 0x0000000000000000 [2] 0x0000000000000000 [2] [C7x_1 ] 105.164328 s: 0x0000000000000500 [3] 0x0000000000000000 [3] [C7x_1 ] 105.164368 s: 0x0000000000000000 [4] 0x0000000000000000 [4] [C7x_1 ] 105.164408 s: 0x0000000000000000 [5] 0x0000000000000000 [5] [C7x_1 ] 105.164449 s: 0x0000000000000000 [6] 0x0000000000000000 [6] [C7x_1 ] 105.164490 s: 0x0000000000000000 [7] 0x0000000000000000 [7] [C7x_1 ] 105.164512 s: [C7x_1 ] 105.164541 s: SE1_0=0x0000000000000000 [0] SE1_1=0x0000000000000000 [0] [C7x_1 ] 105.164583 s: 0x0000000000000000 [1] 0x0000000000000000 [1] [C7x_1 ] 105.164622 s: 0x0000000000000000 [2] 0x0000000000000000 [2] [C7x_1 ] 105.164663 s: 0x0000000000000000 [3] 0x0000000000000000 [3] [C7x_1 ] 105.164702 s: 0x0000000000000000 [4] 0x0000000000000000 [4] [C7x_1 ] 105.164742 s: 0x0000000000000000 [5] 0x0000000000000000 [5] [C7x_1 ] 105.164783 s: 0x0000000000000000 [6] 0x0000000000000000 [6] [C7x_1 ] 105.164824 s: 0x0000000000000000 [7] 0x0000000000000000 [7] [C7x_1 ] 105.164847 s: [C7x_1 ] 105.164884 s: SE1_2=0x0000000000000000 [0] SE1_3=0x0219f0f2ac64be00 [0] [C7x_1 ] 105.164935 s: 0x0000000000000000 [1] 0x830820466c02283e [1] [C7x_1 ] 105.164984 s: 0x0000000000000000 [2] 0xea01d44f436108ec [2] [C7x_1 ] 105.165026 s: 0x0000000000000000 [3] 0x0000000000000808 [3] [C7x_1 ] 105.165083 s: 0x3254601ea14862d7 [4] 0xcbc4481c93ee191a [4] [C7x_1 ] 105.165140 s: 0x16cca7f303be03e0 [5] 0x01efed72112caae5 [5] [C7x_1 ] 105.165197 s: 0x886a01cad808b578 [6] 0x344061020db47186 [6] [C7x_1 ] 105.165251 s: 0x000fffffffffffff [7] 0x4004000000000000 [7] [C7x_1 ] 105.165276 s: [C7x_1 ] 105.165315 s: SA0CR=0xc3595cfe28872185 [0] SA1CR=0x0000000000000000 [0] [C7x_1 ] 105.165365 s: 0x893c2c4211190f59 [1] 0x0000000000000000 [1] [C7x_1 ] 105.165414 s: 0x18c48601820e1d90 [2] 0x0000000000000000 [2] [C7x_1 ] 105.165467 s: 0x3b164a444547b16d [3] 0x0000000024924925 [3] [C7x_1 ] 105.165524 s: 0x4c5695f3088a2036 [4] 0x190c60ee9401490b [4] [C7x_1 ] 105.165580 s: 0xdeaa1662f8d470e2 [5] 0x18350210b9808dc0 [5] [C7x_1 ] 105.165637 s: 0x05815359a9d91b51 [6] 0x0a3b240376160d23 [6] [C7x_1 ] 105.165688 s: 0x0000000000000004 [7] 0x56a3a002bebf183b [7] [C7x_1 ] 105.165710 s: [C7x_1 ] 105.165750 s: SA2CR=0x0000000000000000 [0] SA3CR=0x86160600649f342a [0] [C7x_1 ] 105.165800 s: 0x0000000000000000 [1] 0x02c0f10c1df3ace7 [1] [C7x_1 ] 105.165850 s: 0x0000000000000000 [2] 0x2e409748c2923271 [2] [C7x_1 ] 105.165891 s: 0x000000000000199c [3] 0x000000000000003c [3] [C7x_1 ] 105.165940 s: 0x0000000000000040 [4] 0x474ee8e00968fce5 [4] [C7x_1 ] 105.165989 s: 0x0000000000000040 [5] 0xda05454ab4011045 [5] [C7x_1 ] 105.166038 s: 0x0000000000000040 [6] 0x4070c84c1680f605 [6] [C7x_1 ] 105.166078 s: 0x0000000000000000 [7] 0x0000000000000006 [7] [C7x_1 ] 105.166101 s: [C7x_1 ] 105.166135 s: SA0CNTR0=0x00000000a106c800 [0] SA1CNTR0=0x0000000000000000 [0] [C7x_1 ] 105.166177 s: 0x0000000000000000 [1] 0x0000000000000000 [1] [C7x_1 ] 105.166217 s: 0x0000000000000000 [2] 0x0000000000000000 [2] [C7x_1 ] 105.166262 s: 0x0000000000000000 [3] 0x00000000b524dec0 [3] [C7x_1 ] 105.166319 s: 0x030848a2872d12fb [4] 0xd888822124230094 [4] [C7x_1 ] 105.166377 s: 0x1063a66b19206a39 [5] 0xca8a580108a9c8e5 [5] [C7x_1 ] 105.166434 s: 0x450b78b1d254d796 [6] 0x15f7db9b1c8a6968 [6] [C7x_1 ] 105.166475 s: 0x0000000000000645 [7] 0x0000000000000000 [7] [C7x_1 ] 105.166498 s: [C7x_1 ] 105.166540 s: SA2CNTR0=0x0000000042800000 [0] SA3CNTR0=0x0280df2a36402de0 [0] [C7x_1 ] 105.166596 s: 0x0000000042800000 [1] 0xd441024d329208c1 [1] [C7x_1 ] 105.166648 s: 0x0000000042800000 [2] 0x9d065080a884178f [2] [C7x_1 ] 105.166690 s: 0x0000000000000000 [3] 0x0000000000006200 [3] [C7x_1 ] 105.166740 s: 0x0000000000000000 [4] 0x114526b40f504011 [4] [C7x_1 ] 105.166790 s: 0x0000000000000000 [5] 0xb1652b8a0111c488 [5] [C7x_1 ] 105.166839 s: 0x0000000000000000 [6] 0x8b2b262fa6c588c4 [6] [C7x_1 ] 105.166880 s: 0x000000000000000a [7] 0x0000000000000000 [7] [C7x_1 ] 105.166902 s: [C7x_1 ] 105.166930 s: Exception at 0x000000009a145dec [C7x_1 ] 105.166964 s: TSR at time of exception: 0x000000000200ff03 [C7x_1 ] 105.166987 s: Page fault: [C7x_1 ] 105.167012 s: IERR=0x0000000000000001 [C7x_1 ] 105.167045 s: IEAR=0xffffffea1fed610c [C7x_1 ] 105.167068 s: IESR=0x0000000000010844 [C7x_1 ] 105.167091 s: Page fault exception: [C7x_1 ] 105.167123 s: .D1 or .D2 uTLB lookup fault, Non-speculative load [C7x_1 ] 105.167154 s: utlb_rstatus=0x844