/dts-v1/;
// magic:		0xd00dfeed
// totalsize:		0x17e9b (97947)
// off_dt_struct:	0x38
// off_dt_strings:	0x16368
// off_mem_rsvmap:	0x28
// version:		17
// last_comp_version:	16
// boot_cpuid_phys:	0x0
// size_dt_strings:	0xb33
// size_dt_struct:	0x16330

/ {
    #address-cells = <0x00000001>;
    #size-cells = <0x00000001>;
    compatible = <0x74692c64 0x72613732 0x2d65766d 0x0074692c 0x64726137 0x32320074 0x692c6472 0x61373200 0x74692c64 0x72613700>;
    interrupt-parent = <0x00000001>;
    model = "TI DRA722";
    chosen {
    };
    aliases {
        i2c0 = "/ocp/i2c@48070000";
        i2c1 = "/ocp/i2c@48072000";
        i2c2 = "/ocp/i2c@48060000";
        i2c3 = "/ocp/i2c@4807a000";
        i2c4 = "/ocp/i2c@4807c000";
        serial0 = "/ocp/serial@4806a000";
        serial1 = "/ocp/serial@4806c000";
        serial2 = "/ocp/serial@48020000";
        serial3 = "/ocp/serial@4806e000";
        serial4 = "/ocp/serial@48066000";
        serial5 = "/ocp/serial@48068000";
        serial6 = "/ocp/serial@48420000";
        serial7 = "/ocp/serial@48422000";
        serial8 = "/ocp/serial@48424000";
        serial9 = "/ocp/serial@4ae2b000";
        ethernet0 = "/ocp/ethernet@48484000/slave@48480200";
        ethernet1 = "/ocp/ethernet@48484000/slave@48480300";
        d_can0 = "/ocp/can@481cc000";
        d_can1 = "/ocp/can@481d0000";
        rproc0 = "/ocp/ipu@58820000";
        rproc1 = "/ocp/ipu@55020000";
        rproc2 = "/ocp/dsp@40800000";
        display0 = "/connector@0";
        display1 = "/ocp/i2c@4807c000/serializer@0D/tlc59108@40";
        i2c11 = "/ocp/i2c@4807c000/deserializer@60";
        i2c12 = "/ocp/i2c@4807c000/deserializer@64";
        i2c13 = "/ocp/i2c@4807c000/deserializer@68";
        i2c14 = "/ocp/i2c@4807c000/deserializer@6c";
    };
    memory {
        device_type = "memory";
        reg = <0x80000000 0x40000000>;
    };
    timer {
        compatible = "arm,armv7-timer";
        interrupts = <0x00000001 0x0000000d 0x00000308 0x00000001 0x0000000e 0x00000308 0x00000001 0x0000000b 0x00000308 0x00000001 0x0000000a 0x00000308>;
    };
    interrupt-controller@48211000 {
        compatible = "arm,cortex-a15-gic";
        interrupt-controller;
        #interrupt-cells = <0x00000003>;
        arm,routable-irqs = <0x000000c0>;
        reg = <0x48211000 0x00001000 0x48212000 0x00001000 0x48214000 0x00002000 0x48216000 0x00002000>;
        interrupts = <0x00000001 0x00000009 0x00000304>;
        linux,phandle = <0x00000001>;
        phandle = <0x00000001>;
    };
    soc {
        compatible = "ti,omap-infra";
        mpu {
            compatible = "ti,omap5-mpu";
            ti,hwmods = "mpu";
        };
    };
    ocp {
        compatible = [74 69 2c 64 72 61 37 2d 6c 33 2d 6e 6f 63 00 73 69 6d 70 6c 65 2d 62 75 73 00];
        #address-cells = <0x00000001>;
        #size-cells = <0x00000001>;
        ranges;
        ti,hwmods = <0x6c335f6d 0x61696e5f 0x31006c33 0x5f6d6169 0x6e5f3200>;
        reg = <0x44000000 0x01000000 0x45000000 0x00001000>;
        interrupts = <0x00000000 0x00000004 0x00000004 0x00000000 0x0000019a 0x00000004>;
        prm@4ae06000 {
            compatible = "ti,dra7-prm";
            reg = <0x4ae06000 0x00003000>;
            interrupts = <0x00000000 0x00000006 0x00000004>;
            clocks {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                sys_clkin1 {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000002 0x00000003 0x00000004 0x00000005 0x00000006 0x00000007 0x00000008>;
                    reg = <0x00000110>;
                    ti,index-starts-at-one;
                    linux,phandle = <0x00000009>;
                    phandle = <0x00000009>;
                };
                abe_dpll_sys_clk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000009 0x0000000a>;
                    reg = <0x00000118>;
                    linux,phandle = <0x0000000b>;
                    phandle = <0x0000000b>;
                };
                abe_dpll_bypass_clk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000000b 0x0000000c>;
                    reg = <0x00000114>;
                    linux,phandle = <0x00000046>;
                    phandle = <0x00000046>;
                };
                abe_dpll_clk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000000b 0x0000000c>;
                    reg = <0x0000010c>;
                    linux,phandle = <0x00000045>;
                    phandle = <0x00000045>;
                };
                abe_24m_fclk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000000d>;
                    reg = <0x0000011c>;
                    ti,dividers = <0x00000008 0x00000010>;
                    linux,phandle = <0x00000073>;
                    phandle = <0x00000073>;
                };
                aess_fclk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000000e>;
                    reg = <0x00000178>;
                    ti,max-div = <0x00000002>;
                    linux,phandle = <0x0000000f>;
                    phandle = <0x0000000f>;
                };
                abe_giclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000000f>;
                    reg = <0x00000174>;
                    ti,max-div = <0x00000002>;
                    linux,phandle = <0x0000003a>;
                    phandle = <0x0000003a>;
                };
                abe_lp_clk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000000d>;
                    reg = <0x000001d8>;
                    ti,dividers = <0x00000010 0x00000020>;
                    linux,phandle = <0x00000034>;
                    phandle = <0x00000034>;
                };
                abe_sys_clk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000009>;
                    reg = <0x00000120>;
                    ti,max-div = <0x00000002>;
                    linux,phandle = <0x00000074>;
                    phandle = <0x00000074>;
                };
                adc_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000009 0x0000000a 0x0000000c>;
                    reg = <0x000001dc>;
                };
                sys_clk1_dclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000009>;
                    ti,max-div = <0x00000040>;
                    reg = <0x000001c8>;
                    ti,index-power-of-two;
                    linux,phandle = <0x0000001a>;
                    phandle = <0x0000001a>;
                };
                sys_clk2_dclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000000a>;
                    ti,max-div = <0x00000040>;
                    reg = <0x000001cc>;
                    ti,index-power-of-two;
                    linux,phandle = <0x0000001b>;
                    phandle = <0x0000001b>;
                };
                per_abe_x1_dclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000010>;
                    ti,max-div = <0x00000040>;
                    reg = <0x000001bc>;
                    ti,index-power-of-two;
                    linux,phandle = <0x0000001c>;
                    phandle = <0x0000001c>;
                };
                dsp_gclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000011>;
                    ti,max-div = <0x00000040>;
                    reg = <0x0000018c>;
                    ti,index-power-of-two;
                    linux,phandle = <0x0000001e>;
                    phandle = <0x0000001e>;
                };
                gpu_dclk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000012>;
                    ti,max-div = <0x00000040>;
                    reg = <0x000001a0>;
                    ti,index-power-of-two;
                    linux,phandle = <0x00000020>;
                    phandle = <0x00000020>;
                };
                emif_phy_dclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000013>;
                    ti,max-div = <0x00000040>;
                    reg = <0x00000190>;
                    ti,index-power-of-two;
                    linux,phandle = <0x00000022>;
                    phandle = <0x00000022>;
                };
                gmac_250m_dclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000014>;
                    ti,max-div = <0x00000040>;
                    reg = <0x0000019c>;
                    ti,index-power-of-two;
                    linux,phandle = <0x00000023>;
                    phandle = <0x00000023>;
                };
                l3init_480m_dclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000015>;
                    ti,max-div = <0x00000040>;
                    reg = <0x000001ac>;
                    ti,index-power-of-two;
                    linux,phandle = <0x00000028>;
                    phandle = <0x00000028>;
                };
                usb_otg_dclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000016>;
                    ti,max-div = <0x00000040>;
                    reg = <0x00000184>;
                    ti,index-power-of-two;
                    linux,phandle = <0x00000029>;
                    phandle = <0x00000029>;
                };
                sata_dclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000009>;
                    ti,max-div = <0x00000040>;
                    reg = <0x000001c0>;
                    ti,index-power-of-two;
                    linux,phandle = <0x0000002a>;
                    phandle = <0x0000002a>;
                };
                pcie2_dclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000017>;
                    ti,max-div = <0x00000040>;
                    reg = <0x000001b8>;
                    ti,index-power-of-two;
                    linux,phandle = <0x0000002b>;
                    phandle = <0x0000002b>;
                };
                pcie_dclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000018>;
                    ti,max-div = <0x00000040>;
                    reg = <0x000001b4>;
                    ti,index-power-of-two;
                    linux,phandle = <0x0000002c>;
                    phandle = <0x0000002c>;
                };
                emu_dclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000009>;
                    ti,max-div = <0x00000040>;
                    reg = <0x00000194>;
                    ti,index-power-of-two;
                    linux,phandle = <0x0000002d>;
                    phandle = <0x0000002d>;
                };
                secure_32k_dclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000019>;
                    ti,max-div = <0x00000040>;
                    reg = <0x000001c4>;
                    ti,index-power-of-two;
                    linux,phandle = <0x0000002e>;
                    phandle = <0x0000002e>;
                };
                clkoutmux0_clk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000001a 0x0000001b 0x0000001c 0x0000001d 0x0000001e 0x0000001f 0x00000020 0x00000021 0x00000022 0x00000023 0x00000024 0x00000025 0x00000026 0x00000027 0x00000028 0x00000029 0x0000002a 0x0000002b 0x0000002c 0x0000002d 0x0000002e 0x0000002f>;
                    reg = <0x00000158>;
                    linux,phandle = <0x00000080>;
                    phandle = <0x00000080>;
                };
                clkoutmux1_clk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000001a 0x0000001b 0x0000001c 0x0000001d 0x0000001e 0x0000001f 0x00000020 0x00000021 0x00000022 0x00000023 0x00000024 0x00000025 0x00000026 0x00000027 0x00000028 0x00000029 0x0000002a 0x0000002b 0x0000002c 0x0000002d 0x0000002e 0x0000002f>;
                    reg = <0x0000015c>;
                };
                clkoutmux2_clk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000001a 0x0000001b 0x0000001c 0x0000001d 0x0000001e 0x0000001f 0x00000020 0x00000021 0x00000022 0x00000023 0x00000024 0x00000025 0x00000026 0x00000027 0x00000028 0x00000029 0x0000002a 0x0000002b 0x0000002c 0x0000002d 0x0000002e 0x0000002f>;
                    reg = <0x00000160>;
                    linux,phandle = <0x00000092>;
                    phandle = <0x00000092>;
                };
                custefuse_sys_gfclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x00000009>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000002>;
                };
                eve_clk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000030 0x00000031>;
                    reg = <0x00000180>;
                };
                hdmi_dpll_clk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000009 0x0000000a>;
                    reg = <0x00000164>;
                    linux,phandle = <0x00000095>;
                    phandle = <0x00000095>;
                };
                mlb_clk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000032>;
                    ti,max-div = <0x00000040>;
                    reg = <0x00000134>;
                    ti,index-power-of-two;
                    linux,phandle = <0x0000007a>;
                    phandle = <0x0000007a>;
                };
                mlbp_clk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000033>;
                    ti,max-div = <0x00000040>;
                    reg = <0x00000130>;
                    ti,index-power-of-two;
                    linux,phandle = <0x0000007b>;
                    phandle = <0x0000007b>;
                };
                per_abe_x1_gfclk2_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000010>;
                    ti,max-div = <0x00000040>;
                    reg = <0x00000138>;
                    ti,index-power-of-two;
                    linux,phandle = <0x0000007c>;
                    phandle = <0x0000007c>;
                };
                timer_sys_clk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000009>;
                    reg = <0x00000144>;
                    ti,max-div = <0x00000002>;
                    linux,phandle = <0x00000035>;
                    phandle = <0x00000035>;
                };
                video1_dpll_clk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000009 0x0000000a>;
                    reg = <0x00000168>;
                    linux,phandle = <0x00000096>;
                    phandle = <0x00000096>;
                };
                video2_dpll_clk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000009 0x0000000a>;
                    reg = <0x0000016c>;
                    linux,phandle = <0x00000097>;
                    phandle = <0x00000097>;
                };
                wkupaon_iclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000009 0x00000034>;
                    reg = <0x00000108>;
                    linux,phandle = <0x0000009c>;
                    phandle = <0x0000009c>;
                };
                gpio1_dbclk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x0000000c>;
                    ti,bit-shift = <0x00000008>;
                    reg = <0x00001838>;
                };
                dcan1_sys_clk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000009 0x0000000a>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001888>;
                    linux,phandle = <0x00000108>;
                    phandle = <0x00000108>;
                };
                timer1_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000035 0x0000000c 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001840>;
                };
                uart10_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000003e 0x0000003f>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001880>;
                };
            };
            clockdomains {
            };
        };
        axi@0 {
            compatible = "simple-bus";
            #size-cells = <0x00000001>;
            #address-cells = <0x00000001>;
            ranges = <0x51000000 0x51000000 0x00003000 0x00000000 0x20000000 0x10000000>;
            pcie@51000000 {
                compatible = "ti,dra7-pcie";
                reg = <0x51000000 0x00002000 0x51002000 0x0000014c 0x00001000 0x00002000>;
                reg-names = <0x72635f64 0x62696373 0x0074695f 0x636f6e66 0x00636f6e 0x66696700>;
                interrupts = <0x00000000 0x000000e8 0x00000004 0x00000000 0x000000e9 0x00000004>;
                #address-cells = <0x00000003>;
                #size-cells = <0x00000002>;
                device_type = "pci";
                ranges = <0x81000000 0x00000000 0x00000000 0x00003000 0x00000000 0x00010000 0x82000000 0x00000000 0x20013000 0x00013000 0x00000000 0x0ffed000>;
                #interrupt-cells = <0x00000001>;
                num-lanes = <0x00000001>;
                ti,hwmods = "pcie1";
                phys = <0x00000040>;
                phy-names = "pcie-phy0";
                interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>;
                interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x00000041 0x00000001 0x00000000 0x00000000 0x00000000 0x00000002 0x00000041 0x00000002 0x00000000 0x00000000 0x00000000 0x00000003 0x00000041 0x00000003 0x00000000 0x00000000 0x00000000 0x00000004 0x00000041 0x00000004>;
                interrupt-controller {
                    interrupt-controller;
                    #address-cells = <0x00000000>;
                    #interrupt-cells = <0x00000001>;
                    linux,phandle = <0x00000041>;
                    phandle = <0x00000041>;
                };
            };
        };
        axi@1 {
            compatible = "simple-bus";
            #size-cells = <0x00000001>;
            #address-cells = <0x00000001>;
            ranges = <0x51800000 0x51800000 0x00003000 0x00000000 0x30000000 0x10000000>;
            status = "disabled";
            pcie@51000000 {
                compatible = "ti,dra7-pcie";
                reg = <0x51800000 0x00002000 0x51802000 0x0000014c 0x00001000 0x00002000>;
                reg-names = <0x72635f64 0x62696373 0x0074695f 0x636f6e66 0x00636f6e 0x66696700>;
                interrupts = <0x00000000 0x00000163 0x00000004 0x00000000 0x00000164 0x00000004>;
                #address-cells = <0x00000003>;
                #size-cells = <0x00000002>;
                device_type = "pci";
                ranges = <0x81000000 0x00000000 0x00000000 0x00003000 0x00000000 0x00010000 0x82000000 0x00000000 0x30013000 0x00013000 0x00000000 0x0ffed000>;
                #interrupt-cells = <0x00000001>;
                num-lanes = <0x00000001>;
                ti,hwmods = "pcie2";
                phys = <0x00000042>;
                phy-names = "pcie-phy0";
                interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>;
                interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x00000043 0x00000001 0x00000000 0x00000000 0x00000000 0x00000002 0x00000043 0x00000002 0x00000000 0x00000000 0x00000000 0x00000003 0x00000043 0x00000003 0x00000000 0x00000000 0x00000000 0x00000004 0x00000043 0x00000004>;
                interrupt-controller {
                    interrupt-controller;
                    #address-cells = <0x00000000>;
                    #interrupt-cells = <0x00000001>;
                    linux,phandle = <0x00000043>;
                    phandle = <0x00000043>;
                };
            };
        };
        bandgap@4a0021e0 {
            reg = <0x4a0021e0 0x0000000c 0x4a00232c 0x0000000c 0x4a002380 0x0000002c 0x4a0023c0 0x0000003c 0x4a002564 0x00000008 0x4a002574 0x00000050>;
            compatible = "ti,dra752-bandgap";
            interrupts = <0x00000000 0x00000079 0x00000004>;
            #thermal-sensor-cells = <0x00000001>;
            linux,phandle = <0x0000011b>;
            phandle = <0x0000011b>;
        };
        cm_core_aon@4a005000 {
            compatible = "ti,dra7-cm-core-aon";
            reg = <0x4a005000 0x00002000>;
            clocks {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                atl_clkin0_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,dra7-atl-clock";
                    clocks = <0x00000044>;
                    linux,phandle = <0x00000079>;
                    phandle = <0x00000079>;
                };
                atl_clkin1_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,dra7-atl-clock";
                    clocks = <0x00000044>;
                    linux,phandle = <0x00000078>;
                    phandle = <0x00000078>;
                };
                atl_clkin2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,dra7-atl-clock";
                    clocks = <0x00000044>;
                    linux,phandle = <0x00000077>;
                    phandle = <0x00000077>;
                };
                atl_clkin3_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,dra7-atl-clock";
                    clocks = <0x00000044>;
                    linux,phandle = <0x00000076>;
                    phandle = <0x00000076>;
                };
                hdmi_clkin_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x00000000>;
                    linux,phandle = <0x00000066>;
                    phandle = <0x00000066>;
                };
                mlb_clkin_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x00000000>;
                    linux,phandle = <0x00000032>;
                    phandle = <0x00000032>;
                };
                mlbp_clkin_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x00000000>;
                    linux,phandle = <0x00000033>;
                    phandle = <0x00000033>;
                };
                pciesref_acs_clk_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x05f5e100>;
                    linux,phandle = <0x00000084>;
                    phandle = <0x00000084>;
                };
                ref_clkin0_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x00000000>;
                    linux,phandle = <0x00000036>;
                    phandle = <0x00000036>;
                };
                ref_clkin1_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x00000000>;
                    linux,phandle = <0x00000037>;
                    phandle = <0x00000037>;
                };
                ref_clkin2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x00000000>;
                    linux,phandle = <0x00000038>;
                    phandle = <0x00000038>;
                };
                ref_clkin3_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x00000000>;
                    linux,phandle = <0x00000039>;
                    phandle = <0x00000039>;
                };
                rmii_clk_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x00000000>;
                };
                sdvenc_clkin_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x00000000>;
                };
                secure_32k_clk_src_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x00008000>;
                    linux,phandle = <0x00000019>;
                    phandle = <0x00000019>;
                };
                sys_clk32_crystal_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x00008000>;
                    linux,phandle = <0x000000a6>;
                    phandle = <0x000000a6>;
                };
                sys_clk32_pseudo_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x00000009>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000262>;
                    linux,phandle = <0x000000a7>;
                    phandle = <0x000000a7>;
                };
                virt_12000000_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x00b71b00>;
                    linux,phandle = <0x00000002>;
                    phandle = <0x00000002>;
                };
                virt_13000000_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x00c65d40>;
                };
                virt_16800000_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x01005900>;
                    linux,phandle = <0x00000004>;
                    phandle = <0x00000004>;
                };
                virt_19200000_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x0124f800>;
                    linux,phandle = <0x00000005>;
                    phandle = <0x00000005>;
                };
                virt_20000000_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x01312d00>;
                    linux,phandle = <0x00000003>;
                    phandle = <0x00000003>;
                };
                virt_26000000_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x018cba80>;
                    linux,phandle = <0x00000006>;
                    phandle = <0x00000006>;
                };
                virt_27000000_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x019bfcc0>;
                    linux,phandle = <0x00000007>;
                    phandle = <0x00000007>;
                };
                virt_38400000_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x0249f000>;
                    linux,phandle = <0x00000008>;
                    phandle = <0x00000008>;
                };
                sys_clkin2 {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x01588800>;
                    linux,phandle = <0x0000000a>;
                    phandle = <0x0000000a>;
                };
                usb_otg_clkin_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x00000000>;
                    linux,phandle = <0x00000016>;
                    phandle = <0x00000016>;
                };
                video1_clkin_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x00000000>;
                    linux,phandle = <0x00000070>;
                    phandle = <0x00000070>;
                };
                video1_m2_clkin_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x00000000>;
                    linux,phandle = <0x00000065>;
                    phandle = <0x00000065>;
                };
                video2_clkin_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x00000000>;
                    linux,phandle = <0x00000071>;
                    phandle = <0x00000071>;
                };
                video2_m2_clkin_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x00000000>;
                    linux,phandle = <0x00000064>;
                    phandle = <0x00000064>;
                };
                dpll_abe_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,omap4-dpll-m4xen-clock";
                    clocks = <0x00000045 0x00000046>;
                    reg = <0x000001e0 0x000001e4 0x000001ec 0x000001e8>;
                    ti,sink-clkdm = <0x00000047>;
                    linux,phandle = <0x00000048>;
                    phandle = <0x00000048>;
                };
                dpll_abe_x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,omap4-dpll-x2-clock";
                    clocks = <0x00000048>;
                    linux,phandle = <0x00000049>;
                    phandle = <0x00000049>;
                };
                dpll_abe_m2x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000049>;
                    ti,max-div = <0x0000001f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x000001f0>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    linux,phandle = <0x0000000d>;
                    phandle = <0x0000000d>;
                };
                abe_clk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000000d>;
                    ti,max-div = <0x00000004>;
                    reg = <0x00000108>;
                    ti,index-power-of-two;
                    linux,phandle = <0x0000000e>;
                    phandle = <0x0000000e>;
                };
                dpll_abe_m2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000048>;
                    ti,max-div = <0x0000001f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x000001f0>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    linux,phandle = <0x00000010>;
                    phandle = <0x00000010>;
                };
                dpll_abe_m3x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000049>;
                    ti,max-div = <0x0000001f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x000001f4>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    linux,phandle = <0x0000004a>;
                    phandle = <0x0000004a>;
                };
                dpll_core_byp_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000009 0x0000004a>;
                    ti,bit-shift = <0x00000017>;
                    reg = <0x0000012c>;
                    linux,phandle = <0x0000004b>;
                    phandle = <0x0000004b>;
                };
                dpll_core_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,omap4-dpll-core-clock";
                    clocks = <0x00000009 0x0000004b>;
                    reg = <0x00000120 0x00000124 0x0000012c 0x00000128>;
                    linux,phandle = <0x0000004c>;
                    phandle = <0x0000004c>;
                };
                dpll_core_x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,omap4-dpll-x2-clock";
                    clocks = <0x0000004c>;
                    linux,phandle = <0x0000004d>;
                    phandle = <0x0000004d>;
                };
                dpll_core_h12x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000004d>;
                    ti,max-div = <0x0000003f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x0000013c>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    linux,phandle = <0x0000004e>;
                    phandle = <0x0000004e>;
                };
                mpu_dpll_hs_clk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x0000004e>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000001>;
                    linux,phandle = <0x0000004f>;
                    phandle = <0x0000004f>;
                };
                dpll_mpu_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,omap5-mpu-dpll-clock";
                    clocks = <0x00000009 0x0000004f>;
                    reg = <0x00000160 0x00000164 0x0000016c 0x00000168>;
                    linux,phandle = <0x00000050>;
                    phandle = <0x00000050>;
                };
                dpll_mpu_m2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000050>;
                    ti,max-div = <0x0000001f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x00000170>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    linux,phandle = <0x00000051>;
                    phandle = <0x00000051>;
                };
                mpu_dclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x00000051>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000001>;
                    linux,phandle = <0x0000001d>;
                    phandle = <0x0000001d>;
                };
                dsp_dpll_hs_clk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x0000004e>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000001>;
                    linux,phandle = <0x00000052>;
                    phandle = <0x00000052>;
                };
                dpll_dsp_byp_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000009 0x00000052>;
                    ti,bit-shift = <0x00000017>;
                    reg = <0x00000240>;
                    linux,phandle = <0x00000053>;
                    phandle = <0x00000053>;
                };
                dpll_dsp_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,omap4-dpll-clock";
                    clocks = <0x00000009 0x00000053>;
                    reg = <0x00000234 0x00000238 0x00000240 0x0000023c>;
                    ti,sink-clkdm = <0x00000054>;
                    linux,phandle = <0x00000055>;
                    phandle = <0x00000055>;
                };
                dpll_dsp_m2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000055>;
                    ti,max-div = <0x0000001f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x00000244>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    ti,set-rate-parent;
                    linux,phandle = <0x00000011>;
                    phandle = <0x00000011>;
                };
                iva_dpll_hs_clk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x0000004e>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000001>;
                    linux,phandle = <0x00000056>;
                    phandle = <0x00000056>;
                };
                dpll_iva_byp_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000009 0x00000056>;
                    ti,bit-shift = <0x00000017>;
                    reg = <0x000001ac>;
                    linux,phandle = <0x00000057>;
                    phandle = <0x00000057>;
                };
                dpll_iva_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,omap4-dpll-clock";
                    clocks = <0x00000009 0x00000057>;
                    reg = <0x000001a0 0x000001a4 0x000001ac 0x000001a8>;
                    ti,sink-clkdm = <0x00000058>;
                    linux,phandle = <0x00000059>;
                    phandle = <0x00000059>;
                };
                dpll_iva_m2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000059>;
                    ti,max-div = <0x0000001f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x000001b0>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    ti,set-rate-parent;
                    linux,phandle = <0x0000005a>;
                    phandle = <0x0000005a>;
                };
                iva_dclk {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x0000005a>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000001>;
                    linux,phandle = <0x0000001f>;
                    phandle = <0x0000001f>;
                };
                dpll_gpu_byp_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000009 0x0000004a>;
                    ti,bit-shift = <0x00000017>;
                    reg = <0x000002e4>;
                    linux,phandle = <0x0000005b>;
                    phandle = <0x0000005b>;
                };
                dpll_gpu_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,omap4-dpll-clock";
                    clocks = <0x00000009 0x0000005b>;
                    reg = <0x000002d8 0x000002dc 0x000002e4 0x000002e0>;
                    ti,sink-clkdm = <0x0000005c>;
                    linux,phandle = <0x0000005d>;
                    phandle = <0x0000005d>;
                };
                dpll_gpu_m2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000005d>;
                    ti,max-div = <0x0000001f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x000002e8>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    ti,set-rate-parent;
                    linux,phandle = <0x00000012>;
                    phandle = <0x00000012>;
                };
                dpll_core_m2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000004c>;
                    ti,max-div = <0x0000001f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x00000130>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    ti,set-rate-parent;
                    linux,phandle = <0x0000005e>;
                    phandle = <0x0000005e>;
                };
                core_dpll_out_dclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x0000005e>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000001>;
                    linux,phandle = <0x00000021>;
                    phandle = <0x00000021>;
                };
                dpll_ddr_byp_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000009 0x0000004a>;
                    ti,bit-shift = <0x00000017>;
                    reg = <0x0000021c>;
                    linux,phandle = <0x0000005f>;
                    phandle = <0x0000005f>;
                };
                dpll_ddr_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,omap4-dpll-clock";
                    clocks = <0x00000009 0x0000005f>;
                    reg = <0x00000210 0x00000214 0x0000021c 0x00000218>;
                    linux,phandle = <0x00000060>;
                    phandle = <0x00000060>;
                };
                dpll_ddr_m2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000060>;
                    ti,max-div = <0x0000001f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x00000220>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    ti,set-rate-parent;
                    linux,phandle = <0x00000013>;
                    phandle = <0x00000013>;
                };
                dpll_gmac_byp_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000009 0x0000004a>;
                    ti,bit-shift = <0x00000017>;
                    reg = <0x000002b4>;
                    linux,phandle = <0x00000061>;
                    phandle = <0x00000061>;
                };
                dpll_gmac_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,omap4-dpll-clock";
                    clocks = <0x00000009 0x00000061>;
                    reg = <0x000002a8 0x000002ac 0x000002b4 0x000002b0>;
                    ti,sink-clkdm = <0x00000062>;
                    linux,phandle = <0x00000063>;
                    phandle = <0x00000063>;
                };
                dpll_gmac_m2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000063>;
                    ti,max-div = <0x0000001f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x000002b8>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    ti,set-rate-parent;
                    linux,phandle = <0x00000014>;
                    phandle = <0x00000014>;
                };
                video2_dclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x00000064>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000001>;
                    linux,phandle = <0x00000024>;
                    phandle = <0x00000024>;
                };
                video1_dclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x00000065>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000001>;
                    linux,phandle = <0x00000025>;
                    phandle = <0x00000025>;
                };
                hdmi_dclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x00000066>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000001>;
                    linux,phandle = <0x00000026>;
                    phandle = <0x00000026>;
                };
                per_dpll_hs_clk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x0000004a>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000002>;
                    linux,phandle = <0x00000088>;
                    phandle = <0x00000088>;
                };
                usb_dpll_hs_clk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x0000004a>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000003>;
                    linux,phandle = <0x0000008c>;
                    phandle = <0x0000008c>;
                };
                eve_dpll_hs_clk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x0000004e>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000001>;
                    linux,phandle = <0x00000067>;
                    phandle = <0x00000067>;
                };
                dpll_eve_byp_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000009 0x00000067>;
                    ti,bit-shift = <0x00000017>;
                    reg = <0x00000290>;
                    linux,phandle = <0x00000068>;
                    phandle = <0x00000068>;
                };
                dpll_eve_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,omap4-dpll-clock";
                    clocks = <0x00000009 0x00000068>;
                    reg = <0x00000284 0x00000288 0x00000290 0x0000028c>;
                    ti,sink-clkdm = <0x00000069>;
                    linux,phandle = <0x0000006a>;
                    phandle = <0x0000006a>;
                };
                dpll_eve_m2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000006a>;
                    ti,max-div = <0x0000001f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x00000294>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    ti,set-rate-parent;
                    linux,phandle = <0x00000030>;
                    phandle = <0x00000030>;
                };
                eve_dclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x00000030>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000001>;
                    linux,phandle = <0x0000002f>;
                    phandle = <0x0000002f>;
                };
                dpll_core_h13x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000004d>;
                    ti,max-div = <0x0000003f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x00000140>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                };
                dpll_core_h14x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000004d>;
                    ti,max-div = <0x0000003f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x00000144>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    linux,phandle = <0x0000009a>;
                    phandle = <0x0000009a>;
                };
                dpll_core_h22x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000004d>;
                    ti,max-div = <0x0000003f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x00000154>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    linux,phandle = <0x00000072>;
                    phandle = <0x00000072>;
                };
                dpll_core_h23x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000004d>;
                    ti,max-div = <0x0000003f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x00000158>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    linux,phandle = <0x000000a4>;
                    phandle = <0x000000a4>;
                };
                dpll_core_h24x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000004d>;
                    ti,max-div = <0x0000003f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x0000015c>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    linux,phandle = <0x000000c3>;
                    phandle = <0x000000c3>;
                };
                dpll_ddr_x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,omap4-dpll-x2-clock";
                    clocks = <0x00000060>;
                    linux,phandle = <0x0000006b>;
                    phandle = <0x0000006b>;
                };
                dpll_ddr_h11x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000006b>;
                    ti,max-div = <0x0000003f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x00000228>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                };
                dpll_dsp_x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,omap4-dpll-x2-clock";
                    clocks = <0x00000055>;
                    linux,phandle = <0x0000006c>;
                    phandle = <0x0000006c>;
                };
                dpll_dsp_m3x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000006c>;
                    ti,max-div = <0x0000001f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x00000248>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    ti,set-rate-parent;
                    linux,phandle = <0x00000031>;
                    phandle = <0x00000031>;
                };
                dpll_gmac_x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,omap4-dpll-x2-clock";
                    clocks = <0x00000063>;
                    linux,phandle = <0x0000006d>;
                    phandle = <0x0000006d>;
                };
                dpll_gmac_h11x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000006d>;
                    ti,max-div = <0x0000003f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x000002c0>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    linux,phandle = <0x0000006e>;
                    phandle = <0x0000006e>;
                };
                dpll_gmac_h12x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000006d>;
                    ti,max-div = <0x0000003f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x000002c4>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                };
                dpll_gmac_h13x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000006d>;
                    ti,max-div = <0x0000003f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x000002c8>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                };
                dpll_gmac_m3x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000006d>;
                    ti,max-div = <0x0000001f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x000002bc>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                };
                gmii_m_clk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x0000006e>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000002>;
                };
                hdmi_clk2_div {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x00000066>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000001>;
                    linux,phandle = <0x0000007f>;
                    phandle = <0x0000007f>;
                };
                hdmi_div_clk {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x00000066>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000001>;
                    linux,phandle = <0x0000003d>;
                    phandle = <0x0000003d>;
                };
                l3_iclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    ti,max-div = <0x00000002>;
                    ti,bit-shift = <0x00000004>;
                    reg = <0x00000100>;
                    clocks = <0x0000004e>;
                    ti,index-power-of-two;
                    linux,phandle = <0x0000006f>;
                    phandle = <0x0000006f>;
                };
                l4_root_clk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x0000006f>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000002>;
                    linux,phandle = <0x000000a5>;
                    phandle = <0x000000a5>;
                };
                video1_clk2_div {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x00000070>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000001>;
                    linux,phandle = <0x0000007d>;
                    phandle = <0x0000007d>;
                };
                video1_div_clk {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x00000070>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000001>;
                    linux,phandle = <0x0000003b>;
                    phandle = <0x0000003b>;
                };
                video2_clk2_div {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x00000071>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000001>;
                    linux,phandle = <0x0000007e>;
                    phandle = <0x0000007e>;
                };
                video2_div_clk {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x00000071>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000001>;
                    linux,phandle = <0x0000003c>;
                    phandle = <0x0000003c>;
                };
                ipu1_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000000d 0x00000072>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00000520>;
                };
                mcasp1_ahclkr_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000073 0x00000074 0x00000075 0x00000076 0x00000077 0x00000078 0x00000079 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000007a 0x0000007b>;
                    ti,bit-shift = <0x0000001c>;
                    reg = <0x00000550>;
                };
                mcasp1_ahclkx_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000073 0x00000074 0x00000075 0x00000076 0x00000077 0x00000078 0x00000079 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000007a 0x0000007b>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00000550>;
                };
                mcasp1_aux_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000007c 0x0000007d 0x0000007e 0x0000007f>;
                    ti,bit-shift = <0x00000016>;
                    reg = <0x00000550>;
                };
                timer5_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000035 0x0000000c 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d 0x00000080>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00000558>;
                };
                timer6_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000035 0x0000000c 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d 0x00000080>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00000560>;
                };
                timer7_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000035 0x0000000c 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d 0x00000080>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00000568>;
                };
                timer8_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000035 0x0000000c 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d 0x00000080>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00000570>;
                };
                uart6_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000003e 0x0000003f>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00000580>;
                };
                dummy_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-clock";
                    clock-frequency = <0x00000000>;
                };
            };
            clockdomains {
            };
        };
        cm_core@4a008000 {
            compatible = "ti,dra7-cm-core";
            reg = <0x4a008000 0x00003000>;
            clocks {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                dpll_pcie_ref_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,omap4-dpll-clock";
                    clocks = <0x00000009 0x00000009>;
                    reg = <0x00000200 0x00000204 0x0000020c 0x00000208>;
                    ti,sink-clkdm = <0x00000081>;
                    linux,phandle = <0x00000082>;
                    phandle = <0x00000082>;
                };
                dpll_pcie_ref_m2ldo_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000082>;
                    ti,max-div = <0x0000001f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x00000210>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    linux,phandle = <0x00000083>;
                    phandle = <0x00000083>;
                };
                apll_pcie_in_clk_mux@4ae06118 {
                    compatible = "ti,mux-clock";
                    clocks = <0x00000083 0x00000084>;
                    #clock-cells = <0x00000000>;
                    reg = <0x0000021c 0x00000004>;
                    ti,bit-shift = <0x00000007>;
                    linux,phandle = <0x00000085>;
                    phandle = <0x00000085>;
                };
                apll_pcie_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,dra7-apll-clock";
                    clocks = <0x00000085 0x00000082>;
                    reg = <0x0000021c 0x00000220>;
                    linux,phandle = <0x00000086>;
                    phandle = <0x00000086>;
                };
                optfclk_pciephy1_32khz@4a0093b0 {
                    compatible = "ti,gate-clock";
                    clocks = <0x0000000c>;
                    #clock-cells = <0x00000000>;
                    reg = <0x000013b0>;
                    ti,bit-shift = <0x00000008>;
                    linux,phandle = <0x000000e9>;
                    phandle = <0x000000e9>;
                };
                optfclk_pciephy2_32khz@4a0093b8 {
                    compatible = "ti,gate-clock";
                    clocks = <0x0000000c>;
                    #clock-cells = <0x00000000>;
                    reg = <0x000013b8>;
                    ti,bit-shift = <0x00000008>;
                    linux,phandle = <0x000000ed>;
                    phandle = <0x000000ed>;
                };
                optfclk_pciephy_div@4a00821c {
                    compatible = "ti,divider-clock";
                    clocks = <0x00000086>;
                    #clock-cells = <0x00000000>;
                    reg = <0x0000021c>;
                    ti,dividers = <0x00000002 0x00000001>;
                    ti,bit-shift = <0x00000008>;
                    ti,max-div = <0x00000002>;
                    linux,phandle = <0x00000087>;
                    phandle = <0x00000087>;
                };
                optfclk_pciephy1_clk@4a0093b0 {
                    compatible = "ti,gate-clock";
                    clocks = <0x00000086>;
                    #clock-cells = <0x00000000>;
                    reg = <0x000013b0>;
                    ti,bit-shift = <0x00000009>;
                    linux,phandle = <0x000000ea>;
                    phandle = <0x000000ea>;
                };
                optfclk_pciephy2_clk@4a0093b8 {
                    compatible = "ti,gate-clock";
                    clocks = <0x00000086>;
                    #clock-cells = <0x00000000>;
                    reg = <0x000013b8>;
                    ti,bit-shift = <0x00000009>;
                    linux,phandle = <0x000000ee>;
                    phandle = <0x000000ee>;
                };
                optfclk_pciephy1_div_clk@4a0093b0 {
                    compatible = "ti,gate-clock";
                    clocks = <0x00000087>;
                    #clock-cells = <0x00000000>;
                    reg = <0x000013b0>;
                    ti,bit-shift = <0x0000000a>;
                    linux,phandle = <0x000000eb>;
                    phandle = <0x000000eb>;
                };
                optfclk_pciephy2_div_clk@4a0093b8 {
                    compatible = "ti,gate-clock";
                    clocks = <0x00000087>;
                    #clock-cells = <0x00000000>;
                    reg = <0x000013b8>;
                    ti,bit-shift = <0x0000000a>;
                    linux,phandle = <0x000000ef>;
                    phandle = <0x000000ef>;
                };
                apll_pcie_clkvcoldo {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x00000086>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000001>;
                };
                apll_pcie_clkvcoldo_div {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x00000086>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000001>;
                };
                apll_pcie_m2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x00000086>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000001>;
                    linux,phandle = <0x00000018>;
                    phandle = <0x00000018>;
                };
                dpll_per_byp_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000009 0x00000088>;
                    ti,bit-shift = <0x00000017>;
                    reg = <0x0000014c>;
                    linux,phandle = <0x00000089>;
                    phandle = <0x00000089>;
                };
                dpll_per_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,omap4-dpll-clock";
                    clocks = <0x00000009 0x00000089>;
                    reg = <0x00000140 0x00000144 0x0000014c 0x00000148>;
                    linux,phandle = <0x0000008a>;
                    phandle = <0x0000008a>;
                };
                dpll_per_m2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000008a>;
                    ti,max-div = <0x0000001f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x00000150>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    ti,set-rate-parent;
                    linux,phandle = <0x0000008b>;
                    phandle = <0x0000008b>;
                };
                func_96m_aon_dclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x0000008b>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000001>;
                    linux,phandle = <0x00000027>;
                    phandle = <0x00000027>;
                };
                dpll_usb_byp_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000009 0x0000008c>;
                    ti,bit-shift = <0x00000017>;
                    reg = <0x0000018c>;
                    linux,phandle = <0x0000008d>;
                    phandle = <0x0000008d>;
                };
                dpll_usb_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,omap4-dpll-j-type-clock";
                    clocks = <0x00000009 0x0000008d>;
                    reg = <0x00000180 0x00000184 0x0000018c 0x00000188>;
                    ti,sink-clkdm = <0x0000008e>;
                    linux,phandle = <0x0000008f>;
                    phandle = <0x0000008f>;
                };
                dpll_usb_m2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000008f>;
                    ti,max-div = <0x0000007f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x00000190>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    ti,set-rate-parent;
                    linux,phandle = <0x00000015>;
                    phandle = <0x00000015>;
                };
                dpll_pcie_ref_m2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000082>;
                    ti,max-div = <0x0000007f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x00000210>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    ti,set-rate-parent;
                    linux,phandle = <0x00000017>;
                    phandle = <0x00000017>;
                };
                dpll_per_x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,omap4-dpll-x2-clock";
                    clocks = <0x0000008a>;
                    linux,phandle = <0x00000090>;
                    phandle = <0x00000090>;
                };
                dpll_per_h11x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000090>;
                    ti,max-div = <0x0000003f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x00000158>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    linux,phandle = <0x00000091>;
                    phandle = <0x00000091>;
                };
                dpll_per_h12x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000090>;
                    ti,max-div = <0x0000003f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x0000015c>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    linux,phandle = <0x00000094>;
                    phandle = <0x00000094>;
                };
                dpll_per_h13x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000090>;
                    ti,max-div = <0x0000003f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x00000160>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    linux,phandle = <0x000000a2>;
                    phandle = <0x000000a2>;
                };
                dpll_per_h14x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000090>;
                    ti,max-div = <0x0000003f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x00000164>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    linux,phandle = <0x0000009b>;
                    phandle = <0x0000009b>;
                };
                dpll_per_m2x2_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000090>;
                    ti,max-div = <0x0000001f>;
                    ti,autoidle-shift = <0x00000008>;
                    reg = <0x00000150>;
                    ti,index-starts-at-one;
                    ti,invert-autoidle-bit;
                    linux,phandle = <0x0000003f>;
                    phandle = <0x0000003f>;
                };
                dpll_usb_clkdcoldo {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x0000008f>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000001>;
                    linux,phandle = <0x00000093>;
                    phandle = <0x00000093>;
                };
                func_128m_clk {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x00000091>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000002>;
                    linux,phandle = <0x0000009d>;
                    phandle = <0x0000009d>;
                };
                func_12m_fclk {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x0000003f>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000010>;
                };
                func_24m_clk {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x0000008b>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000004>;
                    linux,phandle = <0x00000075>;
                    phandle = <0x00000075>;
                };
                func_48m_fclk {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x0000003f>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000004>;
                    linux,phandle = <0x0000003e>;
                    phandle = <0x0000003e>;
                };
                func_96m_fclk {
                    #clock-cells = <0x00000000>;
                    compatible = "fixed-factor-clock";
                    clocks = <0x0000003f>;
                    clock-mult = <0x00000001>;
                    clock-div = <0x00000002>;
                };
                l3init_60m_fclk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000015>;
                    reg = <0x00000104>;
                    ti,dividers = <0x00000001 0x00000008>;
                };
                clkout2_clk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x00000092>;
                    ti,bit-shift = <0x00000008>;
                    reg = <0x000006b0>;
                };
                l3init_960m_gfclk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x00000093>;
                    ti,bit-shift = <0x00000008>;
                    reg = <0x000006c0>;
                    linux,phandle = <0x00000098>;
                    phandle = <0x00000098>;
                };
                dss_32khz_clk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x0000000c>;
                    ti,bit-shift = <0x0000000b>;
                    reg = <0x00001120>;
                };
                dss_48mhz_clk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x0000003e>;
                    ti,bit-shift = <0x00000009>;
                    reg = <0x00001120>;
                    linux,phandle = <0x00000103>;
                    phandle = <0x00000103>;
                };
                dss_dss_clk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x00000094>;
                    ti,bit-shift = <0x00000008>;
                    reg = <0x00001120>;
                    ti,set-rate-parent;
                    linux,phandle = <0x000000ff>;
                    phandle = <0x000000ff>;
                };
                dss_hdmi_clk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x00000095>;
                    ti,bit-shift = <0x0000000a>;
                    reg = <0x00001120>;
                    linux,phandle = <0x00000104>;
                    phandle = <0x00000104>;
                };
                dss_video1_clk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x00000096>;
                    ti,bit-shift = <0x0000000c>;
                    reg = <0x00001120>;
                    linux,phandle = <0x00000100>;
                    phandle = <0x00000100>;
                };
                dss_video2_clk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x00000097>;
                    ti,bit-shift = <0x0000000d>;
                    reg = <0x00001120>;
                    linux,phandle = <0x00000101>;
                    phandle = <0x00000101>;
                };
                gpio2_dbclk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x0000000c>;
                    ti,bit-shift = <0x00000008>;
                    reg = <0x00001760>;
                };
                gpio3_dbclk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x0000000c>;
                    ti,bit-shift = <0x00000008>;
                    reg = <0x00001768>;
                };
                gpio4_dbclk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x0000000c>;
                    ti,bit-shift = <0x00000008>;
                    reg = <0x00001770>;
                };
                gpio5_dbclk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x0000000c>;
                    ti,bit-shift = <0x00000008>;
                    reg = <0x00001778>;
                };
                gpio6_dbclk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x0000000c>;
                    ti,bit-shift = <0x00000008>;
                    reg = <0x00001780>;
                };
                gpio7_dbclk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x0000000c>;
                    ti,bit-shift = <0x00000008>;
                    reg = <0x00001810>;
                };
                gpio8_dbclk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x0000000c>;
                    ti,bit-shift = <0x00000008>;
                    reg = <0x00001818>;
                };
                mmc1_clk32k {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x0000000c>;
                    ti,bit-shift = <0x00000008>;
                    reg = <0x00001328>;
                };
                mmc2_clk32k {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x0000000c>;
                    ti,bit-shift = <0x00000008>;
                    reg = <0x00001330>;
                };
                mmc3_clk32k {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x0000000c>;
                    ti,bit-shift = <0x00000008>;
                    reg = <0x00001820>;
                };
                mmc4_clk32k {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x0000000c>;
                    ti,bit-shift = <0x00000008>;
                    reg = <0x00001828>;
                };
                sata_ref_clk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x00000009>;
                    ti,bit-shift = <0x00000008>;
                    reg = <0x00001388>;
                    linux,phandle = <0x000000e6>;
                    phandle = <0x000000e6>;
                };
                usb_otg_ss1_refclk960m {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x00000098>;
                    ti,bit-shift = <0x00000008>;
                    reg = <0x000013f0>;
                    linux,phandle = <0x000000f3>;
                    phandle = <0x000000f3>;
                };
                usb_otg_ss2_refclk960m {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x00000098>;
                    ti,bit-shift = <0x00000008>;
                    reg = <0x00001340>;
                    linux,phandle = <0x000000f7>;
                    phandle = <0x000000f7>;
                };
                usb_phy1_always_on_clk32k {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x0000000c>;
                    ti,bit-shift = <0x00000008>;
                    reg = <0x00000640>;
                    linux,phandle = <0x000000f2>;
                    phandle = <0x000000f2>;
                };
                usb_phy2_always_on_clk32k {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x0000000c>;
                    ti,bit-shift = <0x00000008>;
                    reg = <0x00000688>;
                    linux,phandle = <0x000000f6>;
                    phandle = <0x000000f6>;
                };
                usb_phy3_always_on_clk32k {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x0000000c>;
                    ti,bit-shift = <0x00000008>;
                    reg = <0x00000698>;
                    linux,phandle = <0x000000f9>;
                    phandle = <0x000000f9>;
                };
                atl_dpll_clk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000000c 0x00000070 0x00000071 0x00000066>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00000c00>;
                    linux,phandle = <0x00000099>;
                    phandle = <0x00000099>;
                };
                atl_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000006f 0x00000010 0x00000099>;
                    ti,bit-shift = <0x0000001a>;
                    reg = <0x00000c00>;
                    linux,phandle = <0x00000044>;
                    phandle = <0x00000044>;
                };
                gmac_gmii_ref_clk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x00000014>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x000013d0>;
                    ti,dividers = <0x00000002>;
                    linux,phandle = <0x000000fd>;
                    phandle = <0x000000fd>;
                };
                gmac_rft_clk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000070 0x00000071 0x00000010 0x00000066 0x0000006f>;
                    ti,bit-shift = <0x00000019>;
                    reg = <0x000013d0>;
                };
                gpu_core_gclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000009a 0x0000009b 0x00000012>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001220>;
                    ti,set-rate-parent;
                    linux,phandle = <0x000000c1>;
                    phandle = <0x000000c1>;
                };
                gpu_hyd_gclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000009a 0x0000009b 0x00000012>;
                    ti,bit-shift = <0x0000001a>;
                    reg = <0x00001220>;
                    ti,set-rate-parent;
                    linux,phandle = <0x000000c2>;
                    phandle = <0x000000c2>;
                };
                l3instr_ts_gclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000009c>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00000e50>;
                    ti,dividers = <0x00000008 0x00000010 0x00000020>;
                };
                mcasp2_ahclkr_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000073 0x00000074 0x00000075 0x00000076 0x00000077 0x00000078 0x00000079 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000007a 0x0000007b>;
                    ti,bit-shift = <0x0000001c>;
                    reg = <0x00001860>;
                };
                mcasp2_ahclkx_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000073 0x00000074 0x00000075 0x00000076 0x00000077 0x00000078 0x00000079 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000007a 0x0000007b>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001860>;
                    linux,phandle = <0x00000109>;
                    phandle = <0x00000109>;
                };
                mcasp2_aux_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000007c 0x0000007d 0x0000007e 0x0000007f>;
                    ti,bit-shift = <0x00000016>;
                    reg = <0x00001860>;
                };
                mcasp3_ahclkx_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000073 0x00000074 0x00000075 0x00000076 0x00000077 0x00000078 0x00000079 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000007a 0x0000007b>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001868>;
                    linux,phandle = <0x0000010b>;
                    phandle = <0x0000010b>;
                };
                mcasp3_aux_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000007c 0x0000007d 0x0000007e 0x0000007f>;
                    ti,bit-shift = <0x00000016>;
                    reg = <0x00001868>;
                };
                mcasp4_ahclkx_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000073 0x00000074 0x00000075 0x00000076 0x00000077 0x00000078 0x00000079 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000007a 0x0000007b>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001898>;
                };
                mcasp4_aux_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000007c 0x0000007d 0x0000007e 0x0000007f>;
                    ti,bit-shift = <0x00000016>;
                    reg = <0x00001898>;
                };
                mcasp5_ahclkx_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000073 0x00000074 0x00000075 0x00000076 0x00000077 0x00000078 0x00000079 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000007a 0x0000007b>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001878>;
                };
                mcasp5_aux_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000007c 0x0000007d 0x0000007e 0x0000007f>;
                    ti,bit-shift = <0x00000016>;
                    reg = <0x00001878>;
                };
                mcasp6_ahclkx_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000073 0x00000074 0x00000075 0x00000076 0x00000077 0x00000078 0x00000079 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000007a 0x0000007b>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001904>;
                    linux,phandle = <0x0000010c>;
                    phandle = <0x0000010c>;
                };
                mcasp6_aux_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000007c 0x0000007d 0x0000007e 0x0000007f>;
                    ti,bit-shift = <0x00000016>;
                    reg = <0x00001904>;
                };
                mcasp7_ahclkx_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000073 0x00000074 0x00000075 0x00000076 0x00000077 0x00000078 0x00000079 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000007a 0x0000007b>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001908>;
                    linux,phandle = <0x0000010d>;
                    phandle = <0x0000010d>;
                };
                mcasp7_aux_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000007c 0x0000007d 0x0000007e 0x0000007f>;
                    ti,bit-shift = <0x00000016>;
                    reg = <0x00001908>;
                };
                mcasp8_ahclkx_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000073 0x00000074 0x00000075 0x00000076 0x00000077 0x00000078 0x00000079 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000007a 0x0000007b>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001890>;
                    linux,phandle = <0x0000010e>;
                    phandle = <0x0000010e>;
                };
                mcasp8_aux_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000007c 0x0000007d 0x0000007e 0x0000007f>;
                    ti,bit-shift = <0x00000016>;
                    reg = <0x00001890>;
                };
                mmc1_fclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000009d 0x0000003f>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001328>;
                    linux,phandle = <0x0000009e>;
                    phandle = <0x0000009e>;
                };
                mmc1_fclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000009e>;
                    ti,bit-shift = <0x00000019>;
                    ti,max-div = <0x00000004>;
                    reg = <0x00001328>;
                    ti,index-power-of-two;
                };
                mmc2_fclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000009d 0x0000003f>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001330>;
                    linux,phandle = <0x0000009f>;
                    phandle = <0x0000009f>;
                };
                mmc2_fclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x0000009f>;
                    ti,bit-shift = <0x00000019>;
                    ti,max-div = <0x00000004>;
                    reg = <0x00001330>;
                    ti,index-power-of-two;
                };
                mmc3_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000003e 0x0000003f>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001820>;
                    linux,phandle = <0x000000a0>;
                    phandle = <0x000000a0>;
                };
                mmc3_gfclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x000000a0>;
                    ti,bit-shift = <0x00000019>;
                    ti,max-div = <0x00000004>;
                    reg = <0x00001820>;
                    ti,index-power-of-two;
                };
                mmc4_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000003e 0x0000003f>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001828>;
                    linux,phandle = <0x000000a1>;
                    phandle = <0x000000a1>;
                };
                mmc4_gfclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x000000a1>;
                    ti,bit-shift = <0x00000019>;
                    ti,max-div = <0x00000004>;
                    reg = <0x00001828>;
                    ti,index-power-of-two;
                };
                qspi_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000009d 0x000000a2>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001838>;
                    linux,phandle = <0x000000a3>;
                    phandle = <0x000000a3>;
                };
                qspi_gfclk_div {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,divider-clock";
                    clocks = <0x000000a3>;
                    ti,bit-shift = <0x00000019>;
                    ti,max-div = <0x00000004>;
                    reg = <0x00001838>;
                    ti,index-power-of-two;
                    linux,phandle = <0x000000e4>;
                    phandle = <0x000000e4>;
                };
                timer10_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000035 0x0000000c 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001728>;
                };
                timer11_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000035 0x0000000c 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001730>;
                };
                timer13_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000035 0x0000000c 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x000017c8>;
                };
                timer14_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000035 0x0000000c 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x000017d0>;
                };
                timer15_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000035 0x0000000c 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x000017d8>;
                };
                timer16_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000035 0x0000000c 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001830>;
                };
                timer2_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000035 0x0000000c 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001738>;
                };
                timer3_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000035 0x0000000c 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001740>;
                };
                timer4_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000035 0x0000000c 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001748>;
                };
                timer9_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x00000035 0x0000000c 0x0000000a 0x00000036 0x00000037 0x00000038 0x00000039 0x0000003a 0x0000003b 0x0000003c 0x0000003d>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001750>;
                };
                uart1_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000003e 0x0000003f>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001840>;
                };
                uart2_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000003e 0x0000003f>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001848>;
                };
                uart3_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000003e 0x0000003f>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001850>;
                };
                uart4_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000003e 0x0000003f>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001858>;
                };
                uart5_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000003e 0x0000003f>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001870>;
                };
                uart7_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000003e 0x0000003f>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x000018d0>;
                };
                uart8_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000003e 0x0000003f>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x000018e0>;
                };
                uart9_gfclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000003e 0x0000003f>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x000018e8>;
                };
                vip1_gclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000006f 0x000000a4>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001020>;
                };
                vip2_gclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000006f 0x000000a4>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001028>;
                };
                vip3_gclk_mux {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x0000006f 0x000000a4>;
                    ti,bit-shift = <0x00000018>;
                    reg = <0x00001030>;
                };
            };
            clockdomains {
                coreaon_clkdm {
                    compatible = "ti,clockdomain";
                    clocks = <0x0000008f>;
                };
                gpu_clkdm {
                    compatible = "ti,clockdomain";
                    linux,phandle = <0x0000005c>;
                    phandle = <0x0000005c>;
                };
                pcie_clkdm {
                    compatible = "ti,clockdomain";
                    linux,phandle = <0x00000081>;
                    phandle = <0x00000081>;
                };
                iva_clkdm {
                    compatible = "ti,clockdomain";
                    linux,phandle = <0x00000058>;
                    phandle = <0x00000058>;
                };
                dsp1_clkdm {
                    compatible = "ti,clockdomain";
                    linux,phandle = <0x00000054>;
                    phandle = <0x00000054>;
                };
                gmac_clkdm {
                    compatible = "ti,clockdomain";
                    linux,phandle = <0x00000062>;
                    phandle = <0x00000062>;
                };
                l3init_clkdm {
                    compatible = "ti,clockdomain";
                    linux,phandle = <0x0000008e>;
                    phandle = <0x0000008e>;
                };
                eve1_clkdm {
                    compatible = "ti,clockdomain";
                    linux,phandle = <0x00000069>;
                    phandle = <0x00000069>;
                };
                atl_clkdm {
                    compatible = "ti,clockdomain";
                    linux,phandle = <0x00000047>;
                    phandle = <0x00000047>;
                };
            };
        };
        ctrl_core@4a002000 {
            compatible = "ti,dra7-ctrl-core";
            reg = <0x4a002000 0x000006d0>;
            clocks {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                dss_deshdcp_clk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x0000006f>;
                    ti,bit-shift = <0x00000000>;
                    reg = <0x00000558>;
                };
                ehrpwm0_tbclk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x000000a5>;
                    ti,bit-shift = <0x00000014>;
                    reg = <0x00000558>;
                };
                ehrpwm1_tbclk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x000000a5>;
                    ti,bit-shift = <0x00000015>;
                    reg = <0x00000558>;
                };
                ehrpwm2_tbclk {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,gate-clock";
                    clocks = <0x000000a5>;
                    ti,bit-shift = <0x00000016>;
                    reg = <0x00000558>;
                };
                sys_32k_ck {
                    #clock-cells = <0x00000000>;
                    compatible = "ti,mux-clock";
                    clocks = <0x000000a6 0x000000a7 0x000000a7 0x000000a7>;
                    ti,bit-shift = <0x00000008>;
                    reg = <0x000006c4>;
                    linux,phandle = <0x0000000c>;
                    phandle = <0x0000000c>;
                };
            };
            clockdomains {
            };
        };
        counter@4ae04000 {
            compatible = "ti,omap-counter32k";
            reg = <0x4ae04000 0x00000040>;
            ti,hwmods = "counter_32k";
        };
        tisysconcore@4a002000 {
            compatible = "syscon";
            reg = <0x4a002000 0x000006d0>;
            linux,phandle = <0x000000e7>;
            phandle = <0x000000e7>;
        };
        tisyscon@4a002e00 {
            compatible = "syscon";
            reg = <0x4a002e00 0x0000007c>;
            linux,phandle = <0x000000a8>;
            phandle = <0x000000a8>;
        };
        pbias_regulator {
            compatible = "ti,pbias-omap";
            reg = <0x00000000 0x00000004>;
            syscon = <0x000000a8>;
            pbias_mmc_omap5 {
                regulator-name = "pbias_mmc_omap5";
                regulator-min-microvolt = <0x001b7740>;
                regulator-max-microvolt = <0x002dc6c0>;
                linux,phandle = <0x000000ce>;
                phandle = <0x000000ce>;
            };
        };
        pinmux@4a003400 {
            compatible = [74 69 2c 64 72 61 37 2d 70 61 64 63 6f 6e 66 00 70 69 6e 63 74 72 6c 2d 73 69 6e 67 6c 65 00];
            reg = <0x4a003400 0x00000464>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            #interrupt-cells = <0x00000001>;
            interrupt-controller;
            pinctrl-single,register-width = <0x00000020>;
            pinctrl-single,function-mask = <0x3fffffff>;
            linux,phandle = <0x000000ab>;
            phandle = <0x000000ab>;
            tps65917_pins_default {
                pinctrl-single,pins = <0x00000424 0x00060001>;
                linux,phandle = <0x000000c4>;
                phandle = <0x000000c4>;
            };
            mmc1_pins_default {
                pinctrl-single,pins = <0x00000354 0x00060000 0x00000358 0x00060000 0x0000035c 0x00060000 0x00000360 0x00060000 0x00000364 0x00060000 0x00000368 0x00060000 0x0000036c 0x00060000>;
                linux,phandle = <0x000000cf>;
                phandle = <0x000000cf>;
            };
            mmc1_pins_virtual1 {
                pinctrl-single,pins = <0x00000354 0x000601f0 0x00000358 0x000601f0 0x0000035c 0x000601f0 0x00000360 0x000601f0 0x00000364 0x000601f0 0x00000368 0x000601f0 0x0000036c 0x00060000>;
                linux,phandle = <0x000000d0>;
                phandle = <0x000000d0>;
            };
            mmc1_pins_manual1 {
                pinctrl-single,pins = <0x00000354 0x00060100 0x00000358 0x00060100 0x0000035c 0x00060100 0x00000360 0x00060100 0x00000364 0x00060100 0x00000368 0x00060100 0x0000036c 0x00060000>;
                linux,phandle = <0x000000d1>;
                phandle = <0x000000d1>;
            };
            mmc1_pins_manual2 {
                pinctrl-single,pins = <0x00000354 0x00060100 0x00000358 0x00060100 0x0000035c 0x00060100 0x00000360 0x00060100 0x00000364 0x00060100 0x00000368 0x00060100 0x0000036c 0x00060000>;
                linux,phandle = <0x000000d3>;
                phandle = <0x000000d3>;
            };
            mmc2_pins_default {
                pinctrl-single,pins = <0x0000008c 0x00060001 0x00000090 0x00060001 0x00000094 0x00060001 0x00000098 0x00060001 0x0000009c 0x00060001 0x000000a0 0x00060001 0x000000a4 0x00060001 0x000000a8 0x00060001 0x000000ac 0x00060001 0x000000b0 0x00060001>;
                linux,phandle = <0x000000d7>;
                phandle = <0x000000d7>;
            };
            mmc2_pins_manual1 {
                pinctrl-single,pins = <0x0000008c 0x00060101 0x00000090 0x00060101 0x00000094 0x00060101 0x00000098 0x00060101 0x0000009c 0x00060101 0x000000a0 0x00060101 0x000000a4 0x00060101 0x000000a8 0x00060101 0x000000ac 0x00060101 0x000000b0 0x00060101>;
                linux,phandle = <0x000000d8>;
                phandle = <0x000000d8>;
            };
            mmc2_pins_manual3 {
                pinctrl-single,pins = <0x0000008c 0x00060101 0x00000090 0x00060101 0x00000094 0x00060101 0x00000098 0x00060101 0x0000009c 0x00060101 0x000000a0 0x00060101 0x000000a4 0x00060101 0x000000a8 0x00060101 0x000000ac 0x00060101 0x000000b0 0x00060101>;
                linux,phandle = <0x000000da>;
                phandle = <0x000000da>;
            };
            pinmux_vin5a_pins {
                pinctrl-single,pins = <0x00000294 0x00040007 0x00000298 0x00040007 0x000002a4 0x00040007 0x000002a8 0x000c0007 0x000002b4 0x000c0007 0x000002b8 0x000c0007 0x000002f4 0x00040007 0x000002f8 0x000c0007 0x0000030c 0x000c0007 0x00000310 0x000c0007 0x00000324 0x00040007 0x00000328 0x000c0007 0x0000032c 0x000c0007>;
                linux,phandle = <0x0000010f>;
                phandle = <0x0000010f>;
            };
            pinmux_vin4b_pins {
                pinctrl-single,pins = <0x0000023c 0x00050005 0x00000060 0x00050006 0x00000260 0x00050005 0x00000240 0x00050005 0x00000248 0x00050005 0x0000024c 0x00050005 0x00000250 0x00050005 0x00000254 0x00050005 0x00000268 0x00050005 0x0000026c 0x00050005 0x00000270 0x00050005>;
                linux,phandle = <0x00000110>;
                phandle = <0x00000110>;
            };
            pinmux_vin2a_pins {
                pinctrl-single,pins = <0x00000154 0x00050000 0x00000164 0x00050000 0x00000168 0x00050000 0x0000016c 0x00050000 0x00000170 0x00050000 0x00000174 0x00050000 0x00000178 0x00050000 0x0000017c 0x00050000 0x00000180 0x00050000 0x00000184 0x00050000>;
                linux,phandle = <0x00000111>;
                phandle = <0x00000111>;
            };
            pinmux_vin2a_hsync_def_pins {
                pinctrl-single,pins = <0x00000160 0x00050000>;
            };
            pinmux_vin3b_pins {
                pinctrl-single,pins = <0x00000374 0x00050004 0x00000378 0x00050004 0x0000037c 0x00050004 0x00000380 0x00050004 0x00000384 0x00050004 0x00000388 0x00050004 0x0000038c 0x00050004 0x00000390 0x00050004 0x00000394 0x00050004 0x00000398 0x00050004 0x000003a0 0x00050004>;
                linux,phandle = <0x00000112>;
                phandle = <0x00000112>;
            };
        };
        padconf@4844a000 {
            compatible = "ti,dra7-iodelay";
            reg = <0x4844a000 0x00000d1c>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            mmc1_iodelay_manual1_conf {
                pinctrl-single,pins = <0x00000618 0x00000000 0x00000620 0x00000549 0x00000624 0x00000000 0x0000062c 0x00000001 0x00000628 0x00000000 0x00000630 0x000001e3 0x00000638 0x00000010 0x00000634 0x00000000 0x0000063c 0x0000007e 0x00000644 0x00000000 0x00000640 0x00000000 0x00000648 0x00000068 0x00000650 0x00000022 0x0000064c 0x00000000 0x00000654 0x00000021 0x0000065c 0x00000012 0x00000658 0x00000000>;
                linux,phandle = <0x000000d2>;
                phandle = <0x000000d2>;
            };
            mmc1_iodelay_manual2_conf {
                pinctrl-single,pins = <0x00000620 0x016d0230 0x0000062c 0x00000000 0x00000628 0x0000007d 0x00000638 0x0000001d 0x00000634 0x0000002b 0x00000644 0x00000000 0x00000640 0x000001b1 0x00000650 0x0000002f 0x0000064c 0x0000011f 0x0000065c 0x0000001e 0x00000658 0x0000015f>;
                linux,phandle = <0x000000d4>;
                phandle = <0x000000d4>;
            };
            mmc2_iodelay_manual1_conf {
                pinctrl-single,pins = <0x0000018c 0x00000000 0x00000194 0x00000064 0x00000190 0x00000000 0x000001a4 0x00000187 0x000001ac 0x000000db 0x000001a8 0x00000000 0x000001b0 0x00000000 0x000001b8 0x00000018 0x000001b4 0x00000000 0x000001bc 0x000000d3 0x000001c4 0x00000058 0x000001c0 0x00000000 0x000001c8 0x00000000 0x000001d0 0x00000272 0x000001d4 0x00000140 0x000001dc 0x00000000 0x000001d8 0x00000000 0x000001e0 0x00000000 0x000001e8 0x000000ac 0x000001e4 0x00000000 0x000001ec 0x0000009f 0x000001f4 0x000000b1 0x000001f0 0x00000000 0x000001f8 0x000000e8 0x00000200 0x00000000 0x000001fc 0x00000000 0x00000360 0x00000000 0x00000368 0x00000000 0x00000364 0x00000000>;
                linux,phandle = <0x000000d9>;
                phandle = <0x000000d9>;
            };
            mmc2_iodelay_manual2_conf {
                pinctrl-single,pins = <0x0000018c 0x00000000 0x00000194 0x00000064 0x00000190 0x00000000 0x000001a4 0x000000ad 0x000001ac 0x000000db 0x000001a8 0x00000000 0x000001b0 0x00000000 0x000001b8 0x00000018 0x000001b4 0x00000000 0x000001bc 0x00000028 0x000001c4 0x00000058 0x000001c0 0x00000000 0x000001c8 0x0aa602cc 0x000001d0 0x00000272 0x000001d4 0x00000085 0x000001dc 0x00000000 0x000001d8 0x00000000 0x000001e0 0x00000000 0x000001e8 0x000000ac 0x000001e4 0x00000000 0x000001ec 0x00000000 0x000001f4 0x000000b1 0x000001f0 0x00000000 0x000001f8 0x00000000 0x00000200 0x00000000 0x000001fc 0x00000000 0x00000360 0x00000000 0x00000368 0x00000000 0x00000364 0x00000000>;
            };
            mmc2_iodelay_manual3_conf {
                pinctrl-single,pins = <0x00000194 0x005f0000 0x00000190 0x000002b7 0x000001ac 0x000000d6 0x000001a8 0x0000039c 0x000001b8 0x00000013 0x000001b4 0x000002cf 0x000001c4 0x00000053 0x000001c0 0x00000338 0x000001d0 0x01a003fc 0x000001dc 0x00000000 0x000001d8 0x0000036d 0x000001e8 0x000000a7 0x000001e4 0x000001be 0x000001f4 0x000000ac 0x000001f0 0x0000034f 0x00000200 0x00000000 0x000001fc 0x0000024a 0x00000368 0x00000028 0x00000364 0x0000040f>;
                linux,phandle = <0x000000db>;
                phandle = <0x000000db>;
            };
        };
        dma-controller@4a056000 {
            compatible = "ti,omap4430-sdma";
            reg = <0x4a056000 0x00001000>;
            interrupts = <0x00000000 0x00000007 0x00000004 0x00000000 0x00000008 0x00000004 0x00000000 0x00000009 0x00000004 0x00000000 0x0000000a 0x00000004>;
            #dma-cells = <0x00000001>;
            dma-channels = <0x00000020>;
            dma-requests = <0x00000080>;
            linux,phandle = <0x000000a9>;
            phandle = <0x000000a9>;
        };
        dma-crossbar@4a002b78 {
            compatible = "ti,dra7-dma-crossbar";
            reg = <0x4a002b78 0x000000fc>;
            #dma-cells = <0x00000001>;
            dma-requests = <0x000000cc>;
            ti,dma-safe-map = <0x00000000>;
            dma-masters = <0x000000a9>;
            linux,phandle = <0x000000ac>;
            phandle = <0x000000ac>;
        };
        edma-controller@43300000 {
            compatible = "ti,edma3";
            reg = <0x43300000 0x0000801c>;
            interrupts = <0x00000000 0x00000169 0x00000004 0x00000000 0x00000168 0x00000004 0x00000000 0x00000167 0x00000004>;
            #dma-cells = <0x00000001>;
            ti,hwmods = [74 70 63 63 00 74 70 74 63 30 00 74 70 74 63 31 00];
            dma-requests = <0x00000040>;
            linux,phandle = <0x000000aa>;
            phandle = <0x000000aa>;
        };
        dma-crossbar@4a002c78 {
            compatible = "ti,dra7-edma-crossbar";
            reg = <0x4a002c78 0x0000007c>;
            #dma-cells = <0x00000001>;
            dma-requests = <0x000000cc>;
            ti,dma-safe-map = <0x00000000>;
            dma-masters = <0x000000aa>;
            linux,phandle = <0x0000010a>;
            phandle = <0x0000010a>;
        };
        gpio@4ae10000 {
            compatible = "ti,omap4-gpio";
            reg = <0x4ae10000 0x00000200>;
            interrupts = <0x00000000 0x00000018 0x00000004>;
            ti,hwmods = "gpio1";
            gpio-controller;
            #gpio-cells = <0x00000002>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            linux,phandle = <0x000000cd>;
            phandle = <0x000000cd>;
        };
        gpio@48055000 {
            compatible = "ti,omap4-gpio";
            reg = <0x48055000 0x00000200>;
            interrupts = <0x00000000 0x00000019 0x00000004>;
            ti,hwmods = "gpio2";
            gpio-controller;
            #gpio-cells = <0x00000002>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            linux,phandle = <0x000000cb>;
            phandle = <0x000000cb>;
        };
        gpio@48057000 {
            compatible = "ti,omap4-gpio";
            reg = <0x48057000 0x00000200>;
            interrupts = <0x00000000 0x0000001a 0x00000004>;
            ti,hwmods = "gpio3";
            gpio-controller;
            #gpio-cells = <0x00000002>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
        };
        gpio@48059000 {
            compatible = "ti,omap4-gpio";
            reg = <0x48059000 0x00000200>;
            interrupts = <0x00000000 0x0000001b 0x00000004>;
            ti,hwmods = "gpio4";
            gpio-controller;
            #gpio-cells = <0x00000002>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
        };
        gpio@4805b000 {
            compatible = "ti,omap4-gpio";
            reg = <0x4805b000 0x00000200>;
            interrupts = <0x00000000 0x0000001c 0x00000004>;
            ti,hwmods = "gpio5";
            gpio-controller;
            #gpio-cells = <0x00000002>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            linux,phandle = <0x00000122>;
            phandle = <0x00000122>;
        };
        gpio@4805d000 {
            compatible = "ti,omap4-gpio";
            reg = <0x4805d000 0x00000200>;
            interrupts = <0x00000000 0x0000001d 0x00000004>;
            ti,hwmods = "gpio6";
            gpio-controller;
            #gpio-cells = <0x00000002>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            linux,phandle = <0x000000c6>;
            phandle = <0x000000c6>;
        };
        gpio@48051000 {
            compatible = "ti,omap4-gpio";
            reg = <0x48051000 0x00000200>;
            interrupts = <0x00000000 0x0000001e 0x00000004>;
            ti,hwmods = "gpio7";
            gpio-controller;
            #gpio-cells = <0x00000002>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
            linux,phandle = <0x0000011e>;
            phandle = <0x0000011e>;
        };
        gpio@48053000 {
            compatible = "ti,omap4-gpio";
            reg = <0x48053000 0x00000200>;
            interrupts = <0x00000000 0x00000074 0x00000004>;
            ti,hwmods = "gpio8";
            gpio-controller;
            #gpio-cells = <0x00000002>;
            interrupt-controller;
            #interrupt-cells = <0x00000002>;
        };
        serial@4806a000 {
            compatible = [74 69 2c 61 6d 33 33 35 32 2d 75 61 72 74 00 74 69 2c 6f 6d 61 70 34 2d 75 61 72 74 00];
            reg = <0x4806a000 0x00000100>;
            interrupts-extended = <0x00000001 0x00000000 0x00000043 0x00000004 0x000000ab 0x000003e0>;
            ti,hwmods = "uart1";
            clock-frequency = <0x02dc6c00>;
            status = "okay";
            dmas = <0x000000ac 0x00000031 0x000000ac 0x00000032>;
            dma-names = [74 78 00 72 78 00];
        };
        serial@4806c000 {
            compatible = [74 69 2c 61 6d 33 33 35 32 2d 75 61 72 74 00 74 69 2c 6f 6d 61 70 34 2d 75 61 72 74 00];
            reg = <0x4806c000 0x00000100>;
            interrupts-extended = <0x00000001 0x00000000 0x00000044 0x00000004>;
            ti,hwmods = "uart2";
            clock-frequency = <0x02dc6c00>;
            status = "okay";
            dmas = <0x000000ac 0x00000033 0x000000ac 0x00000034>;
            dma-names = [74 78 00 72 78 00];
        };
        serial@48020000 {
            compatible = [74 69 2c 61 6d 33 33 35 32 2d 75 61 72 74 00 74 69 2c 6f 6d 61 70 34 2d 75 61 72 74 00];
            reg = <0x48020000 0x00000100>;
            interrupts-extended = <0x00000001 0x00000000 0x00000045 0x00000004>;
            ti,hwmods = "uart3";
            clock-frequency = <0x02dc6c00>;
            status = "okay";
            dmas = <0x000000ac 0x00000035 0x000000ac 0x00000036>;
            dma-names = [74 78 00 72 78 00];
        };
        serial@4806e000 {
            compatible = [74 69 2c 61 6d 33 33 35 32 2d 75 61 72 74 00 74 69 2c 6f 6d 61 70 34 2d 75 61 72 74 00];
            reg = <0x4806e000 0x00000100>;
            interrupts-extended = <0x00000001 0x00000000 0x00000041 0x00000004>;
            ti,hwmods = "uart4";
            clock-frequency = <0x02dc6c00>;
            status = "disabled";
            dmas = <0x000000ac 0x00000037 0x000000ac 0x00000038>;
            dma-names = [74 78 00 72 78 00];
        };
        serial@48066000 {
            compatible = [74 69 2c 61 6d 33 33 35 32 2d 75 61 72 74 00 74 69 2c 6f 6d 61 70 34 2d 75 61 72 74 00];
            reg = <0x48066000 0x00000100>;
            interrupts-extended = <0x00000001 0x00000000 0x00000064 0x00000004>;
            ti,hwmods = "uart5";
            clock-frequency = <0x02dc6c00>;
            status = "disabled";
            dmas = <0x000000ac 0x0000003f 0x000000ac 0x00000040>;
            dma-names = [74 78 00 72 78 00];
        };
        serial@48068000 {
            compatible = [74 69 2c 61 6d 33 33 35 32 2d 75 61 72 74 00 74 69 2c 6f 6d 61 70 34 2d 75 61 72 74 00];
            reg = <0x48068000 0x00000100>;
            interrupts-extended = <0x00000001 0x00000000 0x00000065 0x00000004>;
            ti,hwmods = "uart6";
            clock-frequency = <0x02dc6c00>;
            status = "disabled";
            dmas = <0x000000ac 0x0000004f 0x000000ac 0x00000050>;
            dma-names = [74 78 00 72 78 00];
        };
        serial@48420000 {
            compatible = [74 69 2c 61 6d 33 33 35 32 2d 75 61 72 74 00 74 69 2c 6f 6d 61 70 34 2d 75 61 72 74 00];
            reg = <0x48420000 0x00000100>;
            interrupts-extended = <0x00000001 0x00000000 0x000000da 0x00000004>;
            ti,hwmods = "uart7";
            clock-frequency = <0x02dc6c00>;
            status = "disabled";
        };
        serial@48422000 {
            compatible = [74 69 2c 61 6d 33 33 35 32 2d 75 61 72 74 00 74 69 2c 6f 6d 61 70 34 2d 75 61 72 74 00];
            reg = <0x48422000 0x00000100>;
            interrupts-extended = <0x00000001 0x00000000 0x000000db 0x00000004>;
            ti,hwmods = "uart8";
            clock-frequency = <0x02dc6c00>;
            status = "disabled";
        };
        serial@48424000 {
            compatible = [74 69 2c 61 6d 33 33 35 32 2d 75 61 72 74 00 74 69 2c 6f 6d 61 70 34 2d 75 61 72 74 00];
            reg = <0x48424000 0x00000100>;
            interrupts-extended = <0x00000001 0x00000000 0x000000dc 0x00000004>;
            ti,hwmods = "uart9";
            clock-frequency = <0x02dc6c00>;
            status = "disabled";
        };
        serial@4ae2b000 {
            compatible = [74 69 2c 61 6d 33 33 35 32 2d 75 61 72 74 00 74 69 2c 6f 6d 61 70 34 2d 75 61 72 74 00];
            reg = <0x4ae2b000 0x00000100>;
            interrupts-extended = <0x00000001 0x00000000 0x000000dd 0x00000004>;
            ti,hwmods = "uart10";
            clock-frequency = <0x02dc6c00>;
            status = "disabled";
        };
        mailbox@4a0f4000 {
            compatible = "ti,omap4-mailbox";
            reg = <0x4a0f4000 0x00000200>;
            interrupts = <0x00000000 0x00000015 0x00000004 0x00000000 0x00000087 0x00000004 0x00000000 0x00000086 0x00000004>;
            ti,hwmods = "mailbox1";
            #mbox-cells = <0x00000001>;
            ti,mbox-num-users = <0x00000003>;
            ti,mbox-num-fifos = <0x00000008>;
            status = "disabled";
            mbox_ipu2 {
                ti,mbox-tx = <0x00000000 0x00000000 0x00000000>;
                ti,mbox-rx = <0x00000001 0x00000000 0x00000000>;
                status = "disabled";
            };
            mbox_dsp1 {
                ti,mbox-tx = <0x00000003 0x00000000 0x00000000>;
                ti,mbox-rx = <0x00000002 0x00000000 0x00000000>;
                status = "disabled";
            };
        };
        mailbox@4883a000 {
            compatible = "ti,omap4-mailbox";
            reg = <0x4883a000 0x00000200>;
            interrupts = <0x00000000 0x000000ed 0x00000004 0x00000000 0x000000ee 0x00000004 0x00000000 0x000000ef 0x00000004 0x00000000 0x000000f0 0x00000004>;
            ti,hwmods = "mailbox2";
            #mbox-cells = <0x00000001>;
            ti,mbox-num-users = <0x00000004>;
            ti,mbox-num-fifos = <0x0000000c>;
            status = "disabled";
            mbox_ipu1 {
                ti,mbox-tx = <0x00000000 0x00000000 0x00000000>;
                ti,mbox-rx = <0x00000001 0x00000000 0x00000000>;
                status = "disabled";
            };
        };
        mailbox@4883c000 {
            compatible = "ti,omap4-mailbox";
            reg = <0x4883c000 0x00000200>;
            interrupts = <0x00000000 0x000000f1 0x00000004 0x00000000 0x000000f2 0x00000004 0x00000000 0x000000f3 0x00000004 0x00000000 0x000000f4 0x00000004>;
            ti,hwmods = "mailbox3";
            #mbox-cells = <0x00000001>;
            ti,mbox-num-users = <0x00000004>;
            ti,mbox-num-fifos = <0x0000000c>;
            status = "disabled";
        };
        mailbox@4883e000 {
            compatible = "ti,omap4-mailbox";
            reg = <0x4883e000 0x00000200>;
            interrupts = <0x00000000 0x000000f5 0x00000004 0x00000000 0x000000f6 0x00000004 0x00000000 0x000000f7 0x00000004 0x00000000 0x000000f8 0x00000004>;
            ti,hwmods = "mailbox4";
            #mbox-cells = <0x00000001>;
            ti,mbox-num-users = <0x00000004>;
            ti,mbox-num-fifos = <0x0000000c>;
            status = "disabled";
        };
        mailbox@48840000 {
            compatible = "ti,omap4-mailbox";
            reg = <0x48840000 0x00000200>;
            interrupts = <0x00000000 0x000000f9 0x00000004 0x00000000 0x000000fa 0x00000004 0x00000000 0x000000fb 0x00000004 0x00000000 0x000000fc 0x00000004>;
            ti,hwmods = "mailbox5";
            #mbox-cells = <0x00000001>;
            ti,mbox-num-users = <0x00000004>;
            ti,mbox-num-fifos = <0x0000000c>;
            status = "okay";
            linux,phandle = <0x000000af>;
            phandle = <0x000000af>;
            mbox_ipu1_legacy {
                ti,mbox-tx = <0x00000006 0x00000002 0x00000002>;
                ti,mbox-rx = <0x00000004 0x00000002 0x00000002>;
                status = "okay";
                linux,phandle = <0x000000b0>;
                phandle = <0x000000b0>;
            };
            mbox_dsp1_legacy {
                ti,mbox-tx = <0x00000005 0x00000002 0x00000002>;
                ti,mbox-rx = <0x00000001 0x00000002 0x00000002>;
                status = "okay";
                linux,phandle = <0x000000be>;
                phandle = <0x000000be>;
            };
        };
        mailbox@48842000 {
            compatible = "ti,omap4-mailbox";
            reg = <0x48842000 0x00000200>;
            interrupts = <0x00000000 0x000000fd 0x00000004 0x00000000 0x000000fe 0x00000004 0x00000000 0x000000ff 0x00000004 0x00000000 0x00000100 0x00000004>;
            ti,hwmods = "mailbox6";
            #mbox-cells = <0x00000001>;
            ti,mbox-num-users = <0x00000004>;
            ti,mbox-num-fifos = <0x0000000c>;
            status = "okay";
            linux,phandle = <0x000000b6>;
            phandle = <0x000000b6>;
            mbox_ipu2_legacy {
                ti,mbox-tx = <0x00000006 0x00000002 0x00000002>;
                ti,mbox-rx = <0x00000004 0x00000002 0x00000002>;
                status = "okay";
                linux,phandle = <0x000000b7>;
                phandle = <0x000000b7>;
            };
        };
        mailbox@48844000 {
            compatible = "ti,omap4-mailbox";
            reg = <0x48844000 0x00000200>;
            interrupts = <0x00000000 0x00000101 0x00000004 0x00000000 0x00000102 0x00000004 0x00000000 0x00000103 0x00000004 0x00000000 0x00000104 0x00000004>;
            ti,hwmods = "mailbox7";
            #mbox-cells = <0x00000001>;
            ti,mbox-num-users = <0x00000004>;
            ti,mbox-num-fifos = <0x0000000c>;
            status = "disabled";
        };
        mailbox@48846000 {
            compatible = "ti,omap4-mailbox";
            reg = <0x48846000 0x00000200>;
            interrupts = <0x00000000 0x00000105 0x00000004 0x00000000 0x00000106 0x00000004 0x00000000 0x00000107 0x00000004 0x00000000 0x00000108 0x00000004>;
            ti,hwmods = "mailbox8";
            #mbox-cells = <0x00000001>;
            ti,mbox-num-users = <0x00000004>;
            ti,mbox-num-fifos = <0x0000000c>;
            status = "disabled";
        };
        mailbox@4885e000 {
            compatible = "ti,omap4-mailbox";
            reg = <0x4885e000 0x00000200>;
            interrupts = <0x00000000 0x00000109 0x00000004 0x00000000 0x0000010a 0x00000004 0x00000000 0x0000010b 0x00000004 0x00000000 0x0000010c 0x00000004>;
            ti,hwmods = "mailbox9";
            #mbox-cells = <0x00000001>;
            ti,mbox-num-users = <0x00000004>;
            ti,mbox-num-fifos = <0x0000000c>;
            status = "disabled";
        };
        mailbox@48860000 {
            compatible = "ti,omap4-mailbox";
            reg = <0x48860000 0x00000200>;
            interrupts = <0x00000000 0x0000010d 0x00000004 0x00000000 0x0000010e 0x00000004 0x00000000 0x0000010f 0x00000004 0x00000000 0x00000110 0x00000004>;
            ti,hwmods = "mailbox10";
            #mbox-cells = <0x00000001>;
            ti,mbox-num-users = <0x00000004>;
            ti,mbox-num-fifos = <0x0000000c>;
            status = "disabled";
        };
        mailbox@48862000 {
            compatible = "ti,omap4-mailbox";
            reg = <0x48862000 0x00000200>;
            interrupts = <0x00000000 0x00000111 0x00000004 0x00000000 0x00000112 0x00000004 0x00000000 0x00000113 0x00000004 0x00000000 0x00000114 0x00000004>;
            ti,hwmods = "mailbox11";
            #mbox-cells = <0x00000001>;
            ti,mbox-num-users = <0x00000004>;
            ti,mbox-num-fifos = <0x0000000c>;
            status = "disabled";
        };
        mailbox@48864000 {
            compatible = "ti,omap4-mailbox";
            reg = <0x48864000 0x00000200>;
            interrupts = <0x00000000 0x00000115 0x00000004 0x00000000 0x00000116 0x00000004 0x00000000 0x00000117 0x00000004 0x00000000 0x00000118 0x00000004>;
            ti,hwmods = "mailbox12";
            #mbox-cells = <0x00000001>;
            ti,mbox-num-users = <0x00000004>;
            ti,mbox-num-fifos = <0x0000000c>;
            status = "disabled";
        };
        mailbox@48802000 {
            compatible = "ti,omap4-mailbox";
            reg = <0x48802000 0x00000200>;
            interrupts = <0x00000000 0x0000017b 0x00000004 0x00000000 0x0000017c 0x00000004 0x00000000 0x0000017d 0x00000004 0x00000000 0x0000017e 0x00000004>;
            ti,hwmods = "mailbox13";
            #mbox-cells = <0x00000001>;
            ti,mbox-num-users = <0x00000004>;
            ti,mbox-num-fifos = <0x0000000c>;
            status = "disabled";
        };
        timer@4ae18000 {
            compatible = "ti,omap5430-timer";
            reg = <0x4ae18000 0x00000080>;
            interrupts = <0x00000000 0x00000020 0x00000004>;
            ti,hwmods = "timer1";
            ti,timer-alwon;
        };
        timer@48032000 {
            compatible = "ti,omap5430-timer";
            reg = <0x48032000 0x00000080>;
            interrupts = <0x00000000 0x00000021 0x00000004>;
            ti,hwmods = "timer2";
        };
        timer@48034000 {
            compatible = "ti,omap5430-timer";
            reg = <0x48034000 0x00000080>;
            interrupts = <0x00000000 0x00000022 0x00000004>;
            ti,hwmods = "timer3";
            linux,phandle = <0x000000b8>;
            phandle = <0x000000b8>;
        };
        timer@48036000 {
            compatible = "ti,omap5430-timer";
            reg = <0x48036000 0x00000080>;
            interrupts = <0x00000000 0x00000023 0x00000004>;
            ti,hwmods = "timer4";
            linux,phandle = <0x000000b9>;
            phandle = <0x000000b9>;
        };
        timer@48820000 {
            compatible = "ti,omap5430-timer";
            reg = <0x48820000 0x00000080>;
            interrupts = <0x00000000 0x00000024 0x00000004>;
            ti,hwmods = "timer5";
            linux,phandle = <0x000000bf>;
            phandle = <0x000000bf>;
        };
        timer@48822000 {
            compatible = "ti,omap5430-timer";
            reg = <0x48822000 0x00000080>;
            interrupts = <0x00000000 0x00000025 0x00000004>;
            ti,hwmods = "timer6";
        };
        timer@48824000 {
            compatible = "ti,omap5430-timer";
            reg = <0x48824000 0x00000080>;
            interrupts = <0x00000000 0x00000026 0x00000004>;
            ti,hwmods = "timer7";
            linux,phandle = <0x000000b2>;
            phandle = <0x000000b2>;
        };
        timer@48826000 {
            compatible = "ti,omap5430-timer";
            reg = <0x48826000 0x00000080>;
            interrupts = <0x00000000 0x00000027 0x00000004>;
            ti,hwmods = "timer8";
            linux,phandle = <0x000000b3>;
            phandle = <0x000000b3>;
        };
        timer@4803e000 {
            compatible = "ti,omap5430-timer";
            reg = <0x4803e000 0x00000080>;
            interrupts = <0x00000000 0x00000028 0x00000004>;
            ti,hwmods = "timer9";
            linux,phandle = <0x000000ba>;
            phandle = <0x000000ba>;
        };
        timer@48086000 {
            compatible = "ti,omap5430-timer";
            reg = <0x48086000 0x00000080>;
            interrupts = <0x00000000 0x00000029 0x00000004>;
            ti,hwmods = "timer10";
            linux,phandle = <0x000000c0>;
            phandle = <0x000000c0>;
        };
        timer@48088000 {
            compatible = "ti,omap5430-timer";
            reg = <0x48088000 0x00000080>;
            interrupts = <0x00000000 0x0000002a 0x00000004>;
            ti,hwmods = "timer11";
            linux,phandle = <0x000000b1>;
            phandle = <0x000000b1>;
        };
        timer@4ae20000 {
            compatible = "ti,omap5430-timer";
            reg = <0x4ae20000 0x00000080>;
            interrupts = <0x00000000 0x0000005a 0x00000004>;
            ti,hwmods = "timer12";
            ti,timer-alwon;
            ti,timer-secure;
            status = "disabled";
        };
        timer@48828000 {
            compatible = "ti,omap5430-timer";
            reg = <0x48828000 0x00000080>;
            interrupts = <0x00000000 0x00000153 0x00000004>;
            ti,hwmods = "timer13";
            status = "disabled";
        };
        timer@4882a000 {
            compatible = "ti,omap5430-timer";
            reg = <0x4882a000 0x00000080>;
            interrupts = <0x00000000 0x00000154 0x00000004>;
            ti,hwmods = "timer14";
            status = "disabled";
        };
        timer@4882c000 {
            compatible = "ti,omap5430-timer";
            reg = <0x4882c000 0x00000080>;
            interrupts = <0x00000000 0x00000155 0x00000004>;
            ti,hwmods = "timer15";
            status = "disabled";
        };
        timer@4882e000 {
            compatible = "ti,omap5430-timer";
            reg = <0x4882e000 0x00000080>;
            interrupts = <0x00000000 0x00000156 0x00000004>;
            ti,hwmods = "timer16";
            status = "disabled";
        };
        wdt@4ae14000 {
            compatible = "ti,omap3-wdt";
            reg = <0x4ae14000 0x00000080>;
            interrupts = <0x00000000 0x0000004b 0x00000004>;
            ti,hwmods = "wd_timer2";
        };
        spinlock@4a0f6000 {
            compatible = "ti,omap4-hwspinlock";
            reg = <0x4a0f6000 0x00001000>;
            ti,hwmods = "spinlock";
            #hwlock-cells = <0x00000001>;
        };
        dmm@4e000000 {
            compatible = [74 69 2c 64 72 61 37 2d 64 6d 6d 00 74 69 2c 6f 6d 61 70 35 2d 64 6d 6d 00];
            reg = <0x4e000000 0x00000800>;
            interrupts = <0x00000000 0x0000006c 0x00000004>;
            ti,hwmods = "dmm";
        };
        ipu@58820000 {
            compatible = "ti,dra7-rproc-ipu";
            reg = <0x58820000 0x00010000>;
            reg-names = "l2ram";
            ti,hwmods = "ipu1";
            iommus = <0x000000ad>;
            ti,rproc-standby-info = <0x4a005520>;
            status = "okay";
            memory-region = <0x000000ae>;
            mboxes = <0x000000af 0x000000b0>;
            timers = <0x000000b1>;
            watchdog-timers = <0x000000b2 0x000000b3>;
        };
        ipu@55020000 {
            compatible = "ti,dra7-rproc-ipu";
            reg = <0x55020000 0x00010000>;
            reg-names = "l2ram";
            ti,hwmods = "ipu2";
            iommus = <0x000000b4>;
            ti,rproc-standby-info = <0x4a008920>;
            status = "okay";
            memory-region = <0x000000b5>;
            mboxes = <0x000000b6 0x000000b7>;
            timers = <0x000000b8>;
            watchdog-timers = <0x000000b9 0x000000ba>;
        };
        dsp@40800000 {
            compatible = "ti,dra7-rproc-dsp";
            reg = <0x40800000 0x00048000>;
            reg-names = "l2ram";
            ti,hwmods = "dsp1";
            iommus = <0x000000bb 0x000000bc>;
            ti,rproc-standby-info = <0x4a005420>;
            status = "okay";
            memory-region = <0x000000bd>;
            mboxes = <0x000000af 0x000000be>;
            timers = <0x000000bf>;
            watchdog-timers = <0x000000c0>;
        };
        gpu@0x56000000 {
            compatible = "ti,omap4-gpu";
            reg = <0x56000000 0x0000ffff>;
            interrupts = <0x00000000 0x00000010 0x00000004>;
            ti,hwmods = "gpu";
            operating-points = <0x00081e20 0x00138800>;
            clocks = <0x0000009a 0x0000009b 0x00000012 0x000000c1 0x000000c2>;
            clock-names = [63 6f 72 65 00 70 65 72 00 67 70 75 00 67 70 75 5f 63 6f 72 65 00 67 70 75 5f 68 79 64 00];
        };
        bb2d {
            compatible = "ti,bb2d";
            ti,hwmods = "bb2d";
            clocks = <0x000000c3>;
            clock-names = "fck";
            reg = <0x59000000 0x00000700>;
            interrupts = <0x00000000 0x00000078 0x00000004>;
        };
        i2c@48070000 {
            compatible = "ti,omap4-i2c";
            reg = <0x48070000 0x00000100>;
            interrupts = <0x00000000 0x00000033 0x00000004>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            ti,hwmods = "i2c1";
            status = "okay";
            clock-frequency = <0x000186a0>;
            tps65917@58 {
                compatible = "ti,tps65917";
                reg = <0x00000058>;
                pinctrl-names = "default";
                pinctrl-0 = <0x000000c4>;
                interrupts-extended = <0x00000001 0x00000000 0x00000002 0x00000000 0x000000ab 0x00000424>;
                interrupt-parent = <0x00000001>;
                interrupt-controller;
                #interrupt-cells = <0x00000002>;
                ti,system-power-controller;
                linux,phandle = <0x000000c5>;
                phandle = <0x000000c5>;
                tps65917_pmic {
                    compatible = "ti,tps65917-pmic";
                    regulators {
                        smps1 {
                            regulator-name = "smps1";
                            regulator-min-microvolt = <0x000cf850>;
                            regulator-max-microvolt = <0x0016e360>;
                            regulator-always-on;
                            regulator-boot-on;
                            linux,phandle = <0x000000de>;
                            phandle = <0x000000de>;
                        };
                        smps2 {
                            regulator-name = "smps2";
                            regulator-min-microvolt = <0x000cf850>;
                            regulator-max-microvolt = <0x0016e360>;
                            regulator-boot-on;
                            regulator-always-on;
                            linux,phandle = <0x000000e3>;
                            phandle = <0x000000e3>;
                        };
                        smps3 {
                            regulator-name = "smps3";
                            regulator-min-microvolt = <0x000cf850>;
                            regulator-max-microvolt = <0x0016e360>;
                            regulator-boot-on;
                            regulator-always-on;
                            linux,phandle = <0x000000e0>;
                            phandle = <0x000000e0>;
                        };
                        smps4 {
                            regulator-name = "smps4";
                            regulator-min-microvolt = <0x001b7740>;
                            regulator-max-microvolt = <0x001b7740>;
                            regulator-always-on;
                            regulator-boot-on;
                        };
                        smps5 {
                            regulator-name = "smps5";
                            regulator-min-microvolt = <0x00149970>;
                            regulator-max-microvolt = <0x00149970>;
                            regulator-boot-on;
                            regulator-always-on;
                        };
                        ldo1 {
                            regulator-name = "ldo1";
                            regulator-min-microvolt = <0x001b7740>;
                            regulator-max-microvolt = <0x00325aa0>;
                            regulator-always-on;
                            regulator-boot-on;
                            linux,phandle = <0x000000d6>;
                            phandle = <0x000000d6>;
                        };
                        ldo2 {
                            regulator-name = "ldo2";
                            regulator-min-microvolt = <0x001b7740>;
                            regulator-max-microvolt = <0x00325aa0>;
                        };
                        ldo3 {
                            regulator-name = "ldo3";
                            regulator-min-microvolt = <0x001b7740>;
                            regulator-max-microvolt = <0x001b7740>;
                            regulator-boot-on;
                            regulator-always-on;
                            linux,phandle = <0x00000105>;
                            phandle = <0x00000105>;
                        };
                        ldo5 {
                            regulator-name = "ldo5";
                            regulator-min-microvolt = <0x001b7740>;
                            regulator-max-microvolt = <0x001b7740>;
                            regulator-always-on;
                            regulator-boot-on;
                            linux,phandle = <0x00000102>;
                            phandle = <0x00000102>;
                        };
                        ldo4 {
                            regulator-name = "ldo4";
                            regulator-min-microvolt = <0x00325aa0>;
                            regulator-max-microvolt = <0x00325aa0>;
                            regulator-boot-on;
                            linux,phandle = <0x000000f4>;
                            phandle = <0x000000f4>;
                        };
                    };
                };
                tps65917_power_button {
                    compatible = "ti,palmas-pwrbutton";
                    interrupt-parent = <0x000000c5>;
                    interrupts = <0x00000001 0x00000000>;
                    wakeup-source;
                    ti,palmas-long-press-seconds = <0x00000006>;
                };
            };
            gpio@20 {
                compatible = "nxp,pcf8575";
                reg = <0x00000020>;
                gpio-controller;
                #gpio-cells = <0x00000002>;
            };
            gpio@27 {
                compatible = "nxp,pcf8575";
                reg = <0x00000027>;
                gpio-controller;
                #gpio-cells = <0x00000002>;
            };
            gpio@21 {
                compatible = "nxp,pcf8575";
                reg = <0x00000021>;
                lines-initial-states = <0x00001408>;
                gpio-controller;
                #gpio-cells = <0x00000002>;
                interrupt-parent = <0x000000c6>;
                interrupts = <0x0000000b 0x00000002>;
                interrupt-controller;
                #interrupt-cells = <0x00000002>;
                cpsw_sel_s0 {
                    gpio-hog;
                    gpios = <0x00000004 0x00000000>;
                    output-low;
                    status = "disabled";
                };
            };
            nvp6124@30 {
                compatible = "nvp6124";
                reg = <0x00000030>;
                ports {
                    #address-cells = <0x00000001>;
                    #size-cells = <0x00000000>;
                    port@0 {
                        #address-cells = <0x00000001>;
                        #size-cells = <0x00000000>;
                        reg = <0x00000000>;
                        endpoint@0 {
                            pclk-sample = <0x00000001>;
                            pixel-mux;
                            channels = <0x00000000>;
                            remote-endpoint = <0x000000c7>;
                            linux,phandle = <0x00000113>;
                            phandle = <0x00000113>;
                        };
                    };
                    port@1 {
                        reg = <0x00000001>;
                        endpoint@1 {
                            pclk-sample = <0x00000001>;
                            pixel-mux;
                            channels = <0x00000002>;
                            remote-endpoint = <0x000000c8>;
                            linux,phandle = <0x00000115>;
                            phandle = <0x00000115>;
                        };
                    };
                    port@2 {
                        reg = <0x00000002>;
                        endpoint {
                            pclk-sample = <0x00000001>;
                            pixel-mux;
                            channels = <0x00000004>;
                            remote-endpoint = <0x000000c9>;
                            linux,phandle = <0x00000114>;
                            phandle = <0x00000114>;
                        };
                    };
                    port@3 {
                        reg = <0x00000003>;
                        endpoint {
                            pclk-sample = <0x00000001>;
                            pixel-mux;
                            channels = <0x00000006>;
                            remote-endpoint = <0x000000ca>;
                            linux,phandle = <0x00000116>;
                            phandle = <0x00000116>;
                        };
                    };
                };
            };
        };
        i2c@48072000 {
            compatible = "ti,omap4-i2c";
            reg = <0x48072000 0x00000100>;
            interrupts = <0x00000000 0x00000034 0x00000004>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            ti,hwmods = "i2c2";
            status = "disabled";
        };
        i2c@48060000 {
            compatible = "ti,omap4-i2c";
            reg = <0x48060000 0x00000100>;
            interrupts = <0x00000000 0x00000038 0x00000004>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            ti,hwmods = "i2c3";
            status = "disabled";
        };
        i2c@4807a000 {
            compatible = "ti,omap4-i2c";
            reg = <0x4807a000 0x00000100>;
            interrupts = <0x00000000 0x00000039 0x00000004>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            ti,hwmods = "i2c4";
            status = "disabled";
        };
        i2c@4807c000 {
            compatible = "ti,omap4-i2c";
            reg = <0x4807c000 0x00000100>;
            interrupts = <0x00000000 0x00000037 0x00000004>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            ti,hwmods = "i2c5";
            status = "okay";
            clock-frequency = <0x00061a80>;
            serializer@0D {
                status = "okay";
                compatible = "ti,ds90uh925q";
                reg = <0x0000000d>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                ranges = <0x0000002c 0x0000002c 0x0000001c 0x0000001c>;
                tlc59108@40 {
                    status = "okay";
                    compatible = "ti,tlc59108-tfcs9700";
                    reg = <0x00000040>;
                    enable-gpios = <0x000000cb 0x00000013 0x00000000>;
                    port@lcd {
                        endpoint {
                            remote-endpoint = <0x000000cc>;
                            linux,phandle = <0x00000107>;
                            phandle = <0x00000107>;
                        };
                    };
                };
            };
            ldc3001@18 {
                compatible = "lgphilips,ldc3001";
                status = "okay";
                reg = <0x00000018>;
                interrupt-parent = <0x000000cd>;
                interrupts = <0x0000000f 0x00000004>;
                max-touch-points = <0x0000000a>;
                res-x = <0x00000500>;
                res-y = <0x00000320>;
            };
            hdmirec@31 {
                reg = <0x00000031>;
            };
            deserializer@60 {
                compatible = "ti,ds90ub914aq";
                reg = <0x00000060>;
                gpios = <0x000000cb 0x00000002 0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                ranges = <0x00000058 0x00000074 0x00000030 0x00000038>;
                serializer@74 {
                    compatible = "ti,ds90ub913aq";
                    reg = <0x00000058>;
                    slave-mode;
                };
                ov10635@38 {
                    compatible = "ovti,ov10635";
                    reg = <0x00000030>;
                    port {
                    };
                };
            };
            deserializer@64 {
                compatible = "ti,ds90ub914aq";
                reg = <0x00000064>;
                gpios = <0x000000cb 0x00000003 0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                ranges = <0x00000058 0x00000075 0x00000030 0x00000039>;
                serializer@75 {
                    compatible = "ti,ds90ub913aq";
                    reg = <0x00000058>;
                    slave-mode;
                };
                ov10635@39 {
                    compatible = "ovti,ov10635";
                    reg = <0x00000030>;
                    port {
                    };
                };
            };
            deserializer@68 {
                compatible = "ti,ds90ub914aq";
                reg = <0x00000068>;
                gpios = <0x000000cb 0x00000004 0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                ranges = <0x00000058 0x00000076 0x00000030 0x0000003a>;
                serializer@76 {
                    compatible = "ti,ds90ub913aq";
                    reg = <0x00000058>;
                    slave-mode;
                };
                ov10635@3a {
                    compatible = "ovti,ov10635";
                    reg = <0x00000030>;
                    port {
                    };
                };
            };
            deserializer@6c {
                compatible = "ti,ds90ub914aq";
                reg = <0x0000006c>;
                gpios = <0x000000cb 0x00000005 0x00000000>;
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                ranges = <0x00000058 0x00000077 0x00000030 0x0000003b>;
                serializer@77 {
                    compatible = "ti,ds90ub913aq";
                    reg = <0x00000058>;
                    slave-mode;
                };
                ov10635@3b {
                    compatible = "ovti,ov10635";
                    reg = <0x00000030>;
                    port {
                    };
                };
            };
        };
        mmc@4809c000 {
            compatible = [74 69 2c 64 72 61 37 2d 68 73 6d 6d 63 00 74 69 2c 6f 6d 61 70 34 2d 68 73 6d 6d 63 00];
            reg = <0x4809c000 0x00000400>;
            interrupts = <0x00000000 0x0000004e 0x00000004>;
            ti,hwmods = "mmc1";
            ti,dual-volt;
            ti,needs-special-reset;
            dmas = <0x000000ac 0x0000003d 0x000000ac 0x0000003e>;
            dma-names = [74 78 00 72 78 00];
            status = "okay";
            pbias-supply = <0x000000ce>;
            pinctrl-names = [64 65 66 61 75 6c 74 00 68 73 00 73 64 72 31 32 00 73 64 72 32 35 00 73 64 72 35 30 00 64 64 72 35 30 00 73 64 72 31 30 34 00];
            pinctrl-0 = <0x000000cf>;
            pinctrl-1 = <0x000000cf>;
            pinctrl-2 = <0x000000cf>;
            pinctrl-3 = <0x000000cf>;
            pinctrl-4 = <0x000000d0>;
            pinctrl-5 = <0x000000d1 0x000000d2>;
            pinctrl-6 = <0x000000d3 0x000000d4>;
            vmmc-supply = <0x000000d5>;
            vmmc_aux-supply = <0x000000d6>;
            bus-width = <0x00000004>;
            cd-gpios = <0x000000c6 0x0000001b 0x00000000>;
            sd-uhs-sdr104;
            sd-uhs-sdr50;
            sd-uhs-ddr50;
            sd-uhs-sdr25;
            sd-uhs-sdr12;
            max-frequency = <0x0b71b000>;
        };
        mmc@480b4000 {
            compatible = [74 69 2c 64 72 61 37 2d 68 73 6d 6d 63 00 74 69 2c 6f 6d 61 70 34 2d 68 73 6d 6d 63 00];
            reg = <0x480b4000 0x00000400>;
            interrupts = <0x00000000 0x00000051 0x00000004>;
            ti,hwmods = "mmc2";
            ti,needs-special-reset;
            dmas = <0x000000ac 0x0000002f 0x000000ac 0x00000030>;
            dma-names = [74 78 00 72 78 00];
            status = "okay";
            pinctrl-names = [64 65 66 61 75 6c 74 00 68 73 00 64 64 72 5f 33 5f 33 76 00 68 73 32 30 30 00];
            pinctrl-0 = <0x000000d7>;
            pinctrl-1 = <0x000000d7>;
            pinctrl-2 = <0x000000d8 0x000000d9>;
            pinctrl-3 = <0x000000da 0x000000db>;
            vmmc-supply = <0x000000dc>;
            bus-width = <0x00000008>;
            ti,non-removable;
            mmc-hs200-1_8v;
            max-frequency = <0x0b71b000>;
        };
        mmc@480ad000 {
            compatible = [74 69 2c 64 72 61 37 2d 68 73 6d 6d 63 00 74 69 2c 6f 6d 61 70 34 2d 68 73 6d 6d 63 00];
            reg = <0x480ad000 0x00000400>;
            interrupts = <0x00000000 0x00000059 0x00000004>;
            ti,hwmods = "mmc3";
            ti,needs-special-reset;
            dmas = <0x000000ac 0x0000004d 0x000000ac 0x0000004e>;
            dma-names = [74 78 00 72 78 00];
            status = "disabled";
        };
        mmc@480d1000 {
            compatible = [74 69 2c 64 72 61 37 2d 68 73 6d 6d 63 00 74 69 2c 6f 6d 61 70 34 2d 68 73 6d 6d 63 00];
            reg = <0x480d1000 0x00000400>;
            interrupts = <0x00000000 0x0000005b 0x00000004>;
            ti,hwmods = "mmc4";
            ti,needs-special-reset;
            dmas = <0x000000ac 0x00000039 0x000000ac 0x0000003a>;
            dma-names = [74 78 00 72 78 00];
            status = "disabled";
        };
        mmu@40d01000 {
            compatible = "ti,dra7-iommu";
            reg = <0x40d01000 0x00000100 0x40d00000 0x00000100>;
            reg-names = [6d 6d 75 5f 63 66 67 00 64 73 70 5f 73 79 73 74 65 6d 00];
            interrupts = <0x00000000 0x00000017 0x00000004>;
            ti,hwmods = "mmu0_dsp1";
            status = "okay";
            linux,phandle = <0x000000bb>;
            phandle = <0x000000bb>;
        };
        mmu@40d02000 {
            compatible = "ti,dra7-iommu";
            reg = <0x40d02000 0x00000100 0x40d00000 0x00000100>;
            reg-names = [6d 6d 75 5f 63 66 67 00 64 73 70 5f 73 79 73 74 65 6d 00];
            interrupts = <0x00000000 0x00000091 0x00000004>;
            ti,hwmods = "mmu1_dsp1";
            status = "okay";
            linux,phandle = <0x000000bc>;
            phandle = <0x000000bc>;
        };
        mmu@58882000 {
            compatible = "ti,dra7-iommu";
            reg = <0x58882000 0x00000100>;
            reg-names = "mmu_cfg";
            interrupts = <0x00000000 0x0000018b 0x00000004>;
            ti,hwmods = "mmu_ipu1";
            ti,iommu-bus-err-back;
            status = "okay";
            linux,phandle = <0x000000ad>;
            phandle = <0x000000ad>;
        };
        mmu@55082000 {
            compatible = "ti,dra7-iommu";
            reg = <0x55082000 0x00000100>;
            reg-names = "mmu_cfg";
            interrupts = <0x00000000 0x0000018c 0x00000004>;
            ti,hwmods = "mmu_ipu2";
            ti,iommu-bus-err-back;
            status = "okay";
            linux,phandle = <0x000000b4>;
            phandle = <0x000000b4>;
        };
        pruss@4b200000 {
            compatible = "ti,am5728-pruss";
            ti,hwmods = "pruss1";
            reg = <0x4b200000 0x00002000 0x4b202000 0x00002000 0x4b210000 0x00008000 0x4b220000 0x00002000 0x4b226000 0x00002000>;
            reg-names = [64 72 61 6d 30 00 64 72 61 6d 31 00 73 68 72 64 72 61 6d 32 00 69 6e 74 63 00 63 66 67 00];
            interrupts = <0x00000000 0x000000ba 0x00000004 0x00000000 0x000000bb 0x00000004 0x00000000 0x000000bc 0x00000004 0x00000000 0x000000bd 0x00000004 0x00000000 0x000000be 0x00000004 0x00000000 0x000000bf 0x00000004 0x00000000 0x000000c0 0x00000004 0x00000000 0x000000c1 0x00000004>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000001>;
            ranges;
            status = "disabled";
            pru@4b234000 {
                compatible = "ti,pru-rproc";
                reg = <0x4b234000 0x00003000 0x4b222000 0x00000400 0x4b222400 0x00000100>;
                reg-names = [69 72 61 6d 00 63 6f 6e 74 72 6f 6c 00 64 65 62 75 67 00];
                status = "disabled";
            };
            pru@4b238000 {
                compatible = "ti,pru-rproc";
                reg = <0x4b238000 0x00003000 0x4b224000 0x00000400 0x4b224400 0x00000100>;
                reg-names = [69 72 61 6d 00 63 6f 6e 74 72 6f 6c 00 64 65 62 75 67 00];
                status = "disabled";
            };
        };
        pruss@4b280000 {
            compatible = "ti,am5728-pruss";
            ti,hwmods = "pruss2";
            reg = <0x4b280000 0x00002000 0x4b282000 0x00002000 0x4b290000 0x00008000 0x4b2a0000 0x00002000 0x4b2a6000 0x00002000>;
            reg-names = [64 72 61 6d 30 00 64 72 61 6d 31 00 73 68 72 64 72 61 6d 32 00 69 6e 74 63 00 63 66 67 00];
            interrupts = <0x00000000 0x000000c4 0x00000004 0x00000000 0x000000c5 0x00000004 0x00000000 0x000000c6 0x00000004 0x00000000 0x000000c7 0x00000004 0x00000000 0x000000c8 0x00000004 0x00000000 0x000000c9 0x00000004 0x00000000 0x000000ca 0x00000004 0x00000000 0x000000cb 0x00000004>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000001>;
            ranges;
            status = "disabled";
            pru@4b2b4000 {
                compatible = "ti,pru-rproc";
                reg = <0x4b2b4000 0x00003000 0x4b2a2000 0x00000400 0x4b2a2400 0x00000100>;
                reg-names = [69 72 61 6d 00 63 6f 6e 74 72 6f 6c 00 64 65 62 75 67 00];
                status = "disabled";
            };
            pru@4b2b8000 {
                compatible = "ti,pru-rproc";
                reg = <0x4b2b8000 0x00003000 0x4b2a4000 0x00000400 0x4b2a4400 0x00000100>;
                reg-names = [69 72 61 6d 00 63 6f 6e 74 72 6f 6c 00 64 65 62 75 67 00];
                status = "disabled";
            };
        };
        regulator-abb-mpu {
            compatible = "ti,abb-v3";
            regulator-name = "abb_mpu";
            #address-cells = <0x00000000>;
            #size-cells = <0x00000000>;
            clocks = <0x00000009>;
            ti,settling-time = <0x00000032>;
            ti,clock-cycles = <0x00000010>;
            reg = <0x4ae07ddc 0x00000004 0x4ae07de0 0x00000004 0x4ae06014 0x00000004 0x4a003b20 0x0000000c 0x4ae0c158 0x00000004>;
            reg-names = <0x73657475 0x702d6164 0x64726573 0x7300636f 0x6e74726f 0x6c2d6164 0x64726573 0x7300696e 0x742d6164 0x64726573 0x73006566 0x7573652d 0x61646472 0x65737300 0x6c646f2d 0x61646472 0x65737300>;
            ti,tranxdone-status-mask = <0x00000080>;
            ti,ldovbb-override-mask = <0x00000400>;
            ti,ldovbb-vset-mask = <0x0000001f>;
            ti,abb_info = <0x0010c8e0 0x00000000 0x00000000 0x00000000 0x02000000 0x01f00000 0x0011b340 0x00000000 0x00000004 0x00000000 0x02000000 0x01f00000 0x00127690 0x00000000 0x00000008 0x00000000 0x02000000 0x01f00000>;
            linux,phandle = <0x000000dd>;
            phandle = <0x000000dd>;
        };
        regulator-abb-ivahd {
            compatible = "ti,abb-v3";
            regulator-name = "abb_ivahd";
            #address-cells = <0x00000000>;
            #size-cells = <0x00000000>;
            clocks = <0x00000009>;
            ti,settling-time = <0x00000032>;
            ti,clock-cycles = <0x00000010>;
            reg = <0x4ae07e34 0x00000004 0x4ae07e24 0x00000004 0x4ae06010 0x00000004 0x4a0025cc 0x0000000c 0x4a002470 0x00000004>;
            reg-names = <0x73657475 0x702d6164 0x64726573 0x7300636f 0x6e74726f 0x6c2d6164 0x64726573 0x7300696e 0x742d6164 0x64726573 0x73006566 0x7573652d 0x61646472 0x65737300 0x6c646f2d 0x61646472 0x65737300>;
            ti,tranxdone-status-mask = <0x40000000>;
            ti,ldovbb-override-mask = <0x00000400>;
            ti,ldovbb-vset-mask = <0x0000001f>;
            ti,abb_info = <0x00102ca0 0x00000000 0x00000000 0x00000000 0x02000000 0x01f00000 0x00118c30 0x00000000 0x00000004 0x00000000 0x02000000 0x01f00000 0x001312d0 0x00000000 0x00000008 0x00000000 0x02000000 0x01f00000>;
            linux,phandle = <0x000000df>;
            phandle = <0x000000df>;
        };
        regulator-abb-dspeve {
            compatible = "ti,abb-v3";
            regulator-name = "abb_dspeve";
            #address-cells = <0x00000000>;
            #size-cells = <0x00000000>;
            clocks = <0x00000009>;
            ti,settling-time = <0x00000032>;
            ti,clock-cycles = <0x00000010>;
            reg = <0x4ae07e30 0x00000004 0x4ae07e20 0x00000004 0x4ae06010 0x00000004 0x4a0025e0 0x0000000c 0x4a00246c 0x00000004>;
            reg-names = <0x73657475 0x702d6164 0x64726573 0x7300636f 0x6e74726f 0x6c2d6164 0x64726573 0x7300696e 0x742d6164 0x64726573 0x73006566 0x7573652d 0x61646472 0x65737300 0x6c646f2d 0x61646472 0x65737300>;
            ti,tranxdone-status-mask = <0x20000000>;
            ti,ldovbb-override-mask = <0x00000400>;
            ti,ldovbb-vset-mask = <0x0000001f>;
            ti,abb_info = <0x00102ca0 0x00000000 0x00000000 0x00000000 0x02000000 0x01f00000 0x00118c30 0x00000000 0x00000004 0x00000000 0x02000000 0x01f00000 0x001312d0 0x00000000 0x00000008 0x00000000 0x02000000 0x01f00000>;
            linux,phandle = <0x000000e1>;
            phandle = <0x000000e1>;
        };
        regulator-abb-gpu {
            compatible = "ti,abb-v3";
            regulator-name = "abb_gpu";
            #address-cells = <0x00000000>;
            #size-cells = <0x00000000>;
            clocks = <0x00000009>;
            ti,settling-time = <0x00000032>;
            ti,clock-cycles = <0x00000010>;
            reg = <0x4ae07de4 0x00000004 0x4ae07de8 0x00000004 0x4ae06010 0x00000004 0x4a003b08 0x0000000c 0x4ae0c154 0x00000004>;
            reg-names = <0x73657475 0x702d6164 0x64726573 0x7300636f 0x6e74726f 0x6c2d6164 0x64726573 0x7300696e 0x742d6164 0x64726573 0x73006566 0x7573652d 0x61646472 0x65737300 0x6c646f2d 0x61646472 0x65737300>;
            ti,tranxdone-status-mask = <0x10000000>;
            ti,ldovbb-override-mask = <0x00000400>;
            ti,ldovbb-vset-mask = <0x0000001f>;
            ti,abb_info = <0x00102ca0 0x00000000 0x00000000 0x00000000 0x02000000 0x01f00000 0x00127690 0x00000000 0x00000004 0x00000000 0x02000000 0x01f00000 0x00138800 0x00000000 0x00000008 0x00000000 0x02000000 0x01f00000>;
            linux,phandle = <0x000000e2>;
            phandle = <0x000000e2>;
        };
        voltdm@4a003b20 {
            compatible = "ti,omap5-voltdm";
            #voltdm-cells = <0x00000000>;
            vbb-supply = <0x000000dd>;
            reg = <0x4a003b20 0x0000000c>;
            ti,efuse-settings = <0x0010c8e0 0x00000000 0x0011b340 0x00000004 0x00127690 0x00000008>;
            ti,absolute-max-voltage-uv = <0x0016e360>;
            vdd-supply = <0x000000de>;
            linux,phandle = <0x00000117>;
            phandle = <0x00000117>;
        };
        voltdm@4a0025cc {
            compatible = "ti,omap5-voltdm";
            #voltdm-cells = <0x00000000>;
            vbb-supply = <0x000000df>;
            reg = <0x4a0025cc 0x0000000c>;
            ti,efuse-settings = <0x00102ca0 0x00000000 0x00118c30 0x00000004 0x001312d0 0x00000008>;
            ti,absolute-max-voltage-uv = <0x0016e360>;
            vdd-supply = <0x000000e0>;
            linux,phandle = <0x00000118>;
            phandle = <0x00000118>;
        };
        voltdm@4a0025e0 {
            compatible = "ti,omap5-voltdm";
            #voltdm-cells = <0x00000000>;
            vbb-supply = <0x000000e1>;
            reg = <0x4a0025e0 0x0000000c>;
            ti,efuse-settings = <0x00102ca0 0x00000000 0x00118c30 0x00000004 0x001312d0 0x00000008>;
            ti,absolute-max-voltage-uv = <0x0016e360>;
            vdd-supply = <0x000000e0>;
            linux,phandle = <0x00000119>;
            phandle = <0x00000119>;
        };
        voltdm@4a003b08 {
            compatible = "ti,omap5-voltdm";
            #voltdm-cells = <0x00000000>;
            vbb-supply = <0x000000e2>;
            reg = <0x4a003b08 0x0000000c>;
            ti,efuse-settings = <0x00102ca0 0x00000000 0x00127690 0x00000004 0x00138800 0x00000008>;
            ti,absolute-max-voltage-uv = <0x0016e360>;
            vdd-supply = <0x000000e0>;
        };
        voltdm@4a0025f4 {
            compatible = "ti,omap5-core-voltdm";
            #voltdm-cells = <0x00000000>;
            reg = <0x4a0025f4 0x00000004>;
            ti,efuse-settings = <0x00102ca0 0x00000000>;
            ti,absolute-max-voltage-uv = <0x0016e360>;
            vdd-supply = <0x000000e3>;
        };
        spi@48098000 {
            compatible = "ti,omap4-mcspi";
            reg = <0x48098000 0x00000200>;
            interrupts = <0x00000000 0x0000003c 0x00000004>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            ti,hwmods = "mcspi1";
            ti,spi-num-cs = <0x00000004>;
            dmas = <0x000000ac 0x00000023 0x000000ac 0x00000024 0x000000ac 0x00000025 0x000000ac 0x00000026 0x000000ac 0x00000027 0x000000ac 0x00000028 0x000000ac 0x00000029 0x000000ac 0x0000002a>;
            dma-names = <0x74783000 0x72783000 0x74783100 0x72783100 0x74783200 0x72783200 0x74783300 0x72783300>;
            status = "disabled";
        };
        spi@4809a000 {
            compatible = "ti,omap4-mcspi";
            reg = <0x4809a000 0x00000200>;
            interrupts = <0x00000000 0x0000003d 0x00000004>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            ti,hwmods = "mcspi2";
            ti,spi-num-cs = <0x00000002>;
            dmas = <0x000000ac 0x0000002b 0x000000ac 0x0000002c 0x000000ac 0x0000002d 0x000000ac 0x0000002e>;
            dma-names = <0x74783000 0x72783000 0x74783100 0x72783100>;
            status = "disabled";
        };
        spi@480b8000 {
            compatible = "ti,omap4-mcspi";
            reg = <0x480b8000 0x00000200>;
            interrupts = <0x00000000 0x00000056 0x00000004>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            ti,hwmods = "mcspi3";
            ti,spi-num-cs = <0x00000002>;
            dmas = <0x000000ac 0x0000000f 0x000000ac 0x00000010>;
            dma-names = <0x74783000 0x72783000>;
            status = "disabled";
        };
        spi@480ba000 {
            compatible = "ti,omap4-mcspi";
            reg = <0x480ba000 0x00000200>;
            interrupts = <0x00000000 0x0000002b 0x00000004>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            ti,hwmods = "mcspi4";
            ti,spi-num-cs = <0x00000001>;
            dmas = <0x000000ac 0x00000046 0x000000ac 0x00000047>;
            dma-names = <0x74783000 0x72783000>;
            status = "disabled";
        };
        qspi@4b300000 {
            compatible = "ti,dra7xxx-qspi";
            reg = <0x4b300000 0x00000100 0x4a002558 0x00000004 0x5c000000 0x03ffffff>;
            reg-names = [71 73 70 69 5f 62 61 73 65 00 71 73 70 69 5f 63 74 72 6c 6d 6f 64 00 71 73 70 69 5f 6d 6d 61 70 00];
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            ti,hwmods = "qspi";
            clocks = <0x000000e4>;
            clock-names = "fck";
            num-cs = <0x00000004>;
            interrupts = <0x00000000 0x00000157 0x00000004>;
            status = "disabled";
        };
        control-phy@4a002374 {
            compatible = "ti,control-phy-pipe3";
            reg = <0x4a002374 0x00000004>;
            reg-names = "power";
            clocks = <0x00000009>;
            clock-names = "sysclk";
            linux,phandle = <0x000000e5>;
            phandle = <0x000000e5>;
        };
        ocp2scp@4a090000 {
            compatible = "ti,omap-ocp2scp";
            #address-cells = <0x00000001>;
            #size-cells = <0x00000001>;
            ranges;
            reg = <0x4a090000 0x00000020>;
            ti,hwmods = "ocp2scp3";
            phy@4A096000 {
                compatible = "ti,phy-pipe3-sata";
                reg = <0x4a096000 0x00000080 0x4a096400 0x00000064 0x4a096800 0x00000040>;
                reg-names = [70 68 79 5f 72 78 00 70 68 79 5f 74 78 00 70 6c 6c 5f 63 74 72 6c 00];
                ctrl-module = <0x000000e5>;
                clocks = <0x00000009 0x000000e6>;
                clock-names = [73 79 73 63 6c 6b 00 72 65 66 63 6c 6b 00];
                syscon-pllreset = <0x000000e7 0x000003fc>;
                #phy-cells = <0x00000000>;
                linux,phandle = <0x000000f0>;
                phandle = <0x000000f0>;
            };
            pciephy@4a094000 {
                compatible = "ti,phy-pipe3-pcie";
                reg = <0x4a094000 0x00000080 0x4a094400 0x00000064>;
                reg-names = [70 68 79 5f 72 78 00 70 68 79 5f 74 78 00];
                ctrl-module = <0x000000e8>;
                clocks = <0x00000082 0x00000083 0x000000e9 0x000000ea 0x000000eb 0x00000087>;
                clock-names = <0x64706c6c 0x5f726566 0x0064706c 0x6c5f7265 0x665f6d32 0x00776b75 0x70636c6b 0x00726566 0x636c6b00 0x6469762d 0x636c6b00 0x7068792d 0x64697600>;
                #phy-cells = <0x00000000>;
                linux,phandle = <0x00000040>;
                phandle = <0x00000040>;
            };
            pciephy@4a095000 {
                compatible = "ti,phy-pipe3-pcie";
                reg = <0x4a095000 0x00000080 0x4a095400 0x00000064>;
                reg-names = [70 68 79 5f 72 78 00 70 68 79 5f 74 78 00];
                ctrl-module = <0x000000ec>;
                clocks = <0x00000082 0x00000083 0x000000ed 0x000000ee 0x000000ef 0x00000087>;
                clock-names = <0x64706c6c 0x5f726566 0x0064706c 0x6c5f7265 0x665f6d32 0x00776b75 0x70636c6b 0x00726566 0x636c6b00 0x6469762d 0x636c6b00 0x7068792d 0x64697600>;
                #phy-cells = <0x00000000>;
                status = "disabled";
                linux,phandle = <0x00000042>;
                phandle = <0x00000042>;
            };
        };
        sata@4a141100 {
            compatible = "snps,dwc-ahci";
            reg = <0x4a140000 0x00001100 0x4a141100 0x00000007>;
            interrupts = <0x00000000 0x00000031 0x00000004>;
            phys = <0x000000f0>;
            phy-names = "sata-phy";
            ti,hwmods = "sata";
        };
        control-phy@0x4a003c40 {
            compatible = "ti,control-phy-pcie";
            reg = <0x4a003c40 0x00000004 0x4a003c14 0x00000004 0x4a003c34 0x00000004>;
            reg-names = [70 6f 77 65 72 00 63 6f 6e 74 72 6f 6c 5f 73 6d 61 00 70 63 69 65 5f 70 63 73 00];
            clocks = <0x00000009>;
            clock-names = "sysclk";
            linux,phandle = <0x000000e8>;
            phandle = <0x000000e8>;
        };
        control-pcie@0x4a003c44 {
            compatible = "ti,control-phy-pcie";
            reg = <0x4a003c44 0x00000004 0x4a003c14 0x00000004 0x4a003c34 0x00000004>;
            reg-names = [70 6f 77 65 72 00 63 6f 6e 74 72 6f 6c 5f 73 6d 61 00 70 63 69 65 5f 70 63 73 00];
            clocks = <0x00000009>;
            clock-names = "sysclk";
            status = "disabled";
            linux,phandle = <0x000000ec>;
            phandle = <0x000000ec>;
        };
        rtcss@48838000 {
            compatible = "ti,am3352-rtc";
            reg = <0x48838000 0x00000100>;
            interrupts = <0x00000000 0x000000d9 0x00000004 0x00000000 0x000000d9 0x00000004>;
            ti,hwmods = "rtcss";
            clocks = <0x0000000c>;
        };
        control-phy@4a002300 {
            compatible = "ti,control-phy-usb2";
            reg = <0x4a002300 0x00000004>;
            reg-names = "power";
            linux,phandle = <0x000000f1>;
            phandle = <0x000000f1>;
        };
        control-phy@4a002370 {
            compatible = "ti,control-phy-pipe3";
            reg = <0x4a002370 0x00000004>;
            reg-names = "power";
            linux,phandle = <0x000000f8>;
            phandle = <0x000000f8>;
        };
        control-phy@0x4a002e74 {
            compatible = "ti,control-phy-usb2-dra7";
            reg = <0x4a002e74 0x00000004>;
            reg-names = "power";
            linux,phandle = <0x000000f5>;
            phandle = <0x000000f5>;
        };
        ocp2scp@4a080000 {
            compatible = "ti,omap-ocp2scp";
            #address-cells = <0x00000001>;
            #size-cells = <0x00000001>;
            ranges;
            reg = <0x4a080000 0x00000020>;
            ti,hwmods = "ocp2scp1";
            phy@4a084000 {
                compatible = "ti,dra7x-usb2";
                reg = <0x4a084000 0x00000400>;
                ctrl-module = <0x000000f1>;
                clocks = <0x000000f2 0x000000f3>;
                clock-names = [77 6b 75 70 63 6c 6b 00 72 65 66 63 6c 6b 00];
                #phy-cells = <0x00000000>;
                phy-supply = <0x000000f4>;
                linux,phandle = <0x000000fa>;
                phandle = <0x000000fa>;
            };
            phy@4a085000 {
                compatible = "ti,dra7x-usb2";
                reg = <0x4a085000 0x00000400>;
                ctrl-module = <0x000000f5>;
                clocks = <0x000000f6 0x000000f7>;
                clock-names = [77 6b 75 70 63 6c 6b 00 72 65 66 63 6c 6b 00];
                #phy-cells = <0x00000000>;
                linux,phandle = <0x000000fc>;
                phandle = <0x000000fc>;
            };
            phy@4a084400 {
                compatible = "ti,omap-usb3";
                reg = <0x4a084400 0x00000080 0x4a084800 0x00000064 0x4a084c00 0x00000040>;
                reg-names = [70 68 79 5f 72 78 00 70 68 79 5f 74 78 00 70 6c 6c 5f 63 74 72 6c 00];
                ctrl-module = <0x000000f8>;
                clocks = <0x000000f9 0x00000009 0x000000f3>;
                clock-names = [77 6b 75 70 63 6c 6b 00 73 79 73 63 6c 6b 00 72 65 66 63 6c 6b 00];
                #phy-cells = <0x00000000>;
                linux,phandle = <0x000000fb>;
                phandle = <0x000000fb>;
            };
        };
        omap_dwc3_1@48880000 {
            compatible = "ti,dwc3";
            ti,hwmods = "usb_otg_ss1";
            reg = <0x48880000 0x00010000>;
            interrupts = <0x00000000 0x00000048 0x00000004>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000001>;
            utmi-mode = <0x00000002>;
            ranges;
            usb@48890000 {
                compatible = "snps,dwc3";
                reg = <0x48890000 0x00017000>;
                interrupts = <0x00000000 0x00000047 0x00000004 0x00000000 0x00000047 0x00000004 0x00000000 0x00000048 0x00000004>;
                interrupt-names = <0x70657269 0x70686572 0x616c0068 0x6f737400 0x6f746700>;
                phys = <0x000000fa 0x000000fb>;
                phy-names = [75 73 62 32 2d 70 68 79 00 75 73 62 33 2d 70 68 79 00];
                tx-fifo-resize;
                maximum-speed = "super-speed";
                dr_mode = "host";
                snps,dis_u3_susphy_quirk;
                snps,dis_u2_susphy_quirk;
            };
        };
        omap_dwc3_2@488c0000 {
            compatible = "ti,dwc3";
            ti,hwmods = "usb_otg_ss2";
            reg = <0x488c0000 0x00010000>;
            interrupts = <0x00000000 0x00000057 0x00000004>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000001>;
            utmi-mode = <0x00000002>;
            ranges;
            usb@488d0000 {
                compatible = "snps,dwc3";
                reg = <0x488d0000 0x00017000>;
                interrupts = <0x00000000 0x00000049 0x00000004 0x00000000 0x00000049 0x00000004 0x00000000 0x00000057 0x00000004>;
                interrupt-names = <0x70657269 0x70686572 0x616c0068 0x6f737400 0x6f746700>;
                phys = <0x000000fc>;
                phy-names = "usb2-phy";
                tx-fifo-resize;
                maximum-speed = "high-speed";
                dr_mode = "otg";
                snps,dis_u3_susphy_quirk;
                snps,dis_u2_susphy_quirk;
            };
        };
        omap_dwc3_3@48900000 {
            compatible = "ti,dwc3";
            ti,hwmods = "usb_otg_ss3";
            reg = <0x48900000 0x00010000>;
            interrupts = <0x00000000 0x00000158 0x00000004>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000001>;
            utmi-mode = <0x00000002>;
            ranges;
            status = "disabled";
            usb@48910000 {
                compatible = "snps,dwc3";
                reg = <0x48910000 0x00017000>;
                interrupts = <0x00000000 0x00000058 0x00000004 0x00000000 0x00000058 0x00000004 0x00000000 0x00000158 0x00000004>;
                interrupt-names = <0x70657269 0x70686572 0x616c0068 0x6f737400 0x6f746700>;
                tx-fifo-resize;
                maximum-speed = "high-speed";
                dr_mode = "otg";
                snps,dis_u3_susphy_quirk;
                snps,dis_u2_susphy_quirk;
            };
        };
        omap_dwc3_4@48940000 {
            compatible = "ti,dwc3";
            ti,hwmods = "usb_otg_ss4";
            reg = <0x48940000 0x00010000>;
            interrupts = <0x00000000 0x0000015a 0x00000004>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000001>;
            utmi-mode = <0x00000002>;
            ranges;
            status = "disabled";
            usb@48950000 {
                compatible = "snps,dwc3";
                reg = <0x48950000 0x00017000>;
                interrupts = <0x00000000 0x00000159 0x00000004 0x00000000 0x00000159 0x00000004 0x00000000 0x0000015a 0x00000004>;
                interrupt-names = <0x70657269 0x70686572 0x616c0068 0x6f737400 0x6f746700>;
                tx-fifo-resize;
                maximum-speed = "high-speed";
                dr_mode = "otg";
            };
        };
        atl@4843c000 {
            compatible = "ti,dra7-atl";
            reg = <0x4843c000 0x000003ff>;
            ti,hwmods = "atl";
            ti,provided-clocks = <0x00000079 0x00000078 0x00000077 0x00000076>;
            clocks = <0x00000044>;
            clock-names = "fck";
            status = "okay";
            atl2 {
                bws = <0x00000003>;
                aws = <0x00000004>;
            };
        };
        crossbar@4a020000 {
            compatible = "ti,irq-crossbar";
            reg = <0x4a002a48 0x00000130>;
            ti,max-irqs = <0x000000a0>;
            ti,max-crossbar-sources = <0x00000190>;
            ti,reg-size = <0x00000002>;
            ti,irqs-reserved = <0x00000000 0x00000001 0x00000002 0x00000003 0x00000005 0x00000006 0x00000083 0x00000084>;
            ti,irqs-skip = <0x0000000a 0x00000085 0x0000008b 0x0000008c>;
            ti,irqs-safe-map = <0x00000000>;
        };
        ethernet@48484000 {
            compatible = "ti,cpsw";
            ti,hwmods = "gmac";
            clocks = <0x00000063 0x000000fd>;
            clock-names = [66 63 6b 00 63 70 74 73 00];
            cpdma_channels = <0x00000008>;
            ale_entries = <0x00000400>;
            bd_ram_size = <0x00002000>;
            no_bd_ram = <0x00000000>;
            rx_descs = <0x00000040>;
            mac_control = <0x00000020>;
            slaves = <0x00000001>;
            active_slave = <0x00000000>;
            cpts_clock_mult = <0x80000000>;
            cpts_clock_shift = <0x0000001d>;
            reg = <0x48484000 0x00001000 0x48485200 0x00000e00>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000001>;
            interrupts = <0x00000000 0x0000014e 0x00000004 0x00000000 0x0000014f 0x00000004 0x00000000 0x00000150 0x00000004 0x00000000 0x00000151 0x00000004>;
            ranges;
            status = "okay";
            ti,no-idle;
            mdio@48485000 {
                compatible = "ti,davinci_mdio";
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                ti,hwmods = "davinci_mdio";
                bus_freq = <0x000f4240>;
                reg = <0x48485000 0x00000100>;
                linux,phandle = <0x000000fe>;
                phandle = <0x000000fe>;
            };
            slave@48480200 {
                mac-address = [00 00 00 00 00 00];
                phy_id = <0x000000fe 0x00000003>;
                phy-mode = "rgmii";
            };
            slave@48480300 {
                mac-address = [00 00 00 00 00 00];
            };
            cpsw-phy-sel@4a002554 {
                compatible = "ti,dra7xx-cpsw-phy-sel";
                reg = <0x4a002554 0x00000004>;
                reg-names = "gmii-sel";
            };
        };
        vpe {
            compatible = "ti,vpe";
            ti,hwmods = "vpe";
            clocks = <0x000000a4>;
            clock-names = "fck";
            reg = <0x489d0000 0x00000120 0x489d0300 0x00000020 0x489d0400 0x00000020 0x489d0500 0x00000020 0x489d0600 0x0000003c 0x489d0700 0x00000080 0x489d5700 0x00000018 0x489dd000 0x00000400>;
            reg-names = [76 70 65 5f 74 6f 70 00 76 70 65 5f 63 68 72 5f 75 73 30 00 76 70 65 5f 63 68 72 5f 75 73 31 00 76 70 65 5f 63 68 72 5f 75 73 32 00 76 70 65 5f 64 65 69 00 73 63 00 63 73 63 00 76 70 64 6d 61 00];
            interrupts = <0x00000000 0x00000162 0x00000004>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
        };
        elm@48078000 {
            compatible = "ti,am3352-elm";
            reg = <0x48078000 0x00000fc0>;
            interrupts = <0x00000000 0x00000001 0x00000004>;
            ti,hwmods = "elm";
            status = "okay";
        };
        gpmc@50000000 {
            compatible = "ti,am3352-gpmc";
            ti,hwmods = "gpmc";
            reg = <0x50000000 0x0000037c>;
            interrupts = <0x00000000 0x0000000f 0x00000004>;
            gpmc,num-cs = <0x00000008>;
            gpmc,num-waitpins = <0x00000002>;
            #address-cells = <0x00000002>;
            #size-cells = <0x00000001>;
            status = "disabled";
        };
        dss@58000000 {
            compatible = "ti,dra7-dss";
            reg = <0x58000000 0x00000080 0x58004054 0x00000004 0x58004300 0x00000020 0x58009054 0x00000004 0x58009300 0x00000020>;
            reg-names = <0x64737300 0x706c6c31 0x5f636c6b 0x6374726c 0x00706c6c 0x3100706c 0x6c325f63 0x6c6b6374 0x726c0070 0x6c6c3200>;
            status = "ok";
            ti,hwmods = "dss_core";
            clocks = <0x000000ff 0x00000100 0x00000101>;
            clock-names = [66 63 6b 00 76 69 64 65 6f 31 5f 63 6c 6b 00 76 69 64 65 6f 32 5f 63 6c 6b 00];
            syscon = <0x000000e7>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000001>;
            ranges;
            vdda_video-supply = <0x00000102>;
            dispc@58001000 {
                compatible = "ti,dra7-dispc";
                reg = <0x58001000 0x00001000>;
                interrupts = <0x00000000 0x00000014 0x00000004>;
                ti,hwmods = "dss_dispc";
                clocks = <0x000000ff>;
                clock-names = "fck";
                syscon = <0x000000e7>;
            };
            encoder@58060000 {
                compatible = "ti,dra7-hdmi";
                reg = <0x58040000 0x00000200 0x58040200 0x00000080 0x58040300 0x00000080 0x58060000 0x00019000>;
                reg-names = <0x77700070 0x6c6c0070 0x68790063 0x6f726500>;
                interrupts = <0x00000000 0x00000060 0x00000004>;
                status = "ok";
                ti,hwmods = "dss_hdmi";
                clocks = <0x00000103 0x00000104>;
                clock-names = <0x66636b00 0x7379735f 0x636c6b00>;
                dmas = <0x000000ac 0x0000004c>;
                dma-names = "audio_tx";
                vdda-supply = <0x00000105>;
                port {
                    endpoint {
                        remote-endpoint = <0x00000106>;
                        linux,phandle = <0x0000011f>;
                        phandle = <0x0000011f>;
                    };
                };
            };
            ports {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                port@lcd {
                    reg = <0x00000000>;
                    endpoint {
                        remote-endpoint = <0x00000107>;
                        data-lines = <0x00000018>;
                        linux,phandle = <0x000000cc>;
                        phandle = <0x000000cc>;
                    };
                };
            };
        };
        aes@4b500000 {
            compatible = "ti,omap4-aes";
            ti,hwmods = "aes1";
            reg = <0x4b500000 0x000000a0>;
            interrupts = <0x00000000 0x00000050 0x00000004>;
            dmas = <0x000000ac 0x0000006f 0x000000ac 0x0000006e>;
            dma-names = [74 78 00 72 78 00];
            clocks = <0x0000006f>;
            clock-names = "fck";
        };
        aes@4b700000 {
            compatible = "ti,omap4-aes";
            ti,hwmods = "aes2";
            reg = <0x4b700000 0x000000a0>;
            interrupts = <0x00000000 0x0000003b 0x00000004>;
            dmas = <0x000000ac 0x00000072 0x000000ac 0x00000071>;
            dma-names = [74 78 00 72 78 00];
            clocks = <0x0000006f>;
            clock-names = "fck";
        };
        des@480a5000 {
            compatible = "ti,omap4-des";
            ti,hwmods = "des";
            reg = <0x480a5000 0x000000a0>;
            interrupts = <0x00000000 0x0000004d 0x00000004>;
            dmas = <0x000000ac 0x00000075 0x000000ac 0x00000074>;
            dma-names = [74 78 00 72 78 00];
            clocks = <0x0000006f>;
            clock-names = "fck";
        };
        sham@53100000 {
            compatible = "ti,omap5-sham";
            ti,hwmods = "sham";
            reg = <0x4b101000 0x00000300>;
            interrupts = <0x00000000 0x0000002e 0x00000004>;
            dmas = <0x000000ac 0x00000077>;
            dma-names = "rx";
            clocks = <0x0000006f>;
            clock-names = "fck";
        };
        rng@48090000 {
            compatible = "ti,omap4-rng";
            ti,hwmods = "rng";
            reg = <0x48090000 0x00002000>;
            interrupts = <0x00000000 0x0000002f 0x00000004>;
            clocks = <0x0000006f>;
            clock-names = "fck";
        };
        can@481cc000 {
            compatible = "ti,dra7-d_can";
            ti,hwmods = "dcan1";
            reg = <0x4ae3c000 0x00002000>;
            syscon-raminit = <0x000000e7 0x00000558 0x00000000>;
            interrupts = <0x00000000 0x000000de 0x00000004>;
            clocks = <0x00000108>;
            status = "disabled";
        };
        can@481d0000 {
            compatible = "ti,dra7-d_can";
            ti,hwmods = "dcan2";
            reg = <0x48480000 0x00002000>;
            syscon-raminit = <0x000000e7 0x00000558 0x00000001>;
            interrupts = <0x00000000 0x000000e1 0x00000004>;
            clocks = <0x00000009>;
            status = "disabled";
        };
        mcasp@48464000 {
            compatible = "ti,dra7-mcasp-audio";
            ti,hwmods = "mcasp2";
            reg = <0x48464000 0x00002000>;
            reg-names = "mpu";
            dmas = <0x000000ac 0x00000083 0x000000ac 0x00000082>;
            dma-names = [74 78 00 72 78 00];
            clocks = <0x00000109>;
            clock-names = "fck";
            status = "disabled";
        };
        mcasp@48468000 {
            compatible = "ti,dra7-mcasp-audio";
            ti,hwmods = "mcasp3";
            reg = <0x48468000 0x00002000 0x46000000 0x00001000>;
            reg-names = <0x6d707500 0x64617400>;
            interrupts = <0x00000000 0x00000097 0x00000004 0x00000000 0x00000096 0x00000004>;
            interrupt-names = [74 78 00 72 78 00];
            dmas = <0x0000010a 0x00000085 0x0000010a 0x00000084>;
            dma-names = [74 78 00 72 78 00];
            clocks = <0x0000010b>;
            clock-names = "fck";
            status = "okay";
            fck_parent = "atl_clkin2_ck";
            op-mode = <0x00000000>;
            tdm-slots = <0x00000002>;
            serial-dir = <0x00000001 0x00000002 0x00000000 0x00000000>;
            tx-num-evt = <0x00000008>;
            rx-num-evt = <0x00000008>;
        };
        mcasp@48474000 {
            compatible = "ti,dra7-mcasp-audio";
            ti,hwmods = "mcasp6";
            reg = <0x48474000 0x00002000 0x4844c000 0x00001000>;
            reg-names = <0x6d707500 0x64617400>;
            interrupts = <0x00000000 0x0000009d 0x00000004 0x00000000 0x0000009c 0x00000004>;
            interrupt-names = [74 78 00 72 78 00];
            dmas = <0x000000ac 0x0000008b 0x000000ac 0x0000008a>;
            dma-names = [74 78 00 72 78 00];
            clocks = <0x0000010c>;
            clock-names = "fck";
            status = "disabled";
        };
        mcasp@48478000 {
            compatible = "ti,dra7-mcasp-audio";
            ti,hwmods = "mcasp7";
            reg = <0x48478000 0x00002000 0x48450000 0x00001000>;
            reg-names = <0x6d707500 0x64617400>;
            interrupts = <0x00000000 0x0000009f 0x00000004 0x00000000 0x0000009e 0x00000004>;
            interrupt-names = [74 78 00 72 78 00];
            dmas = <0x000000ac 0x0000008d 0x000000ac 0x0000008c>;
            dma-names = [74 78 00 72 78 00];
            clocks = <0x0000010d>;
            clock-names = "fck";
            status = "okay";
            #sound-dai-cells = <0x00000000>;
            op-mode = <0x00000000>;
            tdm-slots = <0x00000004>;
            serial-dir = <0x00000002 0x00000001 0x00000000 0x00000000>;
            tx-num-evt = <0x00000008>;
            rx-num-evt = <0x00000008>;
        };
        mcasp@4847c000 {
            compatible = "ti,dra7-mcasp-audio";
            ti,hwmods = "mcasp8";
            reg = <0x4847c000 0x00002000 0x48454000 0x00001000>;
            reg-names = <0x6d707500 0x64617400>;
            interrupts = <0x00000000 0x000000a1 0x00000004 0x00000000 0x000000a0 0x00000004>;
            interrupt-names = [74 78 00 72 78 00];
            dmas = <0x000000ac 0x0000008f 0x000000ac 0x0000008e>;
            dma-names = [74 78 00 72 78 00];
            clocks = <0x0000010e>;
            clock-names = "fck";
            status = "disabled";
        };
        vip@0x48970000 {
            compatible = "ti,vip1";
            reg = <0x48970000 0x00010000 0x4897d000 0x00001000>;
            reg-names = [76 69 70 00 76 70 64 6d 61 00];
            ti,hwmods = "vip1";
            interrupts = <0x00000000 0x0000015f 0x00000004 0x00000000 0x00000188 0x00000004>;
            syscon = <0x000000e7>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            status = "okay";
            pinctrl-names = "default";
            pinctrl-0 = <0x0000010f 0x00000110 0x00000111 0x00000112>;
            port@0 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000000>;
                status = "okay";
                linux,phandle = <0x000000c7>;
                phandle = <0x000000c7>;
                endpoint@0 {
                    slave-mode;
                    remote-endpoint = <0x00000113>;
                };
            };
            port@1 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000001>;
                status = "okay";
                linux,phandle = <0x000000c9>;
                phandle = <0x000000c9>;
                endpoint@0 {
                    slave-mode;
                    remote-endpoint = <0x00000114>;
                };
            };
            port@2 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000002>;
                status = "okay";
                linux,phandle = <0x000000c8>;
                phandle = <0x000000c8>;
                endpoint@0 {
                    slave-mode;
                    remote-endpoint = <0x00000115>;
                };
            };
            port@3 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000003>;
                status = "okay";
                linux,phandle = <0x000000ca>;
                phandle = <0x000000ca>;
                endpoint@0 {
                    slave-mode;
                    remote-endpoint = <0x00000116>;
                };
            };
        };
        vip@0x48990000 {
            compatible = "ti,vip2";
            reg = <0x48990000 0x00010000 0x4899d000 0x00001000>;
            reg-names = [76 69 70 00 76 70 64 6d 61 00];
            ti,hwmods = "vip2";
            interrupts = <0x00000000 0x00000160 0x00000004 0x00000000 0x00000189 0x00000004>;
            syscon = <0x000000e7>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            status = "disabled";
            port@0 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000000>;
                status = "disabled";
            };
            port@1 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000001>;
                status = "disabled";
            };
            port@2 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000002>;
                status = "disabled";
            };
            port@3 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000003>;
                status = "disabled";
            };
        };
        vip@0x489b0000 {
            compatible = "ti,vip3";
            reg = <0x489b0000 0x00010000 0x489bd000 0x00001000>;
            reg-names = [76 69 70 00 76 70 64 6d 61 00];
            ti,hwmods = "vip3";
            interrupts = <0x00000000 0x00000161 0x00000004 0x00000000 0x0000018a 0x00000004>;
            syscon = <0x000000e7>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            status = "disabled";
            port@0 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000000>;
                status = "disabled";
            };
            port@1 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000001>;
                status = "disabled";
            };
        };
        cal@4845b000 {
            compatible = "ti,cal";
            ti,hwmods = "cal";
            reg = <0x4845b000 0x00000400 0x4845b800 0x00000040 0x4845b900 0x00000040 0x4a002e94 0x00000004>;
            reg-names = [63 61 6c 5f 74 6f 70 00 63 61 6c 5f 72 78 5f 63 6f 72 65 30 00 63 61 6c 5f 72 78 5f 63 6f 72 65 31 00 63 61 6d 65 72 72 78 5f 63 6f 6e 74 72 6f 6c 00];
            interrupts = <0x00000000 0x00000077 0x00000004>;
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            status = "disable";
            port@0 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000000>;
            };
            port@1 {
                #address-cells = <0x00000001>;
                #size-cells = <0x00000000>;
                reg = <0x00000001>;
            };
        };
        epwmss@4843e000 {
            compatible = <0x74692c64 0x72613778 0x782d7077 0x6d737300 0x74692c61 0x6d333378 0x782d7077 0x6d737300>;
            reg = <0x4843e000 0x00000030>;
            ti,hwmods = "epwmss0";
            #address-cells = <0x00000001>;
            #size-cells = <0x00000001>;
            status = "disabled";
            ranges = <0x4843e100 0x4843e100 0x00000080 0x4843e180 0x4843e180 0x00000080 0x4843e200 0x4843e200 0x00000080>;
            ehrpwm@4843e200 {
                compatible = [74 69 2c 64 72 61 37 78 78 2d 65 68 72 70 77 6d 00 74 69 2c 61 6d 33 33 78 78 2d 65 68 72 70 77 6d 00];
                #pwm-cells = <0x00000003>;
                reg = <0x4843e200 0x00000080>;
                ti,hwmods = "ehrpwm0";
                status = "disabled";
            };
        };
        epwmss@48440000 {
            compatible = <0x74692c64 0x72613778 0x782d7077 0x6d737300 0x74692c61 0x6d333378 0x782d7077 0x6d737300>;
            reg = <0x48440000 0x00000030>;
            ti,hwmods = "epwmss1";
            #address-cells = <0x00000001>;
            #size-cells = <0x00000001>;
            status = "disabled";
            ranges = <0x48440100 0x48440100 0x00000080 0x48440180 0x48440180 0x00000080 0x48440200 0x48440200 0x00000080>;
            ehrpwm@48440200 {
                compatible = [74 69 2c 64 72 61 37 78 78 2d 65 68 72 70 77 6d 00 74 69 2c 61 6d 33 33 78 78 2d 65 68 72 70 77 6d 00];
                #pwm-cells = <0x00000003>;
                reg = <0x48440200 0x00000080>;
                ti,hwmods = "ehrpwm1";
                status = "disabled";
            };
        };
        epwmss@48442000 {
            compatible = <0x74692c64 0x72613778 0x782d7077 0x6d737300 0x74692c61 0x6d333378 0x782d7077 0x6d737300>;
            reg = <0x48442000 0x00000030>;
            ti,hwmods = "epwmss2";
            #address-cells = <0x00000001>;
            #size-cells = <0x00000001>;
            status = "disabled";
            ranges = <0x48442100 0x48442100 0x00000080 0x48442180 0x48442180 0x00000080 0x48442200 0x48442200 0x00000080>;
            ehrpwm@48442200 {
                compatible = [74 69 2c 64 72 61 37 78 78 2d 65 68 72 70 77 6d 00 74 69 2c 61 6d 33 33 78 78 2d 65 68 72 70 77 6d 00];
                #pwm-cells = <0x00000003>;
                reg = <0x48442200 0x00000080>;
                ti,hwmods = "ehrpwm2";
                status = "disabled";
            };
        };
    };
    cpus {
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        cpu@0 {
            device_type = "cpu";
            compatible = "arm,cortex-a15";
            reg = <0x00000000>;
            operating-points = <0x000f4240 0x0010c8e0>;
            clocks = <0x00000050>;
            clock-names = "cpu";
            clock-latency = <0x000493e0>;
            cooling-min-level = <0x00000000>;
            cooling-max-level = <0x00000002>;
            #cooling-cells = <0x00000002>;
            cpu0-voltdm = <0x00000117>;
            voltage-tolerance = <0x00000001>;
            linux,phandle = <0x0000011d>;
            phandle = <0x0000011d>;
        };
    };
    iva_coproc {
        compatible = "ti,coproc";
        clocks = <0x0000005a 0x00000059>;
        clock-names = [66 63 6c 6b 00 64 70 6c 6c 00];
        clock-target-frequency = <0x1fb5ad00>;
        operating-points = <0x0005ec68 0x00102ca0 0x00068fb0 0x00118c30 0x00081e20 0x001312d0>;
        coproc-voltdm = <0x00000118>;
        voltage-tolerance = <0x00000001>;
    };
    dsp_coproc {
        compatible = "ti,coproc";
        clocks = <0x00000011 0x00000055>;
        clock-names = [66 63 6c 6b 00 64 70 6c 6c 00];
        clock-target-frequency = <0x29b92700>;
        operating-points = <0x000927c0 0x00102ca0 0x000aae60 0x00118c30>;
        coproc-voltdm = <0x00000119>;
        voltage-tolerance = <0x00000001>;
    };
    pinmux@4a002e8c {
        compatible = "pinctrl-single";
        reg = <0x4a002e8c 0x00000004>;
        #address-cells = <0x00000001>;
        #size-cells = <0x00000000>;
        pinctrl-single,register-width = <0x00000020>;
        pinctrl-single,function-mask = <0x0000007f>;
        pinctrl-names = "default";
        pinctrl-0 = <0x0000011a>;
        pinmux_vin5a_pins {
            pinctrl-single,pins = <0x00000000 0x00000020>;
            linux,phandle = <0x0000011a>;
            phandle = <0x0000011a>;
        };
    };
    thermal-zones {
        cpu_thermal {
            polling-delay-passive = <0x000000fa>;
            polling-delay = <0x000001f4>;
            thermal-sensors = <0x0000011b 0x00000000>;
            trips {
                cpu_alert {
                    temperature = <0x000186a0>;
                    hysteresis = <0x000007d0>;
                    type = "passive";
                    linux,phandle = <0x0000011c>;
                    phandle = <0x0000011c>;
                };
                cpu_crit {
                    temperature = <0x0001e848>;
                    hysteresis = <0x000007d0>;
                    type = "critical";
                };
            };
            cooling-maps {
                map0 {
                    trip = <0x0000011c>;
                    cooling-device = <0x0000011d 0xffffffff 0xffffffff>;
                };
            };
        };
    };
    pmu {
        compatible = "arm,cortex-a15-pmu";
        interrupts = <0x00000000 0x00000213 0x00000004>;
    };
    encoder@0 {
        compatible = "ti,tpd12s015";
        gpios = <0x0000011e 0x00000008 0x00000000 0x0000011e 0x00000009 0x00000000 0x0000011e 0x0000000c 0x00000000>;
        ports {
            #address-cells = <0x00000001>;
            #size-cells = <0x00000000>;
            port@0 {
                reg = <0x00000000>;
                endpoint@0 {
                    remote-endpoint = <0x0000011f>;
                    linux,phandle = <0x00000106>;
                    phandle = <0x00000106>;
                };
            };
            port@1 {
                reg = <0x00000001>;
                endpoint@0 {
                    remote-endpoint = <0x00000120>;
                    linux,phandle = <0x00000121>;
                    phandle = <0x00000121>;
                };
            };
        };
    };
    connector@0 {
        compatible = "hdmi-connector";
        label = "hdmi";
        type = "a";
        port {
            endpoint {
                remote-endpoint = <0x00000121>;
                linux,phandle = <0x00000120>;
                phandle = <0x00000120>;
            };
        };
    };
    reserved-memory {
        #address-cells = <0x00000001>;
        #size-cells = <0x00000001>;
        ranges;
        ipu2_cma@95800000 {
            compatible = "shared-dma-pool";
            reg = <0x95800000 0x03800000>;
            reusable;
            status = "okay";
            linux,phandle = <0x000000b5>;
            phandle = <0x000000b5>;
        };
        dsp1_cma@99000000 {
            compatible = "shared-dma-pool";
            reg = <0x99000000 0x04000000>;
            reusable;
            status = "okay";
            linux,phandle = <0x000000bd>;
            phandle = <0x000000bd>;
        };
        ipu1_cma@9d000000 {
            compatible = "shared-dma-pool";
            reg = <0x9d000000 0x02000000>;
            reusable;
            status = "okay";
            linux,phandle = <0x000000ae>;
            phandle = <0x000000ae>;
        };
        app_cma@9F000000 {
            compatible = "shared-dma-pool";
            reg = <0x9f000000 0x10000000>;
            reusable;
            status = "okay";
        };
    };
    extcon_usb1 {
        compatible = "linux,extcon-usb-gpio";
        id-gpios = <0x000000c6 0x00000010 0x00000001>;
    };
    extcon_usb2 {
        compatible = "linux,extcon-usb-gpio";
        id-gpios = <0x000000c6 0x0000000f 0x00000001>;
    };
    fixedregulator-sd {
        compatible = "regulator-fixed";
        regulator-name = "evm_3v3_sd";
        regulator-min-microvolt = <0x00325aa0>;
        regulator-max-microvolt = <0x00325aa0>;
        enable-active-high;
        gpio = <0x0000011e 0x0000000b 0x00000000>;
        linux,phandle = <0x000000d5>;
        phandle = <0x000000d5>;
    };
    fixedregulator-evm_3v3 {
        compatible = "regulator-fixed";
        regulator-name = "evm_3v3";
        regulator-min-microvolt = <0x00325aa0>;
        regulator-max-microvolt = <0x00325aa0>;
        linux,phandle = <0x000000dc>;
        phandle = <0x000000dc>;
    };
    fixedregulator-aic_dvdd {
        compatible = "regulator-fixed";
        regulator-name = "aic_dvdd";
        vin-supply = <0x000000dc>;
        regulator-min-microvolt = <0x001b7740>;
        regulator-max-microvolt = <0x001b7740>;
    };
    fixedregulator-mmcwl {
        compatible = "regulator-fixed";
        regulator-name = "vmmcwl_fixed";
        regulator-min-microvolt = <0x001b7740>;
        regulator-max-microvolt = <0x001b7740>;
        gpio = <0x00000122 0x00000008 0x00000000>;
        enable-active-high;
    };
};
