MAIN_Cortex_R5_0_1: GEL Output: --------------------------------------------- MAIN_Cortex_R5_0_1: GEL Output: -------CPSWnG ALE TABLE---------------------- MAIN_Cortex_R5_0_1: GEL Output: --------------------------------------------- MAIN_Cortex_R5_0_1: GEL Output: --------------------------------------------- MAIN_Cortex_R5_0_1: GEL Output: Entry 0 - VLAN INNER MAIN_Cortex_R5_0_1: GEL Output: --------------------------------------------- MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE = 2 MAIN_Cortex_R5_0_1: GEL Output: IVLAN_ID = 300 MAIN_Cortex_R5_0_1: GEL Output: NO FRAG = 0 MAIN_Cortex_R5_0_1: GEL Output: REG_MCAST_FLOOD = 511 MAIN_Cortex_R5_0_1: GEL Output: FWDUTAG = 511 MAIN_Cortex_R5_0_1: GEL Output: LMT NEXT HDR = 0 MAIN_Cortex_R5_0_1: GEL Output: UNREG_MCAST_FLOOD = 0 MAIN_Cortex_R5_0_1: GEL Output: VLAN_MEMBER_LIST = 511 MAIN_Cortex_R5_0_1: GEL Output: --------------------------------------------- MAIN_Cortex_R5_0_1: GEL Output: Entry 1 - VLAN INNER MAIN_Cortex_R5_0_1: GEL Output: --------------------------------------------- MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE = 2 MAIN_Cortex_R5_0_1: GEL Output: IVLAN_ID = 0 MAIN_Cortex_R5_0_1: GEL Output: NO FRAG = 0 MAIN_Cortex_R5_0_1: GEL Output: REG_MCAST_FLOOD = 19 MAIN_Cortex_R5_0_1: GEL Output: FWDUTAG = 19 MAIN_Cortex_R5_0_1: GEL Output: LMT NEXT HDR = 0 MAIN_Cortex_R5_0_1: GEL Output: UNREG_MCAST_FLOOD = 19 MAIN_Cortex_R5_0_1: GEL Output: VLAN_MEMBER_LIST = 19 MAIN_Cortex_R5_0_1: GEL Output: --------------------------------------------- MAIN_Cortex_R5_0_1: GEL Output: Entry 2 - VLAN INNER MAIN_Cortex_R5_0_1: GEL Output: --------------------------------------------- MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE = 2 MAIN_Cortex_R5_0_1: GEL Output: IVLAN_ID = 1 MAIN_Cortex_R5_0_1: GEL Output: NO FRAG = 0 MAIN_Cortex_R5_0_1: GEL Output: REG_MCAST_FLOOD = 493 MAIN_Cortex_R5_0_1: GEL Output: FWDUTAG = 493 MAIN_Cortex_R5_0_1: GEL Output: LMT NEXT HDR = 0 MAIN_Cortex_R5_0_1: GEL Output: UNREG_MCAST_FLOOD = 0 MAIN_Cortex_R5_0_1: GEL Output: VLAN_MEMBER_LIST = 493 MAIN_Cortex_R5_0_1: GEL Output: --------------------------------------------- MAIN_Cortex_R5_0_1: GEL Output: Entry 3 - Multicast MAIN_Cortex_R5_0_1: GEL Output: --------------------------------------------- MAIN_Cortex_R5_0_1: GEL Output: PORT_MASK = 0x000001EC MAIN_Cortex_R5_0_1: GEL Output: SUPER = 0 MAIN_Cortex_R5_0_1: GEL Output: MCAST IGNORE BITS= 0 MAIN_Cortex_R5_0_1: GEL Output: MCAST_FWD_STATE = 0 MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE = 1 MAIN_Cortex_R5_0_1: GEL Output: MULTICAST_ADDR = 0x0000FFFF 0xFFFFFFFF MAIN_Cortex_R5_0_1: GEL Output: --------------------------------------------- MAIN_Cortex_R5_0_1: GEL Output: Entry 4 - Unicast MAIN_Cortex_R5_0_1: GEL Output: --------------------------------------------- MAIN_Cortex_R5_0_1: GEL Output: TRUNK = 0 MAIN_Cortex_R5_0_1: GEL Output: PORT_NUMBER = 0 MAIN_Cortex_R5_0_1: GEL Output: BLOCK = 0 MAIN_Cortex_R5_0_1: GEL Output: SECURE = 1 MAIN_Cortex_R5_0_1: GEL Output: TOUCH = 0 MAIN_Cortex_R5_0_1: GEL Output: AGEABLE = 0 MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE = 1 MAIN_Cortex_R5_0_1: GEL Output: UNICAST_ADDR = 0x000070FF 0x761D92C3 MAIN_Cortex_R5_0_1: GEL Output: --------------------------------------------- MAIN_Cortex_R5_0_1: GEL Output: Entry 6 - Multicast MAIN_Cortex_R5_0_1: GEL Output: --------------------------------------------- MAIN_Cortex_R5_0_1: GEL Output: PORT_MASK = 0x00000001 MAIN_Cortex_R5_0_1: GEL Output: SUPER = 0 MAIN_Cortex_R5_0_1: GEL Output: MCAST IGNORE BITS= 0 MAIN_Cortex_R5_0_1: GEL Output: MCAST_FWD_STATE = 0 MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE = 1 MAIN_Cortex_R5_0_1: GEL Output: MULTICAST_ADDR = 0x00000180 0xC200000E MAIN_Cortex_R5_0_1: GEL Output: --------------------------------------------- MAIN_Cortex_R5_0_1: GEL Output: Entry 7 - Multicast MAIN_Cortex_R5_0_1: GEL Output: --------------------------------------------- MAIN_Cortex_R5_0_1: GEL Output: PORT_MASK = 0x00000001 MAIN_Cortex_R5_0_1: GEL Output: SUPER = 0 MAIN_Cortex_R5_0_1: GEL Output: MCAST IGNORE BITS= 0 MAIN_Cortex_R5_0_1: GEL Output: MCAST_FWD_STATE = 0 MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE = 1 MAIN_Cortex_R5_0_1: GEL Output: MULTICAST_ADDR = 0x0000011B 0x19000000 MAIN_Cortex_R5_0_1: GEL Output: --------------------------------------------- MAIN_Cortex_R5_0_1: GEL Output: Entry 8 - Unicast MAIN_Cortex_R5_0_1: GEL Output: --------------------------------------------- MAIN_Cortex_R5_0_1: GEL Output: TRUNK = 0 MAIN_Cortex_R5_0_1: GEL Output: PORT_NUMBER = 0 MAIN_Cortex_R5_0_1: GEL Output: BLOCK = 0 MAIN_Cortex_R5_0_1: GEL Output: SECURE = 0 MAIN_Cortex_R5_0_1: GEL Output: TOUCH = 0 MAIN_Cortex_R5_0_1: GEL Output: AGEABLE = 0 MAIN_Cortex_R5_0_1: GEL Output: ENTRY_TYPE = 1 MAIN_Cortex_R5_0_1: GEL Output: UNICAST_ADDR = 0x000070FF 0x761D92C4 MAIN_Cortex_R5_0_1: GEL Output: Completed analysis of 1024 ALE entries