The output for “omapconf show dpll” is:
|--------------------------------------------                          |
| DPLL Configuration                     | DPLL_PER        |
|--------------------------------------------                          |
| Status                                             | Locked              |
|                                                         |                           |
| Mode                                             | Lock                  |
| Automatic Control                      | Not Supported |
|  LPST = Low-Power STop            |                           |
|  LPBP = Low-Power ByPass       |                           |
|  FRBP = Fast-Relock ByPass       |                           |
|  MNBP = MN ByPass                   |                           |
|                                                         |                           |
| Sigma-Delta Divider                    | 4                        |
| SELFREQDCO                                | 0                        |
|                                                         |                           |
| Ref. Frequency (MHz)                | 24.000              |
| M Multiplier Factor                    | 960                    |
| N Divider Factor                          | 23                      |
| Lock Frequency (MHz)               | 960                    |
|                                                         |                           |
| CLKOUT Output                           |                           |
|   Status                                           | Enabled            |
|   Clock Divider                              | 5                        |
|   Clock Speed (MHz)                    | 192                    |
|                                                         |                           |
| CLK_DCO_LDO Output               |                           |
|   Status                                           | Enabled            |
|   Clock Speed (MHz)                    | 960                    |
|                                                         |                           |
|--------------------------------------------                          |

|---------------------------------------------------------------------------------------------                                               |
| DPLL Configuration                     | DPLL_CORE     | DPLL_MPU      | DPLL_DDR      | DPLL_DISP                    |
|---------------------------------------------------------------------------------------------                                               |
| Status                                            | Locked              | Locked              | Locked              | Bypassed                     |
|                                                         |                           |                           |                           |                              |
| Mode                                             | Lock                  | Lock                  | Lock                  | MNBP                         |
| Automatic Control                      | Not Supported | Not Supported | Not Supported | Not Supported |
|  LPBP = Low-Power ByPass       |                           |                           |                           |                              |
|  FRBP = Fast-Relock ByPass       |                           |                           |                           |                              |
|  MNBP = MN ByPass                   |                           |                           |                           |                              |
| Low-Power Mode                       | Disabled           | Disabled           | Disabled           | Disabled                     |
|                                                         |                           |                           |                           |                              |
| Automatic Recalibration            | Disabled           | Disabled           | Disabled           | Disabled                     |
| Clock Ramping during Relock   | Disabled           | Disabled           | Disabled           | Disabled                     |
| Ramping Rate (x REFCLK(s))      | 2                        | 2                        | 2                        | 2                            |
| Ramping Levels                            | No Ramp          | No Ramp          | No Ramp          | No Ramp                      |
|                                                         |                           |                           |                           |                              |
| Bypass Clock                                 | CLKINP             | CLKINP             | CLKINP             | CLKINP                       |
| Bypass Clock Divider                   |                           |                           |                           |                              |
| REGM4XEN Mode                       | Disabled           | Disabled           | Disabled           | Disabled                     |
|                                                         |                           |                           |                           |                              |
| Ref. Frequency (MHz)                | 24.000              | 24.000              | 24.000              | 24.000                       |
| M Multiplier Factor                    | 1000                 | 25                      | 400                    | 0                            |
| N Divider Factor                          | 23                      | 1                        | 23                      | 0                            |
| Lock Frequency (MHz)               | 1000                 | 300                    | 400                    | 0 (0)                        |
|                                                         |                           |                           |                           |                              |
| M2 Output                                    |                           |                           |                           |                              |
|   Status                                          |                           | Enabled            | Enabled            | Gated                        |
|   Clock Divider                              |                           | 1                        | 1                        | 1                            |
|   Clock Speed (MHz)                    |                           | 300                    | 400                    | 24 (24)                      |
|                                                         |                           |                           |                           |                              |
| CLK_DCO_LDO Output               |                           |                           |                           |                              |
|   Status                                          | Gated               |                           |                           |                              |
|   Clock Speed (MHz)                    | 2000                 |                           |                           |                              |
|                                                         |                           |                           |                           |                              |
|                                                         |                           |                           |                           |                              |
| M4 Output                                    |                           |                           |                           |                              |
|   Status                                          | Enabled            |                           |                           |                              |
|   Clock Divider                              | 10                      |                           |                           |                              |
|   Clock Speed (MHz)                    | 200                    |                           |                           |                              |
|                                                         |                           |                           |                           |                              |
| M5 Output                                    |                           |                           |                           |                              |
|   Status                                          | Enabled            |                           |                           |                              |
|   Clock Divider                              | 8                        |                           |                           |                              |
|   Clock Speed (MHz)                    | 250                    |                           |                           |                              |
|                                                         |                           |                           |                           |                              |
| M6 Output                                    |                           |                           |                           |                              |
|   Status                                          | Gated               |                           |                           |                              |
|   Clock Divider                              | 4                        |                           |                           |                              |
|   Clock Speed (MHz)                    | 500                    |                           |                           |                              |
|---------------------------------------------------------------------------------------------                                               |