//---------------------- // GEL file for AM335x BBB -- Enable Timer 2-7 @ 32KHz // rev 1.0 // // ***************************************************************************/ // This file initialize all clocks needed to enable DMtimers from 2 to 7, // with 32KHz as clock source. // // It performs all initialization following routines included in // C:\ti\pdk_am335x_1_0_17\packages\ti\starterware // ***************************************************************************/ //***************************************************************************** // Dual Mode Timers //***************************************************************************** #define CM_PER (0x44e00000) #define CM_DPLL (0x44e00500) // macro for access register #define HWREG(addr) *(unsigned int*)(addr) #define CM_DPLL_CLKSEL_TIMER2_CLK (0x08) #define CM_DPLL_CLKSEL_TIMER3_CLK (0x0C) #define CM_DPLL_CLKSEL_TIMER4_CLK (0x10) #define CM_DPLL_CLKSEL_TIMER5_CLK (0x18) #define CM_DPLL_CLKSEL_TIMER6_CLK (0x1C) #define CM_DPLL_CLKSEL_TIMER7_CLK (0x04) #define CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL (0x03) #define CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL_CLK_M_OSC (0x01) #define CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL_32KHz (0x02) #define CM_PER_TIMERx_CLKCTRL_IDLEST (0x30000) #define CM_PER_TIMERx_CLKCTRL_IDLEST_FUNC (0x0) #define CM_PER_TIMERx_CLKCTRL_MODULEMODE (0x03) #define CM_PER_L3S_CLKSTCTRL (0x04) #define CM_PER_L3_CLKSTCTRL (0x0C) #define CM_PER_L3_INSTR_CLKCTRL (0x0DC) #define CM_PER_L3_CLKCTRL (0xE0) #define CM_PER_OCPWP_L3_CLKSTCTRL (0x12C) #define CM_PER_L4LS_CLKSTCTRL (0x00) #define CM_PER_L4LS_CLKCTRL (0x60) #define CM_PER_CLKDIV32K_CLKCTRL (0x14c) #define CM_PER_L3S_CLKSTCTRL_CLKTRCTRL (0x03) #define CM_PER_L3_CLKSTCTRL_CLKTRCTRL (0x03) #define CM_PER_L3_INSTR_CLKCTRL_MODULEMODE (0x03) #define CM_PER_L3_CLKCTRL_MODULEMODE (0x03) #define CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL (0x03) #define CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL (0x03) #define CM_PER_L4LS_CLKCTRL_MODULEMODE (0x03) #define CM_PER_CLKDIV32K_CLKCTRL_MODULEMODE (0x03) #define CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x02) #define CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x02) #define CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE (0x02) #define CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE (0x02) #define CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x02) #define CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x02) #define CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE (0x02) #define CM_PER_TIMERx_CLKCTRL_MODULEMODE_ENABLE (0x02) #define CM_PER_CLKDIV32K_CLKCTRL_MODULEMODE_ENABLE (0x02) #define CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK (0x08) #define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK (0x10) #define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK (0x10) #define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK (0x20) #define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK (0x100) #define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK (0x100) #define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER2_GCLK (0x4000) #define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER3_GCLK (0x8000) #define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER4_GCLK (0x10000) #define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER5_GCLK (0x8000000) #define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER6_GCLK (0x10000000) #define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK (0x2000) #define CM_PER_TIMER2_CLKCTRL (0x80) #define CM_PER_TIMER3_CLKCTRL (0x84) #define CM_PER_TIMER4_CLKCTRL (0x88) #define CM_PER_TIMER5_CLKCTRL (0xEC) #define CM_PER_TIMER6_CLKCTRL (0xF0) #define CM_PER_TIMER7_CLKCTRL (0x7C) hotmenu EnableTimers_32KHz() { // ************************************************************* // STEPS for enabling DMTimers 2-7 // ************************************************************* GEL_TextOut("**** Timers initializaion .... ****\n","Output",1,1,1); GEL_TextOut("enabling clocks..\n","Output",1,1,1); // Enable L3S & L3 clock HWREG(CM_PER + CM_PER_L3S_CLKSTCTRL) = CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP; while((HWREG(CM_PER + CM_PER_L3S_CLKSTCTRL) & CM_PER_L3S_CLKSTCTRL_CLKTRCTRL) != CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP); HWREG(CM_PER + CM_PER_L3_CLKSTCTRL) = CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP; while((HWREG(CM_PER + CM_PER_L3_CLKSTCTRL) & CM_PER_L3_CLKSTCTRL_CLKTRCTRL) != CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP); HWREG(CM_PER + CM_PER_L3_INSTR_CLKCTRL) = CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE; while((HWREG(CM_PER + CM_PER_L3_INSTR_CLKCTRL) & CM_PER_L3_INSTR_CLKCTRL_MODULEMODE) != CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE); HWREG(CM_PER + CM_PER_L3_CLKCTRL) = CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE; while((HWREG(CM_PER + CM_PER_L3_CLKCTRL) & CM_PER_L3_CLKCTRL_MODULEMODE) != CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE); // Enable OCPWP clock HWREG(CM_PER + CM_PER_OCPWP_L3_CLKSTCTRL) = CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP; while((HWREG(CM_PER + CM_PER_OCPWP_L3_CLKSTCTRL) & CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL) != CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP); // Enable L4 clock HWREG(CM_PER + CM_PER_L4LS_CLKSTCTRL) = CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP; while((HWREG(CM_PER + CM_PER_L4LS_CLKSTCTRL) & CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL) != CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP); HWREG(CM_PER + CM_PER_L4LS_CLKCTRL) = CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE; while((HWREG(CM_PER + CM_PER_L4LS_CLKCTRL) & CM_PER_L4LS_CLKCTRL_MODULEMODE) != CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE); // Enable L4 clock HWREG(CM_PER + CM_PER_CLKDIV32K_CLKCTRL) = CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE; while((HWREG(CM_PER + CM_PER_CLKDIV32K_CLKCTRL) & CM_PER_CLKDIV32K_CLKCTRL_MODULEMODE) != CM_PER_CLKDIV32K_CLKCTRL_MODULEMODE_ENABLE); GEL_TextOut("OK!\n","Output",1,1,1); GEL_TextOut("enabling timers..\n","Output",1,1,1); // Select the clock source for the Timer 2 instance. HWREG(CM_DPLL + CM_DPLL_CLKSEL_TIMER2_CLK) &= ~(CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL); HWREG(CM_DPLL + CM_DPLL_CLKSEL_TIMER2_CLK) |= CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL_32KHz; while((HWREG(CM_DPLL + CM_DPLL_CLKSEL_TIMER2_CLK) & CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL) != CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL_32KHz); // Enable timer 2 HWREG(CM_PER + CM_PER_TIMER2_CLKCTRL) |= CM_PER_TIMERx_CLKCTRL_MODULEMODE_ENABLE; while((HWREG(CM_PER + CM_PER_TIMER2_CLKCTRL) & CM_PER_TIMERx_CLKCTRL_MODULEMODE) != CM_PER_TIMERx_CLKCTRL_MODULEMODE_ENABLE); while((HWREG(CM_PER + CM_PER_TIMER2_CLKCTRL) & CM_PER_TIMERx_CLKCTRL_IDLEST) != CM_PER_TIMERx_CLKCTRL_IDLEST_FUNC); // Select the clock source for the Timer 3 instance. HWREG(CM_DPLL + CM_DPLL_CLKSEL_TIMER3_CLK) &= ~(CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL); HWREG(CM_DPLL + CM_DPLL_CLKSEL_TIMER3_CLK) |= CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL_32KHz; while((HWREG(CM_DPLL + CM_DPLL_CLKSEL_TIMER3_CLK) & CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL) != CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL_32KHz); // Enable timer 3 HWREG(CM_PER + CM_PER_TIMER3_CLKCTRL) |= CM_PER_TIMERx_CLKCTRL_MODULEMODE_ENABLE; while((HWREG(CM_PER + CM_PER_TIMER3_CLKCTRL) & CM_PER_TIMERx_CLKCTRL_MODULEMODE) != CM_PER_TIMERx_CLKCTRL_MODULEMODE_ENABLE); while((HWREG(CM_PER + CM_PER_TIMER3_CLKCTRL) & CM_PER_TIMERx_CLKCTRL_IDLEST) != CM_PER_TIMERx_CLKCTRL_IDLEST_FUNC); // Select the clock source for the Timer 4 instance. HWREG(CM_DPLL + CM_DPLL_CLKSEL_TIMER4_CLK) &= ~(CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL); HWREG(CM_DPLL + CM_DPLL_CLKSEL_TIMER4_CLK) |= CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL_32KHz; while((HWREG(CM_DPLL + CM_DPLL_CLKSEL_TIMER4_CLK) & CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL) != CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL_32KHz); // Enable timer 4 HWREG(CM_PER + CM_PER_TIMER4_CLKCTRL) |= CM_PER_TIMERx_CLKCTRL_MODULEMODE_ENABLE; while((HWREG(CM_PER + CM_PER_TIMER4_CLKCTRL) & CM_PER_TIMERx_CLKCTRL_MODULEMODE) != CM_PER_TIMERx_CLKCTRL_MODULEMODE_ENABLE); while((HWREG(CM_PER + CM_PER_TIMER4_CLKCTRL) & CM_PER_TIMERx_CLKCTRL_IDLEST) != CM_PER_TIMERx_CLKCTRL_IDLEST_FUNC); // Select the clock source for the Timer 5 instance. HWREG(CM_DPLL + CM_DPLL_CLKSEL_TIMER5_CLK) &= ~(CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL); HWREG(CM_DPLL + CM_DPLL_CLKSEL_TIMER5_CLK) |= CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL_32KHz; while((HWREG(CM_DPLL + CM_DPLL_CLKSEL_TIMER5_CLK) & CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL) != CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL_32KHz); // Enable timer 5 HWREG(CM_PER + CM_PER_TIMER5_CLKCTRL) |= CM_PER_TIMERx_CLKCTRL_MODULEMODE_ENABLE; while((HWREG(CM_PER + CM_PER_TIMER5_CLKCTRL) & CM_PER_TIMERx_CLKCTRL_MODULEMODE) != CM_PER_TIMERx_CLKCTRL_MODULEMODE_ENABLE); while((HWREG(CM_PER + CM_PER_TIMER5_CLKCTRL) & CM_PER_TIMERx_CLKCTRL_IDLEST) != CM_PER_TIMERx_CLKCTRL_IDLEST_FUNC); // Select the clock source for the Timer 6 instance. HWREG(CM_DPLL + CM_DPLL_CLKSEL_TIMER6_CLK) &= ~(CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL); HWREG(CM_DPLL + CM_DPLL_CLKSEL_TIMER6_CLK) |= CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL_32KHz; while((HWREG(CM_DPLL + CM_DPLL_CLKSEL_TIMER6_CLK) & CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL) != CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL_32KHz); // Enable timer 6 HWREG(CM_PER + CM_PER_TIMER6_CLKCTRL) |= CM_PER_TIMERx_CLKCTRL_MODULEMODE_ENABLE; while((HWREG(CM_PER + CM_PER_TIMER6_CLKCTRL) & CM_PER_TIMERx_CLKCTRL_MODULEMODE) != CM_PER_TIMERx_CLKCTRL_MODULEMODE_ENABLE); while((HWREG(CM_PER + CM_PER_TIMER6_CLKCTRL) & CM_PER_TIMERx_CLKCTRL_IDLEST) != CM_PER_TIMERx_CLKCTRL_IDLEST_FUNC); // Select the clock source for the Timer 7 instance. HWREG(CM_DPLL + CM_DPLL_CLKSEL_TIMER7_CLK) &= ~(CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL); HWREG(CM_DPLL + CM_DPLL_CLKSEL_TIMER7_CLK) |= CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL_32KHz; while((HWREG(CM_DPLL + CM_DPLL_CLKSEL_TIMER7_CLK) & CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL) != CM_DPLL_CLKSEL_TIMERx_CLK_CLKSEL_32KHz); // Enable timer 7 HWREG(CM_PER + CM_PER_TIMER7_CLKCTRL) |= CM_PER_TIMERx_CLKCTRL_MODULEMODE_ENABLE; while((HWREG(CM_PER + CM_PER_TIMER7_CLKCTRL) & CM_PER_TIMERx_CLKCTRL_MODULEMODE) != CM_PER_TIMERx_CLKCTRL_MODULEMODE_ENABLE); while((HWREG(CM_PER + CM_PER_TIMER7_CLKCTRL) & CM_PER_TIMERx_CLKCTRL_IDLEST) != CM_PER_TIMERx_CLKCTRL_IDLEST_FUNC); GEL_TextOut("OK!\n","Output",1,1,1); // check L3S activity OK while(!(HWREG(CM_PER + CM_PER_L3S_CLKSTCTRL) & CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK)); // check L3 activity OK while(!(HWREG(CM_PER + CM_PER_L3_CLKSTCTRL) & CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK)); // check OCPWP activity OK while(!(HWREG(CM_PER + CM_PER_OCPWP_L3_CLKSTCTRL) & (CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK | CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK))); // check Timers activity OK while(!(HWREG(CM_PER + CM_PER_L4LS_CLKSTCTRL) & (CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK | CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER2_GCLK | CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER3_GCLK | CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER4_GCLK | CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER5_GCLK | CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER6_GCLK | CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK))); GEL_TextOut("**** Timers 2-7 enabled for 32KHz. ****\n","Output",1,1,1); }