/*
 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "am57xx-idk-common.dtsi"

/ {
	model = "TI AM5718 IDK";
	compatible = "ti,am5718-idk", "ti,am5718", "ti,dra722",
		     "ti,dra72", "ti,dra7";

	aliases {
	/*	ethernet2 = &pruss1_emac0;
		ethernet3 = &pruss1_emac1;
		ethernet4 = &pruss2_emac0;
		ethernet5 = &pruss2_emac1;	*//*delete by zhang jian 2018.01.04*/
	//	dcan3 = &can3;			/* add by zhang jian 2018.01.04*/
	//	dcan4 = &can4;			/* ... */
	//	dcan5 = &can5;			/* ... */
	//	dcan6 = &can6;			/* ... */
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x40000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ipu2_cma_pool: ipu2_cma@95800000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x95800000 0x0 0x3800000>;
			reusable;
			status = "okay";
		};

		dsp1_cma_pool: dsp1_cma@99000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x99000000 0x0 0x4000000>;
			reusable;
			status = "okay";
		};

		ipu1_cma_pool: ipu1_cma@9d000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9d000000 0x0 0x2000000>;
			reusable;
			status = "okay";
		};
	};

	leds@1 {
		compatible = "gpio-leds";
	/*	status = "disabled";	*/	/*add by zhang jian 2018.01.04*/
						/*delete by zhang jian 2018.01.10*/
		pinctrl-names = "default";			/*add by zhang jian 2018.01.17*/
		pinctrl-0 = <&gpio_leds_pins>;			/*add by zhang jian 2018.01.17*/
		led@0 {
		/*	label = "status0:red:cpu0";*/		/*delete by zhang jian 2018.01.10*/
			label = "status0:green:heartbeat";	/*add by zhang jian 2018.01.10*/
		/*	gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;*/	/*delete by zhang jian 2018.01.10*/
			gpios = <&gpio8 1 GPIO_ACTIVE_HIGH>;	/*add by zhang jian 2018.01.10*/
			default-state = "off";			/*delete by zhang jian 2018.01.10*/
		/*	default-state = "on";	*/		/*add by zhang jian 2018.01.10*/
		/*	linux,default-trigger = "cpu0";*/	/*delete by zhang jian 2018.01.10*/
			linux,default-trigger = "heartbeat"; 	/*add by zhang jian 2018.01.10*/
		};

		led@1 {
			label = "status0:green:usr";
			status = "disabled";		/*add by zhang jian 2018.01.10*/
			gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led@2 {
			label = "status0:blue:heartbeat";
			status = "disabled";		/*add by zhang jian 2018.01.10*/
			gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "heartbeat";
		};

		led@3 {
			label = "status1:red:usr";
			status = "disabled";		/*add by zhang jian 2018.01.10*/
			gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led@4 {
			label = "status1:green:usr";
			status = "disabled";		/*add by zhang jian 2018.01.10*/
			gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};

		led@5 {
			label = "status1:blue:mmc0";
			status = "disabled";		/*add by zhang jian 2018.01.10*/
			gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
			default-state = "off";
			linux,default-trigger = "mmc0";
		};
	};

	extcon_usb2: extcon_usb2 {
	     compatible = "linux,extcon-usb-gpio";
	     id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
	};

	/* Dual mac ethernet application node on icss2 */
	pruss1_eth: pruss1_eth {
	/*	status = "okay";	*/	/*delete by zhang jian 2018.01.04*/
		status = "disabled";		/*add by zhang jian 2018.01.04*/
		compatible = "ti,am57-prueth";
		pruss = <&pruss1>;
		sram = <&ocmcram1>;
		interrupt-parent = <&pruss1_intc>;

		pruss1_emac0: ethernet-mii0 {
			phy-handle = <&pruss1_eth0_phy>;
			phy-mode = "mii";
			interrupts = <20>, <22>;
			interrupt-names = "rx", "tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};

		pruss1_emac1: ethernet-mii1 {
			phy-handle = <&pruss1_eth1_phy>;
			phy-mode = "mii";
			interrupts = <21>, <23>;
			interrupt-names = "rx", "tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};
	};

};

&dra7_pmx_core {
	mmc1_pins_default: mmc1_pins_default {
		pinctrl-single,pins = <
			0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
			0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
			0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
			0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
			0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
			0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
		>;
	};

	mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
		pinctrl-single,pins = <
			0x354 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_clk.clk */
			0x358 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_cmd.cmd */
			0x35c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat0.dat0 */
			0x360 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat1.dat1 */
			0x364 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat2.dat2 */
			0x368 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat3.dat3 */
		>;
	};

	mmc1_pins_hs: mmc1_pins_hs {
		pinctrl-single,pins = <
			0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
			0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
			0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
			0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
			0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
			0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
		>;
	};

	mmc1_pins_sdr25: pinmux_mmc1_sdr25_pins {
		pinctrl-single,pins = <
			0x354 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_clk.clk */
			0x358 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_cmd.cmd */
			0x35c (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat0.dat0 */
			0x360 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat1.dat1 */
			0x364 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat2.dat2 */
			0x368 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_dat3.dat3 */
		>;
	};

	mmc1_pins_sdr50: pinmux_mmc1_sdr50_pins {
		pinctrl-single,pins = <
			0x354 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_clk.clk */
			0x358 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_cmd.cmd */
			0x35c (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_dat0.dat0 */
			0x360 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_dat1.dat1 */
			0x364 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_dat2.dat2 */
			0x368 (PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)	/* mmc1_dat3.dat3 */
		>;
	};

	mmc1_pins_ddr50: pinmux_mmc1_ddr50_pins {
		pinctrl-single,pins = <
			0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_clk.clk */
			0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_cmd.cmd */
			0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat0.dat0 */
			0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat1.dat1 */
			0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat2.dat2 */
			0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat3.dat3 */
		>;
	};

	mmc1_pins_sdr104: pinmux_mmc1_sdr104_pins {
		pinctrl-single,pins = <
			0x354 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_clk.clk */
			0x358 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_cmd.cmd */
			0x35c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat0.dat0 */
			0x360 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat1.dat1 */
			0x364 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat2.dat2 */
			0x368 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE0)	/* mmc1_dat3.dat3 */
		>;
	};

	mmc2_pins_default: mmc2_pins_default {
		pinctrl-single,pins = <
			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc2_pins_hs: mmc2_pins_hs {
		pinctrl-single,pins = <
			0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};

	mmc2_pins_ddr_1_8v: mmc2_pins_ddr_1_8v {
		pinctrl-single,pins = <
			0x9c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a23.mmc2_clk */
			0xb0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
			0xa0 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
			0xa4 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
			0xa8 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
			0xac (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
			0x8c (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
			0x90 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
			0x94 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
			0x98 (PIN_INPUT_PULLUP | MANUAL_MODE | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
		>;
	};
};

&dra7_iodelay_core {

	mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {
		pinctrl-single,pins = <
			0x618 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_CLK_IN */
			0x624 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_CMD_IN */
			0x630 (A_DELAY(495) | G_DELAY(0))	/* CFG_MMC1_DAT0_IN */
			0x63C (A_DELAY(116) | G_DELAY(0))	/* CFG_MMC1_DAT1_IN */
			0x648 (A_DELAY(117) | G_DELAY(0))	/* CFG_MMC1_DAT2_IN */
			0x654 (A_DELAY(32) | G_DELAY(0))	/* CFG_MMC1_DAT3_IN */
			0x620 (A_DELAY(1224) | G_DELAY(0))	/* CFG_MMC1_CLK_OUT */
			0x62C (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_CMD_OUT */
			0x638 (A_DELAY(44) | G_DELAY(0))	/* CFG_MMC1_DAT0_OUT */
			0x644 (A_DELAY(64) | G_DELAY(0))	/* CFG_MMC1_DAT1_OUT */
			0x650 (A_DELAY(79) | G_DELAY(0))	/* CFG_MMC1_DAT2_OUT */
			0x65C (A_DELAY(87) | G_DELAY(0))	/* CFG_MMC1_DAT3_OUT */
			0x628 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_CMD_OEN */
			0x634 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT0_OEN */
			0x640 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT1_OEN */
			0x64C (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT2_OEN */
			0x658 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT3_OEN */
		>;
	};

	mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf {
		pinctrl-single,pins = <
			0x620 (A_DELAY(520) | G_DELAY(320))	/* CFG_MMC1_CLK_OUT */
			0x62c (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_CMD_OUT */
			0x638 (A_DELAY(40) | G_DELAY(0))	/* CFG_MMC1_DAT0_OUT */
			0x644 (A_DELAY(83) | G_DELAY(0))	/* CFG_MMC1_DAT1_OUT */
			0x650 (A_DELAY(98) | G_DELAY(0))	/* CFG_MMC1_DAT2_OUT */
			0x65c (A_DELAY(106) | G_DELAY(0))	/* CFG_MMC1_DAT3_OUT */
			0x628 (A_DELAY(51) | G_DELAY(0))	/* CFG_MMC1_CMD_OEN */
			0x634 (A_DELAY(0) | G_DELAY(0))		/* CFG_MMC1_DAT0_OEN */
			0x640 (A_DELAY(363) | G_DELAY(0))	/* CFG_MMC1_DAT1_OEN */
			0x64c (A_DELAY(199) | G_DELAY(0))	/* CFG_MMC1_DAT2_OEN */
			0x658 (A_DELAY(273) | G_DELAY(0))	/* CFG_MMC1_DAT3_OEN */
		>;
	};

	mmc2_iodelay_ddr_1_8v_conf: mmc2_iodelay_ddr_1_8v_conf {
		pinctrl-single,pins = <
			0x18c (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A19_IN */
			0x1a4 (A_DELAY(121) | G_DELAY(0))	/* CFG_GPMC_A20_IN */
			0x1b0 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A21_IN */
			0x1bc (A_DELAY(20) | G_DELAY(0))	/* CFG_GPMC_A22_IN */
			0x1c8 (A_DELAY(108) | G_DELAY(0))	/* CFG_GPMC_A23_IN */
			0x1d4 (A_DELAY(31) | G_DELAY(0))	/* CFG_GPMC_A24_IN */
			0x1e0 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A25_IN */
			0x1ec (A_DELAY(24) | G_DELAY(0))	/* CFG_GPMC_A26_IN */
			0x1f8 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A27_IN */
			0x360 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_CS1_IN */
			0x194 (A_DELAY(152) | G_DELAY(0))	/* CFG_GPMC_A19_OUT */
			0x1ac (A_DELAY(206) | G_DELAY(0))	/* CFG_GPMC_A20_OUT */
			0x1b8 (A_DELAY(78) | G_DELAY(0))	/* CFG_GPMC_A21_OUT */
			0x1c4 (A_DELAY(2) | G_DELAY(0))		/* CFG_GPMC_A22_OUT */
			0x1d0 (A_DELAY(266) | G_DELAY(0))	/* CFG_GPMC_A23_OUT */
			0x1dc (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A24_OUT */
			0x1e8 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A25_OUT */
			0x1f4 (A_DELAY(43) | G_DELAY(0))	/* CFG_GPMC_A26_OUT */
			0x200 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A27_OUT */
			0x368 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_CS1_OUT */
			0x190 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A19_OEN */
			0x1a8 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A20_OEN */
			0x1b4 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A21_OEN */
			0x1c0 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A22_OEN */
			0x1d8 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A24_OEN */
			0x1e4 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A25_OEN */
			0x1f0 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A26_OEN */
			0x1fc (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_A27_OEN */
			0x364 (A_DELAY(0) | G_DELAY(0))		/* CFG_GPMC_CS1_OEN */
		>;
	};
};

&mmc1 {
	pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
	pinctrl-0 = <&mmc1_pins_default>;
	pinctrl-1 = <&mmc1_pins_hs>;
	pinctrl-2 = <&mmc1_pins_sdr12>;
	pinctrl-3 = <&mmc1_pins_sdr25>;
	pinctrl-4 = <&mmc1_pins_sdr50>;
	pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr50_conf>;
	pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_conf>;
};

&mmc2 {
	pinctrl-names = "default", "hs", "ddr_1_8v";
	pinctrl-0 = <&mmc2_pins_default>;
	pinctrl-1 = <&mmc2_pins_hs>;
	pinctrl-2 = <&mmc2_pins_ddr_1_8v &mmc2_iodelay_ddr_1_8v_conf>;
};

&oppdm_mpu {
	vdd-supply = <&smps12_reg>;
};

&oppdm_dspeve {
	vdd-supply = <&smps45_reg>;
};

&oppdm_gpu {
	vdd-supply = <&smps6_reg>;
};

&oppdm_ivahd {
	vdd-supply = <&smps45_reg>;
};

&oppdm_core {
	vdd-supply = <&smps7_reg>;
};

&mailbox5 {
	status = "okay";		/*invalid notes: delete by zhang jian 2018.01.04*/
	/*status = "disabled";	*/	/*invalid notes: add by zhang jian 2018.01.04*/
	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
		status = "okay";	/*invalid notes: delete by zhang jian 2018.01.04*/
	/*	status = "disabled";*/	/*invalid notes: add by zhang jian 2018.01.04*/
	};
	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
		status = "okay";	/*invalid notes: delete by zhang jian 2018.01.04*/
	/*	status = "disabled";*/	/*invalid notes: add by zhang jian 2018.01.04*/
	};
};

&mailbox6 {
	status = "okay";		/*invalid notes: delete by zhang jian 2018.01.04*/
	/*status = "disabled";	*/	/*invalid notes: add by zhang jian 2018.01.04*/
	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
		status = "okay";	/*invalid notes: delete by zhang jian 2018.01.04*/
	/*	status = "disabled";*/	/*invalid notes: add by zhang jian 2018.01.04*/
	};
};

&mmu0_dsp1 {
	status = "okay";
};

&mmu1_dsp1 {
	status = "okay";
};

&mmu_ipu1 {
	status = "okay";
};

&mmu_ipu2 {
	status = "okay";
};

&ipu2 {
	status = "okay";
	memory-region = <&ipu2_cma_pool>;
	mboxes = <&mailbox6 &mbox_ipu2_ipc3x>;
	timers = <&timer3>;
	watchdog-timers = <&timer4>, <&timer9>;
};

&ipu1 {
	status = "okay";
	memory-region = <&ipu1_cma_pool>;
	mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
	timers = <&timer11>;
};

&dsp1 {
	status = "okay";
	memory-region = <&dsp1_cma_pool>;
	mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
	timers = <&timer5>;
};

&ov2659_1 {
	remote-endpoint = <&vin1b>;
};

&vin1b {
	status = "okay";

	endpoint@2 {
		slave-mode;
		remote-endpoint = <&ov2659_1>;
	};
};

&vip1 {
	status = "okay";
};

&sn65hvs882 {
	load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
};

&pruss1_mdio {
	/*status = "okey";	*/	/*delete by zhang jian 2018.01.04*/
	status = "disabled";		/*add by zhang jian 2018.01.04*/
	reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
	pruss1_eth0_phy: ethernet-phy@0 {
		reg = <0>;
		interrupt-parent = <&gpio3>;
		interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
	};

	pruss1_eth1_phy: ethernet-phy@1 {
		reg = <1>;
		interrupt-parent = <&gpio3>;
		interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
	};
};

&pruss2_mdio {
	reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
};

&pru1_1 {
	ti,pruss-gp-mux-sel = <4>;	/* MII2, needed for PRUSS1_MII1 */
};

&pru2_0 {
	ti,pruss-gp-mux-sel = <4>;	/* MII2, needed for PRUSS1_MII0 */
};

&pru2_1 {
	ti,pruss-gp-mux-sel = <4>;	/* MII2, needed for PRUSS1_MII1 */
};

&omap_dwc3_2 {
	extcon = <&extcon_usb2>;
};
/*add by zhang jian 2018.01.05*/
&dra7_pmx_core {
	can3_pins_default: can3_pins_default {
		pinctrl-single,pins = <
		/*	0x3a4   (PIN_OUTPUT_PULLUP | MUX_MODE0) *//* spi1_sclk *//*delete by zhang jian 2018.01.09*/
			0x3a4   (PIN_INPUT | MUX_MODE0) /* spi1_sclk *//*delete by zhang jian 2018.01.09*/
			0x3a8   (PIN_INPUT_PULLUP | MUX_MODE0) /* spi1_d1 */
			0x3ac   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi1_d0 */
			0x3b0   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi1_cs0 */
			0x198	(PIN_INPUT_PULLUP | MUX_MODE14)	/* vin2a_d12.gpio4-13 *//*add by zhang jian 2018.01.16*/
		>;
	};

	can3_pins_sleep: can3_pins_sleep {
		pinctrl-single,pins = <
			0x3a4   (MUX_MODE15 | PULL_UP) /* spi1_sclk.off */
			0x3a8   (MUX_MODE15 | PULL_UP) /* spi1_d1.off */
			0x3ac   (MUX_MODE15 | PULL_UP) /* spi1_d0.off */
			0x3b0   (MUX_MODE15 | PULL_UP) /* spi1_cs0.off */
		>;
	};

	can4_pins_default: can4_pins_default {
		pinctrl-single,pins = <
			0x3c0   (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
			0x3c4   (PIN_INPUT_PULLUP | MUX_MODE0) /* spi2_d1 */
			0x3c8   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi2_d0 */
			0x3cc   (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi2_cs0 */
			0x19c	(PIN_INPUT_PULLUP | MUX_MODE14)	/* vin2a_d13.gpio4-14 *//*add by zhang jian 2018.01.16*/
		>;
	};
/*add by zhang jian 2018.01.17*/
		can5_pins_default: can5_pins_default {
		pinctrl-single,pins = <
			0x2d4   (PIN_INPUT | MUX_MODE3) /* mcasp1_axr8.spi3_sclk */
			0x2d8   (PIN_INPUT_PULLUP | MUX_MODE3) /* mcasp1_axr9.spi3_d1 */
			0x2dc   (PIN_OUTPUT_PULLUP | MUX_MODE3) /* mcasp1_axr10.spi3_d0 */
			0x2e0   (PIN_OUTPUT_PULLUP | MUX_MODE3) /* mcasp1_axr11.spi3_cs0 */
			0x1a0	(PIN_INPUT_PULLUP | MUX_MODE14)	/* vin2a_d14.gpio4-15 */
		>;
	};
/*add by zhang jian 2018.01.17*/
	can6_pins_default: can6_pins_default {
		pinctrl-single,pins = <
			0x60   (PIN_INPUT | MUX_MODE8) /* gpmc_a8.spi4_sclk */
			0x64   (PIN_INPUT_PULLUP | MUX_MODE8) /* gpmc_a9.spi4_d1 */
			0x68   (PIN_OUTPUT_PULLUP | MUX_MODE8) /* gpmc_a10.spi4_d0 */
			0x6c   (PIN_OUTPUT_PULLUP | MUX_MODE8) /* gpmc_a11.spi4_cs0 */
			0x1a4	(PIN_INPUT_PULLUP | MUX_MODE14)	/* vin2a_d15.gpio4-16 */
		>;
	};

	gpio_leds_pins:	gpio_pins_default {
		pinctrl-single,pins = <
		//	0x1e0 	(PIN_INPUT_PULLUP | MUX_MODE14)
		>;	
	};
};
/*add by zhang jian 2018.01.05*/
&cm_core_clocks{
	mcp2515_clock: mcp2515_clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <5000000>;
	};
	mcp2515_clock2: mcp2515_clock2 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <5000000>;
	};
	mcp2515_clock3: mcp2515_clock3 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <5000000>;
	};
	mcp2515_clock4: mcp2515_clock4 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <5000000>;
	};
};
/*add by zhang jian 2018.01.05*/
&mcspi1 {
	status = "okay";
//	pinctrl-names = "default", "sleep", "active";
	pinctrl-names = "default";
	pinctrl-0 = <&can3_pins_default>;
//	pinctrl-1 = <&can3_pins_sleep>;
//	pinctrl-2 = <&can3_pins_default>;
	ti,pindir-d0-out-d1-in;

	can3: can@0 {
		compatible = "microchip,mcp2515";
		status = "okay";			/*add by zhang jian 2018.01.12*/
		reg = <0>;
		clocks = <&mcp2515_clock>;
		interrupt-parent = <&gpio4>;
		interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
		spi-max-frequency = <25000000>; // 5 MHz
		vdd-supply = <&v3_3d>;			/*add by zhang jian 2018.01.09*/
		xceiver-supply = <&v3_3d>;		/*add by zhang jian 2018.01.09*/
	};
};

&mcspi2 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&can4_pins_default>;
//	pinctrl-1 = <&can4_pins_sleep>;
//	pinctrl-2 = <&can4_pins_default>;
	ti,pindir-d0-out-d1-in;

	can4: can@0 {
		compatible = "microchip,mcp2515";
		reg = <0>;
		clocks = <&mcp2515_clock2>;
		interrupt-parent = <&gpio4>;
		interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
		spi-max-frequency = <25000000>; // 25 MHz
		vdd-supply = <&v3_3d>;
		xceiver-supply = <&v3_3d>;
	};
};

&mcspi3 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&can5_pins_default>;
	ti,pindir-d0-out-d1-in;

	can5: can@0 {
		compatible = "microchip,mcp2515";
		reg = <0>;
		clocks = <&mcp2515_clock3>;
		interrupt-mcp2515_clock = <&gpio4>;
		interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
		spi-max-frequency = <25000000>; // 5 MHz
	//	vdd-supply = <&reg5v0>;
	//	xceiver-supply = <&reg5v0>;
	};
};

&mcspi4 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&can6_pins_default>;
	ti,pindir-d0-out-d1-in;

	can6: can@0 {
		compatible = "microchip,mcp2515";
		reg = <0>;
		clocks = <&mcp2515_clock4>;
		interrupt-parent = <&gpio4>;
		interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
		spi-max-frequency = <25000000>; // 5 MHz
	//	vdd-supply = <&reg5v0>;
	//	xceiver-supply = <&reg5v0>;
	};
};

#include "am57xx-evm-cmem-am571x.dtsi"
