/*
 *  Copyright (c) Texas Instruments Incorporated 2019
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#define UInt32	unsigned int
#define UInt64	unsigned long long
#define WR_MEM_32(addr, data)   *(UInt32*)(addr) = (UInt32)(data)
#define RD_MEM_32(addr)         *(UInt32*)(addr)
#define RD_MEM_64(addr)         *(UInt64*)(addr)

#define PADCFG_CTRL0_CFG0_BASE 0xF0000
#define MCSPI2_CFG_BASE 0x20120000

Read32(UInt32 addr)
{
   UInt32 regVal,regAddr;
   regAddr = addr;
   regVal = RD_MEM_32(regAddr);
   GEL_TextOut("Reg_%x = %x\n",,,,,regAddr, regVal);
}

MCSPI2_CFG(UInt32 BaseAddr)
{

	UInt32 RegAddr;
	RegAddr = BaseAddr + 0x0;
	Read32(RegAddr, "CFG_HL_REV");

	RegAddr = BaseAddr + 0x4;
	Read32(RegAddr, "CFG_HL_HWINFO");

	RegAddr = BaseAddr + 0x10;
	Read32(RegAddr, "CFG_HL_SYSCONFIG");

	RegAddr = BaseAddr + 0x100;
	Read32(RegAddr, "CFG_REVISION");

	RegAddr = BaseAddr + 0x110;
	Read32(RegAddr, "CFG_SYSCONFIG");
	
	RegAddr = BaseAddr + 0x114;
	Read32(RegAddr, "CFG_SYSSTATUS");
	
	RegAddr = BaseAddr + 0x118;
	Read32(RegAddr, "CFG_IRQSTATUS");
	
	RegAddr = BaseAddr + 0x11C;
	Read32(RegAddr, "CFG_IRQENABLE");

	RegAddr = BaseAddr + 0x120;
	Read32(RegAddr, "CFG_WAKEUPENABLE");

	RegAddr = BaseAddr + 0x124;
	Read32(RegAddr, "CFG_SYST");

	RegAddr = BaseAddr + 0x128;
	Read32(RegAddr, "CFG_MODULCTRL");

	RegAddr = BaseAddr + 0x12C;
	Read32(RegAddr, "CFG_CH0CONF");

	RegAddr = BaseAddr + 0x130;
	Read32(RegAddr, "CFG_CH0STAT");
	
	RegAddr = BaseAddr + 0x134;
	Read32(RegAddr, "CFG_CH0CTRL");
				
	RegAddr = BaseAddr + 0x138;
	Read32(RegAddr, "CFG_TX0");

	RegAddr = BaseAddr + 0x13C;
	Read32(RegAddr, "CFG_RX0");

	RegAddr = BaseAddr + 0x140;
	Read32(RegAddr, "CFG_CH1CONF");

	RegAddr = BaseAddr + 0x144;
	Read32(RegAddr, "CFG_CH1STAT");
	
	RegAddr = BaseAddr + 0x148;
	Read32(RegAddr, "CFG_CH1CTRL");
		
	RegAddr = BaseAddr + 0x14C;
	Read32(RegAddr, "CFG_TX1");

	RegAddr = BaseAddr + 0x150;
	Read32(RegAddr, "CFG_RX1");
	
	RegAddr = BaseAddr + 0x154;
	Read32(RegAddr, "CFG_CH2CONF");

	RegAddr = BaseAddr + 0x158;
	Read32(RegAddr, "CFG_CH2STAT");
	
	RegAddr = BaseAddr + 0x15c;
	Read32(RegAddr, "CFG_CH2CTRL");	

	RegAddr = BaseAddr + 0x160;
	Read32(RegAddr, "CFG_TX2");

	RegAddr = BaseAddr + 0x164;
	Read32(RegAddr, "CFG_RX2");
	
	RegAddr = BaseAddr + 0x168;
	Read32(RegAddr, "CFG_CH3CONF");

	RegAddr = BaseAddr + 0x16c;
	Read32(RegAddr, "CFG_CH3STAT");

	RegAddr = BaseAddr + 0x170;
	Read32(RegAddr, "CFG_CH3CTRL");

	RegAddr = BaseAddr + 0x174;
	Read32(RegAddr, "CFG_TX3");

	RegAddr = BaseAddr + 0x178;
	Read32(RegAddr, "CFG_RX3");

	RegAddr = BaseAddr + 0x17C;
	Read32(RegAddr, "CFG_XFERLEVEL");

	RegAddr = BaseAddr + 0x180;
	Read32(RegAddr, "CFG_DAFTX");

	RegAddr = BaseAddr + 0x1A0;
	Read32(RegAddr, "CFG_DAFRX");

}

PADCFG_CTRL0_CFG0(UInt32 BaseAddr)
{

	UInt32 RegAddr;
	RegAddr = BaseAddr + 0x4210;
	Read32(RegAddr, "CFG0_PADCONFIG132");
	
	RegAddr = BaseAddr + 0x4200;
	Read32(RegAddr, "CFG0_PADCONFIG128");

	RegAddr = BaseAddr + 0x4198;
	Read32(RegAddr, "CFG0_PADCONFIG102");
	
	RegAddr = BaseAddr + 0x41AC;
	Read32(RegAddr, "CFG0_PADCONFIG107");

}


menuitem "AM62A SPI2 DUMP"

hotmenu register_dump()
{
  PADCFG_CTRL0_CFG0(PADCFG_CTRL0_CFG0_BASE);
  MCSPI2_CFG(MCSPI2_CFG_BASE);
}