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 AM62Q LP SK DDR Test at 667MHz Clock
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Connecting Target...

SMS_CM4_0_TIFS_0: GEL Output: Configuring ATCM for the DM R5F

SMS_CM4_0_TIFS_0: GEL Output: ATCM Configured.

SMS_CM4_0_TIFS_0: GEL Output: DM R5F Halt bit set.

SMS_CM4_0_TIFS_0: GEL Output: Configuring DM R5F bootvector

SMS_CM4_0_TIFS_0: GEL Output: DM R5F Bootvector configured.

SMS_CM4_0_TIFS_0: GEL Output: Programming all PLLs.

SMS_CM4_0_TIFS_0: GEL Output: Programming Main PLL 0 (Main PLL)

SMS_CM4_0_TIFS_0: GEL Output: Main PLL 0 (Main PLL) Set.

SMS_CM4_0_TIFS_0: GEL Output: Programming Main PLL 1 (Peripheral 0 PLL)

SMS_CM4_0_TIFS_0: GEL Output: Main PLL 1 (Peripheral 0 PLL) Set.

SMS_CM4_0_TIFS_0: GEL Output: Programming Main PLL 2 (Peripheral 1 PLL)

SMS_CM4_0_TIFS_0: GEL Output: Main PLL 2 (Peripheral 1 PLL) Set.

SMS_CM4_0_TIFS_0: GEL Output: Programming Main PLL 8 (ARM0 PLL)

SMS_CM4_0_TIFS_0: GEL Output: Main PLL 8 (ARM0 PLL) Set.

SMS_CM4_0_TIFS_0: GEL Output: Programming Main PLL 12 (DDR PLL)

SMS_CM4_0_TIFS_0: GEL Output: Main PLL 12 (DDR PLL) Set.

SMS_CM4_0_TIFS_0: GEL Output: Programming Main PLL 15 (SMS PLL)

SMS_CM4_0_TIFS_0: GEL Output: Main PLL 15 (SMS PLL) Set.

SMS_CM4_0_TIFS_0: GEL Output: Programming Main PLL 16 (DSS0 PLL)

SMS_CM4_0_TIFS_0: GEL Output: Main PLL 16 (DSS0 PLL) Set.

SMS_CM4_0_TIFS_0: GEL Output: Programming Main PLL 17 (DSS1 PLL)

SMS_CM4_0_TIFS_0: GEL Output: Main PLL 17 (DSS1 PLL) Set.

SMS_CM4_0_TIFS_0: GEL Output: Programming MCU PLL 0 (MCU PLL)

SMS_CM4_0_TIFS_0: GEL Output: MCU PLL 0 (MCU PLL) Set.

SMS_CM4_0_TIFS_0: GEL Output: All PLLs programmed.

SMS_CM4_0_TIFS_0: GEL Output: Powering up all PSC power domains in progress...

SMS_CM4_0_TIFS_0: GEL Output: Powering up MAIN domain peripherals...

SMS_CM4_0_TIFS_0: GEL Output: Powering up GP_CORE_CTL.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_MAIN_DM

SMS_CM4_0_TIFS_0: GEL Output: No change needed.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_DM2MAIN_ISO

SMS_CM4_0_TIFS_0: GEL Output: No change needed.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_MAIN_IP

SMS_CM4_0_TIFS_0: GEL Output: No change needed.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_EMIF_LOCAL

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_GPMC

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_MAIN_MCASP_0

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_MAIN_MCASP_1

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_MAIN_MCASP_2

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_EMMC_8B

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_EMMC_4B_0

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_EMMC_4B_1

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_USB_0

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_USB_1

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_DPHY_0

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_CSI_RX_0

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_FSS_OSPI

SMS_CM4_0_TIFS_0: GEL Output: No change needed.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_MAIN_MCANSS_0

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_SMS_COMMON

SMS_CM4_0_TIFS_0: GEL Output: No change needed.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_TIFS

SMS_CM4_0_TIFS_0: GEL Output: No change needed.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_HSM

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_SA3UL

SMS_CM4_0_TIFS_0: GEL Output: No change needed.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_HSM_ISO

SMS_CM4_0_TIFS_0: GEL Output: No change needed.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_EMIF_CFG_ISO

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_EMIF_DATA_ISO

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_MAIN_USB0_ISO

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_MAIN_USB1_ISO

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_DM2MAIN_INFRA_ISO

SMS_CM4_0_TIFS_0: GEL Output: No change needed.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_MAIN2DM_ISO

SMS_CM4_0_TIFS_0: GEL Output: No change needed.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_DM2CENTRAL_ISO

SMS_CM4_0_TIFS_0: GEL Output: No change needed.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_CENTRAL2DM_ISO

SMS_CM4_0_TIFS_0: GEL Output: No change needed.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_DM_PBIST

SMS_CM4_0_TIFS_0: GEL Output: No change needed.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_MAIN_TEST

SMS_CM4_0_TIFS_0: GEL Output: No change needed.

SMS_CM4_0_TIFS_0: GEL Output: Powering up GP_CORE_CTL done.

SMS_CM4_0_TIFS_0: GEL Output: Powering up PD_ICSSM

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_ICSSM

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up PD_ICSSM done.

SMS_CM4_0_TIFS_0: GEL Output: Powering up PD_CPSW

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_CPSW3G

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up PD_CPSW done.

SMS_CM4_0_TIFS_0: GEL Output: Powering up PD_A53_CLUSTER_0.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_A53_CLUSTER_0

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_A53_CLUSTER_0_PBIST

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_A53_CLUSTER_1_PBIST

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up PD_A53_CLUSTER_0 done.

SMS_CM4_0_TIFS_0: GEL Output: Powering up PD_A53_0.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_A53_0

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up PD_A53_0 done.

SMS_CM4_0_TIFS_0: GEL Output: Powering up PD_A53_1.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_A53_1

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up PD_A53_1 done.

SMS_CM4_0_TIFS_0: GEL Output: Powering up PD_A53_2.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_A53_2

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up PD_A53_2 done.

SMS_CM4_0_TIFS_0: GEL Output: Powering up PD_A53_3.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_A53_3

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up PD_A53_3 done.

SMS_CM4_0_TIFS_0: GEL Output: Powering up PD_GPU.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_GPU

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_GPU_PBIST

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up PD_GPU done.

SMS_CM4_0_TIFS_0: GEL Output: Powering up PD_DSS.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_DSS

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up PD_DSS done.

SMS_CM4_0_TIFS_0: GEL Output: Powering up all MAIN domain peripherals done.

SMS_CM4_0_TIFS_0: GEL Output: Powering up MCU Domain peripherals.

SMS_CM4_0_TIFS_0: GEL Output: Powering up GP_CORE_CTL_MCU.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_MCU2MAIN_ISO

SMS_CM4_0_TIFS_0: GEL Output: No change needed.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_DM2SAFE_ISO

SMS_CM4_0_TIFS_0: GEL Output: No change needed.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_MCU2DM_ISO

SMS_CM4_0_TIFS_0: GEL Output: No change needed.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_MCU_TEST

SMS_CM4_0_TIFS_0: GEL Output: No change needed.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_MAIN2MCU_ISO

SMS_CM4_0_TIFS_0: GEL Output: No change needed.

SMS_CM4_0_TIFS_0: GEL Output: Powering up GP_CORE_CTL_MCU done.

SMS_CM4_0_TIFS_0: GEL Output: Powering up PD_MCU_M4F.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_MCU_COMMON

SMS_CM4_0_TIFS_0: GEL Output: No change needed.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_MCU_M4F

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_MCU_MCANSS_0

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up LPSC_MCU_MCANSS_1

SMS_CM4_0_TIFS_0: GEL Output: Power domain and module state changed successfully.

SMS_CM4_0_TIFS_0: GEL Output: Powering up PD_MCU_M4F done.

SMS_CM4_0_TIFS_0: GEL Output: Powering up MCU Domain peripherals done.

SMS_CM4_0_TIFS_0: GEL Output: Powering up all PSC power domains done!

SMS_CM4_0_TIFS_0: GEL Output:

SMS_CM4_0_TIFS_0: GEL Output: *****Use R5 or A53 GELs to configure DDR


AM62x GEL Init Successful!

CortexA53_0: GEL Output: Running from A53

CortexA53_0: GEL Output: --->>> ECC Disabled! <<<---

CortexA53_0: GEL Output: --->>> LPDDR4 Initialization is in progress ... <<<---

CortexA53_0: GEL Output: --->>> DDR controller programming in progress.. <<<---

CortexA53_0: GEL Output: --->>> DDR controller programming completed... <<<---

CortexA53_0: GEL Output: --->>> DDR PI programming in progress.. <<<---

CortexA53_0: GEL Output: --->>> DDR PI programming completed... <<<---

CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 0 programming in progress.. <<<---

CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 0 programming completed... <<<---

CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 1 programming in progress.. <<<---

CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 1 programming completed... <<<---

CortexA53_0: GEL Output: --->>> DDR PHY Address Slice 0 programming in progress.. <<<---

CortexA53_0: GEL Output: --->>> DDR PHY Data Slice 2 programming completed... <<<---

CortexA53_0: GEL Output: --->>> DDR PHY Address Slice 1 programming in progress.. <<<---

CortexA53_0: GEL Output: --->>> DDR PHY Address Slice 1 programming completed... <<<---

CortexA53_0: GEL Output: --->>> DDR PHY Address slice 2 programming in progress.. <<<---

CortexA53_0: GEL Output: --->>> DDR PHY Address Slice 2 programming completed... <<<---

CortexA53_0: GEL Output: --->>> DDR PHY programming in progress.. <<<---

CortexA53_0: GEL Output: --->>> Set PHY registers for all FSPs simultaneously (multicast)... <<<---

CortexA53_0: GEL Output: --->>> DDR PHY programming completed... <<<---

CortexA53_0: GEL Output: Running from R5 or A53

CortexA53_0: GEL Output: Setting MAIN_PLL12_HSDIV0_CLKOUT_25MHz

CortexA53_0: GEL Output: MAIN_PLL12_HSDIV0_CLKOUT set.

CortexA53_0: GEL Output: --->>> Set DDR PLL to 25MHz for FSP F0... <<<---

CortexA53_0: GEL Output: --->>> DDR PI initialization started... <<<---

CortexA53_0: GEL Output: --->>> DDR CTL initialization started... <<<---

CortexA53_0: GEL Output: --->>> Inside DDR_Change_freq_ack function ... <<<---

CortexA53_0: GEL Output: --->>> Waiting for first frequency change request ... <<<---

CortexA53_0: GEL Output: Iter 1: Frequency change request type 1 received from controller

CortexA53_0: GEL Output: Running from R5 or A53

CortexA53_0: GEL Output: Setting MAIN_PLL12_HSDIV0_CLKOUT_333MHz

CortexA53_0: GEL Output: MAIN_PLL12_HSDIV0_CLKOUT set.

CortexA53_0: GEL Output: Iter 2: Frequency change request type 0 received from controller

CortexA53_0: GEL Output: Running from R5 or A53

CortexA53_0: GEL Output: Setting MAIN_PLL12_HSDIV0_CLKOUT_25MHz

CortexA53_0: GEL Output: MAIN_PLL12_HSDIV0_CLKOUT set.

CortexA53_0: GEL Output: Iter 3: Frequency change request type 1 received from controller

CortexA53_0: GEL Output: Running from R5 or A53

CortexA53_0: GEL Output: Setting MAIN_PLL12_HSDIV0_CLKOUT_333MHz

CortexA53_0: GEL Output: MAIN_PLL12_HSDIV0_CLKOUT set.

CortexA53_0: GEL Output: Iter 4: Frequency change request type 2 received from controller

CortexA53_0: GEL Output: Running from R5 or A53

CortexA53_0: GEL Output: Setting MAIN_PLL12_HSDIV0_CLKOUT_333MHz

CortexA53_0: GEL Output: MAIN_PLL12_HSDIV0_CLKOUT set.

CortexA53_0: GEL Output: Iter 5: Frequency change request type 1 received from controller

CortexA53_0: GEL Output: Running from R5 or A53

CortexA53_0: GEL Output: Setting MAIN_PLL12_HSDIV0_CLKOUT_333MHz

CortexA53_0: GEL Output: MAIN_PLL12_HSDIV0_CLKOUT set.

CortexA53_0: GEL Output: Iter 6: Frequency change request type 2 received from controller

CortexA53_0: GEL Output: Running from R5 or A53

CortexA53_0: GEL Output: Setting MAIN_PLL12_HSDIV0_CLKOUT_333MHz

CortexA53_0: GEL Output: MAIN_PLL12_HSDIV0_CLKOUT set.

CortexA53_0: GEL Output: --->>> Frequency Change request handshake is completed... <<<---

CortexA53_0: GEL Output: pi_int_status = 0x27C0A001...

CortexA53_0: GEL Output:  - PI_INIT_DONE_BIT set: The power-on initialization training in PI has been completed.

CortexA53_0: GEL Output:  - PI_LVL_DONE_BIT set: The leveling operation has completed.

CortexA53_0: GEL Output:  - PI_TDFI_INIT_TIME_OUT_BIT set: The tDFI init complete timed out.

CortexA53_0: GEL Output:  - PI_RDLVL_GATE_DONE_BIT set: A read leveling gate training operation has been completed.

CortexA53_0: GEL Output:  - PI_RDLVL_DONE_BIT set: A read leveling operation has been completed.

CortexA53_0: GEL Output:  - PI_WRLVL_DONE_BIT set: A write leveling operation has been completed.

CortexA53_0: GEL Output:  - PI_CALVL_DONE_BIT set: A CA training operation has been completed.

CortexA53_0: GEL Output:  - PI_WDQLVL_DONE_BIT set: A write DQ training operation has been completed.

CortexA53_0: GEL Output:  - Not documented bit set.

CortexA53_0: GEL Output: ctl_int_status = 0x02000000...

CortexA53_0: GEL Output: --->>> DDR Initialization completed... <<<---

CortexA53_0: GEL Output: --->>> LPDDR4 Initialization is DONE! <<<---


Connected to MPU Core

Running the Program. Check UART console for the Log!!

Program Run Begin

Press any key to continue . . .