(venv) yeverino@yeverino-pc:~/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools$ ./scripts/run_python_examples.sh X64 Architecture Running 1 Models - ['od-tfl-ssd_mobilenet_v1_1_default_1'] Running_Model : od-tfl-ssd_mobilenet_v1_1_default_1 TIDL Meta PipeLine (Proto) File : Number of OD backbone nodes = 0 Size of odBackboneNodeIds = 0 Number of subgraphs:1 , 64 nodes delegated out of 64 nodes Warning : concat requires 4D input tensors - only 3 dims present.. Ignore if object detection network Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal ************** Frame index 1 : Running float import ************* WARNING: [TIDL_E_DATAFLOW_INFO_NULL] Network compiler returned with error or didn't executed, this model can only be used on PC/Host emulation mode, it is not expected to work on target/EVM. **************************************************** ** 1 WARNINGS 0 ERRORS ** **************************************************** The soft limit is 2048 The hard limit is 2048 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INIT:Enabled 0.3s: VX_ZONE_ERROR:Enabled 0.4s: VX_ZONE_WARNING:Enabled 0.1045s: VX_ZONE_INIT:[tivxInit:184] Initialization Done !!! ************ Frame index 1 : Running float inference **************** ************ Frame index 2 : Running fixed point mode for calibration **************** ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-tfl-ssd_mobilenet_v1_1_default_1/tempDir/170_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 1505.62 .... ..... ... .... ..... # 1 . .. T 1505.21 .... ..... ... .... ..... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-tfl-ssd_mobilenet_v1_1_default_1/tempDir/170_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 1423.69 .... ..... ... .... ..... # 1 . .. T 1420.09 .... ..... ... .... ..... ***************** Calibration iteration number 0 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-tfl-ssd_mobilenet_v1_1_default_1/tempDir/170_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 1441.71 .... ..... ... .... ..... # 1 . .. T 1445.24 .... ..... ... .... ..... ***************** Calibration iteration number 1 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-tfl-ssd_mobilenet_v1_1_default_1/tempDir/170_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 1444.95 .... ..... ... .... ..... # 1 . .. T 1446.02 .... ..... ... .... ..... ***************** Calibration iteration number 2 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-tfl-ssd_mobilenet_v1_1_default_1/tempDir/170_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 1424.94 .... ..... ... .... ..... # 1 . .. T 1421.72 .... ..... ... .... ..... ***************** Calibration iteration number 3 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-tfl-ssd_mobilenet_v1_1_default_1/tempDir/170_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 1457.14 .... ..... ... .... ..... # 1 . .. T 1460.16 .... ..... ... .... ..... ***************** Calibration iteration number 4 completed ************************ ------------------ Network Compiler Traces ----------------------------- successful Memory allocation **************************************************** ** ALL MODEL CHECK PASSED ** **************************************************** Completed_Model : 1, Name : od-tfl-ssd_mobilenet_v1_1_default_1 , Total time : 16544.59, Offload Time : 0.00 , DDR RW MBs : 18446744073709.55, Output File : py_out_od-tfl-ssd_mobilenet_v1_1_default_1_ADE_val_00001801.jpg MEM: Deinit ... !!! MEM: Alloc's: 30 alloc's of 109980764 bytes MEM: Free's : 30 free's of 109980764 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! Running 1 Models - ['od-tfl-ssd_mobilenet_v1_1_default_1'] Running_Model : od-tfl-ssd_mobilenet_v1_1_default_1 Number of subgraphs:1 , 64 nodes delegated out of 64 nodes The soft limit is 2048 The hard limit is 2048 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INIT:Enabled 0.7s: VX_ZONE_ERROR:Enabled 0.9s: VX_ZONE_WARNING:Enabled 0.1337s: VX_ZONE_INIT:[tivxInit:184] Initialization Done !!! Saving image to ../../../output_images/ Completed_Model : 1, Name : od-tfl-ssd_mobilenet_v1_1_default_1 , Total time : 1517.22, Offload Time : 1517.21 , DDR RW MBs : 18446744073709.55, Output File : py_out_od-tfl-ssd_mobilenet_v1_1_default_1_ADE_val_00001801.jpg MEM: Deinit ... !!! MEM: Alloc's: 30 alloc's of 40779308 bytes MEM: Free's : 30 free's of 40779308 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! Available execution providers : ['TIDLExecutionProvider', 'TIDLCompilationProvider', 'CPUExecutionProvider'] Running 4 Models - ['cl-ort-resnet18-v1', 'cl-ort-caffe_squeezenet_v1_1', 'ss-ort-deeplabv3lite_mobilenetv2', 'od-ort-ssd-lite_mobilenetv2_fpn'] Running_Model : cl-ort-resnet18-v1 Running shape inference on model ../../../models/public/resnet18_opset9.onnx 2023-03-31 19:12:52.025685907 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer4.1.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:12:52.025705859 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer4.1.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:12:52.025711430 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer4.0.downsample.1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:12:52.025716146 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer4.0.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:12:52.025720518 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer3.1.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:12:52.025725250 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer1.1.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:12:52.025729420 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer1.0.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:12:52.025733439 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer4.0.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:12:52.025737412 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer3.0.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:12:52.025741802 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer3.0.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:12:52.025746082 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:12:52.025750388 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer1.0.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:12:52.025755286 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer2.0.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:12:52.025759805 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer1.1.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:12:52.025763799 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer2.0.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:12:52.025767871 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer2.0.downsample.1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:12:52.025772369 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer2.1.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:12:52.025777215 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer2.1.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:12:52.025781395 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer3.1.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:12:52.025785993 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer3.0.downsample.1.num_batches_tracked'. It is not used by any node and should be removed from the model. Preliminary subgraphs created = 1 Final number of subgraphs created are : 1, - Offloaded Nodes - 52, Total Nodes - 52 ************** Frame index 1 : Running float import ************* WARNING: [TIDL_E_DATAFLOW_INFO_NULL] Network compiler returned with error or didn't executed, this model can only be used on PC/Host emulation mode, it is not expected to work on target/EVM. **************************************************** ** 1 WARNINGS 0 ERRORS ** **************************************************** The soft limit is 2048 The hard limit is 2048 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INIT:Enabled 0.3s: VX_ZONE_ERROR:Enabled 0.4s: VX_ZONE_WARNING:Enabled 0.1291s: VX_ZONE_INIT:[tivxInit:184] Initialization Done !!! ********** Frame Index 1 : Running float inference ********** ********** Frame Index 2 : Running fixed point mode for calibration ********** ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-resnet18-v1/tempDir/191_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 3660.30 .... ..... ... .... ..... # 1 . .. T 3658.31 .... ..... ... .... ..... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-resnet18-v1/tempDir/191_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 3702.65 .... ..... ... .... ..... # 1 . .. T 3696.65 .... ..... ... .... ..... ***************** Calibration iteration number 0 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-resnet18-v1/tempDir/191_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 3714.51 .... ..... ... .... ..... # 1 . .. T 3678.75 .... ..... ... .... ..... ***************** Calibration iteration number 1 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-resnet18-v1/tempDir/191_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 3686.02 .... ..... ... .... ..... # 1 . .. T 3687.73 .... ..... ... .... ..... ***************** Calibration iteration number 2 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-resnet18-v1/tempDir/191_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 3695.34 .... ..... ... .... ..... # 1 . .. T 3678.84 .... ..... ... .... ..... ***************** Calibration iteration number 3 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-resnet18-v1/tempDir/191_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 3700.54 .... ..... ... .... ..... # 1 . .. T 3684.02 .... ..... ... .... ..... ***************** Calibration iteration number 4 completed ************************ ------------------ Network Compiler Traces ----------------------------- successful Memory allocation **************************************************** ** ALL MODEL CHECK PASSED ** **************************************************** Completed_Model : 1, Name : cl-ort-resnet18-v1 , Total time : 27672.63, Offload Time : 3609.72 , DDR RW MBs : 0, Output File : py_out_cl-ort-resnet18-v1_ADE_val_00001801.jpg MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 144052744 bytes MEM: Free's : 27 free's of 144052744 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! Running_Model : cl-ort-caffe_squeezenet_v1_1 Running shape inference on model ../../../models/public/caffe_squeezenet_v1_1.onnx Preliminary subgraphs created = 1 Final number of subgraphs created are : 1, - Offloaded Nodes - 68, Total Nodes - 68 Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal ************** Frame index 1 : Running float import ************* WARNING: [TIDL_E_DATAFLOW_INFO_NULL] Network compiler returned with error or didn't executed, this model can only be used on PC/Host emulation mode, it is not expected to work on target/EVM. **************************************************** ** 1 WARNINGS 0 ERRORS ** **************************************************** The soft limit is 2048 The hard limit is 2048 MEM: Init ... !!! MEM: Init ... Done !!! 55.984767s: VX_ZONE_INIT:Enabled 55.984768s: VX_ZONE_ERROR:Enabled 55.984769s: VX_ZONE_WARNING:Enabled 55.985770s: VX_ZONE_INIT:[tivxInit:184] Initialization Done !!! ********** Frame Index 1 : Running float inference ********** ********** Frame Index 2 : Running fixed point mode for calibration ********** ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-caffe_squeezenet_v1_1/tempDir/prob_Y_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 817.89 .... ..... ... .... ..... # 1 . .. T 815.46 .... ..... ... .... ..... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-caffe_squeezenet_v1_1/tempDir/prob_Y_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 803.88 .... ..... ... .... ..... # 1 . .. T 805.41 .... ..... ... .... ..... ***************** Calibration iteration number 0 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-caffe_squeezenet_v1_1/tempDir/prob_Y_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 805.24 .... ..... ... .... ..... # 1 . .. T 805.99 .... ..... ... .... ..... ***************** Calibration iteration number 1 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-caffe_squeezenet_v1_1/tempDir/prob_Y_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 806.54 .... ..... ... .... ..... # 1 . .. T 806.33 .... ..... ... .... ..... ***************** Calibration iteration number 2 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-caffe_squeezenet_v1_1/tempDir/prob_Y_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 806.22 .... ..... ... .... ..... # 1 . .. T 807.93 .... ..... ... .... ..... ***************** Calibration iteration number 3 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-ort-caffe_squeezenet_v1_1/tempDir/prob_Y_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 811.63 .... ..... ... .... ..... # 1 . .. T 811.72 .... ..... ... .... ..... ***************** Calibration iteration number 4 completed ************************ ------------------ Network Compiler Traces ----------------------------- successful Memory allocation **************************************************** ** ALL MODEL CHECK PASSED ** **************************************************** Completed_Model : 2, Name : cl-ort-caffe_squeezenet_v1_1 , Total time : 6491.80, Offload Time : 815.89 , DDR RW MBs : 0, Output File : py_out_cl-ort-caffe_squeezenet_v1_1_ADE_val_00001801.jpg MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 66747396 bytes MEM: Free's : 27 free's of 66747396 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! Running_Model : ss-ort-deeplabv3lite_mobilenetv2 Running shape inference on model ../../../models/public/deeplabv3lite_mobilenetv2.onnx Preliminary subgraphs created = 1 Final number of subgraphs created are : 1, - Offloaded Nodes - 124, Total Nodes - 124 Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal ************** Frame index 1 : Running float import ************* INFORMATION: [TIDL_ResizeLayer] 571 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. INFORMATION: [TIDL_ResizeLayer] 576 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. WARNING: [TIDL_E_DATAFLOW_INFO_NULL] Network compiler returned with error or didn't executed, this model can only be used on PC/Host emulation mode, it is not expected to work on target/EVM. **************************************************** ** 3 WARNINGS 0 ERRORS ** **************************************************** The soft limit is 2048 The hard limit is 2048 MEM: Init ... !!! MEM: Init ... Done !!! 69.516071s: VX_ZONE_INIT:Enabled 69.516074s: VX_ZONE_ERROR:Enabled 69.516075s: VX_ZONE_WARNING:Enabled 69.517139s: VX_ZONE_INIT:[tivxInit:184] Initialization Done !!! ********** Frame Index 1 : Running float inference ********** ********** Frame Index 2 : Running fixed point mode for calibration ********** ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/ss-ort-deeplabv3lite_mobilenetv2/tempDir/566TIDL_cast_out_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 7644.77 .... ..... ... .... ..... # 1 . .. T 7574.74 .... ..... ... .... ..... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/ss-ort-deeplabv3lite_mobilenetv2/tempDir/566TIDL_cast_out_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 8753.92 .... ..... ... .... ..... # 1 . .. T 8752.04 .... ..... ... .... ..... ***************** Calibration iteration number 0 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/ss-ort-deeplabv3lite_mobilenetv2/tempDir/566TIDL_cast_out_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 8796.15 .... ..... ... .... ..... # 1 . .. T 8774.02 .... ..... ... .... ..... ***************** Calibration iteration number 1 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/ss-ort-deeplabv3lite_mobilenetv2/tempDir/566TIDL_cast_out_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 9167.16 .... ..... ... .... ..... # 1 . .. T 9147.49 .... ..... ... .... ..... ***************** Calibration iteration number 2 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/ss-ort-deeplabv3lite_mobilenetv2/tempDir/566TIDL_cast_out_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 8778.31 .... ..... ... .... ..... # 1 . .. T 8776.19 .... ..... ... .... ..... ***************** Calibration iteration number 3 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/ss-ort-deeplabv3lite_mobilenetv2/tempDir/566TIDL_cast_out_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 8802.42 .... ..... ... .... ..... # 1 . .. T 8789.70 .... ..... ... .... ..... ***************** Calibration iteration number 4 completed ************************ ------------------ Network Compiler Traces ----------------------------- successful Memory allocation INFORMATION: [TIDL_ResizeLayer] 571 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. INFORMATION: [TIDL_ResizeLayer] 576 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. **************************************************** ** 2 WARNINGS 0 ERRORS ** **************************************************** Completed_Model : 3, Name : ss-ort-deeplabv3lite_mobilenetv2 , Total time : 60737.31, Offload Time : 7812.97 , DDR RW MBs : 0, Output File : py_out_ss-ort-deeplabv3lite_mobilenetv2_ADE_val_00001801.jpg MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 648302352 bytes MEM: Free's : 27 free's of 648302352 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! Running_Model : od-ort-ssd-lite_mobilenetv2_fpn Running shape inference on model ../../../models/public/ssd-lite_mobilenetv2_fpn.onnx TIDL Meta PipeLine (Proto) File : ../../../models/public/ssd-lite_mobilenetv2_fpn.prototxt ssd Number of OD backbone nodes = 159 Size of odBackboneNodeIds = 159 Preliminary subgraphs created = 1 Final number of subgraphs created are : 1, - Offloaded Nodes - 494, Total Nodes - 494 TIDL Meta PipeLine (Proto) File : ../../../models/public/ssd-lite_mobilenetv2_fpn.prototxt ssd Warning :: img_w & img_h or img_size is not provided as part of prior_box_param, hence using img_w = 512 and img_h = 512 in prior box decoding Warning :: img_w & img_h or img_size is not provided as part of prior_box_param, hence using img_w = 512 and img_h = 512 in prior box decoding Warning :: img_w & img_h or img_size is not provided as part of prior_box_param, hence using img_w = 512 and img_h = 512 in prior box decoding Warning :: img_w & img_h or img_size is not provided as part of prior_box_param, hence using img_w = 512 and img_h = 512 in prior box decoding Warning :: img_w & img_h or img_size is not provided as part of prior_box_param, hence using img_w = 512 and img_h = 512 in prior box decoding Warning :: img_w & img_h or img_size is not provided as part of prior_box_param, hence using img_w = 512 and img_h = 512 in prior box decoding Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal ************** Frame index 1 : Running float import ************* INFORMATION: [TIDL_ResizeLayer] Resize_153 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. INFORMATION: [TIDL_ResizeLayer] Resize_156 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. WARNING: [TIDL_E_DATAFLOW_INFO_NULL] Network compiler returned with error or didn't executed, this model can only be used on PC/Host emulation mode, it is not expected to work on target/EVM. **************************************************** ** 3 WARNINGS 0 ERRORS ** **************************************************** The soft limit is 2048 The hard limit is 2048 MEM: Init ... !!! MEM: Init ... Done !!! 195.69804s: VX_ZONE_INIT:Enabled 195.69806s: VX_ZONE_ERROR:Enabled 195.69807s: VX_ZONE_WARNING:Enabled 195.70826s: VX_ZONE_INIT:[tivxInit:184] Initialization Done !!! ********** Frame Index 1 : Running float inference ********** ********** Frame Index 2 : Running fixed point mode for calibration ********** ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-ort-ssd-lite_mobilenetv2_fpn/tempDir/boxeslabels_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 5790.22 .... ..... ... .... ..... # 1 . .. T 5725.99 .... ..... ... .... ..... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-ort-ssd-lite_mobilenetv2_fpn/tempDir/boxeslabels_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 6546.82 .... ..... ... .... ..... # 1 . .. T 6520.11 .... ..... ... .... ..... ***************** Calibration iteration number 0 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-ort-ssd-lite_mobilenetv2_fpn/tempDir/boxeslabels_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 6799.32 .... ..... ... .... ..... # 1 . .. T 6764.82 .... ..... ... .... ..... ***************** Calibration iteration number 1 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-ort-ssd-lite_mobilenetv2_fpn/tempDir/boxeslabels_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 6842.37 .... ..... ... .... ..... # 1 . .. T 6808.67 .... ..... ... .... ..... ***************** Calibration iteration number 2 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-ort-ssd-lite_mobilenetv2_fpn/tempDir/boxeslabels_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 6779.08 .... ..... ... .... ..... # 1 . .. T 6735.65 .... ..... ... .... ..... ***************** Calibration iteration number 3 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/od-ort-ssd-lite_mobilenetv2_fpn/tempDir/boxeslabels_tidl_io_.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 6501.35 .... ..... ... .... ..... # 1 . .. T 6449.74 .... ..... ... .... ..... ***************** Calibration iteration number 4 completed ************************ ------------------ Network Compiler Traces ----------------------------- successful Memory allocation INFORMATION: [TIDL_ResizeLayer] Resize_153 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. INFORMATION: [TIDL_ResizeLayer] Resize_156 Any resize ratio which is power of 2 and greater than 4 will be placed by combination of 4x4 resize layer and 2x2 resize layer. For example a 8x8 resize will be replaced by 4x4 resize followed by 2x2 resize. **************************************************** ** 2 WARNINGS 0 ERRORS ** **************************************************** Completed_Model : 4, Name : od-ort-ssd-lite_mobilenetv2_fpn , Total time : 46126.27, Offload Time : 5780.16 , DDR RW MBs : 0, Output File : py_out_od-ort-ssd-lite_mobilenetv2_fpn_ADE_val_00001801.jpg MEM: Deinit ... !!! MEM: Alloc's: 28 alloc's of 420292439 bytes MEM: Free's : 28 free's of 420292439 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! Available execution providers : ['TIDLExecutionProvider', 'TIDLCompilationProvider', 'CPUExecutionProvider'] Running 4 Models - ['cl-ort-resnet18-v1', 'cl-ort-caffe_squeezenet_v1_1', 'ss-ort-deeplabv3lite_mobilenetv2', 'od-ort-ssd-lite_mobilenetv2_fpn'] Running_Model : cl-ort-resnet18-v1 2023-03-31 19:17:40.518569510 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer4.1.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:17:40.518589831 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer4.1.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:17:40.518617024 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer4.0.downsample.1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:17:40.518622488 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer4.0.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:17:40.518627931 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer3.1.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:17:40.518633879 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer1.1.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:17:40.518639331 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer1.0.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:17:40.518643929 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer4.0.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:17:40.518649020 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer3.0.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:17:40.518654265 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer3.0.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:17:40.518659393 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:17:40.518664668 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer1.0.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:17:40.518669579 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer2.0.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:17:40.518674911 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer1.1.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:17:40.518679990 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer2.0.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:17:40.518685147 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer2.0.downsample.1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:17:40.518690731 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer2.1.bn1.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:17:40.518696292 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer2.1.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:17:40.518701616 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer3.1.bn2.num_batches_tracked'. It is not used by any node and should be removed from the model. 2023-03-31 19:17:40.518706820 [W:onnxruntime:, graph.cc:3106 CleanUnusedInitializers] Removing initializer 'layer3.0.downsample.1.num_batches_tracked'. It is not used by any node and should be removed from the model. libtidl_onnxrt_EP loaded 0x25164c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 52, Total Nodes - 52 The soft limit is 2048 The hard limit is 2048 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INIT:Enabled 0.37s: VX_ZONE_ERROR:Enabled 0.38s: VX_ZONE_WARNING:Enabled 0.1207s: VX_ZONE_INIT:[tivxInit:184] Initialization Done !!! , 0 23.311415 warplane, military plane ,, 1 22.239624 aircraft carrier, carrier, flattop, attack aircraft carrier ,, 2 18.488363 projectile, missile ,, 3 18.220415 missile ,, 4 15.540942 wing , Saving image to ../../../output_images/ Completed_Model : 1, Name : cl-ort-resnet18-v1 , Total time : 4090.97, Offload Time : 4090.93 , DDR RW MBs : 0, Output File : py_out_cl-ort-resnet18-v1_airshow.jpg MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 58015244 bytes MEM: Free's : 27 free's of 58015244 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! Running_Model : cl-ort-caffe_squeezenet_v1_1 libtidl_onnxrt_EP loaded 0x25164c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 68, Total Nodes - 68 The soft limit is 2048 The hard limit is 2048 MEM: Init ... !!! MEM: Init ... Done !!! 12.363897s: VX_ZONE_INIT:Enabled 12.363900s: VX_ZONE_ERROR:Enabled 12.363904s: VX_ZONE_WARNING:Enabled 12.364649s: VX_ZONE_INIT:[tivxInit:184] Initialization Done !!! , 0 0.638574 warplane, military plane ,, 1 0.192364 aircraft carrier, carrier, flattop, attack aircraft carrier ,, 2 0.057901 airliner ,, 3 0.057901 projectile, missile ,, 4 0.045576 missile , Saving image to ../../../output_images/ Completed_Model : 2, Name : cl-ort-caffe_squeezenet_v1_1 , Total time : 862.63, Offload Time : 862.59 , DDR RW MBs : 0, Output File : py_out_cl-ort-caffe_squeezenet_v1_1_airshow.jpg MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 27453287 bytes MEM: Free's : 27 free's of 27453287 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! Running_Model : ss-ort-deeplabv3lite_mobilenetv2 libtidl_onnxrt_EP loaded 0x25164c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 124, Total Nodes - 124 The soft limit is 2048 The hard limit is 2048 MEM: Init ... !!! MEM: Init ... Done !!! 15.42544s: VX_ZONE_INIT:Enabled 15.42547s: VX_ZONE_ERROR:Enabled 15.42549s: VX_ZONE_WARNING:Enabled 15.43300s: VX_ZONE_INIT:[tivxInit:184] Initialization Done !!! Saving image to ../../../output_images/ Completed_Model : 3, Name : ss-ort-deeplabv3lite_mobilenetv2 , Total time : 6746.31, Offload Time : 6746.27 , DDR RW MBs : 0, Output File : py_out_ss-ort-deeplabv3lite_mobilenetv2_ADE_val_00001801.jpg MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 137242860 bytes MEM: Free's : 27 free's of 137242860 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! Running_Model : od-ort-ssd-lite_mobilenetv2_fpn libtidl_onnxrt_EP loaded 0x25164c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 494, Total Nodes - 494 The soft limit is 2048 The hard limit is 2048 MEM: Init ... !!! MEM: Init ... Done !!! 36.86804s: VX_ZONE_INIT:Enabled 36.86808s: VX_ZONE_ERROR:Enabled 36.86809s: VX_ZONE_WARNING:Enabled 36.87777s: VX_ZONE_INIT:[tivxInit:184] Initialization Done !!! Saving image to ../../../output_images/ Completed_Model : 4, Name : od-ort-ssd-lite_mobilenetv2_fpn , Total time : 5259.47, Offload Time : 5259.40 , DDR RW MBs : 0, Output File : py_out_od-ort-ssd-lite_mobilenetv2_fpn_ADE_val_00001801.jpg MEM: Deinit ... !!! MEM: Alloc's: 28 alloc's of 118938559 bytes MEM: Free's : 28 free's of 118938559 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ../../../models/public/mobilenetv2-1.0.onnx Generating subgraph boundary tensors for calibration... Building graph on host for tensor data collection... Running graph on host for tensor data collection... Importing subgraph into TIDL... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 658.23 .... ..... ... .... ..... # 1 . .. T 657.78 .... ..... ... .... ..... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 646.99 .... ..... ... .... ..... # 1 . .. T 645.25 .... ..... ... .... ..... ***************** Calibration iteration number 0 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 640.89 .... ..... ... .... ..... # 1 . .. T 638.42 .... ..... ... .... ..... ***************** Calibration iteration number 1 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 643.76 .... ..... ... .... ..... # 1 . .. T 639.35 .... ..... ... .... ..... ***************** Calibration iteration number 2 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 656.53 .... ..... ... .... ..... # 1 . .. T 656.33 .... ..... ... .... ..... ***************** Calibration iteration number 3 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 641.44 .... ..... ... .... ..... # 1 . .. T 638.37 .... ..... ... .... ..... ***************** Calibration iteration number 4 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 642.43 .... ..... ... .... ..... # 1 . .. T 641.45 .... ..... ... .... ..... ***************** Calibration iteration number 5 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 642.41 .... ..... ... .... ..... # 1 . .. T 637.73 .... ..... ... .... ..... ***************** Calibration iteration number 6 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 652.37 .... ..... ... .... ..... # 1 . .. T 653.91 .... ..... ... .... ..... ***************** Calibration iteration number 7 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 629.36 .... ..... ... .... ..... # 1 . .. T 623.62 .... ..... ... .... ..... ***************** Calibration iteration number 8 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 640.46 .... ..... ... .... ..... # 1 . .. T 637.06 .... ..... ... .... ..... ***************** Calibration iteration number 9 completed ************************ ------------------ Network Compiler Traces ----------------------------- successful Memory allocation **************************************************** ** ALL MODEL CHECK PASSED ** **************************************************** TIDL import of 1 Relay IR subgraphs succeeded. TIDL artifacts are stored at ../../../model-artifacts/cl-dlr-onnx_mobilenetv2 Generating subgraph boundary tensors for calibration... Building graph on host for tensor data collection... conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. Running graph on host for tensor data collection... Importing subgraph into TIDL... Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 13356.33 .... ..... ... .... ..... # 1 . .. T 13323.41 .... ..... ... .... ..... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 13088.24 .... ..... ... .... ..... # 1 . .. T 13101.15 .... ..... ... .... ..... ***************** Calibration iteration number 0 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 13141.48 .... ..... ... .... ..... # 1 . .. T 13148.97 .... ..... ... .... ..... ***************** Calibration iteration number 1 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 13522.05 .... ..... ... .... ..... # 1 . .. T 13489.93 .... ..... ... .... ..... ***************** Calibration iteration number 2 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 13416.06 .... ..... ... .... ..... # 1 . .. T 13405.17 .... ..... ... .... ..... ***************** Calibration iteration number 3 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 13072.22 .... ..... ... .... ..... # 1 . .. T 13071.72 .... ..... ... .... ..... ***************** Calibration iteration number 4 completed ************************ ------------------ Network Compiler Traces ----------------------------- successful Memory allocation **************************************************** ** ALL MODEL CHECK PASSED ** **************************************************** TIDL import of 1 Relay IR subgraphs succeeded. TIDL artifacts are stored at ../../../model-artifacts/cl-dlr-tflite_inceptionnetv3 ../../../models/public/mobilenetv2-1.0.onnx Generating subgraph boundary tensors for calibration... Building graph on host for tensor data collection... Running graph on host for tensor data collection... Importing subgraph into TIDL... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 660.84 .... ..... ... .... ..... # 1 . .. T 658.92 .... ..... ... .... ..... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 644.52 .... ..... ... .... ..... # 1 . .. T 638.54 .... ..... ... .... ..... ***************** Calibration iteration number 0 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 640.05 .... ..... ... .... ..... # 1 . .. T 639.24 .... ..... ... .... ..... ***************** Calibration iteration number 1 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 641.99 .... ..... ... .... ..... # 1 . .. T 638.94 .... ..... ... .... ..... ***************** Calibration iteration number 2 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 642.41 .... ..... ... .... ..... # 1 . .. T 640.06 .... ..... ... .... ..... ***************** Calibration iteration number 3 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 641.29 .... ..... ... .... ..... # 1 . .. T 638.19 .... ..... ... .... ..... ***************** Calibration iteration number 4 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 641.70 .... ..... ... .... ..... # 1 . .. T 638.26 .... ..... ... .... ..... ***************** Calibration iteration number 5 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 640.49 .... ..... ... .... ..... # 1 . .. T 636.87 .... ..... ... .... ..... ***************** Calibration iteration number 6 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 638.65 .... ..... ... .... ..... # 1 . .. T 637.87 .... ..... ... .... ..... ***************** Calibration iteration number 7 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 642.17 .... ..... ... .... ..... # 1 . .. T 637.69 .... ..... ... .... ..... ***************** Calibration iteration number 8 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-onnx_mobilenetv2_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 641.05 .... ..... ... .... ..... # 1 . .. T 638.12 .... ..... ... .... ..... ***************** Calibration iteration number 9 completed ************************ ------------------ Network Compiler Traces ----------------------------- successful Memory allocation **************************************************** ** ALL MODEL CHECK PASSED ** **************************************************** TIDL import of 1 Relay IR subgraphs succeeded. TIDL artifacts are stored at ../../../model-artifacts/cl-dlr-onnx_mobilenetv2_device Generating subgraph boundary tensors for calibration... Building graph on host for tensor data collection... conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. conv2d NHWC layout is not optimized for x86 with autotvm. Running graph on host for tensor data collection... Importing subgraph into TIDL... Warning : Requested Output Data Convert Layer is not Added to the network, It is currently not Optimal ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 13353.79 .... ..... ... .... ..... # 1 . .. T 13306.76 .... ..... ... .... ..... ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 13465.43 .... ..... ... .... ..... # 1 . .. T 13428.22 .... ..... ... .... ..... ***************** Calibration iteration number 0 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 13454.91 .... ..... ... .... ..... # 1 . .. T 13434.18 .... ..... ... .... ..... ***************** Calibration iteration number 1 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 13042.18 .... ..... ... .... ..... # 1 . .. T 13025.13 .... ..... ... .... ..... ***************** Calibration iteration number 2 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 13074.77 .... ..... ... .... ..... # 1 . .. T 13071.15 .... ..... ... .... ..... ***************** Calibration iteration number 3 completed ************************ ~~~~~Running TIDL in PC emulation mode to collect Activations range for each layer~~~~~ Processing config file #0 : /home/yeverino/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools/model-artifacts/cl-dlr-tflite_inceptionnetv3_device/tempDir/tidl_import_subgraph0.txt.qunat_stats_config.txt ----------------------- TIDL Process with REF_ONLY FLOW ------------------------ # 0 . .. T 13521.82 .... ..... ... .... ..... # 1 . .. T 13447.20 .... ..... ... .... ..... ***************** Calibration iteration number 4 completed ************************ ------------------ Network Compiler Traces ----------------------------- successful Memory allocation **************************************************** ** ALL MODEL CHECK PASSED ** **************************************************** TIDL import of 1 Relay IR subgraphs succeeded. TIDL artifacts are stored at ../../../model-artifacts/cl-dlr-tflite_inceptionnetv3_device Traceback (most recent call last): File "tvm_compilation_mxnet_example.py", line 38, in from gluoncv import model_zoo ModuleNotFoundError: No module named 'gluoncv' Running Inference on Model - ../../../model-artifacts/cl-dlr-tflite_inceptionnetv3 2023-03-31 19:25:31,772 INFO Could not find libdlr.so in model artifact. Using dlr from /home/yeverino/Documents/git/fordos_tilinux64_host/venv/dlr/libdlr.so The soft limit is 2048 The hard limit is 2048 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INIT:Enabled 0.4s: VX_ZONE_ERROR:Enabled 0.5s: VX_ZONE_WARNING:Enabled 0.1106s: VX_ZONE_INIT:[tivxInit:184] Initialization Done !!! Processing time in ms : 13883.2 , 0 0.490434 warplane, military plane ,, 1 0.351332 aircraft carrier, carrier, flattop, attack aircraft carrier ,, 2 0.019505 projectile, missile ,, 3 0.017461 missile ,, 4 0.002945 wing , Saving image to ../../../output_images/ Completed_Model : 1, Name : cl-dlr-tflite_inceptionnetv3 , Total time : 13883.16, Offload Time : 13883.16 , DDR RW MBs : 0, Output File : py_out_cl-dlr-tflite_inceptionnetv3_airshow.jpg MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 105941750 bytes MEM: Free's : 27 free's of 105941750 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! Running Inference on Model - ../../../model-artifacts/cl-dlr-onnx_mobilenetv2 2023-03-31 19:26:14,179 INFO Could not find libdlr.so in model artifact. Using dlr from /home/yeverino/Documents/git/fordos_tilinux64_host/venv/dlr/libdlr.so The soft limit is 2048 The hard limit is 2048 MEM: Init ... !!! MEM: Init ... Done !!! 41.884783s: VX_ZONE_INIT:Enabled 41.884784s: VX_ZONE_ERROR:Enabled 41.884785s: VX_ZONE_WARNING:Enabled 41.885788s: VX_ZONE_INIT:[tivxInit:184] Initialization Done !!! Processing time in ms : 646.6 , 0 12.777789 missile ,, 1 12.292557 projectile, missile ,, 2 11.807323 aircraft carrier, carrier, flattop, attack aircraft carrier ,, 3 11.645579 warplane, military plane ,, 4 10.028138 airship, dirigible , Saving image to ../../../output_images/ Completed_Model : 2, Name : cl-dlr-onnx_mobilenetv2 , Total time : 646.61, Offload Time : 646.61 , DDR RW MBs : 0, Output File : py_out_cl-dlr-onnx_mobilenetv2_airshow.jpg MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 40116748 bytes MEM: Free's : 27 free's of 40116748 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! (venv) yeverino@yeverino-pc:~/Documents/git/fordos_tilinux64_host/Fnv4VX/edgeai-tidl-tools$