Data Write
Data Write Worstcases
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- Click on the second-level header (e.g., "Margin," "Measurement," or "Pass/Fail") to sort the table by that column
- * Indicates that this measurement column from BER Eye, not PRBS Waveform
Data Write Worstcases
| |
Signal/Controller/DRAM |
Status |
Corner |
|
|
Setup |
Hold |
Pulse Width |
tDIVW_1bit |
Min Slew Rate |
Max Slew Rate |
Voltage Margin between Signal and Eye-Mask |
Peak Voltage |
Overshoot |
Undershoot |
Overshoot Area |
Undershoot Area |
|
|---|
| # |
Signal |
Driving Controller.Pin |
Receiving DRAM.Pin |
Pass/Fail |
Case |
tUI [ps] |
Widest horizontal eye [mV] |
Reference voltage used [mV] |
Measurement [ps] |
Output Variation [ps] |
Base Requirement [ps] |
Margin [ps] |
Measurement [ps] |
Output Variation [ps] |
Base Requirement [ps] |
Margin [ps] |
Measurement [ps] |
Output Variation [ps] |
Base Requirement [ps] |
Margin [ps] |
Measurement [ps] |
Output Variation [ps] |
Base Requirement [ps] |
Margin [ps] |
Measurement [V/ns] |
Limit [V/ns] |
Margin [V/ns] |
Measurement [V/ns] |
Limit [V/ns] |
Margin [V/ns] |
Margin [mV] |
Above/Below Reference Voltage [mV] |
Above/Below Reference Voltage Required [mV] |
Above/Below Reference Voltage Margin [mV] |
Measurement [mV] |
Limit [mV] |
Margin [mV] |
Measurement [mV] |
Limit [mV] |
Margin [mV] |
Measurement [V*ns] |
Limit [V*ns] |
Margin [V*ns] |
Measurement [V*ns] |
Limit [V*ns] |
Margin [V*ns] |
Monotonic |
| 1 |
LPDDR4_DMI0_4 |
U6.E3 |
U7.C3 |
Pass |
Typ |
625.0 |
242.0 |
241.1 |
319.1 |
-8.0 |
-69.0 |
242.100 |
260.3 |
-8.0 |
-69.0 |
183.3 |
616.4 |
-16.0 |
-281.0 |
319.2 |
N/A |
N/A |
N/A |
N/A |
4.268 |
1.000 |
3.268 |
4.671 |
7.000 |
2.329 |
155.742 |
241.8 |
90.0 |
151.8 |
0.0 |
300.0 |
300.0 |
21.7 |
300.0 |
278.3 |
0.000 |
0.100 |
0.100 |
0.003 |
0.100 |
0.097 |
Pass |
| 2 |
LPDDR4_DMI1_4 |
U6.R4 |
U7.C10 |
Pass |
Typ |
625.0 |
238.7 |
241.1 |
352.3 |
-8.0 |
-69.0 |
275.3 |
238.4 |
-8.0 |
-69.0 |
161.4 |
621.1 |
-16.0 |
-281.0 |
323.8 |
N/A |
N/A |
N/A |
N/A |
4.451 |
1.000 |
3.451 |
4.966 |
7.000 |
2.034 |
163.841 |
240.9 |
90.0 |
150.9 |
0.0 |
300.0 |
300.0 |
23.7 |
300.0 |
276.3 |
0.000 |
0.100 |
0.100 |
0.002 |
0.100 |
0.099 |
Pass |
| 3 |
LPDDR4_DQ0_4 |
U6.C2 |
U7.F2 |
Pass |
Typ |
625.0 |
242.4 |
241.1 |
322.4 |
-8.0 |
-69.0 |
245.7 |
256.5 |
-8.0 |
-69.0 |
179.5 |
616.2 |
-16.0 |
-281.0 |
319.0 |
N/A |
N/A |
N/A |
N/A |
4.053 |
1.000 |
3.053 |
4.682 |
7.000 |
2.318 |
156.042 |
241.0 |
90.0 |
151.0 |
0.0 |
300.0 |
300.0 |
23.7 |
300.0 |
276.3 |
0.000 |
0.100 |
0.100 |
0.002 |
0.100 |
0.098 |
Pass |
| 4 |
LPDDR4_DQ10_4 |
U6.T2 |
U7.E11 |
Pass |
Typ |
625.0 |
244.4 |
241.1 |
306.3 |
-8.0 |
-69.0 |
229.6 |
257.9 |
-8.0 |
-69.0 |
181.2 |
611.4 |
-16.0 |
-281.0 |
314.1 |
N/A |
N/A |
N/A |
N/A |
3.918 |
1.000 |
2.918 |
5.043 |
7.000 |
1.957 |
149.617 |
241.7 |
90.0 |
151.7 |
0.0 |
300.0 |
300.0 |
37.6 |
300.0 |
262.4 |
0.000 |
0.100 |
0.100 |
0.007 |
0.100 |
0.093 |
Pass |
| 5 |
LPDDR4_DQ11_4 |
U6.U2 |
U7.B11 |
Pass |
Typ |
625.0 |
241.5 |
241.1 |
325.2 |
-8.0 |
-69.0 |
248.4 |
254.6 |
-8.0 |
-69.0 |
177.9 |
617.8 |
-16.0 |
-281.0 |
320.5 |
N/A |
N/A |
N/A |
N/A |
4.125 |
1.000 |
3.125 |
5.036 |
7.000 |
1.964 |
155.075 |
242.2 |
90.0 |
152.2 |
0.0 |
300.0 |
300.0 |
35.6 |
300.0 |
264.4 |
0.000 |
0.100 |
0.100 |
0.003 |
0.100 |
0.097 |
Pass |
| 6 |
LPDDR4_DQ12_4 |
U6.U3 |
U7.C11 |
Pass |
Typ |
625.0 |
237.8 |
241.1 |
317.5 |
-8.0 |
-69.0 |
240.5 |
256.3 |
-8.0 |
-69.0 |
179.3 |
613.8 |
-16.0 |
-281.0 |
316.5 |
N/A |
N/A |
N/A |
N/A |
4.002 |
1.000 |
3.002 |
4.943 |
7.000 |
2.057 |
154.281 |
242.4 |
90.0 |
152.4 |
0.0 |
300.0 |
300.0 |
27.1 |
300.0 |
272.9 |
0.000 |
0.100 |
0.100 |
0.004 |
0.100 |
0.096 |
Pass |
| 7 |
LPDDR4_DQ13_4 |
U6.U4 |
U7.F11 |
Pass |
Typ |
625.0 |
241.2 |
241.1 |
323.4 |
-8.0 |
-69.0 |
246.7 |
256.3 |
-8.0 |
-69.0 |
179.3 |
616.5 |
-16.0 |
-281.0 |
319.2 |
N/A |
N/A |
N/A |
N/A |
4.223 |
1.000 |
3.223 |
5.039 |
7.000 |
1.961 |
160.485 |
241.4 |
90.0 |
151.4 |
0.0 |
300.0 |
300.0 |
26.7 |
300.0 |
273.3 |
0.000 |
0.100 |
0.100 |
0.003 |
0.100 |
0.097 |
Pass |
| 8 |
LPDDR4_DQ14_4 |
U6.T4 |
U7.F9 |
Pass |
Typ |
625.0 |
241.8 |
241.1 |
319.3 |
-8.0 |
-69.0 |
242.3 |
265.3 |
-8.0 |
-69.0 |
188.6 |
618.9 |
-16.0 |
-281.0 |
321.6 |
N/A |
N/A |
N/A |
N/A |
4.186 |
1.000 |
3.186 |
4.676 |
7.000 |
2.324 |
153.909 |
241.1 |
90.0 |
151.1 |
0.0 |
300.0 |
300.0 |
11.7 |
300.0 |
288.3 |
0.000 |
0.100 |
0.100 |
0.002 |
0.100 |
0.098 |
Pass |
| 9 |
LPDDR4_DQ15_4 |
U6.T5 |
U7.E9 |
Pass |
Typ |
625.0 |
239.3 |
241.1 |
329.8 |
-8.0 |
-69.0 |
252.8 |
259.3 |
-8.0 |
-69.0 |
182.6 |
619.8 |
-16.0 |
-281.0 |
322.5 |
N/A |
N/A |
N/A |
N/A |
4.471 |
1.000 |
3.471 |
4.868 |
7.000 |
2.132 |
164.052 |
240.9 |
90.0 |
150.9 |
0.0 |
300.0 |
300.0 |
22.3 |
300.0 |
277.7 |
0.000 |
0.100 |
0.100 |
0.002 |
0.100 |
0.098 |
Pass |
| 10 |
LPDDR4_DQ1_4 |
U6.E4 |
U7.E4 |
Pass |
Typ |
625.0 |
241.5 |
241.1 |
309.0 |
-8.0 |
-69.0 |
232.0 |
265.8 |
-8.0 |
-69.0 |
188.8 |
615.7 |
-16.0 |
-281.0 |
318.4 |
N/A |
N/A |
N/A |
N/A |
4.042 |
1.000 |
3.042 |
4.867 |
7.000 |
2.133 |
157.053 |
241.6 |
90.0 |
151.6 |
0.0 |
300.0 |
300.0 |
22.6 |
300.0 |
277.4 |
0.000 |
0.100 |
0.100 |
0.004 |
0.100 |
0.097 |
Pass |
| 11 |
LPDDR4_DQ2_4 |
U6.D3 |
U7.E2 |
Pass |
Typ |
625.0 |
241.1 |
241.1 |
320.5 |
-8.0 |
-69.0 |
243.5 |
260.8 |
-8.0 |
-69.0 |
183.8 |
617.5 |
-16.0 |
-281.0 |
320.2 |
N/A |
N/A |
N/A |
N/A |
4.158 |
1.000 |
3.158 |
4.622 |
7.000 |
2.378 |
155.745 |
241.2 |
90.0 |
151.2 |
0.0 |
300.0 |
300.0 |
13.6 |
300.0 |
286.4 |
0.000 |
0.100 |
0.100 |
0.002 |
0.100 |
0.098 |
Pass |
| 12 |
LPDDR4_DQ3_4 |
U6.E5 |
U7.F4 |
Pass |
Typ |
625.0 |
242.6 |
241.1 |
317.8 |
-8.0 |
-69.0 |
240.8 |
268.4 |
-8.0 |
-69.0 |
191.6 |
619.8 |
-16.0 |
-281.0 |
322.6 |
N/A |
N/A |
N/A |
N/A |
4.314 |
1.000 |
3.314 |
4.577 |
7.000 |
2.423 |
157.816 |
242.4 |
90.0 |
152.4 |
0.0 |
300.0 |
300.0 |
12.9 |
300.0 |
287.1 |
0.000 |
0.100 |
0.100 |
0.001 |
0.100 |
0.099 |
Pass |
| 13 |
LPDDR4_DQ4_4 |
U6.D2 |
U7.C2 |
Pass |
Typ |
625.0 |
241.4 |
241.1 |
320.1 |
-8.0 |
-69.0 |
243.4 |
255.7 |
-8.0 |
-69.0 |
179.0 |
617.5 |
-16.0 |
-281.0 |
320.2 |
N/A |
N/A |
N/A |
N/A |
3.985 |
1.000 |
2.985 |
5.111 |
7.000 |
1.889 |
152.306 |
241.6 |
90.0 |
151.6 |
0.0 |
300.0 |
300.0 |
35.6 |
300.0 |
264.4 |
0.000 |
0.100 |
0.100 |
0.006 |
0.100 |
0.094 |
Pass |
| 14 |
LPDDR4_DQ5_4 |
U6.F3 |
U7.C4 |
Pass |
Typ |
625.0 |
242.0 |
241.1 |
320.4 |
-8.0 |
-69.0 |
243.7 |
255.4 |
-8.0 |
-69.0 |
178.7 |
614.9 |
-16.0 |
-281.0 |
317.7 |
N/A |
N/A |
N/A |
N/A |
3.956 |
1.000 |
2.956 |
4.804 |
7.000 |
2.196 |
157.102 |
241.9 |
90.0 |
151.9 |
0.0 |
300.0 |
300.0 |
27.7 |
300.0 |
272.3 |
0.000 |
0.100 |
0.100 |
0.004 |
0.100 |
0.096 |
Pass |
| 15 |
LPDDR4_DQ6_4 |
U6.F1 |
U7.B4 |
Pass |
Typ |
625.0 |
240.8 |
241.1 |
327.3 |
-8.0 |
-69.0 |
250.6 |
253.8 |
-8.0 |
-69.0 |
176.8 |
617.6 |
-16.0 |
-281.0 |
320.4 |
N/A |
N/A |
N/A |
N/A |
4.288 |
1.000 |
3.288 |
5.037 |
7.000 |
1.963 |
158.429 |
241.2 |
90.0 |
151.2 |
0.0 |
300.0 |
300.0 |
34.4 |
300.0 |
265.6 |
0.000 |
0.100 |
0.100 |
0.003 |
0.100 |
0.097 |
Pass |
| 16 |
LPDDR4_DQ7_4 |
U6.F2 |
U7.B2 |
Pass |
Typ |
625.0 |
242.9 |
241.1 |
318.0 |
-8.0 |
-69.0 |
241.0 |
257.0 |
-8.0 |
-69.0 |
180.3 |
615.1 |
-16.0 |
-281.0 |
317.8 |
N/A |
N/A |
N/A |
N/A |
4.000 |
1.000 |
3.000 |
5.206 |
7.000 |
1.794 |
154.190 |
241.0 |
90.0 |
151.0 |
0.0 |
300.0 |
300.0 |
36.2 |
300.0 |
263.8 |
0.000 |
0.100 |
0.100 |
0.004 |
0.100 |
0.096 |
Pass |
| 17 |
LPDDR4_DQ8_4 |
U6.R3 |
U7.C9 |
Pass |
Typ |
625.0 |
243.2 |
241.1 |
317.7 |
-8.0 |
-69.0 |
241.0 |
256.1 |
-8.0 |
-69.0 |
179.4 |
613.4 |
-16.0 |
-281.0 |
316.1 |
N/A |
N/A |
N/A |
N/A |
4.058 |
1.000 |
3.058 |
4.746 |
7.000 |
2.254 |
152.734 |
242.6 |
90.0 |
152.6 |
0.0 |
300.0 |
300.0 |
23.6 |
300.0 |
276.4 |
0.000 |
0.100 |
0.100 |
0.004 |
0.100 |
0.096 |
Pass |
| 18 |
LPDDR4_DQ9_4 |
U6.R2 |
U7.B9 |
Pass |
Typ |
625.0 |
242.4 |
241.1 |
329.8 |
-8.0 |
-69.0 |
252.8 |
247.1 |
-8.0 |
-69.0 |
170.3 |
615.7 |
-16.0 |
-281.0 |
318.5 |
N/A |
N/A |
N/A |
N/A |
4.002 |
1.000 |
3.002 |
5.168 |
7.000 |
1.832 |
152.356 |
241.9 |
90.0 |
151.9 |
0.0 |
300.0 |
300.0 |
31.3 |
300.0 |
268.7 |
0.000 |
0.100 |
0.100 |
0.004 |
0.100 |
0.096 |
Pass |
| 19 |
LPDDR4_DMI0_4 |
U6.E3 |
U7.C3 |
Pass |
Slow |
625.0 |
253.5 |
251.2 |
317.4 |
-8.0 |
-69.0 |
240.6 |
258.5 |
-8.0 |
-69.0 |
181.5 |
614.9 |
-16.0 |
-281.0 |
317.6 |
N/A |
N/A |
N/A |
N/A |
3.931 |
1.000 |
2.931 |
4.450 |
7.000 |
2.550 |
167.330 |
251.8 |
90.0 |
161.8 |
0.0 |
300.0 |
300.0 |
23.0 |
300.0 |
277.0 |
0.000 |
0.100 |
0.100 |
0.003 |
0.100 |
0.097 |
Pass |
| 20 |
LPDDR4_DMI1_4 |
U6.R4 |
U7.C10 |
Pass |
Slow |
625.0 |
252.6 |
251.2 |
351.0 |
-8.0 |
-69.0 |
274.0 |
236.3 |
-8.0 |
-69.0 |
159.3 |
620.7 |
-16.0 |
-281.0 |
323.4 |
N/A |
N/A |
N/A |
N/A |
4.261 |
1.000 |
3.261 |
4.437 |
7.000 |
2.563 |
174.196 |
251.0 |
90.0 |
161.0 |
0.0 |
300.0 |
300.0 |
25.8 |
300.0 |
274.2 |
0.000 |
0.100 |
0.100 |
0.002 |
0.100 |
0.098 |
Pass |
| 21 |
LPDDR4_DQ0_4 |
U6.C2 |
U7.F2 |
Pass |
Slow |
625.0 |
252.0 |
251.2 |
320.6 |
-8.0 |
-69.0 |
243.9 |
255.4 |
-8.0 |
-69.0 |
178.4 |
615.1 |
-16.0 |
-281.0 |
317.9 |
N/A |
N/A |
N/A |
N/A |
3.868 |
1.000 |
2.868 |
4.438 |
7.000 |
2.562 |
165.392 |
251.1 |
90.0 |
161.1 |
0.0 |
300.0 |
300.0 |
25.9 |
300.0 |
274.1 |
0.000 |
0.100 |
0.100 |
0.002 |
0.100 |
0.098 |
Pass |
| 22 |
LPDDR4_DQ10_4 |
U6.T2 |
U7.E11 |
Pass |
Slow |
625.0 |
251.5 |
251.2 |
304.8 |
-8.0 |
-69.0 |
228.1 |
255.9 |
-8.0 |
-69.0 |
178.9 |
610.1 |
-16.0 |
-281.0 |
312.9 |
N/A |
N/A |
N/A |
N/A |
3.602 |
1.000 |
2.602 |
4.704 |
7.000 |
2.296 |
158.717 |
251.6 |
90.0 |
161.6 |
0.0 |
300.0 |
300.0 |
33.9 |
300.0 |
266.1 |
0.000 |
0.100 |
0.100 |
0.007 |
0.100 |
0.093 |
Pass |
| 23 |
LPDDR4_DQ11_4 |
U6.U2 |
U7.B11 |
Pass |
Slow |
625.0 |
254.9 |
251.2 |
324.6 |
-8.0 |
-69.0 |
247.600 |
253.3 |
-8.0 |
-69.0 |
176.3 |
617.4 |
-16.0 |
-281.0 |
320.1 |
N/A |
N/A |
N/A |
N/A |
4.076 |
1.000 |
3.076 |
4.779 |
7.000 |
2.221 |
163.882 |
250.6 |
90.0 |
160.6 |
0.0 |
300.0 |
300.0 |
40.1 |
300.0 |
259.9 |
0.000 |
0.100 |
0.100 |
0.005 |
0.100 |
0.095 |
Pass |
| 24 |
LPDDR4_DQ12_4 |
U6.U3 |
U7.C11 |
Pass |
Slow |
625.0 |
247.6 |
251.2 |
314.2 |
-8.0 |
-69.0 |
237.4 |
254.8 |
-8.0 |
-69.0 |
177.8 |
613.3 |
-16.0 |
-281.0 |
316.0 |
N/A |
N/A |
N/A |
N/A |
3.795 |
1.000 |
2.795 |
4.686 |
7.000 |
2.314 |
164.319 |
252.6 |
90.0 |
162.6 |
0.0 |
300.0 |
300.0 |
26.8 |
300.0 |
273.2 |
0.000 |
0.100 |
0.100 |
0.004 |
0.100 |
0.096 |
Pass |
| 25 |
LPDDR4_DQ13_4 |
U6.U4 |
U7.F11 |
Pass |
Slow |
625.0 |
252.6 |
251.2 |
322.3 |
-8.0 |
-69.0 |
245.3 |
254.1 |
-8.0 |
-69.0 |
177.3 |
615.8 |
-16.0 |
-281.0 |
318.5 |
N/A |
N/A |
N/A |
N/A |
3.968 |
1.000 |
2.968 |
4.792 |
7.000 |
2.208 |
171.428 |
251.4 |
90.0 |
161.4 |
0.0 |
300.0 |
300.0 |
29.3 |
300.0 |
270.7 |
0.000 |
0.100 |
0.100 |
0.003 |
0.100 |
0.097 |
Pass |
| 26 |
LPDDR4_DQ14_4 |
U6.T4 |
U7.F9 |
Pass |
Slow |
625.0 |
254.6 |
251.2 |
318.1 |
-8.0 |
-69.0 |
241.4 |
262.9 |
-8.0 |
-69.0 |
186.1 |
616.4 |
-16.0 |
-281.0 |
319.2 |
N/A |
N/A |
N/A |
N/A |
3.948 |
1.000 |
2.948 |
4.388 |
7.000 |
2.612 |
162.234 |
251.1 |
90.0 |
161.1 |
0.0 |
300.0 |
300.0 |
12.7 |
300.0 |
287.3 |
0.000 |
0.100 |
0.100 |
0.002 |
0.100 |
0.098 |
Pass |
| 27 |
LPDDR4_DQ15_4 |
U6.T5 |
U7.E9 |
Pass |
Slow |
625.0 |
254.3 |
251.2 |
328.5 |
-8.0 |
-69.0 |
251.5 |
256.3 |
-8.0 |
-69.0 |
179.3 |
619.1 |
-16.0 |
-281.0 |
321.8 |
N/A |
N/A |
N/A |
N/A |
4.147 |
1.000 |
3.147 |
4.428 |
7.000 |
2.572 |
173.730 |
250.9 |
90.0 |
160.9 |
0.0 |
300.0 |
300.0 |
23.9 |
300.0 |
276.1 |
0.000 |
0.100 |
0.100 |
0.002 |
0.100 |
0.098 |
Pass |
| 28 |
LPDDR4_DQ1_4 |
U6.E4 |
U7.E4 |
Pass |
Slow |
625.0 |
251.7 |
251.2 |
307.4 |
-8.0 |
-69.0 |
230.7 |
263.8 |
-8.0 |
-69.0 |
186.8 |
614.2 |
-16.0 |
-281.0 |
316.9 |
N/A |
N/A |
N/A |
N/A |
3.813 |
1.000 |
2.813 |
4.549 |
7.000 |
2.451 |
165.631 |
251.7 |
90.0 |
161.7 |
0.0 |
300.0 |
300.0 |
22.0 |
300.0 |
278.0 |
0.000 |
0.100 |
0.100 |
0.003 |
0.100 |
0.097 |
Pass |
| 29 |
LPDDR4_DQ2_4 |
U6.D3 |
U7.E2 |
Pass |
Slow |
625.0 |
253.5 |
251.2 |
318.6 |
-8.0 |
-69.0 |
241.600 |
258.4 |
-8.0 |
-69.0 |
181.6 |
615.2 |
-16.0 |
-281.0 |
318.0 |
N/A |
N/A |
N/A |
N/A |
3.815 |
1.000 |
2.815 |
4.406 |
7.000 |
2.594 |
164.672 |
251.2 |
90.0 |
161.2 |
0.0 |
300.0 |
300.0 |
13.7 |
300.0 |
286.3 |
0.000 |
0.100 |
0.100 |
0.002 |
0.100 |
0.098 |
Pass |
| 30 |
LPDDR4_DQ3_4 |
U6.E5 |
U7.F4 |
Pass |
Slow |
625.0 |
254.6 |
251.2 |
315.8 |
-8.0 |
-69.0 |
238.8 |
266.3 |
-8.0 |
-69.0 |
189.6 |
617.8 |
-16.0 |
-281.0 |
320.6 |
N/A |
N/A |
N/A |
N/A |
3.980 |
1.000 |
2.980 |
4.291 |
7.000 |
2.709 |
166.521 |
252.4 |
90.0 |
162.4 |
0.0 |
300.0 |
300.0 |
14.3 |
300.0 |
285.7 |
0.000 |
0.100 |
0.100 |
0.002 |
0.100 |
0.099 |
Pass |
| 31 |
LPDDR4_DQ4_4 |
U6.D2 |
U7.C2 |
Pass |
Slow |
625.0 |
252.1 |
251.2 |
319.0 |
-8.0 |
-69.0 |
242.0 |
253.9 |
-8.0 |
-69.0 |
177.2 |
616.9 |
-16.0 |
-281.0 |
319.6 |
N/A |
N/A |
N/A |
N/A |
3.870 |
1.000 |
2.870 |
4.816 |
7.000 |
2.184 |
163.724 |
251.8 |
90.0 |
161.8 |
0.0 |
300.0 |
300.0 |
37.1 |
300.0 |
262.9 |
0.000 |
0.100 |
0.100 |
0.005 |
0.100 |
0.095 |
Pass |
| 32 |
LPDDR4_DQ5_4 |
U6.F3 |
U7.C4 |
Pass |
Slow |
625.0 |
251.7 |
251.2 |
317.9 |
-8.0 |
-69.0 |
241.2 |
253.4 |
-8.0 |
-69.0 |
176.4 |
612.6 |
-16.0 |
-281.0 |
315.4 |
N/A |
N/A |
N/A |
N/A |
3.705 |
1.000 |
2.705 |
4.482 |
7.000 |
2.518 |
167.142 |
252.1 |
90.0 |
162.1 |
0.0 |
300.0 |
300.0 |
27.0 |
300.0 |
273.0 |
0.000 |
0.100 |
0.100 |
0.004 |
0.100 |
0.096 |
Pass |
| 33 |
LPDDR4_DQ6_4 |
U6.F1 |
U7.B4 |
Pass |
Slow |
625.0 |
253.7 |
251.2 |
325.9 |
-8.0 |
-69.0 |
249.1 |
251.8 |
-8.0 |
-69.0 |
174.8 |
615.5 |
-16.0 |
-281.0 |
318.3 |
N/A |
N/A |
N/A |
N/A |
4.164 |
1.000 |
3.164 |
4.752 |
7.000 |
2.248 |
169.786 |
251.1 |
90.0 |
161.1 |
0.0 |
300.0 |
300.0 |
34.5 |
300.0 |
265.5 |
0.000 |
0.100 |
0.100 |
0.003 |
0.100 |
0.097 |
Pass |
| 34 |
LPDDR4_DQ7_4 |
U6.F2 |
U7.B2 |
Pass |
Slow |
625.0 |
252.9 |
251.2 |
316.8 |
-8.0 |
-69.0 |
239.8 |
254.8 |
-8.0 |
-69.0 |
178.1 |
615.1 |
-16.0 |
-281.0 |
317.8 |
N/A |
N/A |
N/A |
N/A |
3.834 |
1.000 |
2.834 |
4.891 |
7.000 |
2.109 |
166.351 |
251.0 |
90.0 |
161.0 |
0.0 |
300.0 |
300.0 |
37.3 |
300.0 |
262.7 |
0.000 |
0.100 |
0.100 |
0.004 |
0.100 |
0.096 |
Pass |
| 35 |
LPDDR4_DQ8_4 |
U6.R3 |
U7.C9 |
Pass |
Slow |
625.0 |
253.7 |
251.2 |
316.6 |
-8.0 |
-69.0 |
239.600 |
253.9 |
-8.0 |
-69.0 |
177.2 |
611.9 |
-16.0 |
-281.0 |
314.6 |
N/A |
N/A |
N/A |
N/A |
3.745 |
1.000 |
2.745 |
4.492 |
7.000 |
2.508 |
163.542 |
252.9 |
90.0 |
162.9 |
0.0 |
300.0 |
300.0 |
23.2 |
300.0 |
276.8 |
0.000 |
0.100 |
0.100 |
0.004 |
0.100 |
0.096 |
Pass |
| 36 |
LPDDR4_DQ9_4 |
U6.R2 |
U7.B9 |
Pass |
Slow |
625.0 |
253.3 |
251.2 |
329.1 |
-8.0 |
-69.0 |
252.100 |
244.2 |
-8.0 |
-69.0 |
167.4 |
614.1 |
-16.0 |
-281.0 |
316.8 |
N/A |
N/A |
N/A |
N/A |
3.917 |
1.000 |
2.917 |
4.894 |
7.000 |
2.106 |
163.065 |
252.4 |
90.0 |
162.4 |
0.0 |
300.0 |
300.0 |
32.3 |
300.0 |
267.7 |
0.000 |
0.100 |
0.100 |
0.004 |
0.100 |
0.096 |
Pass |
| 37 |
LPDDR4_DMI0_4 |
U6.E3 |
U7.C3 |
Pass |
Fast |
625.0 |
243.4 |
241.7 |
319.1 |
-8.0 |
-69.0 |
242.100 |
261.0 |
-8.0 |
-69.0 |
184.0 |
617.5 |
-16.0 |
-281.0 |
320.2 |
N/A |
N/A |
N/A |
N/A |
4.247 |
1.000 |
3.247 |
4.642 |
7.000 |
2.358 |
156.615 |
242.0 |
90.0 |
152.0 |
0.0 |
300.0 |
300.0 |
18.9 |
300.0 |
281.1 |
0.000 |
0.100 |
0.100 |
0.003 |
0.100 |
0.097 |
Pass |
| 38 |
LPDDR4_DMI1_4 |
U6.R4 |
U7.C10 |
Pass |
Fast |
625.0 |
236.7 |
241.7 |
352.5 |
-8.0 |
-69.0 |
275.5 |
238.0 |
-8.0 |
-69.0 |
161.0 |
621.0 |
-16.0 |
-281.0 |
323.7 |
N/A |
N/A |
N/A |
N/A |
4.364 |
1.000 |
3.364 |
4.912 |
7.000 |
2.088 |
164.991 |
241.2 |
90.0 |
151.2 |
0.0 |
300.0 |
300.0 |
18.7 |
300.0 |
281.3 |
0.000 |
0.100 |
0.100 |
0.001 |
0.100 |
0.099 |
Pass |
| 39 |
LPDDR4_DQ0_4 |
U6.C2 |
U7.F2 |
Pass |
Fast |
625.0 |
242.8 |
241.7 |
322.5 |
-8.0 |
-69.0 |
245.8 |
257.0 |
-8.0 |
-69.0 |
180.0 |
617.2 |
-16.0 |
-281.0 |
319.9 |
N/A |
N/A |
N/A |
N/A |
3.992 |
1.000 |
2.992 |
4.582 |
7.000 |
2.418 |
159.115 |
241.3 |
90.0 |
151.3 |
0.0 |
300.0 |
300.0 |
17.5 |
300.0 |
282.5 |
0.000 |
0.100 |
0.100 |
0.002 |
0.100 |
0.098 |
Pass |
| 40 |
LPDDR4_DQ10_4 |
U6.T2 |
U7.E11 |
Pass |
Fast |
625.0 |
246.6 |
241.7 |
306.2 |
-8.0 |
-69.0 |
229.4 |
258.8 |
-8.0 |
-69.0 |
182.1 |
612.6 |
-16.0 |
-281.0 |
315.4 |
N/A |
N/A |
N/A |
N/A |
4.040 |
1.000 |
3.040 |
5.008 |
7.000 |
1.992 |
152.167 |
242.1 |
90.0 |
152.1 |
0.0 |
300.0 |
300.0 |
40.6 |
300.0 |
259.4 |
0.000 |
0.100 |
0.100 |
0.007 |
0.100 |
0.092 |
Pass |
| 41 |
LPDDR4_DQ11_4 |
U6.U2 |
U7.B11 |
Pass |
Fast |
625.0 |
241.4 |
241.7 |
324.8 |
-8.0 |
-69.0 |
247.8 |
255.6 |
-8.0 |
-69.0 |
178.8 |
617.9 |
-16.0 |
-281.0 |
320.7 |
N/A |
N/A |
N/A |
N/A |
3.957 |
1.000 |
2.957 |
5.017 |
7.000 |
1.983 |
151.392 |
240.8 |
90.0 |
150.8 |
0.0 |
300.0 |
300.0 |
36.6 |
300.0 |
263.4 |
0.000 |
0.100 |
0.100 |
0.005 |
0.100 |
0.095 |
Pass |
| 42 |
LPDDR4_DQ12_4 |
U6.U3 |
U7.C11 |
Pass |
Fast |
625.0 |
241.0 |
241.7 |
317.9 |
-8.0 |
-69.0 |
241.1 |
256.7 |
-8.0 |
-69.0 |
180.0 |
614.3 |
-16.0 |
-281.0 |
317.1 |
N/A |
N/A |
N/A |
N/A |
3.990 |
1.000 |
2.990 |
4.863 |
7.000 |
2.137 |
157.328 |
242.4 |
90.0 |
152.4 |
0.0 |
300.0 |
300.0 |
28.0 |
300.0 |
272.0 |
0.000 |
0.100 |
0.100 |
0.004 |
0.100 |
0.096 |
Pass |
| 43 |
LPDDR4_DQ13_4 |
U6.U4 |
U7.F11 |
Pass |
Fast |
625.0 |
241.0 |
241.7 |
323.2 |
-8.0 |
-69.0 |
246.4 |
257.3 |
-8.0 |
-69.0 |
180.3 |
616.8 |
-16.0 |
-281.0 |
319.5 |
N/A |
N/A |
N/A |
N/A |
4.099 |
1.000 |
3.099 |
4.904 |
7.000 |
2.096 |
161.943 |
241.6 |
90.0 |
151.6 |
0.0 |
300.0 |
300.0 |
21.8 |
300.0 |
278.2 |
0.000 |
0.100 |
0.100 |
0.003 |
0.100 |
0.097 |
Pass |
| 44 |
LPDDR4_DQ14_4 |
U6.T4 |
U7.F9 |
Pass |
Fast |
625.0 |
239.5 |
241.7 |
320.4 |
-8.0 |
-69.0 |
243.7 |
266.8 |
-8.0 |
-69.0 |
190.1 |
618.9 |
-16.0 |
-281.0 |
321.7 |
N/A |
N/A |
N/A |
N/A |
4.271 |
1.000 |
3.271 |
4.660 |
7.000 |
2.340 |
156.978 |
241.4 |
90.0 |
151.4 |
0.0 |
300.0 |
300.0 |
10.1 |
300.0 |
289.9 |
0.000 |
0.100 |
0.100 |
0.001 |
0.100 |
0.099 |
Pass |
| 45 |
LPDDR4_DQ15_4 |
U6.T5 |
U7.E9 |
Pass |
Fast |
625.0 |
238.1 |
241.7 |
330.0 |
-8.0 |
-69.0 |
253.0 |
259.6 |
-8.0 |
-69.0 |
182.600 |
620.0 |
-16.0 |
-281.0 |
322.8 |
N/A |
N/A |
N/A |
N/A |
4.378 |
1.000 |
3.378 |
4.820 |
7.000 |
2.180 |
165.414 |
241.2 |
90.0 |
151.2 |
0.0 |
300.0 |
300.0 |
18.2 |
300.0 |
281.8 |
0.000 |
0.100 |
0.100 |
0.001 |
0.100 |
0.099 |
Pass |
| 46 |
LPDDR4_DQ1_4 |
U6.E4 |
U7.E4 |
Pass |
Fast |
625.0 |
242.5 |
241.7 |
309.7 |
-8.0 |
-69.0 |
233.0 |
266.3 |
-8.0 |
-69.0 |
189.3 |
616.2 |
-16.0 |
-281.0 |
318.9 |
N/A |
N/A |
N/A |
N/A |
4.079 |
1.000 |
3.079 |
4.856 |
7.000 |
2.144 |
159.951 |
242.0 |
90.0 |
152.0 |
0.0 |
300.0 |
300.0 |
24.6 |
300.0 |
275.4 |
0.000 |
0.100 |
0.100 |
0.004 |
0.100 |
0.096 |
Pass |
| 47 |
LPDDR4_DQ2_4 |
U6.D3 |
U7.E2 |
Pass |
Fast |
625.0 |
241.2 |
241.7 |
320.8 |
-8.0 |
-69.0 |
243.8 |
262.4 |
-8.0 |
-69.0 |
185.6 |
617.7 |
-16.0 |
-281.0 |
320.5 |
N/A |
N/A |
N/A |
N/A |
4.191 |
1.000 |
3.191 |
4.614 |
7.000 |
2.386 |
158.058 |
241.5 |
90.0 |
151.5 |
0.0 |
300.0 |
300.0 |
13.5 |
300.0 |
286.5 |
0.000 |
0.100 |
0.100 |
0.002 |
0.100 |
0.098 |
Pass |
| 48 |
LPDDR4_DQ3_4 |
U6.E5 |
U7.F4 |
Pass |
Fast |
625.0 |
240.6 |
241.7 |
318.8 |
-8.0 |
-69.0 |
241.8 |
269.7 |
-8.0 |
-69.0 |
193.0 |
620.5 |
-16.0 |
-281.0 |
323.3 |
N/A |
N/A |
N/A |
N/A |
4.359 |
1.000 |
3.359 |
4.560 |
7.000 |
2.440 |
161.288 |
243.0 |
90.0 |
153.0 |
0.0 |
300.0 |
300.0 |
10.8 |
300.0 |
289.2 |
0.000 |
0.100 |
0.100 |
0.001 |
0.100 |
0.099 |
Pass |
| 49 |
LPDDR4_DQ4_4 |
U6.D2 |
U7.C2 |
Pass |
Fast |
625.0 |
243.2 |
241.7 |
320.1 |
-8.0 |
-69.0 |
243.4 |
255.2 |
-8.0 |
-69.0 |
178.5 |
617.4 |
-16.0 |
-281.0 |
320.1 |
N/A |
N/A |
N/A |
N/A |
3.838 |
1.000 |
2.838 |
4.905 |
7.000 |
2.095 |
153.615 |
241.8 |
90.0 |
151.8 |
0.0 |
300.0 |
300.0 |
30.3 |
300.0 |
269.7 |
0.000 |
0.100 |
0.100 |
0.006 |
0.100 |
0.094 |
Pass |
| 50 |
LPDDR4_DQ5_4 |
U6.F3 |
U7.C4 |
Pass |
Fast |
625.0 |
242.2 |
241.7 |
320.5 |
-8.0 |
-69.0 |
243.5 |
256.4 |
-8.0 |
-69.0 |
179.6 |
616.7 |
-16.0 |
-281.0 |
319.5 |
N/A |
N/A |
N/A |
N/A |
4.000 |
1.000 |
3.000 |
4.829 |
7.000 |
2.171 |
158.237 |
242.2 |
90.0 |
152.2 |
0.0 |
300.0 |
300.0 |
28.1 |
300.0 |
271.9 |
0.000 |
0.100 |
0.100 |
0.005 |
0.100 |
0.095 |
Pass |
| 51 |
LPDDR4_DQ6_4 |
U6.F1 |
U7.B4 |
Pass |
Fast |
625.0 |
241.8 |
241.7 |
326.5 |
-8.0 |
-69.0 |
249.8 |
253.8 |
-8.0 |
-69.0 |
177.1 |
618.1 |
-16.0 |
-281.0 |
320.9 |
N/A |
N/A |
N/A |
N/A |
4.076 |
1.000 |
3.076 |
4.965 |
7.000 |
2.035 |
159.165 |
241.5 |
90.0 |
151.5 |
0.0 |
300.0 |
300.0 |
30.3 |
300.0 |
269.7 |
0.000 |
0.100 |
0.100 |
0.003 |
0.100 |
0.097 |
Pass |
| 52 |
LPDDR4_DQ7_4 |
U6.F2 |
U7.B2 |
Pass |
Fast |
625.0 |
244.4 |
241.7 |
317.3 |
-8.0 |
-69.0 |
240.3 |
256.5 |
-8.0 |
-69.0 |
179.8 |
615.8 |
-16.0 |
-281.0 |
318.5 |
N/A |
N/A |
N/A |
N/A |
3.836 |
1.000 |
2.836 |
4.932 |
7.000 |
2.068 |
154.706 |
241.3 |
90.0 |
151.3 |
0.0 |
300.0 |
300.0 |
30.6 |
300.0 |
269.4 |
0.000 |
0.100 |
0.100 |
0.004 |
0.100 |
0.096 |
Pass |
| 53 |
LPDDR4_DQ8_4 |
U6.R3 |
U7.C9 |
Pass |
Fast |
625.0 |
243.2 |
241.7 |
318.0 |
-8.0 |
-69.0 |
241.0 |
257.5 |
-8.0 |
-69.0 |
180.5 |
614.7 |
-16.0 |
-281.0 |
317.5 |
N/A |
N/A |
N/A |
N/A |
4.064 |
1.000 |
3.064 |
4.718 |
7.000 |
2.282 |
153.543 |
242.3 |
90.0 |
152.3 |
0.0 |
300.0 |
300.0 |
22.7 |
300.0 |
277.3 |
0.000 |
0.100 |
0.100 |
0.004 |
0.100 |
0.096 |
Pass |
| 54 |
LPDDR4_DQ9_4 |
U6.R2 |
U7.B9 |
Pass |
Fast |
625.0 |
243.3 |
241.7 |
329.0 |
-8.0 |
-69.0 |
252.0 |
247.6 |
-8.0 |
-69.0 |
170.8 |
615.8 |
-16.0 |
-281.0 |
318.6 |
N/A |
N/A |
N/A |
N/A |
3.862 |
1.000 |
2.862 |
5.055 |
7.000 |
1.945 |
153.493 |
241.6 |
90.0 |
151.6 |
0.0 |
300.0 |
300.0 |
26.9 |
300.0 |
273.1 |
0.000 |
0.100 |
0.100 |
0.004 |
0.100 |
0.096 |
Pass |